JP7199834B2 - semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a driver circuit for a display such as a liquid crystal display.

Conventionally, Patent Document 1 is known as a document related to an output circuit of a display driver. Patent Document 1 describes a Vref voltage generation circuit for a liquid crystal display device for driving liquid crystal in the liquid crystal display device, which is provided with a circuit for correcting distortion of the voltage waveform due to variations in the input impedance of the driver IC. A Vref voltage generating circuit for a liquid crystal display device is disclosed. That is, Patent Document 1 is an invention relating to a liquid crystal driver for the purpose of improving image quality, and discloses a configuration in which a damping resistor is provided at the output end of an OP amplifier in order to suppress oscillation of a drive signal. As described above, in the output circuit of a display driver, it is conventionally known to stabilize a signal by using a damping resistor having a high resistance value.

The output circuit of the display driver will be described in more detail with reference to the display driver 50 according to the comparative example shown in FIG. As shown in FIG. 5A, the display driver 50 includes a digital-to-analog conversion circuit 12, an output amplifier 14, and a resistor 22. As shown in FIG. A voltage follower type operational amplifier is generally used as the output amplifier 14 of the display driver, and is connected to the output terminal out via a resistor 22 which is a damping resistor for preventing oscillation.

A data line of a display panel (not shown), for example, is connected as a load connected to the output terminal out. In FIG. 5A, the load is represented by a resistor R and a capacitor C. The resistor R represents, for example, an equivalent circuit of electrode resistance of the display, and the capacitor C represents an equivalent circuit of the load capacitance of the display. Generally, the number of output terminals out of a display driver is greater than the number of data lines, and the remaining output terminals out are not connected to anything as shown in FIG. 5(b).

JP-A-11-271708

By the way, the driving time is getting shorter (driving speed is getting higher) as the display panel becomes larger these days, and as a result, it becomes necessary to reduce the value of the damping resistor (resistor 22). Decreasing the damping resistance lowers the stability of the output amplifier 14 against oscillation, and in particular, the output amplifier 14 not connected to the data line of the display panel is more likely to oscillate. If the unloaded output amplifier 14 oscillates, there is a risk that oscillation noise will be mixed into the normally operating output amplifier 14 that is not oscillating. Therefore, it is necessary to increase the standby current of the output amplifier 14 so as not to oscillate even when the data line is not connected. However, this countermeasure increases the current consumption of the display driver.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device capable of reducing current consumption without impairing circuit stability.

A semiconductor device according to the present invention includes a plurality of output amplifiers for outputting drive signals for driving a display device based on an input signal; and one or more oscillation prevention circuits for outputting a stop signal to the output amplifier to stop the operation of the output amplifier when the output amplifier stops operating, and the oscillation prevention circuit is connected to an output section of the output amplifier. an oscillation detection circuit for detecting oscillation of the output amplifier during a period set so that a disable circuit for switching whether to detect oscillation of the output amplifier detects oscillation of the output amplifier; and a pulse counter that counts the number of pulses caused by the oscillation within a predetermined measurement period when the oscillation detection circuit detects oscillation; a latch circuit that generates the stop signal when the pulse count value is equal to or greater than a predetermined number; at least a part of which is shared, wherein the shared circuits are one or a plurality of the oscillation detection circuits and the pulse counter provided for each of the groups, and the output section of the output amplifier and each of the groups one or more first switches connected between the input section of the oscillation detection circuit and one switch arranged between the output section of the pulse counter for each group and the input section of the latch circuit; and one or a plurality of second switches for controlling the first switch and the second switch such that the stop signal is output to the output amplifier for each group.

According to the present invention, it is possible to provide a semiconductor device capable of reducing current consumption without impairing circuit stability.

1 is a block diagram showing an example of a configuration of a display driver circuit according to a first embodiment; FIG. 1A is a circuit diagram showing an example of the configuration of an oscillation detection circuit according to a first embodiment, and FIG. 1B is a diagram showing inputs and outputs of the oscillation detection circuit; FIG. FIG. 10 is a circuit diagram showing an example of the configuration of an oscillation detection circuit according to a second embodiment; FIG. 11 is a block diagram showing an example of the configuration of a display driver according to a third embodiment; FIG. (a) and (b) are block diagrams showing the configuration of a display driver according to a comparative example.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the following description, as an example of a semiconductor device according to the present invention, a semiconductor device including a driver circuit for a display such as a liquid crystal display (hereinafter referred to as "display driver circuit") will be described. A plurality of display driver circuits according to this embodiment are provided corresponding to a plurality of channels of the display. In the display driver circuit according to the present embodiment, current consumption is reduced by adjusting the current amount of the output amplifier depending on whether or not the output of the output amplifier is oscillating. As a result, the display driver circuit according to this embodiment can reduce the standby current of the output amplifier.

[First embodiment]
A display driver circuit 10 according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. As shown in FIG. 1, the display driver circuit 10 includes a digital-to-analog conversion circuit 12 (labeled "DAC" in FIG. 1), an output amplifier 14 (labeled "output amp" in FIG. 1), a resistor 22, and an anti-oscillation circuit. It is configured including a circuit 24 . A display driver circuit 10 is a circuit for driving a display device (display) such as a liquid crystal. A drive signal for driving a display (not shown) is input to a digital-to-analog conversion circuit 12, and an output terminal out shown in FIG. Each channel is connected, and the display is driven by the drive signal output from the output terminal out.

The digital-to-analog conversion circuit 12 receives a display drive signal as a digital signal from a signal source (not shown) and converts it into an analog signal. The output amplifier 14 is a buffer circuit for a display connected as a load, and is a voltage follower type amplifier circuit in this embodiment. However, the present invention is not limited to this, and the output amplifier 14 may have a gain. Resistor 22 is the damping resistor described above.

The oscillation prevention circuit 24 is branched from a node A between the output of the output amplifier 14 and the resistor 22 , and the output of the oscillation prevention circuit 24 is fed back to the output amplifier 14 . As shown in FIG. 1, the oscillation prevention circuit 24 includes an oscillation detection circuit 16, a pulse counter 18, and a latch circuit 20 (denoted as "latch" in FIG. 1).

The oscillation detection circuit 16 is connected to the output of the output amplifier 14, monitors the state of the display driver circuit 10, and outputs a signal (hereinafter referred to as an "oscillation signal") corresponding to the state of oscillation when oscillation is detected. . A pulse counter 18 receives the output of the oscillation detection circuit 16 (node B) and, if the output is an oscillation signal, counts the number of pulses based on the oscillation signal. The latch circuit 20 receives the output of the pulse counter 18 (node C), and holds the detection when the oscillation state is detected according to a predetermined condition. A signal indicating that the latch circuit 20 has detected oscillation (hereinafter referred to as a "latch signal") is fed back to the control circuit (not shown) of the output amplifier 14 (node D), and the current of the output amplifier 14 is controlled by the latch signal. The operation of the output amplifier 14 is controlled by controlling the circuit.

Oscillation detection circuit 16 according to the present embodiment will be described in more detail with reference to FIG. As shown in FIG. 2A, the oscillation detection circuit 16 includes a self-bias generation circuit 26 and a current control buffer 28. The input of the oscillation detection circuit 16 is connected to node A, and the oscillation detection circuit 16 is connected to node B. A capacitance 30 shown in FIG. 2(a) is a coupling capacitance. On the other hand, an N-type MOS (Metal Oxide Semiconductor) transistor (hereinafter referred to as "NMOS transistor") N7 has a gate connected to a disable terminal DE and has a function of a disable circuit for switching the oscillation detection circuit 16 between operation and non-operation. are doing. In this embodiment, the disable signal input to the disable terminal DE is low level (hereinafter referred to as "L") for operation (enable) and high level (hereinafter referred to as "H") for non-operation (disable). . Note that in the present embodiment, the oscillation detection circuit 16 side of the node A is a low voltage (LV) circuit, and the connection source of the oscillation detection circuit 16 (that is, the output terminal out) is a high voltage (HV) circuit. . Hereinafter, the high potential side of HV is referred to as "VDDH", the low potential side as "VSSH", the high potential side of LV as "VDDI", and the low potential side as "VSSI". As shown in FIG. 2A, the oscillation detection circuit 16 according to this embodiment is connected between VDDI and VSSI.

The self-bias generation circuit 26 is connected to the capacitor 30 and includes P-type MOS transistors (hereinafter referred to as "PMOS transistors") P1, P2 and NMOS transistors N1, N2. The PMOS transistor P2 and the NMOS transistor N1 are diode-connected, the gate of the PMOS transistor P1 is connected to a bias terminal pb supplied with a bias voltage, and the gate of the NMOS transistor N2 is connected to a bias terminal nb supplied with a bias voltage. there is

The current control buffer 28 includes PMOS transistors P3, P4, P5 and P6 and NMOS transistors N3, N4, N5 and N6, and has a two-stage configuration of a front stage and a rear stage. The pre-stage buffer includes PMOS transistors P3, P4 and NMOS transistors N3, N4. The gates of the PMOS transistor P4 and the NMOS transistor N3 are connected to the output of the self-bias generation circuit 26, respectively. is connected to a bias terminal pb, and the gate of the NMOS transistor N4 is connected to a bias terminal nb.

On the other hand, the post-stage buffer includes PMOS transistors P5 and P6 and NMOS transistors N5 and N6, and has the same circuit configuration as the pre-stage buffer composed of PMOS transistors P3 and P4 and NMOS transistors N3 and N4. That is, the gate of the PMOS transistor P6 and the gate of the NMOS transistor N5 are connected to the output of the pre-stage buffer, respectively, the bias terminal pb is connected to the gate of the PMOS transistor P5, and the bias terminal nb is connected to the gate of the NMOS transistor N6. there is The current control buffer 28 according to the present embodiment is capable of amplifying minute oscillations in a pulse form by connecting in series a front-stage buffer and a rear-stage buffer of the same size. The number of stages of buffers forming the current control buffer 28 may be one, or may be three or more, depending on the oscillation detection sensitivity and the like.

Next, the operation of the oscillation detection circuit 16 will be described with reference to FIG. 2(b). FIG. 2(b) shows simulation results of waveforms of each part (output terminal out, node E, node B) of the oscillation detection circuit 16. FIG. When detecting the presence or absence of oscillation of the display driver circuit 10, the disable terminal DE is set to L to turn off the disable circuit (NMOS transistor N7). At this time, the node E inside the oscillation detection circuit 16 shown in FIG.

When the output amplifier 14 oscillates, the output terminal out of the display driver circuit 10 oscillates at a frequency corresponding to the oscillation, as shown in FIG. 2(b). This oscillation of the output terminal out causes the potential of the node E to finely fluctuate via the capacitor 30 . As a result, the input of the post-stage buffer (PMOS transistors P5, P6, NMOS transistors N5, N6) fluctuates across the threshold voltage. converted to a symmetrical signal. An oscillation measurement period MT, which is a period for detecting oscillation, is set in the pulse counter 18 in advance. counting).

When the number of pulses counted by the pulse counter 18 is equal to or greater than a predetermined number (hereinafter referred to as "oscillation threshold"), it is assumed that the output amplifier 14 is oscillating, and the pulse counter 18 outputs H to node C. . Receiving H output from the pulse counter 18 , the latch circuit 20 holds H even after the oscillation measurement period MT ends, and feeds back this H to the output amplifier 14 . The output amplifier 14 that receives the H cuts (shuts off) the current of the output amplifier 14 to disable the output amplifier.

As described in detail above, according to the display driver circuit of this embodiment, the output amplifier 14 to which no data line is connected cuts the current, which affects the output to which other data lines are connected. never As a result, it is possible to reduce the standby current to the extent that it oscillates in a no-load state.

[Second embodiment]
A display driver circuit according to the present embodiment will be described with reference to FIG. The display driver circuit according to this embodiment is obtained by replacing the oscillation detection circuit 16 of the display driver circuit according to the above embodiment with an oscillation detection circuit 16A. Therefore, the display driver circuit will be omitted from the illustration, with reference to FIG. 1 as necessary. In addition, in the oscillation detection circuit 16A, components having the same functions as those in the oscillation detection circuit 16 are denoted by the same reference numerals, and detailed description thereof will be omitted.

Although the output terminal out of the display driver circuit 10 is HV, in the above embodiment, the output terminal out oscillates at HV, but the oscillation detection circuit 16 detects it by converting it to LV. In the present embodiment, the HV of the output terminal out is not converted to LV, and HV is detected as it is. Thus, in the present embodiment, it is possible to detect HV as it is without converting HV at the output terminal out to LV.

The operation of the oscillation detection circuit 16A according to the present embodiment will be described with reference to FIG. As shown in FIG. 3, the oscillation detection circuit 16A includes a self-bias generation circuit 26A and a current control buffer 28A, which are connected between power supplies VDDH and VSSH. The circuit configurations of the self-bias generation circuit 26A and the current control buffer 28A according to the present embodiment are similar to the circuit configurations of the self-bias generation circuit 26 and the current control buffer 28 according to the above-described embodiment, respectively, except for the power supply. In the oscillation detection circuit 16A, when the disable terminal DE is set to L to turn off the disable circuit (NMOS transistor N7), the potential of the node E changes to the HV inverter (self-bias generation) between the HV power supply VDDH and VSSH. equal to the threshold voltage of circuit 26A). When the output amplifier 14 oscillates in this state, the potential of the node E rises and falls across the threshold voltage of the HV inverter. When this is buffered, a HV pulse-like output is obtained at the node B, and by counting the number of pulses, it is possible to determine the presence or absence of oscillation. Since subsequent operations are the same as those of the above embodiment, detailed description thereof will be omitted.

As in the above embodiment, according to the display driver circuit of this embodiment, the current is cut off in the output amplifier 14 to which no data line is connected, and the output to which other data lines are connected is not affected. never give. Therefore, it is possible to reduce the standby current to the extent that it oscillates in a no-load state.

[Third embodiment]
A display driver circuit 10A according to the present embodiment will be described with reference to FIG. The display driver circuit 10A shares a part of the oscillation prevention circuit 24 of the display driver circuit 10 according to each of the above embodiments for each of a plurality of predetermined channels. Accordingly, in the display driver circuit 10A, components having the same functions as those of the display driver circuit 10 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 4, the display driver circuits 10A according to the present embodiment are provided as many as the number of channels, and further include shared circuits 32 provided for each of the plurality of display driver circuits 10A. The display driver circuit 10A includes a digital-analog conversion circuit 12, an output amplifier 14, a resistor 22, a latch circuit 20, and switches SW1 and SW2. Shared circuit 32 includes oscillation detection circuit 16 and pulse counter 18 . That is, in each of the above-described embodiments, the oscillation detection circuit 16 (16A) is provided for each channel. one for each channel (shared by multiple channels). The switches SW1 and SW2 switch the output amplifier 14 connected to the shared circuit 32 in a time division manner to detect oscillation.

A display driver circuit 10A according to the present embodiment will be described using a specific example. For example, assume that the number of channels is 30, and these 30 channels are grouped into 3 groups of 10 channels each. In this case, there are three shared circuits 32: a shared circuit 32-1 for channels 1-10, a shared circuit 32-2 for channels 11-20, and a shared circuit 32-3 for channels 21-30. For example, the display driver circuits 10A for channels 1 to 10 are each connected to the common circuit 32-1 via ten series of switches SW1 and SW2. When the oscillation of channel 1 is detected, the common circuit 32-1 is connected to the output amplifier 14 of channel 1 by switches SW1 and SW2, and when the oscillation of channel 2 is detected, the channel 2 signal is detected by switches SW1 and SW2. A shared circuit 32-1 is connected to the output amplifier 14 of . The same is true for channels 3-10, and also for other channel groups.

In this embodiment, a plurality of channels of the display are divided into a plurality of groups, and an oscillation detection circuit is arranged for each group. Alternatively, two oscillation detection circuits may be arranged and the connected output amplifier 14 may be switched. Also, the number of channels grouped may be equal or different.

As described above, according to the display driver circuit 10A of the present embodiment, at least part of the oscillation detection circuit 16 is shared by a group of a plurality of display driver circuits 10A by time-division control, whereby oscillation detection is performed. It is possible to reduce the circuit scale of the circuit 16 to approximately one/the number of groups.

10, 10A Display driver circuit 12 Digital-to-analog conversion circuit 14 Output amplifiers 16, 16A Oscillation detection circuit 18 Pulse counter 20 Latch circuit 22 Resistor 24 Oscillation prevention circuit 26, 26A Self-bias generation circuit 28, 28A Current control buffer 30 Capacitor 32 Shared circuit MT Oscillation measurement period out Output terminals P1 to P6 PMOS transistors N1 to N7 NMOS transistors pb, nb Bias terminals SW1, SW2 Switch

Claims (5)

a plurality of output amplifiers that output drive signals for driving the display device based on the input signals;
One or more oscillation prevention circuits that output a stop signal to the output amplifier to stop the operation of the output amplifier when an input is connected to the output of the output amplifier and oscillation of the output amplifier is detected. and including
The oscillation prevention circuit is connected to the output section of the output amplifier, and the disable circuit for switching whether or not to detect oscillation of the output amplifier detects oscillation of the output amplifier during a period set to detect oscillation of the output amplifier. an oscillation detection circuit for detecting oscillation of the output amplifier, connected to the oscillation detection circuit and counting the number of pulses caused by the oscillation within a predetermined measurement period when the oscillation detection circuit detects oscillation; and a latch circuit connected to the pulse counter and configured to generate the stop signal when the number of pulses counted by the pulse counter is equal to or greater than a predetermined number ,
at least part of the oscillation prevention circuit is shared by one or a plurality of groups of a predetermined number of the output amplifiers;
the shared circuits are one or more of the oscillation detection circuits and the pulse counter provided for each of the groups;
one or more first switches connected between the output of the output amplifier and the input of the oscillation detection circuit for each group;
one or more second switches arranged between the output of the pulse counter for each group and the input of the latch circuit;
controlling the first switch and the second switch so that the stop signal is output to the output amplifier for each group;
semiconductor equipment. an output terminal for outputting the drive signal;
a resistor connected between the output of the output amplifier and the output terminal;
2. The semiconductor device according to claim 1, further comprising a capacitor included in said oscillation detection circuit and having one terminal connected to an output section of said output amplifier. 3. The semiconductor device according to claim 1, wherein the oscillation prevention circuit stops the operation of the output amplifier by interrupting the current of the output amplifier with the stop signal. The oscillation detection circuit includes a self-bias generation circuit connected to the output of the output amplifier and generating a bias potential, and a current buffering the output of the self-bias generation circuit connected to the self-bias generation circuit. 4. The semiconductor device according to claim 1, comprising a controlled buffer circuit. 5. The semiconductor device according to claim 4, wherein the buffer circuit includes a plurality of buffer circuits having the same configuration connected in series.

Images