JP7201004B2 - semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device having a structure for suppressing fluctuations in breakdown voltage due to external factors and improving stability.

In order to improve the breakdown voltage of a semiconductor device, a structure for improving the breakdown voltage is formed in a peripheral region around an element region in which a semiconductor element is formed. For example, an attempt is made to improve the breakdown voltage of a semiconductor device by arranging a trench in which a conductive film is buried inside a trench having an insulating film formed on the inner wall surface in the peripheral region (see Patent Document 1).

JP-A-2007-59766

When the depletion layer spreads in the peripheral region and reaches the surface of the semiconductor substrate, the semiconductor device becomes susceptible to external ions and the like. For example, the shape of the depletion layer is distorted due to the influence of ions entering from the outside, and the breakdown voltage may fluctuate or become unstable. In addition, it is necessary to prevent the depletion layer spreading outward from reaching the side surface of the chipped semiconductor device. For this reason, for example, it is conceivable to widen the width of the peripheral region up to the dice line for chipping the semiconductor devices formed on the wafer. However, this measure increases the chip size. Further, if the channel stopper region is formed deeply at the outer edge of the peripheral region, there is a problem that the manufacturing process becomes long.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a compact semiconductor device in which fluctuations in breakdown voltage due to external factors such as external ions are suppressed.

According to one aspect of the present invention, the element region and the peripheral region surrounding the element region are provided with a semiconductor substrate defined on the main surface, and the peripheral region includes a groove extending from the upper surface of the semiconductor substrate in the film thickness direction. A peripheral trench having an insulating film disposed on the wall surface and a conductive film disposed on the insulating film within the trench is disposed, and a semiconductor substrate is formed over the element region and the peripheral region. and a channel stopper region having an impurity concentration higher than that of the first semiconductor layer, electrically connected to the conductor film in the outer trench, and formed in the peripheral region apart from the outer trench. A semiconductor device is provided that includes:

According to the present invention, it is possible to provide a small-sized semiconductor device in which variations in breakdown voltage due to external factors such as external ions are suppressed.

1 is a schematic cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the invention; FIG. 4 is a schematic cross-sectional view showing spread of a depletion layer of the semiconductor device according to the embodiment of the invention; FIG. FIG. 10 is a schematic cross-sectional view showing spread of a depletion layer in a semiconductor device of a comparative example; FIG. 3 is a schematic cross-sectional view showing the configuration of a semiconductor device of a comparative example; It is a schematic cross-sectional view showing the configuration of a semiconductor device according to a modification of the embodiment of the present invention.

Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and that the relationship between thickness and planar dimensions, the length ratio of each part, and the like are different from the actual ones. Therefore, specific dimensions should be determined with reference to the following description. In addition, it is a matter of course that there are portions with different dimensional relationships and ratios between the drawings.

Moreover, the embodiments shown below illustrate devices and methods for embodying the technical idea of the present invention. The technical idea of the present invention does not specify the shape, structure, arrangement, etc. of the components as described below.

A semiconductor device according to an embodiment of the present invention, as shown in FIG. 1, includes a semiconductor substrate 10 having an element region 110 and a peripheral region 120 surrounding the element region 110 defined on its main surface. An interlayer insulating film 30 is arranged on the upper surface of the semiconductor substrate 10 .

In the peripheral region 120 , a plurality of peripheral trenches 20 are arranged in multiple layers so as to surround the device region 110 while being spaced apart from each other. That is, the annular outer trench 20 is arranged around the element region 110 in plan view. The outer trench 20 has an insulating film 21 arranged on the inner wall surface of the groove extending in the film thickness direction from the upper surface of the semiconductor substrate 10, and a conductor film 22 arranged on the insulating film 21 inside the groove. For example, the groove of the outer peripheral trench 20 of the semiconductor substrate 10 having the configuration in which the second semiconductor layer 12 of the second conductivity type is laminated on the first semiconductor layer 11 of the first conductivity type extends from the upper surface of the second semiconductor layer 12. and reaches the first semiconductor layer 11 . The conductor film 22 and the semiconductor substrate 10 face each other with the insulating film 21 interposed therebetween on the side and bottom surfaces of the outer trench 20 . Here, the bottom of the insulating film 21 is positioned below the PN junction surface between the first semiconductor layer 11 and the second semiconductor layer 12 . In the following description, it is assumed that the first conductivity type is n-type and the second conductivity type is p-type.

Although illustration is omitted, a semiconductor element that operates by applying a voltage between two main electrodes is formed in the element region 110 . For example, a vertical switching element such as a MOSFET with a gate trench structure or an insulated gate bipolar transistor (IGBT) is formed in the element region 110 . When a vertical switching element is formed in the element region 110, a configuration in which a front surface electrode (not shown) is arranged on the front surface of the semiconductor substrate 10 and a rear surface electrode 60 is arranged on the rear surface of the semiconductor substrate 10 may be used. . In the following description, the front electrode arranged on the upper surface of the semiconductor substrate 10 is the negative main electrode of the semiconductor element, and the back electrode 60 arranged on the lower surface of the semiconductor substrate 10 is the positive main electrode of the semiconductor element. explain.

In the semiconductor device shown in FIG. 1, the conductor film 22 of the outer trench 20 located closest to the outer edge of the semiconductor substrate 10 (hereinafter referred to as the "outermost edge trench") among the outer trenches 20 is the conductor film 22 of the semiconductor element. It is set to a potential higher than the potential of the main electrode on the negative side. In the semiconductor device shown in FIG. 1, the outermost trench is connected to the upper conductor film 50 arranged on the upper surface of the semiconductor substrate 10 through the opening of the interlayer insulating film 30 . The conductor films 22 of the outer peripheral trenches 20 other than the outermost trenches are in an electrically floating state.

The upper conductor film 50 is connected to the upper surface of the channel stopper region 40 arranged along the outer edge of the semiconductor substrate 10 . A channel stopper region 40 of the same conductivity type as that of the first semiconductor layer 11 of the semiconductor substrate 10 is formed annularly in a plan view in a part of the upper portion of the first semiconductor layer 11 of the peripheral region 120 . The channel stopper region 40 is arranged for the purpose of suppressing fluctuations in breakdown voltage due to external factors such as external ions in the peripheral region 120 , and the impurity concentration of the channel stopper region 40 is lower than that of the first semiconductor layer 11 . set high. Since the depletion layer is bent near the interface between the channel stopper region 40 and the first semiconductor layer 11 , the depletion layer is prevented from reaching the diced side surface (outer edge) of the semiconductor substrate 10 . The first semiconductor layer 11 is formed up to the outer edge of the peripheral region 120 , but the end of the second semiconductor layer 12 does not reach the outer edge of the semiconductor substrate 10 . Thus, it is desirable that the end of the second semiconductor layer 12 be inside the channel stopper region 40 . That is, the first semiconductor layer 11 is sandwiched between the end portion of the second semiconductor layer 12 and the channel stopper region 40 on the upper surface of the semiconductor substrate 10 . For example, the end of the second semiconductor layer 12 is in contact with the inner wall of the outermost trench, but the second semiconductor layer 12 does not extend to the outer edge side of the semiconductor substrate 10 beyond the outer wall of the outermost trench. The end portion of the second semiconductor layer 12 may extend to the channel stopper region 40 side from the outermost edge trench. Moreover, although the example in which the bottom of the outermost trench is below the PN junction surface between the first semiconductor layer 11 and the second semiconductor layer 12 is shown, the bottom of the outermost trench is located between the first semiconductor layer 11 and the second semiconductor layer 11 . It does not have to reach the PN junction with layer 12 .

In the semiconductor device shown in FIG. 1, the conductor film 22 of the outermost trench is electrically connected to the back electrode 60 through the upper conductor film 50 and the semiconductor substrate 10 . For example, when the semiconductor element formed in the element region 110 is a transistor, and the negative main electrode is the emitter electrode and the positive main electrode is the collector electrode, the conductor film 22 in the outermost trench is the collector electrode. set to a potential. When the main electrode on the negative side is the source electrode and the main electrode on the positive side is the drain electrode, the conductor film 22 in the outermost edge trench is set to the potential of the drain electrode. Alternatively, if the semiconductor element formed in the element region 110 is a diode, the conductor film 22 in the outermost trench is set to the potential of the anode.

When the semiconductor device is turned off or reverse-biased, the depletion layer extends from the first semiconductor layer 11 and the second semiconductor layer 12 on the side of the element region 110, causing the depletion layer to extend laterally and downward in the peripheral region 120. spreads, and the concentration of the electric field is relieved. The conductor film 22 in the outermost trench is electrically connected to the positive side main electrode of the semiconductor element, and set to a potential higher than the potential of the negative side main electrode of the semiconductor element. This suppresses the expansion of the depletion layer in the peripheral region 120 upward or toward the outer edge. Furthermore, the channel stopper region 40 and the conductor film 22 in the outermost trench are electrically connected, and the first semiconductor layer 11 is present between the outermost trench and the channel stopper region 40, so that the depletion layer can be suppressed from approaching the vicinity of the channel stopper region 40 . FIG. 2 shows the spread of the depletion layer 100 in the peripheral region 120 of the semiconductor device shown in FIG. 1, and FIG. 3 shows the spread of the depletion layer 100 in the peripheral region 120 of the semiconductor device of the comparative example. In the comparative example shown in FIG. 3, the conductor films 22 of all the peripheral trenches 20 are in an electrically floating state.

2 and 3, in the semiconductor device shown in FIG. 1, the depletion layer 100 is suppressed from extending above and to the outer edge of the peripheral region 120 as compared with the comparative example. This is because, according to the semiconductor device shown in FIG. 1, the conductor film 22 in the outermost trench is set to a potential higher than the potential of the main electrode on the negative side of the semiconductor element, so that the depletion layer 100 is reduced to the semiconductor substrate 10. This is because an electric field is generated in a direction that inhibits extension toward the upper surface of the .

On the other hand, when the depletion layer 100 extends as shown in FIG. 3, the depletion layer 100 tends to reach the upper surface of the semiconductor substrate 10 and the dice line on the side surface. In particular, as the voltage applied between the main electrodes of the semiconductor element increases, the depletion layer spreads outward. If the width from the element region 110 to the dice line is increased so that the depletion layer 100 does not reach the side surface of the chipped semiconductor device, the chip size increases. Therefore, as shown in FIG. 4, for example, the channel stopper region 40 is formed deep. However, this causes problems such as widening the width of the channel stopper region 40 and prolonging the manufacturing process. In addition, since the depletion layer 100 reaches the upper surface of the semiconductor substrate 10, the semiconductor device becomes susceptible to external influences.

On the other hand, in the semiconductor device shown in FIG. 1, the extension of the depletion layer toward the outer edge of the peripheral region 120 is suppressed by the outermost edge trench. Therefore, there is no need to widen the width of the die line, and an increase in chip size is suppressed. Moreover, it is not necessary to form the channel stopper region 40 deeply. Furthermore, according to the semiconductor device shown in FIG. 1, the depletion layer is suppressed from reaching the upper surface of the semiconductor substrate 10, so that the semiconductor device can be prevented from being affected by the outside.

The peripheral trench 20 is formed, for example, as follows. First, the groove of the outer peripheral trench 20 is formed in the peripheral region 120 . After that, an insulating film 21 is formed on the inner wall surface of the trench by using a thermal oxidation method or the like. Next, a conductor film 22 is formed inside the trench. The conductor film 22 is, for example, a polysilicon film. For example, the conductor film 22 is formed over the entire upper surface of the semiconductor substrate 10 so that the grooves are filled with the conductor film 22 . Then, the upper surface of the conductor film 22 of the outer trench 20 is planarized so that it is lower than or equal to the upper surface of the semiconductor substrate 10 .

When forming a semiconductor element having a gate trench structure in the element region 110, the groove of the outer peripheral trench 20 may be formed simultaneously with the formation of the gate trench. Then, the insulating film 21 of the outer trench 20 is formed simultaneously with the formation of the gate insulating film on the inner wall surface of the gate trench, and the conductor film 22 is formed simultaneously with the formation of the gate electrode.

By the way, in the semiconductor device shown in FIG. 1, the upper conductive film 50 extends beyond the outermost edge trench to the inner peripheral trench 20 . In the portion located above the semiconductor substrate 10, the top conductor film 50 can function like a field plate. By setting the conductor film 22 in the outermost edge trench to a potential higher than the potential of the main electrode on the negative side of the semiconductor element, and further extending the upper surface conductor film 50 to above the inner peripheral trench 20, the upper surface The conductive film 50 controls the depletion layer on the upper surface of the semiconductor substrate 10, and the depletion layer can be extended downward by the outermost edge trench, thereby obtaining a synergistic effect. However, in order to prevent the depletion layer from bending toward the element region 110 due to the effect of the field plate, it is preferable that the top conductive film 50 not extend to a region close to the element region 110 .

As described above, in the semiconductor device according to the embodiment of the present invention, the conductor film 22 in the outermost trench among the outer trenches 20 is set to a potential higher than the potential of the main electrode on the negative side of the semiconductor element. do. As a result, the spread of the depletion layer in the peripheral region 120 is suppressed, and a semiconductor device in which fluctuations in breakdown voltage due to external factors such as external ions are suppressed can be realized.

Furthermore, by adopting a configuration in which the back surface electrode 60 and the conductor film 22 of the outermost trench are electrically connected, the conductor film 22 of the outermost trench can be set at a potential higher than the potential of the main electrode on the negative side of the semiconductor element. can be easily realized. Therefore, the semiconductor device shown in FIG. 1 is easy to manufacture.

<Modification>
In the semiconductor device according to the modified example of the embodiment of the invention shown in FIG. By increasing the width W of the conductor film 22 in the outermost trench, the strength of the electric field that makes the depletion layer 100 more likely to extend toward the lower surface of the peripheral region 120 increases.

As a result, in the semiconductor device shown in FIG. 5, extension of the depletion layer 100 toward the upper surface and the outer edge of the peripheral region 120 is suppressed. Therefore, it is not necessary to increase the width of the die line or to form the channel stopper region 40 deep.

(Other embodiments)
Although the present invention has been described by way of embodiments as described above, the discussion and drawings forming part of this disclosure should not be understood to limit the present invention. Various alternative embodiments, implementations and operational techniques will become apparent to those skilled in the art from this disclosure.

For example, in the above description, the case where the outermost edge trench is electrically connected to the back surface electrode 60 arranged on the lower surface of the semiconductor substrate 10 is exemplified. Other electrodes of the device may be electrically connected to the outermost trench.

Also, the depth of the outermost edge trench may be deeper than the depth of at least one of the other peripheral trenches 20 and the gate trenches.

Also, the outer trench 20 may be only the outermost trench, and the outer trench 20 other than the outermost trench may be replaced with a known breakdown voltage improving region such as a RESURF region or an FLR. In other words, it is sufficient that the conductor film 22 in the outer trench 20 and the channel stopper region 40 are electrically connected. Further, it is desirable that the outer trench 20 and the channel stopper region 40 are separated from each other on the upper surface side of the semiconductor substrate 10 and the first semiconductor layer 11 is interposed between the outer trench 20 and the channel stopper region 40 .

Thus, the present invention naturally includes various embodiments and the like not described here.

INDUSTRIAL APPLICABILITY The semiconductor device of the present invention can be used in the electronic equipment industry, including the manufacturing industry that manufactures semiconductor devices that suppress variations in breakdown voltage due to external factors such as external ions.

DESCRIPTION OF SYMBOLS 10... Semiconductor substrate 20... Outer trench 21... Insulating film 22... Conductive film 30... Interlayer insulating film 40... Channel stopper region 50... Upper surface conductive film 60... Back surface electrode 100... Depletion layer 110... Element region 120... Peripheral region

Claims (3)

a semiconductor substrate having a main surface defined with an element region and a peripheral region surrounding the element region;
In the peripheral region, an outer peripheral trench having an insulating film arranged on an inner wall surface of a groove extending in a film thickness direction from the upper surface of the semiconductor substrate, and a conductor film arranged on the insulating film inside the groove. is placed and
The semiconductor substrate is
a first conductivity type first semiconductor layer formed over the element region and the peripheral region;
a channel stopper region having an impurity concentration higher than that of the first semiconductor layer, electrically connected to the conductor film in the outer trench, and formed in the peripheral region apart from the outer trench. A semiconductor device characterized by: 2. The semiconductor device according to claim 1 , wherein a semiconductor layer of the first conductivity type is arranged on said semiconductor substrate between said outer trench and said channel stopper region. A plurality of trenches are arranged between the peripheral trench and the element region,
each of the plurality of trenches has an insulating film disposed on an inner wall surface of the trench extending in a film thickness direction from the upper surface of the semiconductor substrate and a conductor film disposed on the insulating film;
2. The semiconductor device according to claim 1, wherein the width or depth of said conductor film in said peripheral trench is wider or deeper than the width or depth of said conductor film in said plurality of trenches.

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