JP7212261B2 - switching power supply - Google Patents

Description

The present invention relates to a switching control type DC power supply device having a transformer for voltage conversion, and more particularly to a technology effective for use in an insulated DC-DC converter having a synchronous rectification switch on the secondary side of the transformer, for example.

Conventionally, as one of switching power supply devices, a MOS transistor (insulated gate field effect transistor) as a switching element for intermittently flowing current to the primary coil of a transformer and a control circuit ( There is a switching power supply device (isolated DC-DC converter) that has an IC), rectifies the current induced in the secondary coil by passing current through the primary coil with a diode, smoothes it with a capacitor, and outputs it.

However, in an isolated DC-DC converter that uses a rectifying diode in the secondary circuit, the loss in the rectifying diode is large, which causes a decrease in efficiency. Therefore, a switching element (MOS transistor) for synchronous rectification is provided instead of the rectifying diode in the secondary circuit, and the terminal voltage (source-drain voltage) of the secondary switching element is detected by the secondary side control circuit. Then, there is a technique for reducing the loss in the rectifying element and improving the efficiency by controlling the turn-on of the secondary side switching element at the timing when the forward current flows through the body diode (for example, Patent Document 1).

Further, in the switching power supply device of the secondary side synchronous rectification method, generally, it is detected that the drain voltage of the synchronous rectification MOS transistor becomes equal to or lower than a predetermined judgment threshold value, and the turn-on signal is raised. However, as shown in FIGS. 9A and 9B, ringing RG occurs immediately after the source-drain voltage VDS falls and the synchronous rectification MOS transistor turns on. This ringing causes erroneous detection of the turn-off timing. Sometimes. Therefore, in order to prevent such erroneous turn-off detection, a technique of setting a minimum ON time is known (for example, Patent Document 2). Since the source terminal of the synchronous rectification MOS transistor is generally connected to the ground point on the secondary side, the source-drain voltage is simply referred to as the drain voltage in the following description.

Techniques for setting the minimum on-time include a fixed method that sets the minimum on-time to a predetermined value and a variable method that varies the minimum on-time. Therefore, in the case of the fixed minimum on-time method, as shown in FIG. When the load is light, the minimum ON time is too long, and there is a risk that reverse current may flow just before turn-off. In FIGS. 9B and 9C, t21 and t22 are desirable turn-off timings.
Therefore, in the invention described in Patent Document 2, the minimum ON time is set based on the secondary side conduction period.

Japanese Patent No. 4862432 U.S. Pat. No. 9,825,548

However, in the method of setting the minimum ON time based on the secondary conduction period, as in the invention described in Patent Document 2, the primary side suddenly turns off due to the influence of noise, etc., and the transformer accumulates When the energy is reduced, this effect shortens the secondary conduction period, creating a gate drive pulse with a minimum on-time longer than the secondary conduction period, which can backflow. If the primary side control method is PWM (Pulse Width Modulation) or QR (Flyback Quasi-Resonant), the following sequence is used: primary side ON → secondary side ON → primary side ON → secondary side ON. Since it is repetitive control, the minimum ON time of the current cycle is determined based on the secondary side conduction period of the previous cycle. Therefore, when the behavior of the primary side suddenly changes greatly, there is a problem that the minimum on-time of the secondary side greatly deviates from an appropriate value.

On the other hand, since the peak period of the drain voltage of the synchronous rectification MOS transistor can be regarded as the conduction period of the primary side, a method of determining the minimum ON time based on the peak period of the drain voltage is also conceivable. With this method, the minimum on-time can be determined according to the actual size of the load. Proportional. Therefore, if only the peak width of the drain voltage is used as a reference, the minimum on-time will be affected by the input voltage. I have a problem that I can't.
In addition, in the case of control that does not stop switching when the input voltage drops, the effect is particularly large, and the minimum on-time becomes too long with respect to the secondary-side conduction period, which may cause a large reverse current.

Therefore, it is conceivable to eliminate the input voltage dependency by determining the minimum on-time using the product of the peak width and the peak value of the drain voltage. A detection function is necessary, and the drain voltage has a wide voltage range of about 10 V to 200 V (depending on the conditions, it may be wider). This increases the difficulty of circuit realization.
Further, during subharmonic oscillation in the PWM method, the relation of peak period of drain voltage>>secondary-side conduction period is established. There is a problem that the minimum ON time becomes too long with respect to the secondary side conduction period, and a reverse current may flow.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. Even if the peak value and the peak width of the current change according to the change of the input voltage, the influence of the input voltage is suppressed and the minimum ON time can be determined according to the magnitude of the load.
Another object of the present invention is to prevent the minimum on-time of the secondary side from deviating greatly from the optimum value when the behavior of the primary side suddenly changes greatly.
Still another object of the present invention is to eliminate the need for a circuit for linearly detecting the drain voltage, that is, to reduce the difficulty of circuit implementation, and to prevent the minimum on-time from becoming too long with respect to the secondary-side conduction period, thereby preventing reverse current flow. It's about making it possible.

In order to achieve the above object, the present invention
A transformer for voltage conversion, a synchronous rectification MOS transistor connected in series with a secondary coil of the transformer, and the synchronous rectification MOS transistor being turned on and off based on the drain voltage of the synchronous rectification MOS transistor. A switching power supply device having a secondary side control circuit that controls
A minimum on-time setting circuit is provided for setting a minimum on-time when the MOS transistor for synchronous rectification is turned on, based on the peak period and the bottom period detected by the secondary-side control circuit.
Here, the secondary side control circuit, for example,
a peak period detection circuit for detecting a peak period of the drain voltage of the synchronous rectification MOS transistor;
a bottom period detection circuit for detecting the bottom period of the drain voltage of the synchronous rectification MOS transistor,
The minimum on-time setting circuit sets a minimum on-time when the synchronous rectification MOS transistor is turned on based on the peak period detected by the peak period detection circuit and the bottom period detected by the bottom period detection circuit. configured to

According to the switching power supply configured as described above, since the minimum ON time is set based on the peak period and the bottom period, even if the peak value and peak width of the drain voltage change according to the increase or decrease of the input voltage, , the minimum on-time can be determined according to the size of the load while suppressing the influence of the input voltage. In addition, like the method that sets the minimum on-time based on the secondary-side conduction period, the primary-side is suddenly turned off due to the influence of noise, etc., shortening the primary-side conduction period, and at the same time, the secondary-side conduction period is shortened. Even if it is shortened, the minimum ON time becomes longer than the secondary side conduction period, and reverse current does not flow. In addition, since it does not require a function to detect the drain voltage linearly, unlike the method that determines the minimum on-time using the product of the peak width and peak value of the drain voltage, it avoids increasing the difficulty of circuit implementation. In addition, there is no possibility that the minimum on-time becomes too long with respect to the secondary-side conduction period, causing a reverse current to flow.

Here, the minimum on-time setting circuit is
a minimum on-time setting reference voltage generation circuit that generates a setting reference voltage corresponding to the detected peak period and the detected bottom period;
an adjustment signal generation circuit that generates an adjustment signal according to the detected ratio of the peak period and the bottom period;
a minimum on-time signal generation circuit for generating a minimum on-time signal corresponding to the minimum on-time according to the reference voltage generated by the minimum on-time setting reference voltage generation circuit and the adjustment signal generated by the adjustment signal generation circuit; ,
It can be realized by configuring to include

Preferably, the minimum on-time setting reference voltage generation circuit, the adjustment signal generation circuit, and the minimum on-time signal generation circuit each generate a setting reference voltage and an adjustment signal for each switching cycle of the synchronous rectification MOS transistor. Configure to generate a minimum on-time signal.
According to such a configuration, the set reference voltage, the adjustment signal, and the minimum on-time signal are generated for each cycle. You can avoid going too far from the value.

Further, preferably, the adjustment signal generation circuit generates the adjustment signal when the detected ratio of the peak period to the bottom period is equal to or greater than a predetermined value, and the minimum on-time signal generation circuit generates the adjustment signal. When received, it is configured to generate a minimum on-time signal adjusted to shorten the minimum on-time.
According to such a configuration, when the adjustment signal is received, the minimum on-time is adjusted in the direction of shortening. In response to an operation in which the power becomes unstable or the load suddenly becomes lighter, the minimum ON time is lengthened and it is possible to prevent reverse flow.

Further preferably, a sample-and-hold circuit that captures and holds the reference voltage for each switching cycle, and a voltage difference determination circuit that determines a difference from the reference voltage one cycle before. The minimum on-time signal generating circuit is configured to generate an adjusted minimum on-time signal in the direction of shortening the minimum on-time when the difference is greater than a predetermined value.
According to such a configuration, it is possible to prevent the minimum on-time of the secondary side from greatly deviating from the optimum value when the behavior of the primary side suddenly changes greatly. In addition, since the minimum on-time is adjusted to be short, it is possible to prevent reverse flow due to an increase in the minimum on-time due to abnormal operation.

Further, desirably, a gate driver circuit comprising a source side switch and a sink side switch and generating a gate drive voltage for controlling on/off of the synchronous rectification MOS transistor;
an off-timing detection circuit for detecting a timing for turning off the synchronous rectification MOS transistor based on the drain voltage of the synchronous rectification MOS transistor;
an on-timing detection circuit that detects timing to turn on the synchronous rectification MOS transistor based on the drain voltage;
an on/off control circuit for generating a control signal for on/off controlling the synchronous rectification MOS transistor based on the detection signal of the off-timing detection circuit, the detection signal of the on-timing detection circuit, and the minimum on-time signal; with
The on/off control circuit is configured to turn off the source-side switch of the gate driver circuit as the minimum on-time indicated by the minimum on-time signal elapses.
According to such a configuration, by turning off the switch on the source side first after the minimum on-time elapses, the waiting time corresponding to the dead time for preventing the switch on the source side and the switch on the sink side from being turned on at the same time is shortened. It is possible to speed up the turn-off of the rectifying MOS transistor.

According to the present invention, in a switching power supply device having secondary-side synchronous rectification switching elements, even if the peak value and peak width of the drain voltage change according to changes in the input voltage, the effect of the input voltage is suppressed. It is possible to make it possible to determine the minimum on-time according to the magnitude of the load. In addition, when the behavior of the primary side suddenly changes greatly, it is possible to prevent the minimum on-time of the secondary side from deviating greatly from the optimum value. Furthermore, there is no need for a circuit for linearly detecting the drain voltage, that is, the difficulty of circuit realization is low, and there is an effect that it is possible to prevent a reverse current from flowing due to the minimum on-time becoming too long with respect to the secondary-side conduction period. be.

1 is a circuit configuration diagram showing a configuration example of a secondary-side synchronous rectification type switching power supply device to which the present invention is effectively applied; FIG. 3 is a block diagram showing a configuration example of a secondary side control circuit that constitutes the switching power supply device of the embodiment; FIG. FIG. 4 is a waveform diagram for explaining functions of a timer value-voltage conversion circuit and an MOT (minimum on-time) timer in the secondary side control circuit of the embodiment; FIG. 4 is a waveform diagram for explaining functions of a sample hold & voltage comparison circuit and an MOT timer in the secondary side control circuit of the embodiment; FIG. 4 is a waveform diagram for explaining the function of a peak/bottom ratio calculation circuit in the secondary side control circuit of the embodiment; 4 is a circuit configuration diagram showing a specific example of a peak period and bottom period detection timer, a timer value-voltage conversion circuit, a sample hold & voltage comparison circuit, and a peak/bottom ratio calculation circuit that constitute the secondary side control circuit of the embodiment; FIG. . 4 is a circuit configuration diagram showing a specific example of an MOT timer that configures the secondary side control circuit of the embodiment; FIG. 3A and 3B are circuit configuration diagrams showing specific examples of an on/off control circuit that constitutes the secondary side control circuit of the embodiment; FIG. FIG. 4 is a waveform diagram showing the relationship between the turn-off timing of a MOS transistor and a fixed minimum on-time signal in a conventional synchronous rectification secondary-side control circuit.

Preferred embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows an embodiment of a synchronous rectification type switching power supply device to which the present invention is applied.
The switching power supply device of this embodiment comprises a transformer 10 for voltage conversion having a primary coil Lp, a secondary coil Ls and an auxiliary winding La, and a switching element comprising an N-channel MOS transistor on the primary side of the transformer 10 SW and its control circuit (primary side control circuit) 11 are provided, and a MOS transistor S0 as a synchronous rectification element and its control circuit (secondary side control circuit) 20 are provided on the secondary side to constitute an isolated DC-DC converter. It is In this embodiment, the transformer 10 has a secondary coil Ls whose polarity is opposite to that of the primary coil Lp, and is configured to operate as a flyback converter.

A primary-side switching element SW is connected in series with the primary-side coil Lp of the transformer 10 . The primary side control circuit 11 and the secondary side control circuit 20 are each configured as a semiconductor integrated circuit (IC) on one semiconductor chip or as a semiconductor device mounted in one package. A diode D1 and a capacitor C1 are connected in series between the terminals of the auxiliary winding La of the transformer 10. The voltage induced in the auxiliary winding La is rectified by the diode D1 and smoothed by the capacitor C1, thereby controlling the primary side. A power supply voltage Vcc1 for the circuit 11 is generated and supplied to the power supply terminal of the primary side control circuit 11 .
Further, the DC-DC converter of this embodiment includes a phototransistor PT for receiving light that is connected to the primary side control circuit 11 and receives a feedback signal from the circuit on the secondary side. , the switching frequency or duty ratio of the switching element SW is changed to cope with fluctuations in the load and input voltage.

On the secondary side of the transformer 10, on the other hand, a MOS transistor S0 for synchronous rectification connected between one terminal of the secondary side coil Ls and the output terminal OUT2 and a voltage generated on the secondary side are connected to the power supply voltage. A secondary side control circuit 20 that detects the drain voltage of the synchronous rectification MOS transistor S0 and generates an ON/OFF control signal for the transistor S0, and a smoothing circuit that is connected between the output terminals OUT1 and OUT2 and stabilizes the output voltage VOUT. and a capacitor C2. The synchronous rectification MOS transistor S0 and the secondary side control circuit 20 may be integrated in one package. A variable resistor LD connected between the output terminals OUT1 and OUT2 represents an example of a load or equivalently describes the load.

A power supply terminal VCC of the secondary side control circuit 20 is connected to the output terminal OUT1, and the output voltage VOUT is supplied to the secondary side control circuit 20 as the power supply voltage Vcc2. Further, the power supply voltage of the secondary side control circuit 20 may be configured to rectify the voltage induced in the auxiliary winding of the transformer 10 and supply the rectified voltage.
Further, on the secondary side of the transformer 10, a feedback photodiode PD and an error amplifier E-AMP are connected between the output terminals OUT1 and OUT2. The error amplifier E-AMP is configured to pass a current proportional to the level of the output voltage VOUT to the photodiode PD.

The photodiode PD on the secondary side and the phototransistor PT on the primary side constitute a photointerrupter as an insulated signal transmission means. A feedback signal is generated according to the intensity of the light received by the transistor PT, and the primary side control circuit 11 controls the switching element SW according to this feedback signal.

The secondary-side control circuit 20 monitors the voltage VDS of the external terminal (drain voltage detection terminal) P1 connected via wiring to the drain terminal of the synchronous rectification MOS transistor S0 as the secondary-side switching element, A control signal (gate driving voltage) VG for turning on or off the MOS transistor S0 for synchronous rectification is generated at the timing and output to the gate terminal of the transistor S0 via the external terminal P2.

FIG. 2 shows a configuration example of the secondary side control circuit 20. As shown in FIG.
As shown in FIG. 2, the secondary side control circuit 20 detects the voltage VDS of the drain voltage detection terminal P1 to which the drain terminal of the synchronous rectification MOS transistor S0 is connected and the predetermined threshold voltage Vth_on (for example, - 200mV), and an off-timing detection circuit 21 consisting of a comparator that compares the voltage VDS of the drain voltage detection terminal P1 with a predetermined threshold voltage Vth_off (for example, 0 to -150mV). A circuit 22 is provided.
Here, the determination threshold value Vth_on of the on-timing detection circuit 21 is a voltage considering the forward voltage of the body diode so as to reliably detect that the current has started to flow in the body diode of the MOS transistor S0 for synchronous rectification. is set to

The secondary-side control circuit 20 also includes a peak period detection timer circuit 23 for detecting the peak period Tp (see FIG. 3) of the drain voltage VDS, a bottom period detection timer circuit 24 for detecting the bottom period Tb of the drain voltage VDS, and A timer value-voltage conversion circuit 25 is provided for converting the timer value detected by the timer circuits 23 and 24 to a voltage (MOT determination reference voltage). Note that the timer circuits 23 and 24 and the timer value-voltage conversion circuit 25 are configured as an integrated circuit by using, for example, a charge charging type analog timer consisting of a constant current source and a capacitor for the timer circuits 23 and 24. is also possible.

Further, the secondary-side control circuit 20 captures and holds the output voltage (minimum on-time setting reference voltage: MOT threshold Vmot1) of the timer value-voltage conversion circuit 25 one cycle before, and the current cycle timer value-voltage A sample hold & voltage comparison circuit 26 for comparing with the output voltage (MOT threshold value Vmot2) of the conversion circuit 25, a peak/bottom ratio calculation circuit 27 for calculating the ratio between the drain peak period Tp and the drain bottom period Tb, and the peak/bottom A MOT timer 28 is provided for counting the minimum ON time based on the output of the ratio calculation circuit 27 and the like.

The sample hold & voltage comparison circuit 26 generates a signal TG1 for shortening the pulse width of the output of the MOT timer 28 when the difference between the MOT threshold value of the previous cycle and the MOT threshold value of the current cycle is greater than a predetermined value. Generate and output. In addition, the sample hold & voltage comparison circuit 26 generates a voltage (MOT threshold value) Vmot corresponding to the drain peak period Tp and the drain bottom period Tb, and supplies it to the MOT timer 28, and the MOT timer 28 receives this MOT threshold value. By measuring the time corresponding to the value Vmot, a minimum ON time signal (pulse) MOT having pulse widths corresponding to Tp and Tb is output. Specifically, the larger the values of Tp and Tb, the wider the pulse width of the minimum on-time signal MOT, and the smaller the values of Tp and Tb, the narrower the pulse width of the minimum on-time signal MOT.

Further, the secondary-side control circuit 20 provides a signal for controlling on/off of the synchronous rectification MOS transistor S0 based on the output ON_SIG of the on-timing detection circuit 21, the output OFF_SIG of the off-timing detection circuit 22, and the output MOT of the MOT timer 28. and a gate driver circuit 30 for receiving the generated on/off control signal and outputting the gate driving voltage VG from the external terminal P2.

The on/off control circuit 29 is composed of a logic circuit (for example, an AND gate) that masks the off-timing detection signal OFF_SIG by the output MOT of the MOT timer 28, an RS flip-flop, and the like, and the output signal ON_SIG of the on-timing detection circuit 21 rises. , the gate drive voltage VG is changed to a high level to turn on the MOS transistor S0 for synchronous rectification, and at the timing of the output signal OFF_SIG of the off-timing detection circuit 22, the gate drive voltage VG is changed to a low level to turn off S0. Generate control signals. At this time, the OFF_SIG signal is masked by the minimum ON time signal MOT output from the MOT timer 28 to prohibit input to the ON/OFF control circuit 29, thereby preventing the efficiency from being lowered by turning off within the MOT period. is configured as

Next, the operation of the secondary side control circuit 20 will be described with reference to FIGS. 3 to 5. FIG. 3 is a waveform diagram for explaining the functions of the timer value-voltage conversion circuit 25 and the MOT timer 28, and FIG. 4 is a waveform diagram for explaining the functions of the sample hold & voltage comparison circuit 26 and the MOT timer 28. is.
3 and 4, (a) is the drain voltage VDS of the MOS transistor S0 for synchronous rectification, and (b) is the MOT generated as a voltage obtained by converting the timer value representing the peak period Tp and the bottom period Tb of the drain voltage VDS. Threshold Vmot, (c) the timer value of the MOT timer 28, and (d) the change in the output (minimum on-time signal) MOT of the MOT timer 28, respectively. In FIG. 3B, the solid line D indicates the value of the timer, and the dashed line S indicates a voltage generated by sampling the solid line D at a specific timing. be.

As shown in FIG. 3(b), the timer value (solid line D) falls (reset) at the turn-on timing t1 when the peak period Tp of the drain voltage VDS shown in (a) ends, and the bottom period of VDS It rises during Tb (t1 to t2), maintains the same value during periods when VDS is neither peak nor bottom, such as current discontinuous periods, and then rises until the next turn-on timing t4. In this process, when the sum of the peak period Tp and the bottom period Tb becomes smaller, the peak value Vmot of the timer becomes lower as indicated by the dashed line S in FIG. 3(b).

When the MOT threshold value Vmot becomes lower, the time required for the timer value of the MOT timer 28 to reach the threshold value Vmot becomes shorter as shown in FIG. The pulse width of the minimum ON time signal MOT output from the MOT timer 28 is narrowed.
As described above, by adjusting the pulse width of the minimum on-time signal MOT according to both the magnitude of the peak period Tp and the magnitude of the bottom period Tb of the drain voltage VDS, the peak value and the peak width of the drain voltage are input. Even if the input voltage changes in proportion to the voltage, the effect of the input voltage is suppressed and the appropriate minimum on-time is determined according to the size of the load, preventing the occurrence of reverse current flow due to the minimum on-time being too long. can do. In FIGS. 3 and 4, the waveform of the drain voltage VDS during the period from t2 to t3 in (a) is a waveform due to resonance appearing in the discontinuous current mode at light load.

In the secondary side control circuit 20 of this embodiment, as shown in FIG. When the difference from the threshold value Vmot2 is greater than a predetermined value, the sample hold & voltage comparison circuit 26 outputs a shortening trigger pulse TG1 to the MOT timer 28 to shorten the pulse width of the minimum ON time signal MOT.
Then, the minimum on-time signal MOT output from the MOT timer 28 originally changes to low level when the timer value of the MOT timer 28 reaches the threshold value Vmot, as indicated by the dotted line in FIG. 4(d). As shown by the solid line, the minimum on-time signal MOT, which is the minimum on-time signal MOT, hastens the falling edge.
By adjusting the pulse width of the minimum on-time signal MOT as described above, if the behavior of the primary side suddenly changes significantly, the minimum on-time of the secondary side may deviate greatly from the optimum value. can be avoided.

Next, the functions of the peak/bottom ratio calculation circuit 27 and the MOT timer 28 will be described with reference to FIG. In FIG. 5, (a) is a simplified waveform of the drain voltage VDS of the synchronous rectification MOS transistor S0, and (b) is the timer value ( dotted line) and the change of the timer value (solid line) for detecting the peak period Tp and bottom period Tb, that is, Tp+Tb, and (c) the signal (pulse) output from the peak/bottom ratio calculation circuit 27, respectively. A signal (pulse) shown in FIG. 5(c) is supplied to the MOT timer 28 as a shortened trigger pulse TG2. In FIG. 5, (d) shows the operation of the MOT timer 28 when the shortened trigger pulse TG2 is supplied.

In the peak-to-bottom ratio calculation circuit 27, a timer for detecting the peak period Tp is provided separately from the timer for detecting Tp+Tb, and time is weighted by changing the slope of the timer value. For example, when the timer is composed of a constant current source and a capacitor, the slope of the timer value can be changed by changing the current value of the constant current source. Then, both timer values are compared at the timing (t11, t12, t13 in FIG. 5) of the end of the peak period Tp of the drain voltage VDS,
When the timer value of Tp>(Tp+Tb), a trigger pulse TG2 (FIG. 5(c)) for shortening the minimum ON time signal MOT of the next cycle is generated and output.

By doing so, the ratio of the timer value of the peak period Tp and the timer value of the bottom period Tb of the drain voltage VDS is calculated. A shortened trigger pulse TG2 can be output.
By adjusting the pulse width of the minimum on-time signal MOT as described above, when the ratio of the peak period Tp and the bottom period Tb changes greatly due to, for example, a large change in the load on the secondary side, , so that the minimum on-time of the secondary side does not deviate too far from the optimum value.

FIG. 6 shows a peak period detection timer circuit 23, a bottom period detection timer circuit 24, a timer value-voltage conversion circuit 25, a sample hold & voltage comparison circuit 26, and a peak-to-bottom ratio calculation circuit which constitute the secondary side control circuit 20. A specific circuit example of the circuit 27 is shown.
Among them, the peak period detection timer circuit 23 includes, as shown in FIG. 6, a comparator CMP1 that compares the drain voltage VDS and a predetermined threshold voltage Vt1 to detect the starting point of the peak period, and a power supply voltage. A bottom period detection timer circuit 24, comprising a constant current source CC1, a switch S1 and a capacitor C0 connected in series between a terminal VCC and a ground point, detects a drain voltage VDS and a predetermined threshold voltage Vt2. It comprises a comparator CMP2 for detecting the starting point of the bottom period by comparison, a constant current source CC2 connected in series between the power supply voltage terminal VCC and the ground point, a switch S2 and a capacitor C0. Capacitor C 0 functions as timer value-voltage conversion circuit 25 . A reset switch Sr for discharging the charge of the capacitor C0 is connected in parallel with the capacitor C0. A one-shot pulse generation circuit OSP is provided for generating a reset pulse RP for discharging the .
As described above, in this embodiment, the peak period detection timer circuit 23, the bottom period detection timer circuit 24, and the timer value-voltage conversion circuit 25 are configured as an integrated circuit with a common capacitor (C0).

The sample hold & voltage comparison circuit 26 includes a capacitor Cs1, a sampling switch S3 connected between a charging node N1 of the capacitor Cs1 and a charging node N0 of the capacitor C0, and impedance conversion of the charging voltage of the capacitor Cs1. a buffer BFF for transmitting to a subsequent stage, a capacitor Cs2 for holding the transmitted voltage, a hold switch S4 connected between the buffer BFF and a charging node N2 of the capacitor Cs2, the switches S3, A sample-and-hold control circuit SHC is provided for generating a signal for turning on/off S4.

Further, the sample-hold & voltage comparison circuit 26 includes a comparator CMP3 to which the voltage held by the capacitor Cs2 is input to one input terminal (+), and a voltage obtained by adding a predetermined offset to the charged voltage of the capacitor Cs1 to the comparator CMP3. The comparator CMP3 compares the voltage of the previous cycle held in the capacitor Cs2 and the voltage of the current cycle taken in the capacitor Cs1. If the difference is equal to or greater than the offset, a shortened trigger pulse TG1 is output to the MOT timer 28. FIG. Also, the voltage held by the capacitor Cs1 is supplied to the MOT timer 28 as the MOT threshold value Vmot.

The peak-to-bottom ratio calculation circuit 27 includes a constant current source CC3 and a capacitor C3 connected in series between the power supply voltage terminal VCC and a ground point, a reset switch S5 connected in parallel with the capacitor C3, and the capacitor C3. It consists of a comparator CMP4 that compares the charge voltage with the charge voltage of the capacitor C0 of the timer value-voltage conversion circuit 25, and a trigger pulse generation circuit TRG2 that converts the output of CMP4 into an input signal (pulse) to the MOT timer 28. there is
The current value of the constant current source CC3 is set to a value greater than the current values of the constant current sources CC1 and CC2, and the switch S5 is controlled by a signal obtained by inverting the output of the comparator CMP1 of the peak period detection timer circuit 23. As a result, the capacitor C3 is charged by the current of the constant current source CC3 during the peak period Tp of the drain voltage VDS.

On the other hand, the capacitor C0 of the timer value-voltage conversion circuit 25 is charged during the sum of the peak period Tp and the bottom period Tb of the drain voltage VDS (Tp+Tb).
Therefore, the comparator CMP4 of the peak/bottom ratio calculation circuit 27 is
It can be determined whether the relationship of timer value of Tp>timer value of (Tp+Tb) is established.
Then, when the relationship of the above inequality is established, the comparator CMP4 outputs the shortened trigger pulse TG2 to the MOT timer 28 via the trigger pulse generation circuit TRG2. The trigger pulse generation circuit TRG2 determines the output of the comparator CMP4 and generates a shortened trigger pulse TG2 in accordance with the timing at which the MOT timer 28 operates. By providing means for giving a predetermined offset to the inverting input terminal of the comparator CMP4, the shortened trigger pulse TG2 may be output when the peak period Tp is longer than the bottom period Tb by a predetermined amount or more. good.

FIG. 7 shows a specific circuit example of the MOT timer 28 that constitutes the secondary side control circuit 20. As shown in FIG.
As shown in FIG. 7, the MOT timer 28 includes a constant current source CC4 and a capacitor C4 connected in series between the power supply voltage terminal VCC and the ground point, and a reset signal connected in parallel with the capacitor C4. A timer circuit TMR comprising a switch S6 is provided. The switch S6 is on/off-controlled by a signal obtained by inverting the detection signal ON_SIG from the on-timing detection circuit 21 . As a result, the timer circuit TMR charges the capacitor C4 with the current of the constant current source CC4 only while the on-timing detection signal ON_SIG is at a high level, thereby generating a timer value corresponding to the period during which the synchronous rectification MOS transistor S0 should be turned on. to output

Further, the MOT timer 28 takes the logical OR of the shortened trigger pulse TG1 from the sample hold & voltage comparison circuit 26 and the shortened trigger pulse TG2 from the peak/bottom ratio calculation circuit 27, and the output of the OR gate G1. A change-over switch S7 selects one of the MOT threshold value Vmot from the sample-and-hold & voltage comparison circuit 26 or a predetermined reference voltage Vref lower than Vmot according to the selected voltage and the charging of the capacitor C4 of the timer circuit TMR. and a comparator CMP5 for comparing voltages, and an AND gate G2 to which the detection signal ON_SIG from the on-timing detection circuit 21 and the output of the comparator CMP5 are input. Then, the output of the AND gate G2 is supplied to the subsequent on/off control circuit 29 as the minimum on-time signal MOT. An AND gate is provided to receive the signal obtained by inverting the output of the AND gate G2 and the detection signal OFF_SIG from the on-timing detection circuit 21, and the output of this AND gate is supplied to the on/off control circuit 29. can be configured to

FIG. 8 shows specific circuit examples of the on/off control circuit 29 and the gate driver circuit 30 that constitute the secondary side control circuit 20. As shown in FIG.
As shown in FIG. 8A, the gate driver circuit 30 comprises a P-channel MOS transistor M1 and an N-channel MOS transistor M2 connected in series between the power supply voltage terminal VCC and the ground point GND. A gate terminal of a synchronous rectification MOS transistor S0 is connected to a connection node between M1 and M2.

On the other hand, the on/off control circuit 29 includes a 3-input NAND gate G3 that receives the output ON_SIG of the on-timing detection circuit 21 and the minimum on-time signal MOT from the MOT timer 28, and the outputs OFF_SIG and MOT of the off-timing detection circuit 22. A 3-input AND gate G4 is provided which receives the signal obtained by inverting the minimum on-time signal MOT from the timer 28 by the inverter INV. The output signal of the inverter INV functions as a mask signal that prohibits the input of the output OFF_SIG of the off-timing detection circuit 22 .

The on/off control circuit 29 also includes delay circuits DLY1 and DLY2 formed of serial inverters that delay the outputs of the NAND gate G3 and the AND gate G4, respectively. Also, the signals delayed by the delay circuit DLY2 are fed back to the NAND gate G3, respectively, so that the MOS transistors M1 and M2 constituting the gate driver circuit 30 are provided with a dead time to prevent a through current from flowing. It's like

In the on/off control circuit 29 of this embodiment, even if the off-timing detection signal OFF_SIG is input immediately after the source-side MOS transistor M1 is turned on by the on-timing detection signal ON_SIG, the AND gate G4 and the minimum on-time Masked by the signal MOT, the source-side MOS transistor M1 is turned off according to the lapse of the minimum ON time, and both the source-side and sink-side MOS transistors M1 and M2 are turned off. Even if the MOS transistor M1 on the source side is turned off, the output voltage VG of the gate driver circuit 30 is maintained by the gate capacitance of the synchronous rectification MOS transistor S0, and the synchronous rectification MOS transistor S0 maintains the on state. Since the output of the delay circuit DLY1 becomes high level after a predetermined delay time, the 3-input AND gate G4 turns on the sink side MOS transistor M2 in accordance with the off-timing detection signal OFF_SIG without waiting for the response of the delay circuit DLY1. can be turned on.

On the other hand, when the source-side transistor M1 is not turned off by the minimum on-time signal MOT, the synchronous rectification MOS transistor S0 is turned off in the order of source-side switch (M1) off->sink-side switch (M2) on. . At this time, dead time is provided by the delay circuits DLY1 and DLY2 to prevent through current due to simultaneous ON of the source side and sink side switches. Therefore, the sink side switch M2 cannot be turned on unless the source side switch M1 is turned off and the delay time by the delay circuit DLY1 elapses, causing a delay in turning off the synchronous rectification MOS transistor S0.
In the on/off control circuit 29 of this embodiment, the source side switch (M1) is turned off first when the minimum on-time has elapsed, so that the delay time of the delay circuit DLY1 can be shortened, and the off-timing detection signal It is possible to speed up the time from detection of OFF_SIG to turn-off of the MOS transistor S0 for synchronous rectification.

The on/off control circuit 29 is not limited to the configuration shown in FIG. 8A. For example, as shown in FIG. A similar effect can be obtained with a configuration changed to a transistor. In this case, the 3-input NAND gate G3 in the ON/OFF control circuit 29 in FIG. 8A can be changed to a 3-input AND gate, and the inverter in the delay circuit DRY1 can be increased by one stage. The number of inverters in the delay circuit DRY1 may be reduced by one instead of being increased by one.
Thus, when the MOS transistor M1 is changed to an N-channel MOS transistor, the maximum value of the gate drive voltage VG is limited to the value obtained by subtracting the threshold voltage of M1 from the gate voltage of the transistor M1. can be easily clamped.

As described above, in the secondary-side control circuit of the above embodiment, the MOT timer circuit sets the minimum ON time MOT based on the peak period and bottom period of the drain voltage VDS of the secondary-side synchronous rectification MOS transistor S0. 28, it is possible to automatically adjust the minimum ON time, which has a different optimal value depending on the operating conditions of the power supply. In addition, since the minimum on-time is set for each pulse (cycle), it is possible to quickly respond to transient operations in which the optimal minimum on-time changes greatly, such as start/stop of the power supply and load fluctuations. can follow.

In the operation of the secondary side, there is a period such as a burst mode or a resonance period during discontinuous current operation, during which switching stops and the drain voltage VDS assumes an intermediate potential. By using only the peak period and bottom period of the drain voltage VDS as a reference, the drain voltage VDS during the switching stop period can be removed, and the optimum minimum ON time can be set. In addition, the peak period of the drain voltage VDS is affected by the AC input voltage, but the bottom period corresponding to the secondary conduction period is not affected, so both the peak period and the bottom period are used as the criteria for setting the minimum on-time. By doing so, the influence of the AC input voltage can be reduced.

Furthermore, in the secondary side control circuit of the above embodiment, since the minimum on-time is adjusted by looking at the ratio of the peak period and the bottom period of the drain voltage VDS, the on-duty of the primary side and the secondary side is indirectly It can be calculated to adjust the minimum on-time. In a typical isolated power supply, the maximum on-duty is about 0.5. If the on-duty exceeds this, it is out of normal operation, so for safety reasons the minimum on-time should be set small. However, in the above embodiment, such adjustment (shortening) of the minimum ON time is possible.

As a specific example of behavior with a large duty, for example, in the case of the PWM method, when subharmonic oscillation is occurring, the on-duty exceeds 0.5, but in this case the conduction period on the secondary side is shortened. , If the minimum on-time is set to be long, a reverse current will flow. In the case of the QR (flyback quasi-resonant) method, the on-duty exceeds 0.5 when the input voltage drops. Despite the maximum value, a light load requires a shorter minimum on-time, which can lead to backflow. Furthermore, in the case of the LLC system, in which a resonant circuit consisting of an inductor and a capacitor is provided on the primary side, the on-duty is controlled to be 0.5. Since the load is unstable or light, if the minimum on-time is lengthened when the on-duty is increased, backflow may occur.

Furthermore, in the secondary-side control circuit of the above embodiment, the set value of the minimum ON time is stored and compared with each pulse (every cycle). Since the on-time is set to the shortest possible time, it is possible to prevent reverse current from occurring when the minimum on-time becomes longer than the secondary-side conduction period due to sudden load reduction or abnormal operation.
In the secondary-side control circuit of the above embodiment, the drive signals for the source (turn-on) side and sink (turn-off) side switches of the gate driver that drives the secondary-side synchronous rectification MOS transistor are divided to At this time, first, the ON state of the source side switch is canceled after the minimum ON time has elapsed. Generally, when turning off, control is performed in the order of source ON release → simultaneous ON prevention dead time → sink activation. By shutting off the source side switch, the turn-off speed of the synchronous rectification MOS transistor can be increased.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment. For example, in the above embodiment, the peak/bottom ratio calculation circuit 27 makes a determination based on the ratio of the peak period Tp of the drain voltage VDS and (Tp+Tb). The circuit 25 may be configured to measure the peak period Tp and the bottom period Tb separately, and the peak/bottom ratio calculation circuit 27 may be configured to make determination based on the ratio of Tp and Tb.
In the above-described embodiment, the timer circuit for timing various periods is composed of an analog timer circuit consisting of a constant current source and a capacitor. can be

Furthermore, the secondary side synchronous rectification control circuit according to the present invention is not limited to the flyback type switching power supply (DC-DC converter) as shown in FIG. can also be applied to the DC-DC converter of It can also be applied to an LLC resonance converter in which a current resonance circuit consisting of an inductor and a capacitor is provided on the primary side.
In the case of a herb-bridge quasi-resonant DC-DC converter having two synchronous rectification MOS transistors, the two synchronous rectification MOS transistors are controlled by secondary-side control circuits provided corresponding to each. Alternatively, the two synchronous rectification MOS transistors may be controlled by a common secondary side control circuit.

In addition, when configured to be controlled by a common secondary-side control circuit, the peak/bottom of the drain voltage VDS on one side of the secondary side corresponds to the bottom/peak of the drain voltage VDS on the other side. It is also possible to reduce the circuit scale by setting the minimum ON time from one drain voltage VDS, or to measure both drain voltages VDS and judge an abnormality when there is a difference between the peak/bottom states. is.

10 Transformer 11 Primary control circuit 20 Secondary control circuit 21 ON timing detection circuit 22 OFF timing detection circuit 23 Peak period detection timer circuit 24 Bottom period detection timer circuit 25 Timer value-voltage conversion circuit (minimum ON time setting reference voltage generation circuit) 26 Sample hold & voltage comparison circuit 27 Peak/bottom ratio calculation circuit (adjustment signal generation circuit ), 28... MOT timer (minimum on-time signal generation circuit), 29... ON/OFF control circuit, 30... Gate driver circuit, S0... MOS transistor for synchronous rectification

Claims (7)

A transformer for voltage conversion, a synchronous rectification MOS transistor connected in series with a secondary coil of the transformer, and the synchronous rectification MOS transistor being turned on and off based on the drain voltage of the synchronous rectification MOS transistor. A switching power supply device comprising a secondary side control circuit for controlling,
The switching device further comprises a minimum on-time setting circuit for setting a minimum on-time when the synchronous rectification MOS transistor is turned on based on the peak period and the bottom period detected by the secondary side control circuit. Power supply. The secondary side control circuit,
a peak period detection circuit for detecting a peak period of the drain voltage of the synchronous rectification MOS transistor;
a bottom period detection circuit for detecting the bottom period of the drain voltage of the synchronous rectification MOS transistor,
The minimum on-time setting circuit sets a minimum on-time when the synchronous rectification MOS transistor is turned on based on the peak period detected by the peak period detection circuit and the bottom period detected by the bottom period detection circuit. 2. The switching power supply device according to claim 1, wherein: The minimum on-time setting circuit is
a minimum on-time setting reference voltage generation circuit that generates a setting reference voltage corresponding to the detected peak period and the detected bottom period;
an adjustment signal generation circuit that generates an adjustment signal according to the detected ratio of the peak period and the bottom period;
a minimum on-time signal generation circuit for generating a minimum on-time signal corresponding to the minimum on-time according to the reference voltage generated by the minimum on-time setting reference voltage generation circuit and the adjustment signal generated by the adjustment signal generation circuit; ,
The switching power supply device according to claim 1 or 2, characterized by comprising: The minimum on-time setting reference voltage generation circuit, the adjustment signal generation circuit, and the minimum on-time signal generation circuit each generate a setting reference voltage, an adjustment signal, and a minimum on-time signal for each switching cycle of the synchronous rectification MOS transistor. 4. The switching power supply of claim 3, wherein the switching power supply is configured to generate a The adjustment signal generation circuit generates the adjustment signal when the detected ratio between the peak period and the bottom period is equal to or greater than a predetermined value, and the minimum ON time signal generation circuit receives the adjustment signal and the minimum ON time 5. The switching power supply according to claim 3, wherein the switching power supply is configured to generate a minimum on-time signal adjusted to shorten the time. A sample-and-hold circuit that captures and holds the reference voltage for each switching cycle, and a voltage difference determination circuit that determines a difference from the reference voltage one cycle before, wherein the difference from the reference voltage one cycle before is greater than a predetermined value. 6. The switching power supply device according to claim 5, wherein said minimum on-time signal generating circuit is configured to generate an adjusted minimum on-time signal in a direction of shortening said minimum on-time when said minimum on-time is longer. a gate driver circuit comprising a source-side switch and a sink-side switch and generating a gate drive voltage for controlling on/off of the synchronous rectification MOS transistor;
an off-timing detection circuit for detecting a timing for turning off the synchronous rectification MOS transistor based on the drain voltage of the synchronous rectification MOS transistor;
an on-timing detection circuit that detects timing to turn on the synchronous rectification MOS transistor based on the drain voltage;
an on/off control circuit for generating a control signal for on/off controlling the synchronous rectification MOS transistor based on the detection signal of the off-timing detection circuit, the detection signal of the on-timing detection circuit, and the minimum on-time signal; with
6. The on/off control circuit is configured to turn off the source-side switch of the gate driver circuit as the minimum on-time indicated by the minimum on-time signal elapses. The switching power supply device according to any one of 1.

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