JP7216614B2 - self-diagnostic circuit - Google Patents

Description

The inventions disclosed herein relate, for example, to monitoring devices (especially self-diagnostic circuits used therein).

2. Description of the Related Art In recent years, monitoring devices (so-called monitoring ICs) that monitor various voltages, clock signals, and the like and detect abnormalities thereof have been used in various applications.

As an example of conventional technology related to the above, Patent Document 1 can be cited.

WO2013/084277

However, in the conventional monitoring device described above, there is room for further improvement in terms of failure detection accuracy of the self-diagnostic circuit that checks its own certainty.

In recent years, in particular, in-vehicle ICs are required to comply with ISO26262 (an international standard for functional safety related to electrical and electronic components of automobiles). Reliability design is important.

SUMMARY OF THE INVENTION The invention disclosed in the present specification aims to provide a self-diagnostic circuit with high failure detection accuracy and a monitoring device using the same, in view of the above-described problems found by the inventors of the present application.

A self-diagnostic circuit disclosed herein includes a switch connected between an inverting input terminal and an output terminal of a differential input stage to be diagnosed, and a switch connected to the differential input terminal when the switch is turned on. an A/D converter for converting a node voltage appearing at the output end of the dynamic input stage into measured value data; a storage unit for storing predetermined reference value data in a non-volatile manner; and the measured value data and the reference value data. and a failure detection unit that compares and determines whether the differential input stage is normal (first configuration).

In the self-diagnostic circuit having the first configuration, the reference value data is the initial value of the measured value data acquired before diagnosing the differential input stage (second configuration). good.

In the self-diagnostic circuit having the second configuration, a configuration (third configuration) in which a predetermined reference voltage is applied to the non-inverting input terminal of the differential input stage when diagnosing the differential input stage. do it.

Further, in the self-diagnostic circuit having any one of the first to third configurations, the fault detection unit detects the differential input stage if the difference between the measured value data and the reference value data is within an allowable range. is determined to be normal (fourth configuration).

Further, in the self-diagnostic circuit having any one of the first to fourth configurations, the failure detection unit is configured to output a deviation value between the measured value data and the reference value data (fifth configuration). good.

Further, the monitoring device disclosed in this specification comprises a comparator for comparing a voltage to be monitored and a predetermined threshold voltage, and any one of the first to fifth configurations above, and checks the likelihood of the comparator. and a self-diagnostic circuit (sixth configuration).

In the monitoring device having the sixth configuration, the self-diagnostic circuit preferably has a configuration (seventh configuration) for individually diagnosing the differential input stage and the output stage of the comparator.

In the monitoring device having the seventh configuration, the self-diagnostic circuit inputs a predetermined test input voltage to the differential input stage and determines an expected value of the output signal output from the output stage. (eighth configuration) for diagnosing the output stage.

Further, the electronic equipment disclosed in this specification has a configuration (ninth configuration) having a monitoring device having any one of the sixth to eighth configurations.

Further, the vehicle disclosed in this specification has a configuration (tenth configuration) having the electronic device having the above ninth configuration.

ADVANTAGE OF THE INVENTION According to the invention disclosed in this specification, it becomes possible to provide a self-diagnostic circuit with high failure detection accuracy and a monitoring device using the same.

Diagram showing the overall configuration of an electronic device Diagram showing the package appearance of the monitoring IC Diagram showing pin arrangement of monitoring IC The figure which shows 1st Embodiment of monitoring IC A diagram showing a configuration example of a test circuit A diagram showing an example of diagnostic operation in the first embodiment. The figure which shows 2nd Embodiment of monitoring IC A diagram showing an example of diagnostic operation in the second embodiment. Diagram showing improvement in fault detection accuracy External view of vehicle

<Electronic equipment>
FIG. 1 is a diagram showing the overall configuration of an electronic device. The electronic device 1 of this configuration example has a monitoring IC 100 , a power management IC 200 , and a microcomputer 300 . The electronic device 1 also includes resistors R1 to R10 and R12 to R16 and capacitors C1 and C2 as discrete components externally attached to the semiconductor devices 100 to 300 described above.

The monitoring IC 100 is a semiconductor integrated circuit device that operates by receiving supply of the power supply voltage VDD (=output voltage VO1) from the power management IC 200. The monitoring IC 100 monitors various output voltages of the power management IC 200 and the output frequency of the microcomputer 300 and monitors them. anomaly detection. The monitor IC 100 has a plurality of external terminals (VDD pin, GND pin, CT pin, MISO pin, MOSI pin, SCLK pin, XSCS pin, WDIN pin, DIN1 ∼ DIN4 pins, PG1 to PG4 pins, XRSTIN pin, and XRSTOUT pin).

The power management IC 200 is a semiconductor integrated circuit device that operates by receiving the supply of the battery voltage VBAT, generates a plurality of output voltages VO1 to VO5, and supplies them to each part of the electronic device 1. FIG. It is also possible to use a plurality of single-output DC/DC converters or LDO [low drop-out] regulators instead of the multi-output power management IC 200 .

The microcomputer 300 is a semiconductor integrated circuit device that operates by receiving a power supply voltage VDD (=output voltage VO1) from the power management IC 200, and controls the overall operation of the electronic device 1 including the monitoring IC 100 and the power management IC 200. do.

The microcomputer 300 is reset by a reset output signal XRSTOUT input from the monitoring IC 100. FIG. More specifically, the microcomputer 300 is in a reset state (=disabled state) when the reset output signal XRSTOUT is at low level, and is in a reset release state (=enabled state) when the reset output signal XRSTOUT is at high level. ).

In addition, the microcomputer 300 determines whether the output voltage VOx of the power management IC 200 is normal according to the logic level of the power good signal PGx (where x=1, 2, 3, and 4; the same applies hereinafter) input from the monitoring IC 100. It has a function to determine whether or not More specifically, the microcomputer 300 determines that the output voltage VOx is normal when the power good signal PGx is at high level, and determines that the output voltage VOx is abnormal (when the power good signal PGx is at low level). For example, it is determined that there is an overvoltage abnormality or a low voltage abnormality).

The microcomputer 300 also has a function of outputting a watchdog input signal WDIN (=reset pulse signal of several tens of Hz) to the WDIN pin of the monitoring IC 100 .

The monitoring IC 100 and the microcomputer 300 each have a function of performing bidirectional communication via an SPI (serial peripheral interface) bus, with the microcomputer 300 as a master and the monitoring IC 100 as a slave. For example, the microcomputer 300 has a function of controlling the oscillation frequency of the oscillator and enabling control of the watchdog timer by register control of the monitoring IC 100 by SPI communication. In addition, the microcomputer 300 also has a function of determining whether the set value to which the microcomputer 300 has instructed to write matches the stored value read from the monitoring IC 100 for the watchdog enable register.

The resistors R1 and R2 are connected in series between the output terminal of the output voltage VO1 and the ground terminal, and function as a voltage dividing circuit for the output voltage VO1. A connection node between the resistors R1 and R2 (=the output terminal of the voltage dividing circuit) is connected to the XRSTIN pin of the monitoring IC 100. FIG.

The resistors R3 and R4 are connected in series between the output terminal of the output voltage VO2 and the ground terminal, and function as a voltage dividing circuit for the output voltage VO2. A connection node between the resistors R3 and R4 (=the output terminal of the voltage dividing circuit) is connected to the DIN1 pin of the monitoring IC 100. FIG.

The resistors R5 and R6 are connected in series between the output terminal of the output voltage VO3 and the ground terminal, and function as a voltage dividing circuit for the output voltage VO3. A connection node between the resistors R5 and R6 (=the output terminal of the voltage dividing circuit) is connected to the DIN2 pin of the monitor IC100.

The resistors R7 and R8 are connected in series between the output terminal of the output voltage VO4 and the ground terminal, and function as a voltage dividing circuit for the output voltage VO4. A connection node between the resistors R7 and R8 (=the output terminal of the voltage dividing circuit) is connected to the DIN3 pin of the monitor IC100.

The resistors R9 and R10 are connected in series between the output terminal of the output voltage VO5 and the ground terminal, and function as a voltage dividing circuit for the output voltage VO5. A connection node between the resistors R9 and R10 (=the output end of the voltage dividing circuit) is connected to the DIN4 pin of the monitor IC100.

The resistor R12 is connected between the XRSTOUT pin of the monitoring IC 100 and the power supply terminal, and functions as a pull-up resistor for pulling up the reset output signal XRSTOUT from the monitoring IC 100 to the microcomputer 300 to the power supply voltage VDD.

The resistor R13 is connected between the PG1 pin of the monitoring IC 100 and the power supply terminal, and functions as a pull-up resistor for pulling up the power good signal PG1 from the monitoring IC 100 to the microcomputer 300 to the power supply voltage VDD.

The resistor R14 is connected between the PG2 pin of the monitoring IC 100 and the power supply terminal, and functions as a pull-up resistor for pulling up the power good signal PG2 from the monitoring IC 100 to the microcomputer 300 to the power supply voltage VDD.

The resistor R15 is connected between the PG3 pin of the monitoring IC 100 and the power supply terminal, and functions as a pull-up resistor for pulling up the power good signal PG3 from the monitoring IC 100 to the microcomputer 300 to the power supply voltage VDD.

The resistor R16 is connected between the PG4 pin of the monitoring IC 100 and the power supply terminal, and functions as a pull-up resistor for pulling up the power good signal PG4 from the monitoring IC 100 to the microcomputer 300 to the power supply voltage VDD.

The capacitor C1 is connected between the VDD pin of the monitoring IC 100 and the ground terminal, and functions as smoothing means for the output voltage VO1 (=power supply voltage VDD).

Capacitor C2 is connected between the CT pin of monitor IC 100 and ground, and functions as a reset time setting element.

<Monitoring IC (package)>
FIG. 2 is a diagram showing the package appearance (top surface and bottom surface) of the monitoring IC 100. As shown in FIG. As shown in this figure, as a package of the monitoring IC 100, for example, a VQFN [very thin quad flat non-leaded] package may be adopted.

More specifically, the monitoring IC 100 has a resin sealing body 101 that is rectangular in plan view, and on the bottom surface of which does not protrude from the resin sealing body 101, a total of 20 lines, five on each side. External terminals 102 are exposed. With such a leadless VQFN package, it is possible to reduce the mounting area compared to a package with leads (such as a QFP [quad flat package]).

The resin sealing body 101 is tapered from the side surface to the bottom surface so that the bottom surface is slightly smaller than the top surface. Also, the external terminals 102 are exposed from the bottom surface to the side surface of the resin sealing body 101 . With such a configuration, mounting work on a printed wiring board (not shown) can be carried out easily and reliably.

Also, on the bottom surface of the resin sealing body 101, the rear surface (=the rear side of the chip mounting surface) of the island 103 on which the semiconductor chip (not shown) of the monitoring IC 100 is mounted is exposed as a heat dissipation pad. With such a configuration, it is possible to improve the heat dissipation of the monitoring IC 100 .

At least one of the four corners of the island 103 is preferably provided with a notch portion 103a (=a thin portion recessed from the bottom surface side of the resin sealing body 101 toward the top surface side). Since the material of the resin sealing body 101 enters into the notch portion 103a, the island 103 is sandwiched between the resin sealing body 101 from both upper and lower sides in the formation region of the notch portion 103a. With such a configuration, it is possible to improve the adhesion with the resin sealing body 101 and prevent the island 103 from coming off.

<Monitoring IC (pin arrangement)>
FIG. 3 is a diagram showing the pin arrangement of the monitoring IC 100 (when a 20-pin VQFN is used). On the first side (bottom side of the figure) of the monitor IC 100, five external terminals (pins 1 to 5) are arranged in order from left to right in the figure. 1 pin is a power supply terminal (VDD pin). 2 pin is an unused terminal (NC [non-connection] pin). 3 pin is a ground terminal (GND pin). 4 pin is an unused terminal (NC pin). Pin 5 is a reset time setting terminal (CT pin).

Five external terminals (pins 6 to 10) are arranged in order from bottom to top in the figure on the second side (right side in the figure) of the monitoring IC 100 . 6 pin is an SPI data output terminal (MIMO pin). A 7 pin is an SPI data input terminal (MOSI pin). Pin 8 is an SPI clock terminal (SCLK pin). Pin 9 is an SPI chip select terminal (XSCS pin). Pin 10 is a watchdog input terminal (WDIN pin).

Five external terminals (pins 11 to 15) are arranged in order from right to left in the figure on the third side (upper side in the figure) of the monitoring IC 100 . The 11th pin is the first monitoring input terminal (DIN1 pin). A 12th pin is a first power good output terminal (PG1 pin). A 13th pin is a second monitoring input terminal (DIN2 pin). A 14th pin is a second power good output terminal (PG2 pin). A 15th pin is a third monitoring input terminal (DIN3 pin).

Five external terminals (pins 16 to 20) are arranged in order from top to bottom in the figure on the fourth side (left side in the figure) of the monitoring IC 100 . A 16th pin is a third power good output terminal (PG3 pin). A 17th pin is a fourth monitoring input terminal (DIN4 pin). The 18th pin is a fourth power good output terminal (PG4 pin). A 19th pin is a reset monitoring input terminal (XRSTIN pin). A 20th pin is a reset output terminal (XRSTOUT pin).

<Monitoring IC (first embodiment)>
FIG. 4 is a diagram showing a first embodiment (basic configuration) of the monitoring IC 100. As shown in FIG. The monitoring IC 100 of this embodiment includes a reference voltage generation unit 111, a sub-reference voltage generation unit 112, a reference voltage detection unit 120, a UVLO [under voltage locked-out] unit 130, and threshold voltage generation units 140 to 149. , comparators 150 to 159, oscillators 161 and 162, a digital processing unit 170, N-channel MOS [metal oxide semiconductor] field effect transistors 180 to 184, and an SPI interface 190 are integrated.

The reference voltage generator 111 generates a predetermined reference voltage VREF from the power supply voltage VDD input to the VDD pin.

The sub-reference voltage generator 112 generates a predetermined sub-reference voltage VREF2 from the power supply voltage VDD.

The reference voltage detection unit 120 operates by receiving the supply of the power supply voltage VDD, detects whether the reference voltage VREF and the sub-reference voltage VREF2 rise normally, and generates the reference voltage detection signal VREF_DET. The reference voltage detection signal VREF_DET becomes low level when both the reference voltage VREF and the sub-reference voltage VREF2 rise normally, and becomes high level when at least one of them does not rise normally. A BIST [built-in self test] enable signal BIST_EN is input to the reference voltage detection unit 120 . That is, the reference voltage detection unit 120 corresponds to a monitoring unit (or one of a plurality of monitoring mechanisms included therein) that is subject to self-diagnosis when the monitoring IC 100 is activated.

The UVLO unit 130 detects a low voltage abnormality of the power supply voltage VDD and outputs a low voltage abnormality signal UVLO. The low voltage abnormality signal UVLO becomes high level when the power supply voltage VDD becomes higher than the low voltage abnormality release value UVLO_OFF, and becomes low level when the power supply voltage VDD becomes lower than the low voltage abnormality detection value UVLO_ON.

Threshold voltage generators 140 and 141 divide the reference voltage VREF to generate an upper threshold voltage Vth0H (eg, 0.88 V) and a lower threshold voltage Vth0L (eg, 0.72 V).

The threshold voltage generators 142 and 143 divide the reference voltage VREF to generate an upper threshold voltage Vth1H (eg, 0.88 V) and a lower threshold voltage Vth1L (eg, 0.72 V).

The threshold voltage generators 144 and 145 divide the reference voltage VREF to generate an upper threshold voltage Vth2H (eg, 0.88 V) and a lower threshold voltage Vth2L (eg, 0.72 V).

The threshold voltage generators 146 and 147 divide the reference voltage VREF to generate an upper threshold voltage Vth3H (eg, 0.88 V) and a lower threshold voltage Vth3L (eg, 0.72 V).

The threshold voltage generators 148 and 149 divide the reference voltage VREF to generate an upper threshold voltage Vth4H (eg, 0.88 V) and a lower threshold voltage Vth4L (eg, 0.72 V).

The comparator 150 receives the supply of the power supply voltage VDD and operates. The input voltage V0 input from the XRSTIN pin to the non-inverting input terminal (+) and the input voltage V0 from the threshold voltage generator 140 to the inverting input terminal (-) are input to the comparator 150. A comparison signal RSTOVD is generated by comparing with the upper threshold voltage Vth0H. The comparison signal RSTOVD becomes high level when V0>Vth0H, and becomes low level when V0<Vth0H.

The comparator 151 receives the supply of the power supply voltage VDD and operates, and receives the input voltage V0 input to the inverting input terminal (-) from the XRSTIN pin and the non-inverting input terminal (-) from the threshold voltage generator 141. A comparison signal RSTUVD is generated by comparing with the lower threshold voltage Vth0L. The comparison signal RSTUVD becomes low level when V0>Vth0L, and becomes high level when V0<Vth0L.

The comparator 152 receives the supply of the power supply voltage VDD and operates, and receives the input voltage V1 input from the DIN1 pin to the non-inverting input terminal (+) and the input voltage V1 from the threshold voltage generator 142 to the inverting input terminal (-). A comparison signal DIN1OVD is generated by comparing with the upper threshold voltage Vth1H. The comparison signal DIN1OVD becomes high level when V1>Vth1H, and becomes low level when V1<Vth1H.

The comparator 153 operates by receiving supply of the power supply voltage VDD, and receives the input voltage V1 input to the inverting input terminal (-) from the DIN1 pin and the non-inverting input terminal (-) from the threshold voltage generator 143. A comparison signal DIN1UVD is generated by comparing with the lower threshold voltage Vth1L. The comparison signal DIN1UVD becomes low level when V1>Vth1L, and becomes high level when V1<Vth1L.

The comparator 154 receives the supply of the power supply voltage VDD and operates, and receives the input voltage V2 input from the DIN2 pin to the non-inverting input terminal (+) and the input voltage V2 from the threshold voltage generator 144 to the inverting input terminal (-). A comparison signal DIN2OVD is generated by comparing with the upper threshold voltage Vth2H. The comparison signal DIN2OVD becomes high level when V2>Vth2H, and becomes low level when V2<Vth2H.

The comparator 155 receives supply of the power supply voltage VDD and operates, and receives the input voltage V2 input to the inverting input terminal (-) from the DIN2 pin and the non-inverting input terminal (-) from the threshold voltage generator 145. A comparison signal DIN2UVD is generated by comparing with the lower threshold voltage Vth2L. The comparison signal DIN2UVD becomes low level when V2>Vth2L, and becomes high level when V2<Vth2L.

The comparator 156 receives the supply of the power supply voltage VDD and operates, and the input voltage V3 input from the DIN3 pin to the non-inverting input terminal (+) and the input voltage V3 from the threshold voltage generator 146 to the inverting input terminal (-). A comparison signal DIN3OVD is generated by comparing with the upper threshold voltage Vth3H. The comparison signal DIN3OVD becomes high level when V3>Vth3H, and becomes low level when V3<Vth3H.

The comparator 157 receives the supply of the power supply voltage VDD and operates, and receives the input voltage V3 input to the inverting input terminal (-) from the DIN3 pin and the non-inverting input terminal (-) from the threshold voltage generator 147. A comparison signal DIN3UVD is generated by comparing with the lower threshold voltage Vth3L. The comparison signal DIN3UVD becomes low level when V3>Vth3L, and becomes high level when V3<Vth3L.

The comparator 158 receives supply of the power supply voltage VDD and operates, and receives the input voltage V4 input from the DIN4 pin to the non-inverting input terminal (+) and the input voltage V4 input from the threshold voltage generator 148 to the inverting input terminal (-). A comparison signal DIN4OVD is generated by comparing with the upper threshold voltage Vth4H. The comparison signal DIN4OVD becomes high level when V4>Vth4H, and becomes low level when V4<Vth4H.

The comparator 159 operates by receiving the power supply voltage VDD, and receives the input voltage V4 input from the DIN4 pin to the inverting input terminal (-) and the input voltage V4 from the threshold voltage generator 149 to the non-inverting input terminal (-). A comparison signal DIN4UVD is generated by comparing with the lower threshold voltage Vth4L. The comparison signal DIN4UVD becomes low level when V4>Vth4L, and becomes high level when V4<Vth4L.

A BIST enable signal BIST_EN is input to each of the comparators 151 to 159 described above. That is, each of the comparators 151 to 159 corresponds to a monitoring section (or one of a plurality of monitoring mechanisms included therein) that is subject to self-diagnosis when the monitoring IC 100 is activated.

The oscillator 161 operates by receiving supply of the power supply voltage VDD and the reference voltage VREF, and generates a clock signal CLK1 having an oscillation frequency f1 (for example, f1=2.2 MHz) used in the digital processing section 170 .

The oscillator 162 operates with the supply of the power supply voltage VDD and the reference voltage VREF, and generates a clock signal CLK2 with an oscillation frequency f2 (for example, f2=500 kHz) used by the digital processing unit 170 (especially the watchdog timer 173). Note that the oscillation frequency f2 of the clock signal CLK2 can be arbitrarily adjusted by SPI communication.

Also, the oscillators 161 and 162 are reset by the low voltage fault signal UVLO. More specifically, the oscillators 161 and 162 are reset (=disabled) when the low voltage error signal UVLO is at low level, and are reset when the low voltage error signal UVLO is at high level. It will be in a released state (=enable state).

The digital processing unit 170 operates by being supplied with the power supply voltage VDD, and performs monitoring processing of various input signals and generation processing of various output signals. Also, the digital processing unit 170 is reset by the low voltage abnormality signal UVLO. More specifically, the digital processing unit 170 is in a reset state (=disabled state) when the low voltage abnormality signal UVLO is at low level, and is in a reset release state when the low voltage abnormality signal UVLO is at high level. (=enable state). The internal configuration and operation of the digital processing unit 170 will be described later.

The transistor 180 is connected between the XRSTOUT pin (=the output terminal of the reset output signal XRSTOUT) and the ground terminal, and is turned on/off according to the gate signal G0 input from the digital processing section 170 . The reset output signal XRSTOUT is at low level (=logic level at reset) when the transistor 181 is on, and at high level (=logic level at reset cancellation) when the transistor 181 is off.

The transistor 181 is connected between the PG1 pin (=the output terminal of the power good signal PG1) and the ground terminal, and is turned on/off according to the gate signal G1 input from the digital processing section 170 . The power good signal PG1 is low level (=abnormal logic level) when the transistor 181 is on, and is high level (=normal logic level) when the transistor 181 is off.

The transistor 182 is connected between the PG2 pin (=the output terminal of the power good signal PG2) and the ground terminal, and is turned on/off according to the gate signal G2 input from the digital processing section 170. FIG. The power good signal PG2 is low level (=abnormal logic level) when the transistor 182 is on, and is high level (=normal logic level) when the transistor 182 is off.

The transistor 183 is connected between the PG3 pin (=the output terminal of the power good signal PG3) and the ground terminal, and is turned on/off according to the gate signal G3 input from the digital processing section 170. FIG. The power good signal PG3 is low level (=abnormal logic level) when the transistor 183 is on, and is high level (=normal logic level) when the transistor 183 is off.

The transistor 184 is connected between the PG4 pin (=the output terminal of the power good signal PG4) and the ground terminal, and is turned on/off according to the gate signal G4 input from the digital processing section 170. FIG. The power good signal PG4 is low level (=abnormal logic level) when the transistor 184 is on, and is high level (=normal logic level) when the transistor 184 is off.

The SPI interface 190 is connected to the XSCS pin, the SCLK pin, the MOSI pin, and the MISO pin, and performs bidirectional communication between the monitor IC 100 (especially the digital processing unit 170) and the microcomputer 300 via the SPI bus. conduct.

<Digital processing section>
Next, the internal configuration of the digital processing section 170 will be described with reference to FIG. The digital processing unit 170 of this configuration example includes a self-diagnosis unit 171, a clock detection unit 172, a watchdog timer 173, filters FLT0 to FLT4, counters CNT0 to CNT4, OR gates OR0 to OR4 and OR10 to OR14. and including.

The self-diagnosis unit 171 checks the reference voltage detection signal VREF_DET and the comparison signals (RSTOVD, RSTUVD, DINxOVD, DINxUVD) when the monitoring IC 100 is activated, so that the reference voltage detection unit 120 and the comparators 150 to 159 are normal. A self-diagnostic operation (hereinafter abbreviated as BIST) is performed to determine whether the system is functioning correctly, and a BIST error signal BIST_ERROR is generated. Note that the BIST error signal BIST_ERROR becomes high level when an abnormality is detected in either the reference voltage detection unit 120 or the comparators 150 to 159 .

Self-diagnosis section 171 also generates a BIST enable signal BIST_EN and sends it to reference voltage detection section 120 and comparators 150 to 159, respectively. Note that the BIST enable signal BIST_EN becomes high level during execution of the BIST.

The clock detector 172 detects frequency anomalies of the clock signals CLK1 and CLK2 and generates a clock detection signal CLK_DET. The clock detection signal CLK_DET becomes high level when the frequency abnormality of the clock signal CLK1 or CLK2 is detected.

The watchdog timer 173 detects frequency anomalies (SLOW anomaly and FAST anomaly) of the microcomputer 300 and generates a watchdog detection signal WDT_DET. The watchdog detection signal WDT_DET becomes high level when the frequency abnormality of the microcomputer 30 is detected. Note that the WDIN pin is pulled down inside the monitoring IC 100 .

OR gate OR0 performs a logical sum operation of comparison signals RSTOVD and RSTUVD. Therefore, the output signal of the OR gate OR0 becomes high level when at least one of the comparison signals RSTOVD and RSTUVD is high level, and becomes low level when both the comparison signals RSTOVD and RSTUVD are low level.

OR gate OR1 performs a logical sum operation of comparison signals DIN1OVD and DIN1UVD. Therefore, the output signal of the OR gate OR1 becomes high level when at least one of the comparison signals DIN1OVD and DIN1UVD is high level, and becomes low level when both the comparison signals DIN1OVD and DIN1UVD are low level.

OR gate OR2 performs a logical sum operation of comparison signals DIN2OVD and DIN2UVD. Therefore, the output signal of the OR gate OR2 becomes high level when at least one of the comparison signals DIN2OVD and DIN2UVD is high level, and becomes low level when both the comparison signals DIN2OVD and DIN2UVD are low level.

OR gate OR3 performs a logical sum operation of comparison signals DIN3OVD and DIN3UVD. Therefore, the output signal of the OR gate OR3 becomes high level when at least one of the comparison signals DIN3OVD and DIN3UVD is high level, and becomes low level when both the comparison signals DIN3OVD and DIN3UVD are low level.

A logical sum gate OR4 performs a logical sum operation of the comparison signals DIN4OVD and DIN4UVD. Therefore, the output signal of the OR gate OR4 becomes high level when at least one of the comparison signals DIN4OVD and DIN4UVD is high level, and becomes low level when both the comparison signals DIN4OVD and DIN4UVD are low level.

Filters FLT0-FLT4 perform predetermined filtering processing on the output signals of OR gates OR0-OR4, respectively, and output the filtered signals to subsequent stages. However, the filters FLT0 to FLT4 are not essential components, and if there is no concern about noise, etc., the filters FLT0 to FLT4 may be omitted and the output signals of the OR gates OR0 to OR4 may be passed through to the subsequent stage. .

The counters CNT0 to CNT4 perform predetermined counter processing on the output signals of the filters FLT0 to FLT4, respectively, and output the results to subsequent stages. The output signal of the counter CNT0 is output to the OR gate OR10 as the reset input detection signal RSTIN_DET. However, the counters CNT0 to CNT4 are not essential components, and if there is no concern about noise, etc., the counters CNT0 to CNT4 can be omitted and the output signals of the OR gates OR0 to OR4 (or the outputs of the filters FLT0 to FLT4) signal) may be passed through to the subsequent stage.

The OR gate OR10 outputs the reset output detection signal RSTOUT_DET by ORing the reference voltage detection signal VREF_DET, the reset input detection signal RSTIN_DET, the BIST error signal BIST_ERROR, the watchdog detection signal WDT_DET, and the clock detection signal CLK_DET. Generate. Therefore, the reset output detection signal RSTOUT_DET becomes high level when any one of the plurality of input signals is high level, and becomes low level when all of them are low level. Note that the reset output detection signal RSTOUT_DET is output to the gate of the transistor 180 as the aforementioned gate signal G0.

OR gates OR11 to OR14 generate power good detection signals PG1_DET to PG4_DET by ORing output signals of counters CNT1 to CNT4 and reference voltage detection signal VREF_DET, respectively. Therefore, when the reference voltage detection signal VREF_DET is at low level, the output signals of the counters CNT1 to CNT4 are directly output as the power good detection signals PG1_DET to PG4_DET. On the other hand, when the reference voltage detection signal VREF_DET is at high level, the power good detection signals PG1_DET to PG4_DET are all fixed at high level regardless of the output signals of the counters CNT1 to CNT4. The power good detection signals PG1_DET to PG4_DET are output to the gates of the transistors 181 to 184 as the aforementioned gate signals G1 to G4.

<Self-diagnosis function>
Next, the self-diagnosis function of the monitor IC 100 will be described in detail. FIG. 5 is a circuit diagram showing a configuration example of a test circuit introduced into a monitoring unit to be self-diagnosed. As shown in the figure, the monitor IC 100 incorporates a plurality of test circuits (T1, T2, T10 to T14) as means for implementing the BIST described above.

The test circuits T1 and T2 are attached to the reference voltage detector 120. FIG. More specifically, the reference voltage detection section 120 includes divided voltage generation sections 121 and 122 and comparators 123 and 124, and the test circuits T1 and T2 are connected to the divided voltage generation sections 121 and 122, respectively. It is connected to the.

The divided voltage generator 121 generates divided voltages Vd1H and Vd1L (Vd1H>Vd1L) from the reference voltage VREF.

The divided voltage generator 122 generates divided voltages Vd2H and Vd2L (Vd2H>Vd2L) from the sub-reference voltage VREF2.

The comparator 123 compares the divided voltage Vd2H input to the non-inverting input terminal (+) and the divided voltage Vd1L input to the inverting input terminal (-) to generate a comparison signal VRDET1. The comparison signal VRDET1 becomes high level when Vd2H>Vd1L, and becomes low level when Vd2H<Vd1L.

The comparator 124 compares the divided voltage Vd1H input to the non-inverting input terminal (+) and the divided voltage Vd2L input to the inverting input terminal (-) to generate a comparison signal VRDET2. The comparison signal VRDET2 becomes high level when Vd1H>Vd2L, and becomes low level when Vd1H<Vd2L.

The test circuit T1 is connected to the middle point node A of the divided voltage generator 121 (=the middle node sandwiched between the output terminals of the divided voltages Vd1H and Vd1L). The voltage value of point node A is switched. Specifically, the test circuit T1 opens the midpoint node A when VRDET1SW=L, and shorts the midpoint node A to the ground when VRDET1SW=H.

The test circuit T2 is connected to the middle point node B of the divided voltage generator 122 (=the middle node sandwiched between the output terminals of the divided voltages Vd2H and Vd2L). Switch the voltage value of the point node B. Specifically, the test circuit T2 opens the midpoint node B when VRDET2SW=L, and shorts the midpoint node B to ground when VRDET2SW=H.

The test circuit T10 is connected to the input terminal of the input voltage V0, and switches the voltage value of the input voltage V0 in accordance with the control signals RSTSW1 to RSTSW4 (=binary signals that are alternatively set to high level). Specifically, test circuit T10 sets V0=XRSTIN when RSTSW1=H, sets V0=V0H (eg, 1.04 V) when RSTSW2=H, and sets V0= when RSTSW3=H. V0M (0.8V, for example), and V0=V0L (0.56V, for example) when RSTSW4=H. The three test input voltages (V0H, V0M, V0L) are preferably generated by dividing the reference voltage VREF.

The test circuit T11 is connected to the input terminal of the input voltage V1, and switches the voltage value of the input voltage V1 according to the control signals DIN1SW1 to DIN1SW4 (=binary signals that are alternatively set to high level). Specifically, the test circuit T11 sets V1=DIN1 when DIN1SW1=H, sets V1=V1H (eg, 1.04 V) when DIN1SW2=H, and sets V1= when DIN1SW3=H. V1M (0.8 V, for example), and V1=V1L (0.56 V, for example) when DIN1SW4=H. The three test input voltages (V1H, V1M, V1L) are preferably generated by dividing the reference voltage VREF.

The test circuit T12 is connected to the application terminal of the input voltage V2, and switches the voltage value of the input voltage V2 according to the control signals DIN2SW1 to DIN2SW4 (=binary signals that are alternatively set to high level). Specifically, the test circuit T12 sets V2=DIN2 when DIN2SW1=H, sets V2=V2H (eg, 1.04 V) when DIN2SW2=H, and sets V2= when DIN2SW3=H. V2M (0.8V, for example), and V2=V2L (0.56V, for example) when DIN2SW4=H. The three test input voltages (V2H, V2M, V2L) are preferably generated by dividing the reference voltage VREF.

The test circuit T13 is connected to the input terminal of the input voltage V3, and switches the voltage value of the input voltage V3 according to the control signals DIN3SW1 to DIN3SW4 (=binary signals that are alternatively set to high level). Specifically, the test circuit T13 sets V3=DIN3 when DIN3SW1=H, sets V3=V3H (eg, 1.04 V) when DIN3SW2=H, and sets V3= when DIN3SW3=H. V3M (for example, 0.8V) and V3=V3L (for example, 0.56V) when DIN3SW4=H. The three test input voltages (V3H, V3M, V3L) are preferably generated by dividing the reference voltage VREF.

The test circuit T14 is connected to the input terminal of the input voltage V4, and switches the voltage value of the input voltage V4 in accordance with the control signals DIN4SW1 to DIN4SW4 (=binary signals that are alternatively set to high level). Specifically, test circuit T14 sets V4=DIN4 when DIN4SW1=H, sets V4=V4H (eg, 1.04 V) when DIN4SW2=H, and sets V4= when DIN4SW3=H. V4M (for example, 0.8V) and V4=V4L (for example, 0.56V) when DIN4SW4=H. The three test input voltages (V4H, V4M, V4L) are preferably generated by dividing the reference voltage VREF.

<BIST>
FIG. 6 is a timing chart showing an example of BIST (focusing only on the DIN1 pin) in the first embodiment, in which the input voltage V1 and the comparison signals DIN1OVD and DIN1UVD are depicted in order from the top.

As indicated by the upward arrows in the figure, in the BIST of this embodiment, the expected value determination of both the comparison signals DIN1OVD and DIN1UVD is performed each time the voltage value of the input voltage V1 is switched. More specifically, during the input period of the test input voltage V1H, an expected value determination is made as to whether DIN1OVD=H and DIN1UVD=L. =L and DIN1UVD=H. Further, during the input period of the test input voltage V1M, an expected value determination is made as to whether or not DIN1OVD=DIN1UVD=L.

In this figure, the BIST of the monitoring mechanism (comparators 152 and 153) connected to the DIN1 pin is taken as an example, but other external terminals (DIN2 pin, DIN3 pin, DIN4 pin, or XRSTIN pin) are also connected. The BIST similar to the above is sequentially performed for the monitoring mechanism that has been selected.

That is, the self-diagnostic section 171 selects a monitoring mechanism to be diagnosed from among a plurality of monitoring mechanisms (for example, comparators 150 to 159) included in the monitoring section (=comparator for inputting test input voltage V*H or V*L). ), while comparing whether or not the output signal matches the expected value, and also for the monitoring mechanism other than the diagnosis object (=comparator to which the test input voltage V*M is input), each output signal matches the expected value.

In this way, according to the BIST method in which each comparator is targeted for diagnosis one by one and the outputs of all comparators are evaluated at all comparison timings, it is possible to improve the failure detection rate of the monitoring IC 100 .

It should be noted that the BIST described above is preferably performed in the monitoring IC 100 after the power management IC 200 starts powering up and before a predetermined reset cancellation waiting time t1 (for example, 10 ms) elapses. If no abnormality is detected in the monitor IC 100, the monitor operation is promptly started, and the reset of the microcomputer 300 is released when the reset release waiting time t1 has passed. As a result, the operation of the microcomputer 300 is started.

Therefore, BIST can be performed without affecting the operation start timing of the microcomputer 300, so that the electronic device 1 can be started at the same timing as before. Focusing on the monitoring IC 100, it is possible to start the original monitoring operation after self-diagnosing whether it is normal or not, so it is possible to improve the failure detection rate.

Prior to the BIST described above, the digital processing unit 170 should perform a self-test such as a scan path to confirm that it operates normally.

By the way, the monitoring IC 100 of this embodiment performs BIST by controlling the test input voltage of the comparator. and complexity. Therefore, in the following, a second embodiment is proposed, which can perform BIST with high fault detection accuracy without requiring a high-precision test input voltage.

<Monitoring IC (second embodiment)>
FIG. 7 is a diagram showing a second embodiment of the monitoring IC 100. As shown in FIG. The monitor IC 100 of the present embodiment is based on the first embodiment described above, and has a threshold voltage generator 14A and a comparator 15A as means for monitoring the input voltage IN (=monitored voltage). Furthermore, it has a self-diagnostic circuit 1A0 as means for checking the accuracy of the comparator 15A. Note that the input voltage IN corresponds to, for example, the input voltages V0 to V4 described above.

The threshold voltage generator 14A includes resistors R21 and R22 connected in series between the application terminal of the reference voltage VREF and the ground terminal, and the threshold voltage Va (=divided voltage of the reference voltage VREF) is generated from the connection node between them. to output The threshold voltage generator 14A corresponds to, for example, the threshold voltage generators 141, 143, 145, 147 and 149 described above.

The comparator 15A includes a differential input stage 15A1 and an output stage 15A2, and generates an output signal OUT by comparing an input voltage IN and a threshold voltage Va. The output signal OUT becomes low level when IN>Va, and becomes high level when IN<Va. Note that the comparator 15A corresponds to, for example, the comparators 151, 153, 155, 157 and 159 described above.

Differential input stage 15A1 includes current source CS1, N-channel MOS field effect transistors N1 and N2, and P-channel MOS field effect transistors P1 and P2. A first end of the current source CS1 is connected to a power supply end. The second end of current source CS1 is connected to the sources of transistors P1 and P2, respectively. The drain of transistor P1 is connected to the drain of transistor N1. The drain of transistor P2 is connected to the drain of transistor N2. The gates of transistors N1 and N2 are both connected to the drain of transistor N1. The sources of the transistors N1 and N2 are both connected to the ground terminal. The gate of transistor P1 corresponds to the non-inverting input terminal (+) of differential input stage 15A1. The gate of the transistor P2 corresponds to the inverting input terminal (-) of the differential input stage 15A1. A connection node between the drain of the transistor P2 and the drain of the transistor N2 corresponds to the output terminal of the differential input stage 15A1.

Output stage 15A2 includes a current source CS2, an inverter INV, and an N-channel MOS field effect transistor N3. A first end of the current source CS2 is connected to the power supply end. A second end of the current source CS2 is connected to the drain of the transistor N3 and the input end of the inverter INV. The source of transistor N3 is connected to the ground terminal. A gate of the transistor N3 is connected to the output terminal of the differential input terminal 15A1. The output end of the inverter INV corresponds to the output end of the output signal OUT.

The self-diagnostic circuit 1A0 is a functional block for checking the likelihood of the comparator 15A, and separately diagnoses the differential input stage 15A1 and the output stage 15A2 of the comparator 15A. In particular, the self-diagnostic circuit 1A0 includes an A/D [analog-to-digital] converter 1A1, a storage section 1A2, a failure detection section 1A3, switches SW1 and SW2, and so on as means for performing BIST of the differential input stage 15A1. and including.

The switch SW1 is connected between the gate and drain of the transistor P2, that is, between the inverting input terminal (-) and the output terminal of the differential input stage 15A1. The switch SW1 is, for example, turned off during normal operation and turned on during BIST.

The switch SW2 is connected between the gate of the transistor P2 and the application terminal of the input voltage IN. The switch SW2 is, for example, turned on during normal operation and turned off during BIST.

The A/D converter 1A1 converts the analog node voltage Vb appearing at the output end of the differential input stage 15A1 into digital measured value data D1 during BIST of the differential input stage 15A1 (SW1 ON, SW2 OFF). The node voltage Vb should match the reference voltage Va applied to the non-inverting input (+) if the differential input stage 15A1 has not failed.

The storage unit 1A2 nonvolatilely stores predetermined reference value data D0. As the reference value data D0, it is preferable to store the initial value of the actual measurement value data D1 acquired before the BIST of the differential input stage 15A1. Specifically, for example, when the monitoring IC 100 is tested for shipment (SW1 ON, SW2 OFF), the node voltage Vb is actually measured, and the measurement result (=initial value of the measured value data D1) is stored as the reference value data D0. It may be stored in the section 1A2 (see the dashed arrow in the figure). For example, an OTPROM [one time programmable read only memory] can be preferably used as the storage unit 1A2.

The failure detection unit 1A3 compares the measured value data D1 and the reference value data D0 to determine whether the differential input stage 15A1 is normal. Note that the failure detection unit 1A3 may be mounted in the digital processing unit 170 described above, for example.

<BIST (differential input stage)>
FIG. 8 is a flow chart showing an example of a diagnostic operation (in particular, BIST for diagnosing the differential input stage 15A1) in the second embodiment. As a major premise of this flow chart, the monitoring IC 100 is a passing product that has passed the shipping test, and the storage unit 1A2 stores the reference value data D0 (=specs required for the monitoring IC 100) acquired during the shipping test. initial value of the measured value data D1) is stored.

When the BIST of the differential input stage 15A1 is started, the switch SW1 is turned on and the switch SW2 is turned off in step S11. As a result, the inverting input terminal (-) and the output terminal of the differential input stage 15A1 are short-circuited, so that the differential input stage 15A1 functions as a buffer. Therefore, a node voltage Vb (ideally Vb=Va) corresponding to the threshold voltage Va appears at the output terminal of the differential input stage 15A1.

Next, in step S12, the node voltage Vb appearing at the output terminal of the differential input stage 15A1 is acquired as the measured value data D1.

Subsequently, in step S13, the failure detection unit 1A3 determines whether or not the measured value data D1 matches the reference value data D0 (=the initial value of the measured value data D1). In step S13, only when the measured value data D1 completely match the reference value data D0, a yes determination (=a determination that the differential input stage 15A1 is normal) may be made, Alternatively, if the divergence value ΔD (=D1-D0) between the measured value data D1 and the reference value data D0 is within the allowable range, a YES determination may be made.

If a YES determination is made in step S13, the flow proceeds to step S14, and after a determination result (OK flag) indicating that the differential input stage 15A1 is normal is output, a series of the flow ends. be done.

On the other hand, if a NO determination is made in step S13, the flow proceeds to step S15, and after a determination result (NG flag) indicating that the differential input stage 15A1 is not normal is output, a series of flows is performed. is terminated.

Further, although not explicitly shown in this flowchart, the failure detection unit 1A3 may output a divergence value ΔD between the measured value data D1 and the reference value data D1 in response to a request from the microcomputer 300, for example. . With such a configuration, an increase in the divergence value ΔD within the allowable range can be detected to detect a sign of failure in advance.

<BIST (output stage)>
Further, the self-diagnostic circuit 1A0 performs BIST of the output stage 15A2 separately from the BIST of the differential input stage 15A1 described above. Specifically, the self-diagnostic circuit 1A0 inputs a predetermined test input voltage to the differential input stage 15A1 and outputs an output signal from the output stage 15A2, as described with reference to FIGS. BIST of the output stage 15A2 is performed by determining the expected value of OUT.

In the BIST of the output stage 15A2, it is sufficient if it can be confirmed whether the logic level (high level/low level) of the output signal OUT is appropriately switched according to the ON/OFF state of the transistor N3. Therefore, no precision test input voltage is required.

<Failure detection accuracy>
FIG. 9 is a diagram showing improvement in failure detection accuracy in the second embodiment. Note that the left side of the figure schematically depicts the failure detection accuracy of a general BIST (=BIST that diagnoses both the differential input stage and the output stage collectively). On the other hand, on the right side of the figure, the failure detection accuracy of BIST (=BIST for diagnosing the differential input stage and the output stage separately) in the second embodiment is schematically depicted.

In order to detect that there are no failures in the comparator within the required specifications, it is necessary to test the operation of the comparator at the upper and lower limits of the required specifications. However, in general BIST (left side of this figure), not only the detection variation of the comparator ±a% (eg ±1%) but also the variation of the upper limit test input voltage ±b% (eg ±1%) and the lower limit test input voltage has a variation of ±c% (eg ±1%). Therefore, the final spec of the comparator is the detection variation ±d% (for example, 3%) including all of the above.

On the other hand, in the BIST of the second embodiment, the comparator is divided into a differential input stage and an output stage, and the likelihood of each stage is individually diagnosed. In particular, in the BIST of the differential input stage, since it is not necessary to use the test input voltage, the detection variation ±e% (eg 1%) of the comparator and the detection variation ±f% (eg 0.05%) of the A/D converter should be considered only. As a result, the final spec of the comparator is the detection variation ±g% (for example, 1.1%) that takes into account both, so that failure detection accuracy can be improved compared to general BIST.

In the above-described second embodiment, the comparator (for example, the comparators 151 and 153 described above) receives the input voltage IN at the inverting input terminal (-) and receives the threshold voltage Va at the non-inverting input terminal (+). , 155, 157 and 159) were given as diagnostic targets, but conversely, the input voltage IN is input to the non-inverting input terminal (+) and the threshold voltage Va is input to the inverting input terminal (-). When the comparators (for example, the comparators 150, 152, 154, 156 and 158 described above) are to be diagnosed, the input polarity of the comparators may be inverted only when BIST is performed.

Further, the self-diagnostic circuit 1A0 can be used for self-diagnosis of general comparators (furthermore, general differential input stages) used for various purposes.

<Application to vehicles>
FIG. 10 is an external view showing one configuration example of the vehicle X. As shown in FIG. The vehicle X of this configuration example is equipped with various electronic devices (in-vehicle devices) X11 to X18 that operate by being supplied with power from a battery. Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual ones for convenience of illustration.

The electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).

The electronic device X12 is a lamp control unit that controls lighting and extinguishing of HID [high intensity discharged lamps] and DRL [daytime running lamps].

The electronic device X13 is a transmission control unit that performs control related to the transmission.

The electronic device X14 is a braking unit that performs control related to the motion of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

The electronic device X15 is a security control unit that drives and controls door locks, security alarms, and the like.

Electronic device X16 includes wipers, electric door mirrors, power windows, dampers (shock absorbers), electric sunroofs, electric seats, and other electronic devices built into vehicle X at the factory shipment stage as standard equipment or manufacturer options. is.

The electronic device X17 is an electronic device arbitrarily mounted on the vehicle X as a user option, such as an in-vehicle A/V [audio/visual] device, a car navigation system, and an ETC [electronic toll collection system].

The electronic device X18 is an electronic device having a high withstand voltage motor, such as an in-vehicle blower, an oil pump, a water pump, and a battery cooling fan.

Note that the monitoring IC 100 described above can be incorporated in any of the electronic devices X11 to X18.

<Other Modifications>
In the above-described embodiment, a monitoring IC mounted on an on-vehicle device was taken as an example, but the application target is not limited to this, and it is possible to apply it widely to electronic devices in general.

In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is not limited to the above-described embodiments. It is to be understood that a range and equivalents are meant to include all changes that fall within the range.

The invention disclosed in this specification can be used, for example, in general electronic devices that require functional safety (vehicle cameras, radars, infotainment, lamps, clusters, power trains, sensor fusion, etc.). is possible.

1 electronic device 100 monitoring IC (monitoring device)
101 resin sealing body 102 external terminal 103 island (radiating pad)
103a notch 111 reference voltage generator 112 sub-reference voltage generator 120 reference voltage detector 121, 122 divided voltage generator 123, 124 comparator 130 UVLO section 140 to 149, 14A threshold voltage generator 150 to 159, 15A comparator 15A1 Differential input stage 15A2 Output stage 161 Oscillator (for digital processing)
162 oscillator (for watchdog timer)
170 digital processing unit 171 self-diagnosis unit 172 clock detection unit 173 watchdog timer 180 to 184 N-channel MOS field effect transistor 190 SPI interface 1A0 self-diagnosis circuit 1A1 A/D converter 1A2 storage unit (OTP)
1A3 failure detection unit 200 power management IC (power supply device)
300 Microcomputer C1, C2 Capacitor CNT0 to CNT4 Counter CS1, CS2 Current source FLT0 to FLT4 Filter INV Inverter N1 to N3 N-channel MOS field effect transistor OR0 to OR4, OR10 to OR14 OR gate P1, P2 P-channel MOS field effect Transistor R1~R10, R12~R16, R21~R22 Resistor SW1, SW2 Switch T1, T2, T10~T14 Test circuit X Vehicle X11~X18 Electronic equipment

Claims (10)

a switch connected between the inverting input and the output of the differential input stage to be diagnosed;
an A/D converter that converts a node voltage appearing at the output end of the differential input stage when the switch is turned on into measured value data;
a storage unit that stores predetermined reference value data in a non-volatile manner;
a failure detection unit that compares the measured value data and the reference value data to determine whether the differential input stage is normal;
A self-diagnostic circuit, comprising: 2. The self-diagnostic circuit according to claim 1, wherein said reference value data is an initial value of said measured value data acquired before diagnosing said differential input stage. 3. A self-diagnostic circuit according to claim 1, wherein a predetermined reference voltage is applied to the non-inverting input terminal of said differential input stage when diagnosing said differential input stage. 3. The failure detection unit determines that the differential input stage is normal if a deviation value between the measured value data and the reference value data is within an allowable range. A self-diagnostic circuit according to any one of Claims 1 to 3. 5. The self-diagnostic circuit according to claim 1, wherein said failure detection unit outputs a deviation value between said measured value data and said reference value data. a comparator that compares the monitored voltage with a predetermined threshold voltage;
A self-diagnostic circuit according to any one of claims 1 to 5, which checks the likelihood of the comparator,
A monitoring device comprising: 7. The monitoring apparatus according to claim 6, wherein the self-diagnostic circuit individually diagnoses the differential input stage and the output stage of the comparator. The self-diagnosis circuit diagnoses the output stage by inputting a predetermined test input voltage to the differential input stage and determining an expected value of an output signal output from the output stage. Item 8. A monitoring device according to Item 7. An electronic device comprising the monitoring device according to any one of claims 6 to 8. A vehicle comprising the electronic device according to claim 9 .

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