JP7226014B2 - Controller and diagnostic program - Google Patents

Description

The disclosure herein relates to a controller and its diagnostic program.

2. Description of the Related Art It is conventionally known to transfer data between a plurality of memories in a microcontroller by DMA (Direct Memory Access). Microcontrollers are also called microcomputers. Data transfer by DMA is performed within the microcontroller independently of the operation of the CPU, so high-speed data transfer can be realized.

Microcontrollers using DMA are used in various places such as engine control devices and airbag control devices in automobiles and the like. In such devices, it is also conventionally known to accumulate motion information data for a predetermined period in the microcontroller. The accumulated operation information data is used to specify the failure location when some abnormality is detected in the controlled object.

However, when a DMA data transfer delay occurs, an abnormality may be erroneously detected even though an abnormality has not occurred in the control target of the microcontroller. This may be caused by a transfer error such as data that should have been transferred to the memory not being transferred due to DMA data transfer delay.

For example, Patent Document 1 discloses a DMA controller having means for checking whether a transfer error such as a parity error or a response time over has occurred. However, Patent Document 1 does not specifically disclose how to detect a transfer error.

JP-A-8-202635

An object of the present disclosure is to make it possible to quickly determine, when an abnormality is detected in a controlled object, whether it is an erroneous detection caused by a transfer error such as a DMA transfer delay or transfer omission in the controller. .

A first aspect of the present invention is a controller comprising a RAM (13) and a DMA section (12) that controls DMA transfer to the RAM. The RAM stores transfer status data that directly or indirectly represents at least one of the transfer delay time and the number of transfer omissions for DMA transfers performed within a predetermined period. The DMA section performs the DMA transfer at a predetermined cycle. The controller further comprises a counter that is reset after counting a reset period having the same length as the predetermined period. The RAM stores the count value of the counter when the DMA transfer is completed as the delay time of the transfer.

A second aspect of the present invention is a diagnostic program for determining an abnormality in a controlled object of the controller (1). This diagnostic program inputs data read from the ROM of the controller to the processor of the computer when an abnormality is detected in the controlled object based on the sensor data, and compares the transfer status data with a predetermined threshold value. and a step of determining whether or not the abnormality in the controlled object is caused by incomplete sensor data due to DMA transfer.

The multiple aspects disclosed in this specification employ different technical means to achieve their respective objectives. Reference numerals in parentheses described in the claims and this section are intended to exemplify the correspondence with portions of the embodiments described later, and are not intended to limit the technical scope. Objects, features, and advantages disclosed in this specification will become clearer with reference to the following detailed description and accompanying drawings.

FIG. 1 is a block diagram showing a schematic configuration of an engine control system according to one embodiment of the present invention. FIG. 2 is a schematic diagram showing an example of data stored in the RAM and ROM shown in FIG. FIG. 3 is a timing diagram showing the basic operation of DMA transfer. FIG. 4 is a timing chart when delay occurs in DMA transfer. FIG. 5 is a timing chart when transfer omission occurs in DMA transfer. FIG. 6A is a schematic diagram of data stored in the RAM when there is no transfer omission. FIG. 6B is a schematic diagram of data stored in the RAM when transfer omission occurs. FIG. 7 is a flow chart showing the processing flow after the delay measurement period ends. FIG. 8 is a flow chart showing a processing flow when a misfire is detected. FIG. 9 is a flow chart showing the processing flow of the diagnostic tool.

A number of embodiments will be described with reference to the drawings. In several embodiments, functionally and/or structurally corresponding and/or related parts may be labeled with the same reference numerals or reference numerals differing by one hundred or more places. For corresponding and/or associated parts, reference can be made to the description of other embodiments.

As shown in FIG. 1, the controller 1 according to the first embodiment is provided in an engine control device 10. As shown in FIG. The controller 1 is sometimes called a microcomputer, microcontroller, or the like. The engine control device 10 includes an input circuit 2, an output circuit 3, and an external IC 4 in addition to the controller 1. FIG. The engine control device 10 outputs from the output circuit 3 a control signal for controlling the operation of each part of the engine such as the ignition module and the fuel injection module. The input circuit 2 receives sensor signals representing operating conditions of various parts of the engine from sensors of various parts of the engine. Examples of the sensor signal include, but are not limited to, an in-cylinder pressure sensor signal and a knock sensor signal. Based on these sensor signals, the controller 1 controls the operation of each part of the engine depending on the situation. The external IC 4 has other control circuits necessary for engine control.

The controller 1 includes a CPU 11 , a DMA section 12 , a RAM 13 , a ROM 14 , an AD conversion section 15 , a timer section 16 and a communication section 17 . The CPU 11 controls operations of each part of the controller 1 . The DMA unit 12 operates independently of the CPU 11 and controls DMA transfer between memories within the controller 1 . Note that the controller 1 may include other modules not shown in FIG.

The controller 1 may be configured as a single IC, or may have respective units dispersedly arranged in two or more ICs. Each unit included in the controller 1 can be implemented as a hardware circuit.

The controller 1 converts the sensor signal received via the input circuit 2 into digital sensor data by the AD converter 15 and stores it in the RAM 13 . The RAM 13 functions as a buffer and can accumulate sensor data for a certain period of time. The sensor data is read from the RAM 13 and stored in an area of the ROM 14 that can be referred to by a diagnostic tool when an abnormality is detected in each part of the engine. As a result, when an abnormality is detected, the sensor data immediately before (and immediately after) the occurrence of the abnormality can be acquired from the ROM 14 and used for analysis by the diagnostic tool.

The controller 1 also acquires transfer status data representing the status of the DMA transfer within a predetermined period and stores it in the RAM 13 . The transfer status data is data representing whether or not there is a delay or transfer omission in the DMA transfer, and the degree thereof. An example of transfer status data is the delay time from when a DMA transfer request is made to when the transfer is actually performed. Another example of transfer status data is the number of times transfer omissions have occurred within a predetermined period (that is, the number of transfer omissions). A transfer omission means that although a DMA transfer request was made, a DMA transfer was not made in response to the request. The transfer status data is not limited to the delay time and the number of transfer omissions themselves. The transfer status data also includes index data obtained based on the transfer time and the number of transfer omissions. The index data is data that numerically represents the degree of delay or transfer omission. An example of index data is a high load factor. The high load factor is the ratio of the number of DMA transfers executed with delay to the total number of DMA transfers executed within a predetermined period.

The transfer status data is read from the RAM 13 and stored in an area of the ROM 14 that can be referred to by a diagnostic tool when some abnormality is detected in the engine.

Here, an example of data stored in the RAM 13 and ROM 14 will be described with reference to FIG. The RAM 13 has a sensor data buffer 13a for storing sensor data and a delay time buffer 13b for storing delay time of DMA. The RAM 13 further has an error data area 13c for storing the latest error data of the DMA. The sensor data buffer 13a sequentially stores the sensor data obtained by the AD converter 15 . In the sensor data buffer 13a, when there is no free space, the oldest sensor data is overwritten with new sensor data. Also in the delay time buffer 13b, when there is no free space, the oldest DMA transfer delay time is overwritten with a new DMA transfer delay time. In FIG. 2, the sensor data buffer 13a and the delay time buffer 13b each have eight data storage areas, but the number of areas is arbitrary. The abnormal data area 13c has areas for storing the number of transfer omissions, the high load factor, and the DMA data acquisition time.

The ROM 14 has an area 14a for storing the measurement period, an area 14b for storing the initial value of the number of transfers, and an area 14c for storing the failure information data. The measurement cycle defines the reset cycle of the counters (the AD conversion counter 16a and the delay counter 16b) of the timer section 16. FIG. As the transfer count initial value, a value that is not less than the number of transfers that can be executed within the period for measuring the delay of DMA transfer is set. The initial value of the number of transfers is preferably an integer value larger than an integer value obtained by dividing the length of the delay measurement period by the length of the measurement cycle and truncating the fractions. The failure information data predetermines the type of data to be stored in the ROM 14 when an abnormality is detected for each abnormality pattern that can occur in the engine. For example, when a spark plug misfire is detected, data from a sensor related to misfire detection is read from the RAM 13 and stored in the ROM 14 . In FIG. 2, when a misfire is detected, the misfire detection time, the number of DMA transfer omissions, the high load factor, and the DMA data acquisition time are stored in the ROM 14 in addition to these data. Here, the number of DMA transfer omissions, the high load factor, and the DMA data acquisition time are read out from the abnormal data area 13c of the RAM 13 and stored in the ROM 14. FIG. The data in the anomaly data area 13c is not limited to misfire detection, and can be used in the same way when various anomalies are detected.

The timer section 16 incorporates a plurality of independently operating counters. The timer section 16 has at least an AD conversion counter 16a and a delay counter 16b. The AD conversion counter 16 a is a counter for controlling the operation of the AD conversion section 15 . The delay counter 16b is a counter for measuring the delay of DMA transfer. The AD conversion counter 16a and the delay counter 16b increase their counter values according to the same reference clock. Each of the AD conversion counter 16a and the delay counter 16b is reset at regular intervals. The AD conversion counter 16a and the delay counter 16b are compare match timers. The AD conversion counter 16a and the delay counter 16b are reset when the counter value reaches a predetermined value. This predetermined value is the measurement period stored in the area 14 a of the ROM 14 . As this predetermined value, the same value is set in both the AD conversion counter 16a and the delay counter 16b. Therefore, the AD conversion counter 16a and the delay counter 16b have the same reset cycle length. However, the delay counter 16b is delayed from the AD conversion counter 16a by at least the sum of the time required for AD conversion processing by the AD conversion section 15 and the time required for DMA transfer of the AD conversion result by the DMA section 12, and is reset. The phase of each cycle is set to reach the cycle. However, there is no problem even if this phase relationship is slightly shifted back and forth. In this way, the AD conversion counter 16a and the delay counter 16b operate independently, and their reset points do not coincide.

The DMA unit 12 DMA-transfers the data of each unit such as the AD conversion unit 15 to the RAM 13 . For example, DMA transfer from the AD converter 15 to the RAM 13 is performed as follows. The AD converter 15 has a register 15a that stores converted data. When the AD converter 15 receives from the timer 16 the signal indicating the compare match of the AD conversion counter 16 a , the AD converter 15 AD converts the sensor signal received from the input circuit 2 . The sensor signal digitized by AD conversion is stored in the register 15a. When the AD conversion is completed, the AD conversion section 15 sends a conversion completion signal indicating the completion of the AD conversion to the DMA section 12 . This conversion complete signal acts as a DMA transfer request signal. Upon receiving the conversion completion signal, the DMA section 12 reads the data stored in the register 15 a of the AD conversion section 15 and writes it to the RAM 13 . DMA transfer from the AD converter 15 to the RAM 13 is performed by the series of operations described above. Furthermore, when the counter value of the delay counter 16b reaches a predetermined value, the DMA unit 12 receives a DMA transfer request signal of the count value of the delay counter 16b from the delay counter 16b. Then, the DMA unit 12 executes DMA transfer of the counter value of the delay counter 16b on condition that the DMA transfer from the AD conversion unit 15 to the RAM 13 is completed. Specifically, the DMA unit 12 reads the counter value of the delay counter 16 b at the time of starting DMA transfer, and writes it to the RAM 13 . Thus, the DMA unit 12 also performs DMA transfer from the timer unit 16 (delay counter 16b) to the RAM 13. FIG.

The DMA section 12 performs DMA transfer between the RAM 13 and the communication section 17 during communication between the external IC 4 and the RAM 13 . The communication unit 17 includes a transmission register 17a and a reception register 17b. When transmitting data to the external IC 4, the DMA unit 12 reads transmission data from the RAM 13 and writes it to the transmission register 17a of the communication module 17 by DMA transfer. When receiving data from the external IC 4 , the DMA unit 12 reads the data written in the reception register 17 b from the external IC 4 and DMA-transfers it to the RAM 13 .

DMA transfer delay measurement in the controller 1 will now be described with reference to FIGS. 3 to 5. FIG. First, based on FIG. 3, the case where there is no delay in DMA transfer will be described.

The controller 1 starts measuring the DMA transfer delay at a predetermined timing. The start time and end time of the delay measurement period can be set individually and arbitrarily. For example, the delay measurement may begin when the ignition of the automobile is turned on. Alternatively, delay measurement may be started in synchronization with the start of a specific event. Alternatively, the delay measurement may end when the vehicle ignition is turned off. Alternatively, delay measurement may end in synchronization with the end of a specific event. In consideration of the processing load on the controller 1, etc., it is preferable that the delay measurement period is intermittently and repeatedly set according to the combustion process of the engine.

The uppermost part of FIG. 3 shows changes in the counter value of the AD conversion counter 16a. In FIG. 3 and other drawings, the counter value is shown to increase continuously for simplification of illustration, but the actual counter value is a discrete value.

As described above, when the AD conversion counter 16a has a compare match, that is, when the AD conversion counter 16a is reset, the AD conversion section 15 starts AD conversion processing. When the AD conversion is completed, a DMA transfer request signal S1 is sent from the AD conversion section 15 to the DMA section 12 . The DMA section 12 receives the DMA transfer request signal S1, reads data from the register 15a of the AD conversion section 15, and transfers the data to the RAM 13. FIG. In FIG. 3, the period during which DMA transfer from the AD converter 15 to the RAM 13 is performed is indicated as T1.

The delay counter 16b starts counting up from the start of delay measurement. When the delay counter 16b generates a compare match, the delay counter 16b issues a DMA transfer request signal S2 to the DMA section 12. FIG. Upon receiving this DMA transfer request signal S2, the DMA section 12 reads out the counter value of the delay counter 16b and transfers it to the RAM 13. FIG. This counter value is stored in the delay time buffer 13b in the RAM 13. FIG. In FIG. 3, the period during which the DMA transfer from the delay counter 16b to the RAM 13 is performed is indicated as T2. In the example of FIG. 3, the DMA transfer of the counter value of the delay counter 16b is performed in the period T2 without delay after the period T1 in which the DMA transfer of the sensor data is performed. Therefore, the counter value stored as the delay time in the delay time buffer 13b is "0x0000" which is the value immediately after the reset.

At the start of delay measurement, the area 14b of the ROM 14 is referred to, and the initial value of the number of transfers is read. In the example of FIG. 3, the number of DMA transfers from the AD converter 15 to be executed within one delay measurement period is four. For example, "0x0005" is set as the transfer count initial value as a larger value than this. The DMA unit 12 has a remaining number register for storing the number of remaining transfers. The controller 1 sets the initial value of the transfer count in the remaining count register at the start of the delay measurement period. The DMA unit 12 subtracts 1 from the register value of the remaining count register each time the DMA transfer from the AD conversion unit 15 is completed once. After the delay measurement period ends, the number of DMA transfers executed can be obtained by obtaining the difference between the transfer number initial value and the register value. For example, in the example of FIG. 3, the register value after the end of the delay measurement period is "0x0001". Therefore, in the example of FIG. 3, it can be seen that four DMA transfers were performed from the AD converter 15 during the delay measurement period.

Next, with reference to FIG. 4, a case where a delay occurs in DMA transfer will be described. In FIG. 4, when the second transfer request (the second pulse of S1) is issued from the AD converter 15 within the delay measurement period, DMA transfer (T4) based on another transfer request is executed. there is This T4 DMA transfer is due, for example, to a DMA transfer request from another module (not shown in FIG. 1) within the controller 1 . Therefore, the transfer (T1(2)) based on the second DMA transfer request from the AD converter 15 is executed after the DMA transfer indicated by T4 is completed. Further, the subsequent DMA transfer request from the delay counter 16b (the second pulse of S2) is also kept waiting because the DMA transfer of T4 is still in progress. Then, after the DMA transfer of T4 is completed, the DMA transfer (T1(2)) from the AD converter 15 is executed. After this DMA transfer is completed, the DMA transfer (T2(2)) from the delay counter 16b is executed. As a result, in the example of FIG. 4, there is a delay time d1 from when the delay counter 16b issues a DMA transfer request to when the transfer is executed. During this delay time d1, the counter value of the delay counter 16b continues to be counted up. Therefore, in the example of FIG. 4, the counter value "0x0010" when the second DMA transfer is executed represents the length of the delay time d1. This counter value is stored in the delay time buffer 13b of the RAM 13 by DMA transfer from the delay counter 16b.

Similarly, when the AD converter 15 issues a third DMA transfer request (the third pulse of S1), DMA transfer (T5) based on another transfer request is being executed. Therefore, the third DMA transfer (T2(3)) from the delay counter 16b is delayed by the delay time d2. The counter value of the delay counter 16b is "0x0008" when the third DMA transfer is executed. This counter value is stored in the delay time buffer 13b of the RAM 13 by DMA transfer from the delay counter 16b.

As described above, in the example of FIG. 4, the four DMA transfers from the AD converter 15 that should be executed within the delay measurement period are all executed within the delay measurement period. However, the second and third DMA transfers are delayed. The delay times of the second and third DMA transfers are stored in the delay time buffer 13b of the RAM 13. FIG. Therefore, by analyzing the data in the delay time buffer 13b, it can be found that the DMA transfer was delayed.

In the example of FIG. 4, the second DMA transfer (T1(2) and T2(2)) is completed before the third DMA transfer request (the third pulse of S1) is issued. Therefore, all requested DMA transfers are performed, albeit with a delay. However, if a next DMA transfer request is issued while waiting for execution of a previous DMA transfer, a transfer leak may occur. The controller 1 can detect the number of transfer omissions.

Next, with reference to FIG. 5, a mechanism for detecting the number of transfer omissions in the controller 1 will be described. In FIG. 5, when the first transfer request (the first pulse of S1) is issued from the AD converter 15 within the delay measurement period, DMA transfer (T4) based on another transfer request is executed. there is Therefore, the first DMA transfer request from the AD converter 15 is in a waiting state. However, before the DMA transfer of T4 ends, the AD converter 15 issues a second transfer request (the second pulse of S1). In this case, the first transfer request will be overwritten by the second transfer request. After that, when the DMA transfer of T4 ends, the DMA transfer (T1(2)) from the AD converter 15 is performed based on the second transfer request. At this time, what is transferred by the DMA transfer of T1(2) is not the data AD-converted at time t1 (C1 in FIG. 5), but the data at time t2 (C2). Therefore, in the example shown in FIG. 5, the sensor data (C1) of the AD converter 15 at time t1 is missing in the sensor data buffer 13a of the RAM 13. FIG. In this way, when sensor data that should be acquired is missing, an abnormality may not be detected correctly. Moreover, due to lack of sensor data, an abnormality may be erroneously detected even though there is no abnormality.

Moreover, in the sensor data buffer 13a, if the sensor data are stored continuously in the order in which they were transferred, the following problem may occur. In particular, as shown in FIG. 6A, when sensor data is stored sequentially according to timer times (t1 to t4 in FIG. 5), a mismatch between the data acquisition time and the data may occur. In the example shown in FIG. 6A, buffer areas are allocated according to timer times (t1 to t4). Assuming that there is no transfer omission, the sensor data C1 to C4 in FIG. 5 are stored in the buffer area in the order of transfer. However, when the transfer omission of the sensor data (C1) at time t1 occurs as in the example of FIG. 5, the sensor data (C2) at time t2 is stored in the area at time t1 as shown in FIG. 6B. After that, the sensor data (C3) at time t3 are stored in the area of time t2, and the sensor data (C4) at time t4 are stored in the area of time t3. Therefore, the sensor data from times t2 to t4 are processed as the sensor data acquired from times t1 to t3. As a result, the relationship between the data acquisition time and the sensor data is deviated, and for example, misfire may be detected erroneously even though no misfire has occurred.

However, in the controller 1, the register value of the remaining count register of the DMA unit 12 is not updated when there is a transfer omission. Therefore, as shown in FIG. 5, the number of remaining transfers after the end of the delay measurement period indicates "0x0002". As a result, it can be seen that the DMA transfer was executed only three times during the delay measurement period, and there was one transfer omission. The number of transfer omissions is stored in the abnormal data area 13c of the RAM 13. FIG. When an abnormality of the engine is detected, it is possible to judge that the abnormality is an erroneous detection caused by the omission of transfer of sensor data by looking at the number of transfer omissions.

Here, the processing flow at the end of the delay measurement period will be described with reference to FIG. Here, it is assumed that the CPU 11 performs this processing, but an external diagnostic tool or the like may perform this processing. First, the current time is set (step S1). The current time can be obtained from the timer unit 16, for example.

Next, the CPU 11 acquires the initial value of the number of transfers from the area 14b of the ROM 14 (step S2). Next, the CPU 11 acquires the remaining number of transfers from the remaining number of transfers register of the DMA unit 12 (step S3). Then, the CPU 11 subtracts the remaining number of transfers obtained in step S3 from the initial value of the number of transfers obtained in step S2, thereby obtaining the number of transfers performed (step S4). Further, the CPU 11 obtains the number of transfer omissions by subtracting the number of transfers that have been executed from the initial value of the number of transfers (step S5).

Next, the CPU 11 sets the initial value 0 to the variable i (step S6). In step S6, the CPU 11 also sets the initial value 0 to the variable Th representing the number of times of high load. Next, the CPU 11 selects one piece of delay time data in the delay time buffer 13b as the delay time Di, and determines whether the delay time Di is greater than a predetermined threshold (step S7). If the delay time Di is greater than this predetermined threshold, it is determined that the DMA unit 12 was in a high load state when the delay time Di was acquired. If the determination result of step S7 is Yes, the process proceeds to step S8 to increase the value of variable Th by one. If the determination result in step S7 is No, the process proceeds to step S9 to increase the value of variable i by one.

Next, the CPU 11 determines whether or not the value of the variable i is equal to the number of transfers that have been executed (step S10). If the determination result in step S10 is No, the process returns to step S7. If the determination result in step S10 is Yes, the process proceeds to step S11 to obtain a high load factor. The high load factor is obtained by dividing the high load count Th obtained in step S8 by the number of transfers performed. Next, the CPU 11 updates the data acquisition time in the abnormal data area 13c of the RAM 13 to the current time (step S12). In addition, the CPU 11 updates the data in the abnormal data area 13c with the number of transfer failures obtained in step S5 and the high load factor obtained in step S12 (step S13).

As described above, the controller 1 updates the data in the abnormal data area 13c of the RAM 13 each time the delay measurement period ends. As described above, the data in the abnormality data area 13c is stored in the ROM 14 as failure information data when an abnormality is detected, and is analyzed by a diagnostic tool or the like.

Here, a processing flow when an abnormality is detected will be described with reference to FIG. This processing is executed by the CPU 11 . FIG. 8 illustrates a case where a spark plug misfire is detected as an abnormality. However, the type of abnormality is not limited to misfiring. First, the CPU 11 acquires the current time from the timer unit 18 and stores it in the ROM 14 as the abnormality detection time (step S21). Next, the CPU 11 reads the data in the abnormal data area 13c of the RAM 13, and stores it in the ROM 14 as misfire detection data (step S22).

A misfire of a spark plug is detected based on sensor data from an in-cylinder pressure sensor and a knock sensor. For example, when the value of the sensor data of the in-cylinder pressure sensor is not a normal value, it is determined that the spark plug has misfired. Therefore, when a misfire is detected, it is desirable to be able to quickly determine whether the spark plug has actually misfired or whether the misfire has been erroneously detected due to insufficient sensor data. According to the controller 1, it is possible to verify the presence or absence of defects in the sensor data based on the presence or absence of DMA transfer delays and transfer omissions.

As described above, according to the controller 1 of the present embodiment, the delay time of DMA transfer is recorded in the delay time buffer 13 a of the RAM 13 . By analyzing the delay situation using a diagnostic tool or the like, when an abnormality is detected, it is possible to quickly determine whether it is a true abnormality or whether the cause is an incomplete sensor data due to a DMA load.

Further, the controller 1 determines whether or not there is any omission in the DMA transfer during the delay measurement period, and records the number of transfer omissions in the RAM 13 . As a result, when an abnormality is detected, it can be quickly determined by a diagnostic tool or the like whether the abnormality is real or is caused by insufficient sensor data due to omission of transfer.

FIG. 9 shows an example of the processing flow of the diagnostic tool. A diagnostic tool is, for example, software installed in a personal computer, a tablet, or the like. Therefore, the processing flow of FIG. 9 is executed by a processor such as a personal computer. The diagnostic tool first accesses the area 14c in which failure information data is stored in the ROM 14 of the controller 1, and reads out the failure information data (step S31). Here, it is assumed that the diagnostic tool accesses the ROM 14 . However, the failure information data read from the ROM 14 may be read into the diagnostic tool via a recording medium or communication medium.

Next, the diagnostic tool extracts transfer status data relating to DMA transfer from the read failure information data (step S32). For example, in the example of FIG. 2, the number of transfer omissions and the high load factor are extracted. However, the transfer status data regarding DMA transfer is not limited to the number of transfer omissions and the high load factor. For example, each delay time stored in the delay time buffer 13b at the time of misfire detection may also be stored in the ROM 14 as transfer status data.

Next, by comparing the extracted transfer status data with a predetermined threshold value, it is determined whether the abnormality detection is caused by insufficient sensor data due to a high load of DMA transfer (step S33). For example, when the high load factor is higher than a predetermined threshold value (including zero), it is possible to grasp that there was a delay in transferring sensor data and the frequency of this occurrence. Also, when delay time data is included in the transfer status data, the delay time is compared with a predetermined threshold, and the larger the number of delay time data exceeding the threshold, the higher the DMA load can be estimated. Also, when there is delay time data exceeding the delay time threshold, it can be estimated that the DMA load was high. In these cases, it can be determined that the abnormality detection is likely caused by insufficient sensor data due to the DMA load.

Also, for example, a diagnostic tool compares the number of transfer omissions with a predetermined threshold, and it can be estimated that the DMA load is higher as the number of transfer omissions exceeds the threshold and the difference between the threshold and the threshold is larger. In this case, it can be determined that the abnormality detection is likely caused by incomplete sensor data due to the DMA load.

The disclosure in this specification, drawings, etc. is not limited to the illustrated embodiments. The disclosure encompasses the illustrated embodiments and variations thereon by those skilled in the art. For example, the disclosure is not limited to the combinations of parts and/or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure encompasses omitting parts and/or elements of the embodiments. The disclosure encompasses permutations or combinations of parts and/or elements between one embodiment and another. The disclosed technical scope is not limited to the description of the embodiments. The disclosed technical scope is indicated by the description of the claims, and should be understood to include all modifications within the meaning and range of equivalents to the description of the claims.

For example, in the above-described embodiment, the RAM 13 stores both the delay time and the number of transfer omissions. However, it is also possible to store in the RAM 13 only one of the delay time and the number of transfer omissions.

Also, in the above embodiment, the controller 1 obtains the high load factor based on the delay time and stores it in the RAM 13 . However, not only the delay time itself, but also index data representing the state of DMA transfer may be obtained based on the delay time, and the index data may be used for the analysis. As such index data, various indexes can be used in addition to the above-described high load factor. For example, the ratio of the number of transfer omissions to the number of executed DMA transfers may be used as index data. Alternatively, the number of times the delay time exceeds the threshold within the delay measurement period may be used as index data.

In the above-described embodiment, the configuration is illustrated in which the delay time is stored in the RAM 13 even when the delay time is zero (0x0000). However, it is also possible to store the delay time in the RAM 13 together with the information on the time of occurrence of the delay only when a substantial delay time occurs. With this configuration, the storage capacity of the RAM 13 can be effectively used.
Further, in the above embodiment, an example has been described in which a DMA transfer request signal for the count value of the delay counter 16b is generated when the count value of the delay counter 16b reaches a predetermined value. However, the DMA transfer request for the count value of the delay counter 16b may be generated in the DMA section 12 in response to completion of the DMA transfer from the AD conversion section 15 to the RAM 13 . In this case, the AD conversion counter 16a can also serve as the delay counter 16b, and the DMA unit 12 reads out the counter value of the AD conversion counter 16a at the time when the DMA transfer of the AD conversion result is completed, and calculates the delay time. It may be transferred to the RAM 13 as data.

In the above embodiment, the controller of the engine control system of the automobile was exemplified. However, the controller of the present disclosure can be applied not only to an automobile engine control device but also to various control devices.

1: controller, 12: DMA unit, 13: RAM

Claims (6)

a RAM (13);
a DMA unit (12) for controlling DMA transfer to the RAM;
with
The RAM stores transfer status data that directly or indirectly represents at least one of a transfer delay time and the number of transfer omissions for the DMA transfer performed within a predetermined period ,
The DMA unit performs the DMA transfer at a predetermined cycle,
further comprising a counter that is reset when counting a reset period having the same length as the predetermined period;
The controller, wherein the RAM stores a count value of the counter when the DMA transfer is completed as the delay time of the transfer . the counter is a delay counter (16b) that is reset when the reset cycle is reached corresponding to the point in time when the DMA transfer is completed;
2. The controller according to claim 1 , wherein said delay counter requests DMA transfer of the counter value of said delay counter to said RAM when a compare match occurs with a predetermined value corresponding to said reset period. a RAM (13);
a DMA unit (12) for controlling DMA transfer to the RAM;
with
The RAM stores transfer status data that directly or indirectly represents at least one of a transfer delay time and the number of transfer omissions for the DMA transfer performed within a predetermined period,
The controller, wherein the transfer status data includes a high load rate representing a ratio of the DMA transfers, among the DMA transfers performed within the predetermined period, for which the delay time of the transfer exceeds a predetermined threshold. a RAM (13);
a DMA unit (12) for controlling DMA transfer to the RAM;
with
The RAM stores transfer status data that directly or indirectly represents at least one of a transfer delay time and the number of transfer omissions for the DMA transfer performed within a predetermined period,
The controller, wherein the number of transfer omissions is obtained from a comparison between the number of DMA transfers that can be performed within the predetermined period and the number of DMA transfers that have been performed within the predetermined period. a RAM (13);
a DMA unit (12) for controlling DMA transfer to the RAM;
with
The RAM stores transfer status data that directly or indirectly represents at least one of a transfer delay time and the number of transfer omissions for the DMA transfer performed within a predetermined period,
a writable ROM (14);
An AD conversion unit (15) that receives a sensor signal from a controlled object and AD converts it to generate sensor data,
the DMA unit DMA-transfers the sensor data from the AD conversion unit to the RAM;
reading at least part of the sensor data from the RAM in addition to at least part of the transfer status data when an abnormality of the controlled object is detected based on the sensor data, and storing the data in the ROM ; controller . A diagnostic program for determining an abnormality in the controlled object of the controller (1) according to claim 5 ,
When an abnormality in the controlled object is detected based on the sensor data,
computer processor,
inputting data read from the ROM of the controller;
and comparing the transfer status data with a predetermined threshold value to determine whether or not the abnormality in the controlled object is caused by the deficiency of the sensor data due to the DMA transfer.

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