JP7232091B2 - game machine - Google Patents

Description

TECHNICAL FIELD The present invention relates to the technical field of game machines having speaker units for emitting sound.

For example, some game machines, such as slot machines and pachinko game machines, are equipped with a speaker section that emits sound to produce sound effects. In addition to sound effects, some game machines perform visual effects such as light and images, and tactile effects using vibration (for example, see Patent Document 1 below).

JP 2015-112184 A

Here, in performing production using vibration, it is common to provide an actuator such as a motor that serves as a vibration source. As a result, the number of parts increases and the associated cost increases.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to overcome the above-described problems and to reduce the number of components and the cost of a gaming machine that performs vibration effects.

A gaming machine according to the present invention comprises a speaker section that emits sound, and drive control means for controlling driving of the speaker section, and the drive control means is provided in a specific section that is at least a part of the gaming machine. Based on the sound signal containing the frequency component of the natural frequency, the speaker section is driven and controlled to vibrate the specific section.
As a result, since the speaker used for sound output can be used as a vibration source, there is no need to separately provide an actuator such as a motor as a vibration source.

In the game machine according to the present invention described above, the drive control means may drive and control the speaker section based on the frequency-swept sound signal.
By sweeping the frequency of the vibration sound, it is possible to adjust the amplitude of the vibration.

In the gaming machine according to the present invention described above, the drive control means can be configured to drive and control the speaker section based on a sound signal whose frequency is reciprocally swept.
As a result, frequency sweeping is performed in the form of a reciprocating sweep in which sweeping on the rising side and sweeping on the falling side of frequency are combined.

In the game machine according to the present invention, the driving control means drives and controls the speaker unit based on the sound signal in which the reciprocating sweep is repeated with a reciprocating period of 0.05 seconds or less. It is possible to
If the reciprocating period is lengthened (that is, the sweep speed is slowed down), the amplitude of vibration is increased, and if it is shortened (sweep speed is increased), the amplitude of vibration is decreased.

The gaming machine according to the present invention described above includes a box-shaped main body case with an open front side, and a front panel attached to the main body case so as to be openable and closable and closing the opening in a closed state. The speaker section may be provided on the front panel so that at least a part of the rear side thereof is exposed to a closed space formed inside the main body case in the closed state.
As a result, the air in the closed space inside the main body case vibrates according to the sound emitted from the back side of the speaker unit, and the entire housing of the gaming machine can vibrate.

In the gaming machine according to the present invention described above, the drive control means can drive and control the speaker section based on the sound signal containing the frequency component in the audible band to vibrate the specific section. be.
As a result, it is possible for the player to perceive the vibration and the low sound at the same time.

In the gaming machine according to the present invention described above, the drive control means can reproduce a plurality of sound signals at the same time. The system used for reproduction is determined for each type of sound classified at least into a certain error sound and a third sound that is a sound other than the vibration sound and the error sound, and the drive control means includes: When reproducing and outputting the sound signal of the vibration sound, it is possible to perform a process of masking the systems other than the vibration sound and the error sound among the plurality of systems.
As a result, it is possible to mask sounds other than the vibration sound while enabling the output of the notification sound when an error is detected.

In the gaming machine according to the present invention described above, the drive control means may be configured to perform a process of masking all of the plurality of systems excluding the error sound system when an error is detected. It is possible.
This prevents the specific portion from vibrating when an error is detected.

According to the present invention, the effect lottery based on the set value can be appropriately performed.

It is a front view of the gaming machine of the embodiment. FIG. 2A is a plan view (FIG. 2A) and a right side view (FIG. 2B) of the gaming machine of the embodiment; It is a rear view of the front panel provided in the gaming machine of the embodiment. It is a front view of a main body case provided in the gaming machine of the embodiment. FIG. 10 is a perspective view schematically showing the state of the gaming machine when the front panel is opened. It is a schematic block diagram of the control configuration inside the game machine. It is the figure which showed the circuit structure of the main-control board with which a game machine is equipped. FIG. 4 is an explanatory diagram of a configuration related to origin detection; FIG. 4 is an explanatory diagram of a pattern formed on a rotating reel (rotating drum); 4 is a flowchart of main control side start-up processing; 4 is a flowchart of operation stop error processing; 8 is a flowchart of setting change processing; 4 is a flowchart of main loop processing; 4 is a flowchart of timer interrupt processing on the main control side; It is a flow chart of production control side main processing. It is a flow chart of 1ms timer interruption processing of production control of an embodiment. It is a flow chart of command analysis processing in production control of the embodiment. It is a flow chart of the command correspondence processing in the production control of the embodiment. It is a flow chart of scenario registration processing in production control of the embodiment. It is a flow chart of scenario deletion processing in production control of the embodiment. It is a flow chart of scenario update processing in production control of the embodiment. It is a flow chart of the sub-scenario update process in the effect control of the embodiment. 4A and 4B are explanatory diagrams of scenario registration information, lamp data registration information, and motor data registration information according to the embodiment; FIG. FIG. 4 is an explanatory diagram of sound data registration information according to the embodiment; FIG. 4 is an explanatory diagram of a main scenario table of the embodiment; FIG. 4 is an explanatory diagram of a sub-scenario table of the embodiment; 6 is a flowchart of sound registration processing according to the embodiment; 7 is a flowchart of SE setting processing according to the embodiment; 7 is a flowchart of sound control setting processing according to the embodiment; FIG. 4 is an explanatory diagram of a data structure of sound control information according to the embodiment; FIG. 10 is an explanatory diagram of conversion processing of fade-type sound control information; FIG. 10 is an explanatory diagram of an example of use of fade-type sound control information; FIG. 10 is an explanatory diagram of a control example of muting a predetermined type of sound by means of a secondary volume; 4 is a flowchart of sound reproduction processing according to the embodiment; 4 is a flow chart illustrating an example of a process related to sound output for vibration; FIG. 10 is a flowchart showing an example of processing for masking sounds other than error sounds when an error occurs; FIG.

Hereinafter, embodiments of the gaming machine according to the present invention will be described in the following order. In addition, in the embodiment, a slot machine (rotary type game machine) is taken as an example of the game machine.

<1. Mechanism configuration of the reel game machine>
<2. Control configuration of the reel game machine>
<3. Rotating reel>
<4. Main control side startup processing>
<5. Setting change processing>
<6. Main loop processing>
<7. Timer interrupt processing>
<9. Production control side main processing and interrupt processing>
<10. Details of processing related to production control>
[10-1. Command analysis processing]
[10-2. Scenario registration/deletion process]
[10-3. Scenario update process]
[10-4. Sound registration processing]
[10-5. Sound playback processing]
<11. Vibration production of the embodiment>
<12. Summary and Modifications>

<1. Mechanism Configuration of Game Machine>

First, with reference to FIGS. 1 to 5, the external configuration of a slot machine, which is an example of a game machine as an embodiment of the present technology, will be described.
1 is a front view of the slot machine, FIG. 2A is a plan view, FIG. 2B is a right side view, FIG. 3 is a rear view of the front panel 2, FIG. 4 is a front view of the main body case 1, and FIG. FIG. 10 is a perspective view schematically showing the state of the slot machine when it is in a state; 5, illustration of various parts accommodated inside the main body case 1 is omitted. Also, FIG. 2 shows the state of the slot machine when the front panel 2 is closed.

In the slot machine of this embodiment, a rectangular box-shaped main body case 1 and a front panel 2 on which various game members are mounted are connected via a hinge mechanism (not shown), and the front panel 2 is attached to the main body case 1. It is installed so that it can be opened and closed freely. The main body case 1 has an opening on the front side (see FIG. 5), and the front panel 2 closes the opening on the front side of the main body case 1 in the closed state (see FIG. 2). In this example, the main body case 1 does not have an opening in the rear part, so when the front panel 2 is closed, the inside of the main body case 1 whose front side opening is closed by the front panel 2 is closed. A closed space is formed in
Here, the front side of the gaming machine means the side facing the player during use.

As shown in FIG. 4, a pattern rotating unit 3 having three rotating reels (rotating drums) 4a, 4b, and 4c is arranged substantially in the center of the main body case 1. As shown in FIG. Further, a medal payout device 5 is arranged below it.
Various patterns, such as BB (big bonus) and RB (regular bonus) patterns, various fruit patterns, and replay patterns, which will be described later, are drawn on each of the rotating reels 4a, 4b, and 4c.
The medal dispensing device 5 has a medal tank 5a for storing medals. A payout motor 75, a payout connection board 73, a hopper board 74, a medal payout sensor 76, etc., which will be described later with reference to FIG. 6, are accommodated in the payout case 5b.
The medals stored in the medal tank 5a are drawn out toward the front of the drawing from the payout port 5c based on the rotation of the payout motor 75. As shown in FIG. The medals stored in excess of the limit amount are configured to drop into the auxiliary tank 6 through the excess medal lead-out portion 5d.

A power board 41 is arranged adjacent to the medal payout device 5 . A main control board 40 is arranged above the symbol rotation unit 3 , and a reel setting board 71 is arranged adjacent to the main control board 40 .
Inside the symbol rotating unit 3, a reel LED (Light Emitting Diode) relay board 56 and a reel relay board 53 shown in FIG. 6 are provided. are placed.

Further, in the body case 1, a door opening sensor 35 for detecting opening of the front panel 2 (opening of the door) is provided on the side of the symbol rotating unit 3. As shown in FIG.

As shown in FIG. 1, an LCD (Liquid Crystal Display) unit 7 is arranged above the front panel 2 . Various characters are displayed on the LCD unit 7 in order to liven up the game action.
A display window 8 for exposing the reels 4a, 4b, and 4c is formed below the LCD unit 7. As shown in FIG. Through the display window 8, approximately three symbols can be visually recognized for each of the rotating reels 4a, 4b, and 4c. In this case, there are 3×3=9 symbol stop positions as positions at which symbols are stopped within the display window 8 when the respective rotating reels 4a, 4b and 4c are stopped. Then, of the nine symbol stop positions in total, three lines connecting the three symbol stop positions lined up in the horizontal direction and two lines connecting the three symbol stop positions lined up in the diagonal direction. It becomes a design stop line.
Among the symbol stop lines, the symbol stop line used for judging whether or not the winning symbols (winning combination) have been completed is a valid line, and the other symbol stop lines are invalid lines. Valid lines and invalid lines are appropriately changed according to various game states such as BB, RB, AT (assist time) and ART (assist replay time). That is, for example, the middle line is the active line during the normal game, but the upper and middle lines are changed into the active lines during the bonus game.

Inside the symbol rotation unit 3, reel LEDs are arranged at positions where each of the nine symbols visible when the reels 4a, 4b, and 4c are stopped can be illuminated from the inside (Fig. 1 (not shown). Each spinning drum LED is turned on/off according to the rotation state or stop state of each reel 4a, 4b, 4c or various effects.

Below the display window 8, there are provided an LED group 9 that indicates the game state, a payout display section 10 that displays the number of medals paid out as a game result, and a stored number display section 11.
The LED group 9 includes, for example, LEDs indicating the number of medals thrown into the game (LEDs indicating the number of bets), LEDs indicating the replay state, and LEDs indicating that the spinning drum is ready to rotate (the It consists of an LED (game start display LED) indicating that a predetermined number of medals required for a game has been inserted, an LED indicating the acceptance state of insertion of medals, and the like.
The payout display unit 10 is configured by connecting two 7-segment LEDs, and functions as an error indicator for specifying the number of payout medals and displaying the content of the abnormality when some kind of abnormal situation occurs.
The accumulated number display portion 11 displays the number of accumulated medals in a credit state.

Above, left, and right of the display window 8, LED effect sections 15a, 15b, and 15c are provided. The LED effect sections 15a, 15b, and 15c are provided with a predetermined pattern and design, and are configured such that the LEDs arranged on the inner side execute a light effect. The effects executed by the LED effect units 15a, 15b, and 15c are, for example, effects indicating winning of BB or RB, effects indicating states such as AT and ART, assist effects during AT and ART, and the like. .
Although individual descriptions are omitted, various other LEDs are arranged on the front panel 2 as LEDs for presenting effects and operating states.

A medal insertion slot 12 for inserting medals is provided on the central right side of the front panel 2, and a return button 13 for returning the medals jammed in the medal insertion slot 12 is provided in the vicinity of this. A keyhole for inserting a dedicated key is provided on the right side of the return button 13 . With the front panel 2 closed with respect to the main body case 1, the front panel 2 is unlocked by turning the key inserted in the keyhole to the right (hereinafter referred to as "unlocking operation"), and the main body of the front panel 2 is unlocked. The case 1 can be opened and closed. Also, by turning the key inserted into the keyhole to the left, the stop state of the game due to a stoppage or an error is canceled (hereinafter referred to as "stop cancellation operation").
Also, on the central left side of the front panel 2, there are provided a credit checkout button 14 for paying out credit medals or bet medals, and a max insertion button 16 for artificially inserting three credit medals. there is

The front panel 2 also has a start lever 17 for starting the rotation of the reels 4a, 4b and 4c, and stop buttons 18a, 18b and 18c for stopping the rotating reels 4a, 4b and 4c. is provided.
When the player operates the start lever 17, normally the three reels 4a, 4b and 4c start rotating in the forward direction. However, there are cases where a reel effect (so-called freeze effect) accompanied by a game interruption state is performed in order to announce an internal winning state. The reel effect can be written as “rotational effect” in the sense of the effect caused by the rotation of the rotating reels 4 . In the reel effect, for example, all or part of the rotating reels 4a, 4b, 4c rotate irregularly (so-called “effect rotation”) and then start rotating in the positive direction.
As a specific example of reel production, for example,
・Slow performance in which the robot rotates very slowly in the forward direction (forward rotation) and stops ・Reverse rotation performance in which the robot rotates in the reverse direction for a predetermined period of time after repeating forward and reverse rotations and then stops ・Rotates forward for the first predetermined time and then stops First rocking effect of repeating reverse rotation and then stopping ・Second rocking motion effect of repeating forward and reverse rotation for a second predetermined time and then stopping ・Forward rotation and reverse rotation for a second predetermined time After repeating the above, it stops, and then it rotates very slowly in the forward direction, and then stops. Swinging reverse rotation effect - After rotating forward or reverse at a predetermined speed, the effect of stopping in line with a predetermined pattern - An effect of maintaining the current rotation state (or stop state) etc. are prepared. During such a reel effect, all or part of the character effect on the LCD unit 7, the lamp effect of blinking the LED lamp, and the sound effect of driving the speaker are appropriately selected and executed.

Below the front panel 2, a horizontally long receiving tray 19 for storing medals and a medal outlet 20 communicating with the payout port 5c of the payout device 5 are provided.

Speakers 30a and 30b are arranged on the upper left and right sides of the front panel 2, and speakers 330c and 30d are arranged on the lower left and right sides. In this example, the upper speakers 30a and 30b are 8Ω, 10W mid-high range speakers, and the lower speakers 30c, 30d are 8Ω, 30W mid-low range speakers.
As can be seen with reference to FIGS. 3 and 5, the lower speakers 30c and 30d have at least a portion of their rear surface exposed (in this example, the entire rear surface side is exposed). That is, when the front panel 2 is closed, at least part of the back side of each of the speakers 30c and 30d is exposed to the closed space inside the main body case 1. As shown in FIG.

Also, on the back side of the front panel 2, there is a medal sorting device 21 for sorting medals inserted into the medal slot 12 shown in FIG. A return passage 22 leading to an exit 20 is provided (see FIG. 3).
A board case 23 is arranged on the upper part of the back side of the front panel 2 . The board case 23 accommodates a performance control board 42, a performance interface board 43, a liquid crystal control board 44, a liquid crystal interface board 45, and the like, which will be described in FIG.
A game relay board 60 (to be described later with reference to FIG. 6) for relaying signals between various game members and the main control board 40 shown in FIG.

<2. Control configuration of the reel game machine>

Next, the configuration of the control system of the slot machine of this embodiment will be described.
FIG. 6 is a schematic block diagram of the internal control structure of the slot machine. The control structure of the slot machine of this embodiment is centered around the main control board 40 .
The main control board 40 is equipped with a microcomputer having a CPU (Central Processing Unit), RAM (Random Access Memory), ROM (Read Only Memory), etc., and a circuit for interface, etc., and is used for general game operations of the slot machine. Such overall control is performed. For example, the main control board 40 controls the operation of various game members including the rotating reels 4a, 4b, and 4c, and grasps the operation status. Also, an effect is executed according to the game action.
The main control board 40 exchanges various signals (command and detection signals).

The power supply board 41 receives AC 24V, rectifies and smoothes it, and obtains a DC voltage. The power supply board 41 includes a converter circuit to generate a power supply voltage required for each part. In the figure, the main control power supply voltage V1 given to each part through the main control board 40 and the effect control power supply voltage V2 given to each part through the effect interface board 43 are shown.
The power supply board 41 is also provided with a power monitoring circuit for detecting a power cutoff state, a backup power supply circuit for supplying a backup power supply voltage to the main control board 40, and the like. Further, the power board 41 generates a power failure signal Ev according to the drop in the power supply voltage, and outputs it to the main control board 40 and effect interface board 43 (not shown).

The effect control board 42 is equipped with a microcomputer and an interface circuit, and controls the effect operation of the slot machine. As illustrated, the effect control board 42 includes a CPU 42a, a ROM 42b, and a RAM 42c that constitute a microcomputer. In addition, the production control board 42 includes a counter circuit and a timer circuit (not shown), and uses them to measure various times.

The production control board 42 includes a sound source IC (Integrated Circuit) 42d.
The sound source IC 42d mixes phrases of a plurality of reproduction channels (sound channel aCH, which will be described later) to obtain a predetermined number of sound signals (predetermined number of output channels). In this example, the speaker 30 is provided with a pair of upper speakers 30a and 30b and a pair of lower speakers 30c and 30d, each pair corresponding to 2-channel output of Lch and Rch. Therefore, the number of output channels of the sound source IC 42d is set to two channels, Lch and Rch, for example.
Also, the sound source IC 42d performs sound control for the phrase designated as the object to be controlled. Specifically, the CPU 42a of the effect control board 42 provides the sound source IC 42d with instruction information relating to the addition of sound effects such as volume change instructions and fade-in reproduction/fade-out reproduction. Playback control of the specified phrase.

The sound source IC 42d used in this example also has a SUB volume setting function and a panning function (horizontal panning and vertical panning).
In this case, the information for requesting an instruction when the sound source IC 42d performs sound output includes at least "phrase number", "primary volume", "primary volume transition amount", "secondary volume", "loop count", "SUB0 volume", and "SUB1 volume". Volume, left/right panpot, left/right panpot transition amount, top/bottom panpot, and top/bottom panpot transition amount. That is, the tone generator IC 42d in this case is provided with a register for each sound channel aCH for receiving the input of the instruction value for each of these items.
Note that the SUB volume is not used in this embodiment. Therefore, "0" is set in the above "SUB0 volume" and "SUB1 volume" registers (see step S1502 in FIG. 34, which will be described later).

Sound signals output by the sound source IC 42d are given to the speakers 30 (30a to 30d) via the performance interface board 43 and the speaker relay board 47. FIG.

It should be noted that the sound source IC 42d is not limited to being provided on the effect control board 42, and can be provided on a board different from the effect control board 42.

Also, the effect control board 42 receives commands from the main control board 40 via the effect interface board 43 . For example, the main control board 40, with respect to the effect control board 42, sound effects by the speakers 30 (30a to 30d), lamp effects by LED lamps and cold cathode ray tube discharge tubes, pattern effects by the LCD unit 7, movement of characters, etc. A control command for realizing a movable body effect using the body is output, and the effect control board 42 performs effect control processing according to the control command.
Here, hereinafter, the control command that the main control board 40 outputs to the effect control board 42 is referred to as "effect control command".

In this example, the effect control command defines a function by a 2-byte configuration consisting of a 1-byte length mode (MODE) and a 1-byte length event (EVENT).
In order to distinguish between MODE and EVENT, Bit 7 of MODE is ON and Bit 7 of EVENT is OFF.
When transmitting these information as valid, a strobe signal is output corresponding to each mode (MODE) and event (EVENT). That is, the main control board 40 (CPU80a to be described later), when there is a command to be transmitted, performs the setting and output of mode (MODE) information for transmitting the command to the effect control board 42, a predetermined time has passed since this setting After that, the first strobe signal is transmitted. Further, event (EVENT) information is set and output after a predetermined period of time has elapsed from the transmission of this strobe signal, and the second strobe signal is transmitted after a predetermined period of time has elapsed from this setting.
The strobe signal is controlled by the main control board 40 to be in an active state for a predetermined period in which the CPU 42a of the effect control board 42 can reliably receive the command.
Also, the CPU 42a) of the effect control board 42 generates an interrupt based on the input of the strobe signal, executes the control program for the command reception interrupt process, and acquires the effect control command in this interrupt process.

When the performance control board 42 receives a performance control command (game start command) for specifying the internal lottery result from the main control board 40, it executes an AT lottery for determining whether or not the assist time winning state is set according to the internal lottery result. .
It should be noted that the effect control board 42, in a predetermined number of games (during AT) after winning the AT lottery, controls the three rotating reels 4a, Control is performed to notify the player of the stop order of 4b and 4c.
When the effect control board 42 receives the effect control command indicating execution of the reel effect from the main control board 40, the effect control board 42 starts the effect operation corresponding to the reel effect executed by the main control board 40. - 特許庁
For such effect control operations, the effect control board 42 performs necessary communication with each part through the effect interface board 43 .

The effect control board 42 is connected to the liquid crystal control board 44 via the effect interface board 43 and the liquid crystal interface board 45 .
The liquid crystal control board 44 controls the effects of image display on the LCD unit 7 . A VDP (Video Display Processor), an image ROM, a VRAM (Video RAM), a liquid crystal control CPU, a liquid crystal control ROM, a liquid crystal control RAM, and the like are mounted on the liquid crystal control board 44 .
The VDP controls overall video output processing such as image expansion processing and image drawing.
The image ROM stores image data (effect image data) for which the VDP performs image expansion processing.
The VRAM is an image memory area for temporarily storing image data developed by the VDP.
The liquid crystal control CPU outputs control data necessary for the VDP to perform display control.
The liquid crystal control ROM stores a program describing the display control operation procedure of the liquid crystal control CPU and various data necessary for the display control.
The liquid crystal control RAM functions as a work area and buffer memory.
Such a liquid crystal control board 44 receives a command relating to display effects from the effect control board 42 and generates a display drive signal accordingly. A display drive signal is supplied to the LCD unit 7 via the liquid crystal interface board 45 to display an image.

In addition, the effect control board 42 realizes various LED lamp effects via the effect interface board 43, the LED board 48, and the reel LED relay board 56.
On the LED board 48, for example, LEDs are arranged as the LED effect sections 15a, 15b, and 15c shown in FIG.
The reel LED relay board 56 relays LED drive signals from the effect control board 42 for the first reel LED board 50a, the second reel LED board 50b, and the third reel LED board 50c.
The first reel LED board 50a is provided with reel LEDs for illuminating the design of the rotating reel 4a from the inside. The second reel LED board 50b is provided with reel LEDs for illuminating the design of the rotating reel 4b from the inside. Further, on the third reel LED board 50c, reel LEDs for illuminating the design of the rotating reel 4c from the inside are arranged.

In addition, the effect control board 42 controls the movable body driving section 102 to realize the movable body effect. The movable body driving unit 102 includes actuators such as motors and solenoids that drive the movable bodies (not shown) provided in the slot machine, and a drive circuit (driver circuit) for the actuators. By controlling the unit 102, the movable body is operated to realize the movable body presentation.

The main control board 40 is connected to various game members of the slot machine via the game relay board 60 as shown in FIG.
The game display board 61 includes an LED group 9 indicating a game state, a payout display section 10 having a 7-segment LED, and a pooled number display section 11 having a 7-segment LED. The main control board 40 transmits a control command to the game display board 61 via the game relay board 60, and controls the display according to the game state.

A start switch by the start lever 17 is mounted on the start switch board 62 .
The stop switch board 63 is equipped with stop switches by stop buttons 18a, 18b, and 18c.
An input switch for the max input button 16 is mounted on the stored medal input switch board 64 .
A settlement switch for the settlement button 14 is mounted on the settlement switch board 65 .
The main control board 40 receives, via the game relay board 60, detection signals of player operations by the switches of these boards (61, 62, 63, 64, 65).

The door sensor 66 is a sensor provided for the aforementioned keyhole of the front panel 2 . The door sensor 66 is capable of recognizing the above-described operation for canceling the stoppage of the game.
A medal passing sensor 67 and a lever detection sensor 68 are provided in the medal sorting device 21 . The medal passing sensor 67 is provided with a first sensor and a second sensor arranged along the medal passing path and each composed of, for example, a photointerrupter, and detects the passing of the sorted regular medals. The lever detection sensor 68 is, for example, a photomicrosensor, and is a sensor shielded by a sensor lever that operates according to the passage of medals inserted from the medal insertion slot 12 . That is, after the medals inserted from the medal insertion slot 12 pass through the lever detection sensor 68 and only legitimate medals are sorted out, the passage of the medals is detected by the medal passing sensor 67 .
The main control board 40 receives detection signals from these sensors ( 66 , 67 , 68 ) via the game relay board 60 . Further, the main control board 40 detects the insertion time and passing direction of the inserted medals from the detection signal received from the sensor, and accepts the inserted medals only when they meet predetermined regulations, and otherwise inserts them. Treat as a medal error.
A blocker solenoid 69 drives ON/OFF a blocker that blocks the passage of fraudulent tokens. The main control board 40 controls the blocker solenoid via the game relay board 60 . In this example, the inserted medals are ejected by turning off the blocker solenoid 69 .

In addition, the main control board 40 has three stepping motors 54 (first drum stepping motor 54a, second drum stepping motor 54b, It is connected to the third barrel stepping motor 54c).
Further, the main control board 40 includes three index sensors 55 (first reel index sensors) for detecting origin positions (origin positions 101 described later) of the reels 4a, 4b, and 4c via the reel relay board 53. sensor 55a, second drum index sensor 55b, and third drum index sensor 55c).
The main control board 40 drives or stops the stepping motors 54a, 54b, 54c to achieve the rotation of the reels 4a, 4b, 4c and the stopping at the target position. The main control board 40 can also detect the origin positions of the reels 4a, 4b and 4c based on the detection signals of the index sensors 55a, 55b and 55c.

In addition, the main control board 40 is also connected to a device section for paying out medals through a payout connection board 73 . A hopper substrate 74 for controlling medal payout, a payout motor 75, and a medal payout sensor 76 are provided as a device unit for paying out medals.
The hopper board 74 rotates the payout motor 75 based on the payout control signal from the main control board 40 to pay out a predetermined amount of medals.
A medal payout sensor 76 detects the passage of payout medals. A detection signal from the medal payout sensor 76 is used to detect an abnormal payout state such as an insufficient number of payout medals or no payout operation.

The main control board 40 is also connected to an external common terminal board 70 . The external centralized terminal board 70 is connected to, for example, a hall computer.

The main control board 40 is also connected to the reel setting board 71 . The drum setting board 71 is provided with a setting key switch 72a which is turned on/off according to the operation of the setting key and a reset switch 72b which is turned on/off according to the operation of the reset button. The drum setting board 71 outputs a signal or the like indicating the set value vd set by the staff using the setting keys and the reset button.
Here, the set value vd is a value representing the probability of winning a lottery process executed by the slot machine, in other words, a value representing a stage of the probability of winning a game state advantageous to the player. It is appropriately set based on the sales strategy of the game hall. In this example, there are six levels of winning probability, and the set value vd can be set to any one of the six levels from setting "1" to setting "6". At this time, "0" to "5" are assigned as values of the set value vd itself.
In this example, the higher the set value vd, the higher the winning probability.

A hall attendant or the like can change the set value vd by a predetermined operation. Specifically, when changing the set value vd, first, the front panel 2 is opened, and the power is turned on while the setting key switch 72a is kept ON (in this example, the setting key is turned to the right). do. Then, a setting value (one of "1" to "6") indicating the stage currently set is displayed on a display provided for the drum setting board 71, and the reset button is pressed in this state. Each time (the reset switch 72b is turned on), the display value is incremented by 1 (returns to "1" after the display value "6"). Further, after the value is selected by the reset button, by operating the start lever 17, the set value vd is set to a value corresponding to the selected value, and then the setting key switch 72a is turned off (in this example, By turning the setting key to the left), the change of the setting value vd is completed.
A setting change process performed by the main control board 40 (the CPU 80a, which will be described later) to enable such a change of the set value vd will be described later with reference to FIG.

Next, the circuit configuration of the main control board 40 will be described with reference to FIG.
As shown in the figure, the main control board 40 comprises a one-chip microcomputer controller 80, an I/O port circuit 83 for inputting and outputting 8-bit parallel data, a counter circuit 81, and an interface section for each section. ing.

The controller 80 incorporates a CPU 80a, a ROM 80b, a RAM 80c, an interrupt controller 80d, a CTC (Counter/Timer Circuit) 80e, and the like. A non-volatile memory is used for the RAM 80c.
The CTC 80e is a circuit in which 8-bit counters and timers are integrated, and provides periodic interrupts in the processing of the CPU 80a, a pulse output generation function (bit rate generator) with a constant period, and a time measurement function. In this example, the CTC 80e is used to issue timer interrupts (see FIG. 11 to be described later) to the CPU 80a at time intervals of 1.49 ms.

The counter circuit 81 is a circuit that generates a random number by hardware. The controller 80 (CPU 80a) uses random numbers generated by the counter circuit 81 to perform lottery processing.

The main control board 40 is provided with an interface between the controller 80 and each board shown in FIG.
The power supply interface 82 is an interface with the power supply circuit of the power supply board 41 .
The game interface 84 is an interface with the game relay board 60 . The controller 80 inputs detection signals from various switches and sensors, and transmits commands for LED control and blocker solenoid control via a game interface 84 .
The rotary drum motor drive unit 85 is an interface with the rotary drum relay board 53 . The controller 80 outputs motor drive signals to the stepping motors 54a, 54b, and 54c from the rotary drum motor drive section 85, and also receives input from the index sensors 55a, 55b, and 55c via the rotary drum motor drive section 85. Acquire the detection signal.
The performance control interface 86 is an interface for the controller 80 to send commands to the performance control board 42 via the performance interface board 43 . Specifically, it is an 8-bit parallel port, for example.
The payout connection interface 87 is an interface with the payout connection board 73 .

The external interface 88 is an interface with the hall computer via the external centralized terminal board 70 .
The drum setting interface 89 is an interface with the drum setting board 71 .

<3. Rotating reel>

Next, the rotating reels 4a, 4b and 4c will be described.
FIG. 8 is an explanatory diagram of a configuration related to origin detection for the rotary reels 4a, 4b, and 4c. Origin detection is detection of a specific position provided on each of the reels 4a, 4b, 4c, that is, the origin.
Since the configuration related to origin detection is the same for each of the rotating reels 4a to 4c, one rotating reel is illustrated as the rotating reel 4 as a representative here. 8A shows a perspective view of a configuration related to origin detection, and FIG. 8B shows a schematic cross-sectional view of the relationship between the detected portion 93d formed on the rotary reel 4 and the origin position 101. FIG.

In FIG. 8A, the rotation axis Ra, which is the central axis of the rotor 54r included in the stepping motor 54, is indicated by a dashed line. The rotating reel 4 includes a reel drum 90 that is rotationally driven around the rotation axis Ra, a backlight section 91 arranged inside the reel drum 90, and a base body that directly or indirectly supports the reel drum 90. 92.

The base body 92 is made of synthetic resin, for example, and has a substantially plate-like base plate 92b and a protrusion 92t that protrudes from the base plate 92b in the direction along the rotation axis Ra. The base plate 92b is arranged along one side (here, right side) of the reel drum 90 in the left-right direction. The stepping motor 54 is fixed to one side (here, the left side) of the base body 92 with the rotor 54r (rotating shaft Ra) facing one side (here, the left side) in the left-right direction.
In this case, the protrusion 92t protrudes leftward from the base plate 92b.

The reel drum 90 includes two reel frames 93 and 94 and a strip-shaped reel seat 95 cylindrically mounted on the outer peripheries of the reel frames 930 and 94 . The reel frames 93 and 94 are made of, for example, black synthetic resin that does not have light transmittance or has extremely low light transmittance, and the outer peripheral portions thereof are formed as rim portions 93r and 94r, respectively. A rim portion 93r of the reel frame 93 and a rim portion 94r of the reel frame 94 are formed in an annular shape along the left and right edges of the reel seat 95, respectively.
The reel frame 93 has a hub portion 93h detachably fixed to the rotor 54r of the stepping motor 54, and a plurality of spoke portions 93s radially connecting the rim portion 93r and the hub portion 93h. .

Here, in the case of this example, the reel frame 94 is not directly connected to the reel frame 94, and the rim portion 94r of the reel frame 94 is connected to the rim portion 93r of the reel frame 93 via the reel seat 95. (Of course, the rim portion 94r and the rim portion 93r can also be integrally connected, for example, at one or more points in the circumferential direction).

The reel sheet 95 is made of, for example, a colorless and transparent synthetic resin sheet and formed into a belt shape with a constant width, wound around the rims 93r and 94r of the reel frames 93 and 94, and adhered with an adhesive, for example. Although not shown in this drawing, a plurality of patterns are formed on the reel sheet 95 by printing.
The pattern forming area of the reel sheet 95 has a relatively high light transmittance, and emits light when the LEDs of the backlight section 91 are lit.

The index sensor 55 is composed of, for example, a transmissive photosensor, and as shown in the figure, is attached to the tip portion of a protruding portion 92t protruding from the base plate 92b to the reel drum 90 in this example. The index sensor 55 has a light-emitting portion 551 and a light-receiving portion 552 arranged so that the light-emitting surface and the light-receiving surface are opposed to each other in the radial direction of the reel frame 93 .

In the case of this example, a predetermined spoke portion 93 s of the reel drum 93 is formed with a detected portion 93 d projecting in a direction facing the index sensor 55 . The detected portion 93d is formed at a position passing through the space between the light emitting portion 551 and the light receiving portion 552 of the index sensor 55 as the reel drum 90 rotates.

With such a configuration, the index sensor 55 as a transmissive photosensor moves between the light-emitting portion 551 and the light-receiving portion 552 once per revolution of the reel drum 90 (rotary reel 4). A detection signal is obtained in which an ON pulse appears as a result of the passage of .

Here, as shown in FIG. 8B, the detected portion 93d has both edges (end portions) in a direction parallel to the rotation direction R (positive rotation direction), and one edge is positioned at the same rotation angle as the origin position 101. positioned to do so. Specifically, the detected portion 93 d of this example is positioned so that the edge on the side of the forward rotation direction (R) is positioned at the same rotation angle as the origin position 101 .

Note that the configuration for origin detection should not be limited to the one described above. For example, instead of the projection-shaped detected portion 93d, a configuration in which a detected portion is provided by a notch as disclosed in Japanese Patent Application Laid-Open No. 2014-33743 may be employed. In this case, the light-emitting portion 551 and the light-receiving portion 552 of the index sensor 55 should be arranged so that the light emitted by the light-emitting portion 551 is received by the light-receiving portion 552 when the notch portion arrives as the rotary reel 4 rotates. good.
The index sensor 55 is not limited to a transmissive photosensor, and a reflective photosensor can also be used.

Next, an example of the relationship between the drive system of the stepping motors 54a, 54b, 54c that rotate the reels 4a, 4b, 4c and the symbols formed on the reels 4a, 4b, 4c will be described.
In this embodiment, the stepping motors 54a, 54b, 54c are unipolar stepping motors, each having two center-tapped drive windings. In this embodiment, the stepping motors 54a, 54b, and 54c are driven by, for example, 1-2 phase excitation in which 1-phase excitation and 2-phase excitation are alternately repeated. A driving method using 1-2 phase excitation can realize smooth driving with half the step angle as compared with a driving method using 1-phase excitation or 2-phase excitation. The update period of the excitation pattern (excitation data) of the 1-2 phase excitation is set to 1.49 ms, which is the period of timer interrupt processing.

FIG. 9 is an explanatory diagram of the patterns formed on the rotating reels 4a, 4b, and 4c.
In this example, patterns for 21 frames are arranged along the rotation direction on the surfaces of the rotating reels 4a, 4b, and 4c. In each of the rotating reels 4a, 4b, and 4c, there are 10 types of symbols (red 7, white 7, bar, character, cherry, watermelon, bell, replay, lose 1, lose 2) in a predetermined order. are arranged in In the drawing, 21 symbols formed on the rotating reel 4a are represented as symbols 4a1, 4a2, . . . , 4a21. Similarly, the 21 symbols formed on the rotating reel 4b are represented by symbols 4b1, 4b2, . ing. The number attached to the end of the code of each design represents the number of that design.

On the reels 4a, 4b, and 4c, the symbols are arranged at regular intervals, and in the figure, the broken lines of the symbols are indicated by dashed lines. In the rotating reels 4a, 4b, and 4c, the origin position 101 is set at a predetermined pattern break position. The origin position 101 in this example is set at a pattern break position between the first patterns 4a1, 4b1 and 4c1 and the 21st patterns 4a21, 4b21 and 4c21.

The arrow R in the drawing represents the direction of rotation of the reels 4a, 4b, and 4c during steady rotation (forward rotation). As can be understood from this, the number assigned to each pattern indicates the order in which the pattern transitions during steady rotation with the origin position 101 as the starting point.

Here, in this example, the stepping motors 54a, 54b, 54c and the rotating reels 4a, 4b, 4c rotate so that the rotating reels 4a, 4b, 4c each rotate 1/63 when the stepping motors 54a, 54b, 54c make one rotation. A rotation ratio between is set. In other words, it is necessary to rotate the stepping motors 54a, 54b, 54c 63 times to rotate the reels 4a, 4b, 4c once.
In this example, the number of drive steps required to rotate the stepping motors 54a, 54b, and 54c once is eight steps. , 54c is 8×63=504.

Since 21 symbols are formed at regular intervals on the rotating reels 4a, 4b and 4c in this example, the number of steps per symbol is 504÷21=24 steps.
Accordingly, for each pattern, a total of 24 positions can be detected as step positions. Here, the step position in the pattern can be detected by decrementing (-1) the number of step in the pattern for each timer interrupt process described later with reference to FIG. That is, the number of detectable step positions in each pattern is 24 from No. 24 (first step position) to No. 1 (last step position). When the symbol step number is further decremented from the state of reaching the final step position (No. 1) of the symbol, the symbol step number returns to No. 24 (= No. 0).

For each symbol, a predetermined step position among the 24th (0) to 1st step positions is determined as a position (stop permission step position) at which the symbol should be allowed to stop. Specifically, the step position of No. 8 is determined as the stop permission step position of the symbol. When the spinning reel 4 is stopped, a stop symbol is determined, and the spinning reel 4 is stopped at the stop symbol. It is defined that the stop is permitted depending on reaching the step position of .

<4. Main control side startup processing>

Main control side startup processing executed by the CPU 80a in the main control board 40 (controller 80) will be described with reference to the flowchart of FIG.
This main control start-up process is executed by the CPU 80a in response to reset signals generated when the power is turned on and when the watchdog timer (WDT) in the controller 80 times out. That is, the main control-side start-up process is executed when the controller 80 is started when the power of the slot machine is turned on, and when the controller 80 is restarted when the operation of the controller 80 is stagnant for a predetermined time or longer due to some trouble.

In FIG. 10, the CPU 80a of the main control board 40 sets the interrupt processing mode to the initial mode as the interrupt mode setting processing in step S101. 8000) (initialization).

Next, the CPU 80a selects the random number circuit to be used and the latching method, and sets the random number latch interrupt prohibition as the random number setting process in step S103. Specifically, one random number circuit (for example, 0) is selected from four random number circuits (0 to 3), hard latch is selected as the latch direction, and an interrupt request is prohibited when a random number is captured. Make settings.
After that, the CPU 80a sets interrupt prohibition in step S104, prohibits access to the RAM 80c in step S105, and sets the sub-boot timer (about 1 second in this example) in step S106. In S107, it is determined whether or not there is an abnormality in the power supply. It should be noted that determination of whether or not there is a power failure is performed by determining whether or not a power failure signal Ev is input from the power supply substrate 41 described above.
If there is a power failure, the CPU 80a repeats the processing from step S101, and if there is no power failure, the CPU 80a proceeds to step S108 to clear the WDT, and then checks the value of the sub-boot timer in step S109. If the value of the sub-boot timer is other than 0, the CPU 80a repeats the process from step S107, and if the value of the sub-boot timer is 0, proceeds to step S110. That is, unless it is determined in step S107 that there is a power failure, a loop is formed in which the WDT clearing process in step S108 is repeated until the time set in the sub-boot timer setting process in step S106 elapses.

In step S110, the CPU 80a determines whether or not the externally input clock is abnormal as a process of determining whether or not the external clock is abnormal. If the external clock is abnormal, the CPU 80a executes operation stop error processing shown in FIG. 11 later.

If the external clock is not abnormal, the CPU 80a advances to step S111 to perform RAM access permission setting (permits access to the RAM 80c), and then receives signals from various sensors and switches in step S112. Specifically, a detection signal from the door opening sensor 35 and a signal from the setting key switch 72a are input.

In subsequent step S113, the CPU 80a determines whether or not the door (front panel 2) is open based on the detection signal from the door open sensor 35. FIG.
If the door is not open, the CPU 80a proceeds to step S115.
If the door is open, the CPU 80a proceeds to step S114 to determine whether the setting key switch 72a is ON. If the setting key switch is not ON, that is, if the door is open but the setting key ON operation has not been performed, the CPU 80a proceeds to step S115.
As can be understood from the above description, if the door is not opened in step S113, ON/OFF determination of the setting key switch 72a is not performed in step S114. In other words, the setting key operation in this case is treated as invalid. By invalidating the setting key operation when the door is not opened in this way, it is possible to prevent fraudulent acts such as falsification of the setting value vd.

In step S115, the CPU 80a determines whether or not the set value vd is within the proper range. Here, in the RAM 80c, an area for storing the set value vd is set in advance. In step S115, the set value vd stored in the predetermined area of the RAM 80c is read out, and the set value vd is within the proper range. (that is, in this example, whether the value is within the range of "0" to "5" corresponding to the setting "1" to "6").

If the set value vd is within the appropriate range, the CPU 80a determines whether the checksum is normal in step S116.
Here, when the power is turned off, the CPU 80a performs a process of calculating a checksum for a predetermined target area of the RAM 80c and storing it in a predetermined area of the RAM 80c (an area different from the above target area). In the process of step S116, the checksum is similarly calculated for the target area in the RAM 80c, and it is determined whether or not the calculated checksum matches the checksum stored in the predetermined area at the time of power shutdown.
If both checksums match (the checksum is normal), the identity of the data stored in the target area before the power shutdown has been proved. However, when the checksum calculation cannot be executed at the time of power shutdown, or even if it can be executed, the data in the target area is damaged or tampered with until the checksum calculation is executed in step S116. There is also In such a case, the determination result of step S116 is a mismatch.

In step S116, if both checksums match and are determined to be normal, the CPU 80a advances to step S117 to determine whether the stack pointer is normal or not.
Although not shown in the drawings, in the recovery process from power failure, various settings are made based on the information stored in the RAM 80c for returning to the state before the power interruption (so-called hot start). The CPU 80a shifts to a main loop process (FIG. 13), which will be described later, in response to executing the power failure recovery process.

Here, the CPU 80a determines that the external clock is abnormal in step S110, or determines that the set value vd is not within the proper range in step S115, or determines that the checksum is not normal in step S116. Otherwise, or if it is determined in step S117 that the stack pointer is not normal, the operation stop error processing shown in FIG. 11 is executed.

In the operation stop error processing shown in FIG. 11, the CPU 80a performs interrupt prohibition setting in step S201, timer interrupt prohibition setting and INT interrupt permission setting in subsequent step S202, and access to the RAM 80c is prohibited in step S203. Make settings to
Then, in subsequent step S204, the CPU 80a performs interrupt permission setting, and thereafter repeatedly executes the error display processing in step S205 (infinite loop). As the error display process, for example, a process for displaying a value representing a predetermined error code on the aforementioned payout display unit 10 is performed.

Thus, when an abnormality of the external clock, the set value vd, the checksum, or the stack pointer is detected in the start-up process of FIG.
When such operation stop error processing is executed, it is no longer possible to progress the game in the slot machine. In this sense, the operation stop error processing can be rephrased as disabling processing for disabling the progress of the game.

Here, by executing the above-described main control-side start-up process, for example, the set value vd may be illegally rewritten, and an inappropriate set value vd may be held (stored) in the RAM 82c at start-up. In this case, the progress of the game is disabled by operation stop error processing.
However, when the setting change operation is detected by the determination processing in steps S113 and S114 and the setting change process is executed, as will be understood from the later description, after the setting change process ends, the CPU 80a Since the process shifts to loop processing, the game can be progressed.
As can be understood from this, in the slot machine of this example, the disabling state of game progress is released on condition that an operation to change the set value vd is performed.

Here, in this example, when various abnormalities (errors) such as the set value vd and the checksum are detected, the CPU 80a controls the effect control command as an error command for notifying the error. Transmit to substrate 42 .

<5. Setting change processing>

When the CPU 80a determines that the setting key switch 72a is ON in step S114 shown in FIG. 10 (when the door is open and the setting key ON operation is performed), the setting change processing shown in FIG. to run.

In the setting change process shown in FIG. 12, the CPU 80a first executes a RAM clear process at the time of setting change in step S301. That is, the processing of clearing the area (not including the storage area of the set value vd) determined corresponding to the setting change in the RAM 80c is performed.
Then, in the next step S302, the CPU 80a sets the interrupt mode corresponding to the setting change process as the interrupt setting process.

In subsequent step S303, the CPU 80a reads out the set value vd stored in the RAM 80c, and in step S304, if the set value vd is greater than or equal to MAX ("5" corresponding to the setting "6" in this example), it is cleared to 0. process. This is because when the set value vd becomes "5" or more as the set value vd is incremented by 1 in response to the operation of the reset button in step S311, which will be described later, the set value vd is set to "0" (set to "1"). corresponding value).

In subsequent step S305, the CPU 80a sets a set value command. The set value command is a command for notifying the CPU 42a of the effect control board 42 of the set value vd stored in the RAM 80c. Commands are set in the transmission buffer in the effect control interface 86 (see FIG. 7).
The command set in the transmission buffer in this way is transmitted to the effect control board 42 side in the command output process (S505) of the timer interrupt process (FIG. 14) described later.

In response to executing the command setting process of step S305, the CPU 80a displays a value corresponding to the current set value vd on the display provided for the reel setting board 71 as the set value display process of step S306. Perform processing to display . The current set value vd referred to here means the set value vd specified in the command set in step S305.
Then, the CPU 80a performs update processing for the random number latched to 0 in step S103 as the random number update processing in subsequent step S307, performs standby processing for one timer interrupt in next step S308, and then performs step S309. proceed to

In step S309, the CPU 80a confirms ON/OFF of the start lever 17 (start switch). This corresponds to confirming whether or not there is an operation to confirm the set value vd.
If the start lever 17 is OFF, the CPU 80a advances to step S310 to check whether the reset button (reset switch 72b) is ON/OFF, that is, whether or not there is an operation to feed the set value vd, and if the reset button is OFF, step S307. return to random number update processing.
As a result, the random number update (S307) and the standby process for one timer interrupt (S308) are performed until either the set value vd is confirmed by the start lever 17 or the set value vd is sent by the reset button. Repeatedly.

In step S310, if the reset button is ON, the CPU 80a proceeds to step S311, increments (+1) the set value vd, and then returns to step S304.

In step S311, if the start lever 17 is ON, the CPU 80a proceeds to step S312 and sets the current set value vd (that is, the set value vd displayed in the most recent step S306) in a predetermined area of the RAM 82c ( remember).

When the setting value vd is set in the RAM 82c in step S312, the CPU 80a causes the setting value determination dot to be displayed in step S313. (For example, the numerical information being displayed on the display is blinked, or the display brightness is increased).

In subsequent steps S314 and S315, the CPU 80a waits for an operation to finish changing the set value vd. That is, after executing a process of waiting for one timer interruption in step S314, ON/OFF of the setting key switch 72a is checked in step S315, and if it is ON, the process returns to step S314.

If the setting key switch 72a is OFF, the CPU 80a advances to step S316, clears the numeric display on the display unit that executed the fixed display in the previous step S313, and sets a setting change end command in step S317. . This setting change end command is a command for notifying the effect control board 42 side that the change processing of the set value vd has ended.

The setting change process shown in this figure ends in response to execution of the command set process in step S317.
After completing the setting change process, the CPU 80a shifts to the main loop process shown in FIG.

<6. Main loop processing>

FIG. 13 is a flowchart of main loop processing executed by the CPU 80a of the main control board 40. As shown in FIG.
The CPU 80a repeats a series of processes represented by steps S401 to S417 as main loop processing. The main loop process is repeatedly executed for each game.
Note that the period of one game is from the occurrence of a trigger that allows the operation of the start lever 17 to be accepted until all the spinning reels 4a, 4b, 4c are stopped in response to the operation of the stop buttons 18a, 18b, 18c. is the period of As will be understood from the description below, in the case of this example, the trigger for accepting the operation of the start lever 17 is when the first medal is bet (maximum insertion button 16 and bets by pseudo-insertion during replaying are also possible). ) is the timing.

In the main loop processing, the CPU 80a first executes RAM initialization processing in step S401. That is, a predetermined area (an area defined to be cleared for each game) in the work area of the RAM 80c is cleared to zero.

In subsequent step S402, the CPU 80a generates a game state flag for the current game. The game state flag is a flag that specifies the current game state of the game. The game state indicates various game states such as "in bonus game", "in bonus internal winning", and "in normal game". Further, in step S402, a replay operation flag is generated which indicates whether or not the replay was won in the game immediately preceding the current game. The value of the replay operation flag is set to either "1" (ON) indicating replay winning or "0" (OFF) indicating replay non-winning.

Further, the CPU 80a executes game medal insertion processing in the next step S403. In other words, it is a process of managing the medals actually inserted from the medal slot 12, or the medals artificially inserted by pressing the max insertion button 16 or winning a replay, and managing the credits (stored medals). be.
It should be noted that the game medal insertion process of step S403 includes a determination process as to whether or not the start lever 17 has been turned ON, and the process ends under the condition that the start lever 17 has been turned ON.

When the game medal insertion process in step S403 ends, the CPU 80a executes internal lottery random number extraction process in step S404. Specifically, the counter value held in the counter circuit 81 is obtained. The obtained counter value is held at a predetermined address in the RAM 80c as a random value.

Then, in subsequent step S405, the CPU 80a determines whether or not the set value vd is within the appropriate range. Specifically, the setting value vd stored in the RAM 82c is a value corresponding to any one of setting "1" to setting "6", that is, a value within the range of "0" to "5". Determine whether or not there is

If the set value vd is not within the proper range, the CPU 80a executes the operation stop error processing described with reference to FIG.
That is, the CPU 80a determines whether or not the set value vd stored in the RAM 82a is within the appropriate range for each game through the process of step S405, and if the value is not within the appropriate range, the game operation is performed. Stops the progress of the game and disables the game progress.

On the other hand, if the set value vd is within the appropriate range, the CPU 80a proceeds to step S406 and executes internal lottery processing (symbol lottery processing) based on the stored random number value. In the symbol lottery process, it is determined whether or not a bonus symbol is won, whether or not a minor winning symbol is won, and whether or not a replay symbol indicating a replay is won or not, and a control command ( "Game start command") is set in the transmission buffer in the effect control interface 86, and is transmitted to the effect control board 42 side by the command output process (S505) of the timer interrupt process. That is, the effect control board 42 side is notified whether or not each symbol is won.
In addition, as the small winning design, for example, "cherry design" (4a10, 4b3, 4c9), "bell design" (4a4, 4b5, 4c3, etc.), "watermelon design" (4a9, 4b12, 4c1, etc.) are exemplified. can do.
Further, in the symbol lottery process, an "expectation effect command" is set in the transmission buffer based on the lottery result. The expectation effect command is a command for designating the content of the expectation effect that is executed at a predetermined timing during one game, such as at the start of a game, for example.

In response to execution of the internal lottery process in step S406, the CPU 80a executes reel effect lottery process for determining whether or not to execute reel effects in step S407. Incidentally, an effect that can be selected in the reel effect lottery process is determined according to the result of the internal lottery process. For example, if a predetermined symbol such as a "watermelon symbol" is in an internal winning state, it is possible to select a predetermined reel effect such as "slow effect of rotating very slowly in the positive direction and standing still" based on a predetermined probability of winning. It is

In response to executing the reel effect lottery process in step S407, the CPU 80a executes stop symbol determination initialization process in step S408, and determines (calculates) the stop position of the rotating reel 4 on which the stop operation has been performed. After initializing the various data used for , in the next step S409, a reel rotation start setting process is executed to start the rotation of the reels 4a to 4c.

The spinning drum rotation start setting process in step S409 differs depending on whether or not the reel effect lottery is won.
Here, the reel effect is executed at various timings, for example, according to the operation of the start lever 17. When the reel performance executed at the timing of the operation of the start lever 17 is won, the reel performance is executed in response to the operation of the start lever 17, and then the rotating reels 4a, 4b, 4c are temporarily stopped, After that, the rotating reels 4a, 4b, and 4c are again started (accelerated rotation) and transitioned to a steady rotation state at a constant speed.
If the reel effect lottery is won, in the drum rotation start setting process of step S409, various setting processes are performed for starting the rotating reels 4a, 4b, and 4c again toward the steady rotation state after the effect rotation. is executed.
On the other hand, if the reel effect lottery is not won, various settings for starting the rotating reels 4a, 4b, and 4c toward a steady state of rotation (state of rotation at a constant speed) are performed in the reel rotation start setting process of step S409. Processing is performed.

By the way, when a certain reel effect is executed in response to the operation of the start lever 17, the player can infer that a predetermined symbol corresponding to the type of reel effect is internally won. The player performs a stop operation so that the target symbols are aligned on the symbol stop line based on such reasoning. Only when the guess is correct and when the stop timing is appropriate, the internal winning state is activated and the predetermined medals are paid out.

After executing the drum rotation start setting process in step S409, the CPU 80a executes a drum stop process in step S410.
In the reel stop processing, processing for determining the stop symbols of the rotating reels 4a, 4b and 4c and stopping the rotating reels 4a, 4b and 4c at the stop symbols in accordance with the operation of the stop buttons 18a, 18b and 18c. Various data setting processing is performed for this purpose. In addition, in the spinning drum stopping process, the matching process of the symbols stopped on the symbol stopping line is also performed.

In the spinning reel stopping process, the corresponding rotating reel 4 among the rotating reels 4a, 4b, and 4c is controlled to stop in accordance with the result of the internal lottery process (S406). That is, if the result of the internal lottery process is that there is some kind of internal winning state, the symbols on the reels 4a, 4b, and 4c are aligned to match the winning result on the condition that the player performs an appropriate stop operation. However, if the timing at which the player presses the stop button 18 or the order of the stop operation is inappropriate, the game is stopped with a lost symbol. As a result, the winning of a small winning combination will be wasted, but the winning of the bonus will be carried over to the next and subsequent games.

The CPU 80a executes the winning judgment process in the subsequent step S411. That is, based on the result of the matching process in the spinning drum stop process of step S410, it is determined whether or not the winning symbols (winning combination) are aligned on the symbol stop line, and the number of medals to be paid out according to the determination result. Calculate
In the winning judgment process of step S411, the winning information command is sent to the production control board 42 to transmit the control command (winning information command) indicating the judgment result as to whether or not the winning symbols are aligned on the symbol stop line. A process of setting in the transmission buffer in is also performed.
In addition, in the winning determination process, a process of setting the number of payouts according to the winning information of the game in a predetermined area of the RAM 82c is also performed.

Further, in subsequent step S412, the CPU 80a counts the number of payout medals based on the detection signal of the medal payout sensor 76 and updates the value of the number of credits in accordance with the payout of medals, as medal payout number monitoring processing. At this time, when the number of payouts is set in the RAM 82c, the value of the number of credits is incremented by 1, and when the credits overflow, the payout control signal is turned ON to pay out the medals to the medal payout device 5. Let When the payout is completed, the payout control signal is turned OFF, and the medal payout number monitoring process ends.
Here, in the medal payout number monitoring process, in order to transmit a control command (payout command) indicating payout of medals or an increment of the number of credits to the production control board 42, there is also a process of setting the payout command in the transmission buffer of the production control interface 86. done. The payout command is set each time the number of credits is incremented and one medal is paid out from the hopper.

In step S413 following step S412, the CPU 80a executes a replay setting process. In the replay setting process, it is determined whether or not the replay winning state is established. If the replay winning state is established, at least a process of setting a replay movement flag is executed as a replay movement start process, and the process proceeds to step S414. If it is not in the replay winning state, the process proceeds to step S414 without executing the replay action start process (that is, without setting the replay action flag). It should be noted that the replay operation flag is used in the above-described game medal insertion process of step S403 to determine whether or not to execute the insertion process corresponding to the replay.

In step S414, the CPU 80a determines whether or not the bonus game is currently in progress. If the bonus game is in progress, the CPU 80a executes predetermined processing corresponding to the case in which the bonus is in operation as processing during bonus operation in step S416, and then returns to the previous step S401.

On the other hand, if the bonus game is not currently in progress, the CPU 80a determines in step S415 whether or not all bonus symbols are present. After executing various corresponding setting processes, the process returns to step S401.
If the bonus symbols are not aligned, the CPU 80a skips the bonus activation start process of step S417 and returns to step S401.

<7. Timer interrupt processing>

FIG. 14 is a flowchart of timer interrupt processing executed by the CPU 80a of the main control board 40. As shown in FIG. The timer interrupt process is activated every 1.49ms.
In FIG. 14, the CPU 80a first saves the value of the register in step S501 (register save processing), acquires the data of the input port that receives various switch signals and sensor signals in step S502, and stores the data in a predetermined area of the RAM 80c, for example. (port input processing). The sensor signals include the medal passing sensor 67, the medal payout sensor 76, the index sensors 55 of the first drum index sensor 55a, the second drum index sensor 55b, and the third drum index sensor 55c, the door sensor 66, and the like. Detected signals from are included. Also, in the port input process, a random number value is taken in from the counter circuit 81 .

Next, the CPU 80a executes drum rotation control processing in step S503. The drum rotation control process is based on the set data in the drum rotation start setting process (S409) and the drum stop process (S410) in the main loop process of FIG. , the excitation data to be output to the stepping motors 54a, 54b and 54c is set in the output buffer.

In subsequent step S504, the CPU 80a executes update processing for various target timers as regular update processing. In particular, in the case of this example, in the regular update process, the credit insertion interval timer (S810) set in the credit insertion detection process (S605) described later with reference to FIG. 17 and the replay medal insertion process described with reference to FIG. The input interval timer (S904) set in (S610) is updated.

In response to executing the regular update process in step S504, the CPU 80a executes command output process in step S505. That is, the control command set in the transmission buffer in the effect control interface 86 is output to the effect control board 42 for each byte.

In subsequent step S506, the CPU 80a updates the display operation of various lamps as display/motor output processing, and causes the drum motor driving section 85 to output the excitation data for each of the stepping motors 54a, 54b, and 54c set in step S503. When the excitation data is output to the stepping motors 54, each stepping motor enters a predetermined excitation state according to the excitation data, and the rotating reel 4 is rotated or stopped by updating the excitation data.

Further, the CPU 80a executes abnormality monitoring processing in the next step S507, and executes external information signal output processing in step S508. In the abnormality monitoring process of step S507, the presence or absence of an abnormality is determined based on the detection signals of the lever detection sensor 68, the medal payout sensor 76, and the door opening sensor 35, and processing is performed according to the determination result (for example, an effect for error notification). (including control command set processing). Further, the external information signal output processing in step S508 is processing related to information output via the external centralized terminal board 70 described above. do.

In subsequent step S509, the CPU 80a restores the register value saved in the previous step S501. The CPU 80a ends the timer interrupt process in response to executing the register return process in step S509.

<9. Production control side main processing and interrupt processing>

Next, various processes executed by the CPU 42a of the effect control board 42 will be described.
First, the effect control side main processing executed by the CPU 42a will be described with reference to the flowchart of FIG.
In FIG. 15, when the power of the slot machine is turned on, the CPU 42a executes effect initialization processing represented by a series of processing in steps S601 to S607. Then, after executing the effect initial setting process, the CPU 42a shifts to a periodic loop process (main loop process on the effect control side) according to the first period (period of 16 ms in this example) shown as the process of steps S608 to S620. do.

First, in the effect initial setting process, the CPU 42a first performs interrupt prohibition setting in step S601, sets its own setting to the initial setting in step S602, clears the value of WDT to 0 in step S603, and further continues in the following step. In S604, various data such as sound, motor, input/output, and scenario data are initialized. In the initialization process, the values stored in the RAM 42c are initialized in order to perform various effects such as a character effect on the LCD unit 7, a lamp effect that blinks the LED lamp, and a sound effect that drives the speaker. Execute.

Next, the CPU 42a executes backup restoration processing in step S605, clears the value of WDT to 0 in step S606, and sets interrupt permission in step S607. Thus, the effect initial setting process ends.
In the backup recovery process in step S605, checksum and power interruption flag confirmation process is performed. That is, confirmation processing of a checksum generated based on the data content in a predetermined target area of the RAM 42c and a checksum calculated and stored based on the data content in the target area of the RAM 42c when the power is turned off, and a checksum when the power is turned off. is stored in a predetermined area of the RAM 82c. The CPU 80a determines whether or not the backup can be restored based on the result of the confirmation process described above. Finish the recovery process. On the other hand, if it is determined that backup recovery is not possible, the CPU 42a initializes the value of the RAM 42c, sets a demonstration scenario in the work area of the RAM 42c, and finishes the backup recovery process.
In this example, when the RAM 42c is initialized because backup cannot be restored, a value representing "1" (that is, a value representing the lowest level) is set as the set value vd stored in the RAM 42 (work area).

Upon completion of the effect initial setting process of steps S601 to S607, the CPU 42a shifts to the main loop process of 16 ms period shown as the process of steps S608 to S620.
First, in step S608, the CPU 42a determines whether or not the value of the interrupt counter is greater than fifteen. The interrupt counter is a value that is reset to 0 in step S609 to be described below and that is successively incremented (+1) by timer interrupt processing with a period of 1 ms to be described later.
If the value of the interrupt counter is not greater than 15, the CPU 42a proceeds to step S620, updates the random number relating to the effect lottery, and returns to step S608.

On the other hand, if the value of the interrupt counter is greater than 15, the CPU 42a proceeds to step S609, resets the value of the interrupt counter to 0, executes the clearing process of WDT in step S610, and performs the effect control board in step S611. 42 is executed to detect various inputs.
Further, the CPU 42a executes predetermined processes as error processing in subsequent step S612 and demonstration processing in further subsequent step S613, and proceeds to step S614.
Here, in the error processing of step S612, the CPU 42a performs scenario registration processing for error reporting when various errors occur, error scenario clearing processing after error reporting, and the like. In particular, in the case of this embodiment, in step S612, the CPU 42a also performs processing for setting a volume MAX error flag according to the detection of a predetermined error. A volume MAX error means an error in which the volume of a sound (error sound) output in response to its occurrence should be maximized. If a volume MAX error is detected, that is, if an error sound should be output at MAX, the volume MAX error flag is set to 0x5A, for example, and if no volume MAX error is detected, the volume MAX error flag is set to 0x00, for example. set.

In step S614, the CPU 42a executes command analysis processing. In the command analysis process, the effect control command received from the CPU 80 of the main control board 40 is analyzed, and the process corresponding to the contents of the analyzed command is executed.
In the command analysis process, an example of the process to be executed for each command content will be described again with reference to FIGS. 17 and 18. FIG.

The CPU 42a executes scenario update processing in step S615 in response to executing the command analysis processing in step S614. In the scenario update process, based on the contents of the command analyzed in the command analysis process of step S614, the contents of the process (effect contents) to be executed by the CPU 42a are determined. Further, in the scenario update process, the scenario number (scenario data) is updated based on the contents of the process to be executed by the CPU 42a. The scenario number is a numerical value that can uniquely identify the effect executed by the CPU 42a.
In addition, in the case of realizing a series of effects by connecting a plurality of one effects specified from one scenario number, in the scenario update process of step S615, the effect duration and the elapsed time set for each effect are compared. , the process of updating to the next scenario number is performed at a predetermined timing.
Here, the scenario update processing in step S615 will be explained again later.

In addition, as a slot machine, the configuration may be such that the CPU 42a of the effect control board 42 performs a lottery as to whether or not to shift to the AT mode or the ART mode.
In this case, the lottery process for determining whether to shift to the AT mode or ART mode may be executed, for example, between the command analysis process in step S614 and the scenario update process in step S615. In this lottery process, a lottery is performed to determine whether or not to shift to the AT mode or the ART mode based on the set value vd received from the main control board 40 side and stored in the RAM 42c. is made to be the probability corresponding to the set value vd.

Subsequently, the CPU 42a executes sound reproduction processing in step S616. In this sound reproduction process, the CPU 42a outputs data such as a phrase number and volume to the sound source IC 42d according to the sound data registered for each sound channel in the work based on the scenario data. As a result, sound effects, music, voice, and the like are reproduced and output from the speaker 25 .
Note that this sound reproduction processing will be described again later.

In step S617 following step S616, the CPU 42a executes movable body error processing. Here, position error determination such as that the movable body to be driven by the movable body drive unit 102 is not returned to the origin is performed.

In step S618 following step S617, the CPU 42a executes liquid crystal/LED processing. In this liquid crystal/LED process, as a process related to the liquid crystal control board 44, a process of setting a control value for causing the liquid crystal control board 44 to execute a predetermined operation corresponding to the scenario number to the work area of the RAM 42c is executed. Further, as a process related to the LED, a process of generating drive data (LED drive data) for driving each LED in the LED board 48 and the first to third reel LED boards 50a to 50c is performed. In this example, a control value is set in the work area of the RAM 42c by sub-scenario update processing in FIG. (“Lamp data registration information” to be described later: see FIG. 23B). In step S618, the CPU 42a generates LED drive data based on the control values thus set in the work area.
The process of outputting the generated LED drive data to the LED board 48 and the reel LED relay board 56 is performed in an interrupt process with a period of 1 ms, which will be described later (see step S705).

Here, in this example, the process of setting the control value (motor control value) of the movable body driving unit 102 to the work area and the process of outputting the set value are performed in an interrupt process with a period of 1 ms, which will be described later (step S705).

In step S619 following step S618, the CPU 42a resets the scenario update counter to zero. The scenario update counter is a counter that is incremented by 1ms timer interrupt processing (FIG. 16), which will be described later.

In response to resetting the scenario update counter to zero in step S619, the CPU 42a executes the random number update process in step S620 described above, and returns to step S608.

By the processing of steps S608 to S620 described above, the processing of steps S609 to S619 is sequentially executed every time the value of the interrupt counter becomes greater than 15, that is, at a cycle of 16 ms.

In addition, as a slot machine, the configuration may be such that the CPU 42a of the effect control board 42 performs a lottery as to whether or not to shift to the AT mode or the ART mode.
In this case, the lottery process for determining whether to shift to the AT mode or ART mode may be executed, for example, between the command analysis process in step S614 and the scenario update process in step S615. In this lottery process, a lottery is performed to determine whether or not to shift to the AT mode or the ART mode based on the set value vd received from the main control board 40 side and stored in the RAM 42c. is made to be the probability corresponding to the set value vd.

Next, referring to FIG. 16, 1ms timer interrupt processing will be described. The CPU 42a executes the 1 ms timer interrupt process of FIG. 16 in response to an interrupt request generated every 1 ms by time counting.
In this 1 ms timer interrupt process, first, in step S701, it is determined whether or not the checksum is being calculated according to the test command from the main control CPU 100. If the checksum is not being calculated, the CPU 42a proceeds to the input processing of step S702.

The input processing in step S702 is processing every 1 ms for performing input detection by operation of the operator together with the input detection processing in step S611 of FIG. 15 described above. For example, in this input process, an input counter is reset when an edge is detected in the signal waveform of the operator operation detection signal, and then the input counter is counted up during a period in which no edge occurs. In the 1ms timer interrupt processing, input information (H or L of the input signal waveform) is detected, and depending on the presence or absence of an edge, the input counter is reset or incremented. Then, in step S611 in the main loop processing (16ms processing), when the value of the input counter is 16 or more and the input information has changed from the previous time, the input change is recognized.
Such input processing (S702) and input detection processing (S611) prevent erroneous input recognition due to noise chattering. Further, an input counter is used, and in the present embodiment, for example, a 16-bit counter is used to count up to 65535 ms (approximately 65 seconds), so that so-called long press can be detected.

In step S703, the CPU 42a performs motor operation update processing. In this case, the CPU 42a performs processing for creating motor drive data based on the motor data registered as the motor channel in the work (motor data registration information described in FIG. 23C) based on the scenario data. That is, it is motor driving data to be output to the driver circuit in the movable body driving section 102 . In this embodiment, the LED drive data is updated every 16 ms by step S618, while the motor data is updated every 1 ms.
In step S704, the CPU 42a outputs motor drive data. That is, it outputs motor drive data to the driver circuit in the movable body drive section 102 .

In step S705, the CPU 42a executes each process according to the value of the interrupt counter. The interrupt counter is reset to zero in step S609 of the 16 ms process described above and incremented in step S707 of the 1 ms timer interrupt process. Therefore, when step S705 is executed in the 1 ms timer interrupt process, the value of the interrupt counter is 0-15.
The processing of step S705 is defined as cases 0 to 15 according to the values 0 to 15 of the interrupt counter. For example, in this embodiment, in case 0, a WDT (watchdog timer) clear signal is turned ON and an initialization process of the LED driver is performed. In cases 1 to 3, initialization processing of the LED driver is performed. In case 8, the WDT clear signal is turned OFF. In cases 12 to 15, LED drive data is output to the LED driver.
Here, the initialization of the LED driver is a process of outputting default values to unused registers in the LED driver circuits of the LED board 48 and the first to third reel LED boards 50a to 50c. This initialization and the output of the LED driving data are performed for two or three driver circuits during one 1 ms timer interrupt process.

In step S706, the CPU 42a outputs a control command to the liquid crystal control board 52. FIG. For example, one command (2 bytes) is transmitted in one 1 ms timer interrupt process. That is, a 2-byte control command as mode and event is transmitted.
Thereafter, the CPU 42a increments the interrupt counter in step S707, and increments the scenario update counter in step S708. Then, if the value of the scenario update counter is less than 100, the 1ms timer interrupt processing is terminated.
Since the scenario update counter is reset to zero in step S619 of the 16 ms process as described above, the value of the scenario update counter does not normally reach 100 or more. The value of 100 or more occurs when the 16 ms process is not executed due to an operation error, process response error, or the like, or when a certain process within the 16 ms process stops progressing. In such a case, an infinite loop is entered to wait for the WDT to perform time-up processing.

If it is determined in step S701 that the checksum is being calculated when the 1ms timer interrupt process is entered, the CPU 42a advances the process to step S710 and clears the WDT. Then, in step S711, a control command is transmitted to the liquid crystal control board 44 and output. Then, in step S712, the interrupt counter is incremented, and the 1 ms timer interrupt processing ends.

<10. Processing Related to Production Control>
[10-1. Command analysis processing]

Next, the command analysis processing performed in step S614 in the 16 ms processing (FIG. 15) will be described with reference to FIGS. 17 and 18. FIG. CPU42a, as the command analysis processing of step S614, monitors whether or not the effect control command supplied from the main control board 40 is stored in the command reception buffer, and reads this command if the effect control command is stored. . As this specific process, steps S801 to S808 in FIG. 17 are performed.

The effect control board 42 is provided with a command reception buffer for taking in the effect control command transmitted from the main control board 40, for example, in the RAM 42c. First, in step S801 of FIG. 17, the CPU 42a confirms the read pointer indicating the read address of the command reception buffer and the write pointer indicating the write address.
The light pointer is updated in response to command reception, and accordingly, the received effect control commands are stored in the address indicated by the light pointer. The read pointer is updated (step S802) when reading from the command reception buffer is performed. Therefore, if the read pointer is not equal to the write pointer, the effect control command that has not yet been read is stored in the command reception buffer. If the read pointer is not equal to the write pointer, the process advances to step S802, and the CPU 42a loads 1-byte command data from the address indicated by the read pointer in the command reception buffer. In this case, the read pointer is incremented for the next read (load).

As described above, one effect control command is composed of two bytes, 1 byte as a mode and 1 byte as an event. In step S803, the CPU 42a confirms whether the loaded 1-byte command data is a mode or an event. This confirmation is performed by the value of Bit7 of the 8 bits (Bit0 to Bit7).
If it is in the mode, the process advances to step S804 as processing for receiving the upper data of the command, and the read command data is saved in the register "command HI byte". It also clears the "command LO byte" register. Then, the process returns to step S801.
Even after that, if the read pointer is not equal to the write pointer, it means that the effect control command that has not yet been read is stored in the command reception buffer. Load 1 byte of command data from address. It also increments the read pointer.
If the read command is an event, the process advances from step S803 to step S805 as processing for receiving lower order data of the command, and the read command data is saved in the register "command LO byte".

By saving the mode and event command data in the "command HI byte" and "command LO byte" registers, the CPU 42a has received one command.
Therefore, in step S806, the CPU 42a performs processing according to the received command. A specific example will be described later with reference to FIG.

The read pointer=write pointer is when the effect control command that the CPU 42a has not yet taken in does not exist in the command reception buffer. Therefore, if the read pointer is equal to the write pointer in step S801, no new fetching is necessary, so the CPU 42a ends the command analysis processing (S614) as shown.

An example of the command handling process in step S806 will be described with reference to FIG.
FIG. 18A shows basic processing as command handling processing. In response to the reception of the 2-byte effect control command, the CPU 42a first checks in step S821 of FIG. 18A whether or not it is currently in the test mode. If it is in the test mode, in step S822 all production scenarios are cleared, sound output is stopped, and the LEDs on the LED board 48 and the like are turned off. Then, in step S823, the test mode is terminated.
These processes are not performed unless in the test mode.
And CPU42a will perform the process about the taken-in production|presentation control command as step S830.

As production control commands, for example, the above-mentioned game start command, expectation production command,
Commands for notifying various errors, etc. are set in various ways. In step S830, the CPU 42a performs processing defined by the program in response to the received command. Here, in FIG. 18B and FIG. 18C, two production control commands are mentioned and specific processing is illustrated.

FIG. 18B shows processing S830a when a power-on command is received as command processing in step S830.
In this case, the CPU 42a clears the RAM 42c in step S837. For example, it clears the contents of the command reception/transmission buffer and the checksum storage area.
Then, in step S838, an error cancellation command is transmitted, in step S839, the movable body error information is cleared, in step S840, the motion of the movable body is stopped, in step S841, the scenario for power-on is registered, and in step S842, power-on is transmitted to the liquid crystal control board 44. Commands are set sequentially.

FIG. 18C shows processing S830b when a RAM clear command is received as command processing in step S830.
In this case, the CPU 42a clears the RAM 42c in step S843. For example, it clears the contents of the command reception/transmission buffer and the storage area of the checksum.
Then, in step S844, an error cancellation command is transmitted, and in step S845, RAM clear error setting and error notification timer setting are performed. Further, in step S846, the information on the lottery process in the RAM 42c is cleared, and in step S847, the information on the scenario is cleared. Then, in step S848, the initial power-on display (RAM clear) command to be transmitted to the liquid crystal control board 44 is set.

[10-2. Scenario registration/deletion process]

Next, scenario registration/deletion processing will be described. A scenario is data that defines various actions to be executed, such as performance control, error processing, and others. Data of the scenario to be executed is registered in the work area of the RAM 42c as scenario registration information. Although the structure of the scenario registration information shown in FIG. 23A will be described later, 64 scenario channels from 0 to 63 are prepared as the scenario registration information. Scenarios registered in these 64 scenario channels can be executed simultaneously. Hereafter, the scenario channel is denoted by "sCH".
The scenario registration process is a process of registering a scenario with a scenario number for which registration is requested in an arbitrary scenario channel sCH in the scenario registration information. In principle, any of the scenario channels sCH0 to sCH63 may be used.

Scenario registration, which will be described below, is invoked and executed when necessary during processing such as error processing in step S612, demonstration processing in step S613, and command analysis processing in step S614. For example, step S841 in FIG. 18B described above is an example of the case where scenario registration is executed.

As the process of FIG. 19, the CPU 42a performs a process of registering in the work (scenario registration information) a scenario number and a waiting time (delay) value corresponding to a scenario designated by a command or program.
In step S901, the CPU 42a first confirms whether or not the scenario number to be registered this time is normal. If the scenario number is an impossible number, the process ends without doing anything.

If the scenario number is correct, the CPU 42a sets the variable B to zero in step S902. Variable B is a variable used to sequentially search for an empty channel among scenario channels sCH0 to sCH63. Furthermore, the variable B also serves as a variable for judging whether or not there remains a scenario channel that has not yet been searched (confirmed whether or not it is a vacant channel).

In step S903, the CPU 42a confirms whether or not the "additional pointer"+B scenario channel is free. The additional pointer is a pointer set in step S907, which will be described later, when the scenario is registered. At the time when the processing of FIG. 19 is started, the value of the additional pointer is the value indicating the next scenario channel of the previously registered scenario channel. Note that the initial value of the additional pointer (the value when the process of FIG. 19 is performed for the first time from the initial state) is 0.
If the "additional pointer"+B scenario channel is not empty, the CPU 42a increments the variable B in step S904.
If B<64 is not satisfied in step S905, the process of FIG. 19 is terminated. This is a case in which, although all scenario channels have been searched, there are no free channels, making it impossible to register the scenario.
At the point in time when all scenario channels have not yet been searched (confirmed whether or not they are empty channels), B<64 in step S905. In that case, the confirmation process of step S906 is performed, and if the value of "addition pointer"+B is not equal to or greater than the value "64" exceeding the maximum value of the scenario channel sCH, the process returns to step S903.
If the value of "additional pointer"+B is greater than or equal to "64", the value of the additional pointer is corrected in step S907. Specifically, when the value of "additional pointer"+B becomes "64", the value of the additional pointer is subtracted by "64". Then, the process returns to step S903.

According to the processing of steps S903 to S907, it is confirmed whether or not the scenario channel is vacant in order from the scenario channel next to the previously registered scenario channel.
That is, by incrementing the variable B in step S904, the scenario channel sCH, which is confirmed each time step S903 is performed, advances one by one.
Also, since the variable B is reset to zero in step S902 and then incremented in step S904, if B<64 does not hold in step S905 (that is, if variable B reaches 64), step S903 has already occurred. is performed 64 times. This is the case when all scenario channels sCH0 to sCH63 have been checked and it is determined that there is no vacancy. Therefore, the process of FIG. 19 is terminated assuming that registration is impossible.

In addition, since the value of the "additional pointer" is a value indicating the next scenario channel of the previously registered scenario channel, even at the time of B<64 when all the scenario channels have not yet been checked for vacancy, the "additional pointer" + B (that is, the number of the scenario channel sCH to be checked next) may be "64" or more. Specifically, the value of "additional pointer"+B is 63 at the point of step S903 immediately before, and the variable B is incremented at step S904 after confirming the scenario channel sCH63. At this rate, the scenario channel sCH64, which does not exist next, will be specified.
Therefore, this point is confirmed in step S906, and if the value of "additional pointer"+B is "64", in step S907, the additional pointer is corrected in order to return the next scenario channel to be confirmed to "sCH0". conduct. That is, by subtracting -64 from the value of the additional pointer, the value of "additional pointer"+B becomes "0". Accordingly, in the next step S903, it is checked whether or not the scenario channel sCH0 is free.

When an empty scenario channel is found in the processing of step S903 at a certain point in time, the CPU 42a proceeds to step S908 and sets a scenario number and a waiting time (delay) to the empty scenario channel. It also clears the data necessary for other scenario management to zero.
Then, in step S909, the additional pointer is updated to the value of the registered scenario channel+1. That is, the value of the scenario channel next to the scenario channel registered this time is stored as an additional pointer so that it can be used in the next registration process. In this embodiment, the scenario channels are 64 channels sCH0 to sCH63, so the maximum value of the additional pointer is 63.

According to the process of FIG. 19, at the time of scenario registration, an empty channel is searched from the scenario channel next to the scenario channel registered last time. The initial value of the additional pointer is "0", and is then updated in step S907 according to the registration. According to this process, in many cases scenario registration is performed by using the scenario channel sCH0 in order. . At the time of scenario registration, vacancy confirmation is performed from the scenario channel next to the previously registered channel. Therefore, in most cases, a free channel can be found quickly, and scenario registration processing can be executed efficiently. This reduces the processing load on the CPU 42a.

As a modification of the process, the value of the additional pointer updated in step S907 may be set to the number of the registered scenario channel, and 1 may be substituted for the variable B in step S902. However, in that case, in step S905, it is determined whether or not B≤65.

Next, scenario deletion processing will be described. This is the process of deleting a scenario registered in a certain scenario channel of a work.
FIG. 20A shows the processing of the CPU 42a when deleting a certain scenario from the scenario registration information.
The CPU 42a starts the processing of FIG. 20A based on the value of the scenario number to be deleted (main scenario number (mcNo), which will be described later), which is specified by a command or program. First, in step S921, the CPU 42a confirms whether or not the scenario number related to the deletion request is normal. If the scenario number is an impossible number, the process ends without deletion.

If the scenario number is correct, the CPU 42a sets the variable B to zero in step S922. In this case, the variable B is a variable used to search for the channel in which the scenario to be deleted is registered among the scenario channels sCH0 to sCH63. Furthermore, the variable B also serves as a variable for determining whether or not there remains a scenario channel that has not yet been searched (confirmed whether or not a scenario to be deleted is registered).

In step S923, the CPU 42a confirms whether or not the scenario registered in area B, that is, scenario channel sCH(B), has the scenario number to be deleted. If the scenario registered in the scenario channel sCH(B) is not the scenario number to be deleted, the variable B is incremented in step S924, B<64 is confirmed in step S925, and the process of step S923 is performed. conduct.
According to the processing of steps S923 and S924, scenarios to be deleted are searched for in order from scenario channel sCH0 to scenario channel sCH63.
If the scenario registered in the scenario channel sCH(B) is the scenario number to be deleted in step S923, the process proceeds to step S926 to delete the scenario registered in the B area, that is, the scenario channel sCH(B). process.
As described above, the process of deleting the scenario of the requested scenario number from the work (scenario registration information) is performed.
If it is determined in step S925 that B<64 is not true, that is, if the variable B reaches 64, all of the scenario channels sCH0 to sCH63 have been searched, but the scenario to be deleted has not been registered. Therefore, the process ends.

FIG. 20B shows the process of deleting a range of scenarios. This processing is performed when the deletion scenario is specified by a range.
When a command or a program instructs deletion within a range of scenario numbers, the CPU 42a first sets the variable B to zero in step S931. In this case, the variable B is a variable used to search for a channel in which a scenario corresponding to the deletion target range is registered among the scenario channels sCH0 to sCH63. Furthermore, the variable B also serves as a variable for judging whether or not there remains a scenario channel that has not yet been searched (confirmed whether or not a scenario corresponding to the range to be deleted is registered).

In step S932, the CPU 42a confirms whether or not the scenario registered in area B, that is, scenario channel sCH(B), has a scenario number within the deletion target range. If the scenario registered in the scenario channel sCH(B) has a scenario number within the deletion target range, the scenario registered in the scenario channel sCH(B) is deleted in step S933. Then, the process proceeds to step S934.
If the scenario registered in the scenario channel sCH(B) is not within the range of scenario numbers to be deleted, the process proceeds to step S934 without performing step S933.
The CPU 42a increments the variable B in step S934, confirms that B<64 in step S935, and returns to step S932. If the variable B has reached 64, this means that all scenario channels sCH0 to sCH63 have been processed, so this scenario range deletion process ends.
As described above, one or more scenarios in the scenario number range are deleted from the work (scenario registration information).

FIG. 20C shows processing for deleting all registered scenarios. For example, this process is called when a scenario is unavoidably deleted for system reasons. It should be noted that the protected scenario should not be deleted.
When the deletion of all scenarios is requested, the CPU 42a first sets the variable B to zero in step S941. In this case, the variable B is a variable used to confirm the scenario channel in which the scenario to be protected is registered among the scenario channels sCH0 to sCH63. Furthermore, the variable B also serves as a variable for determining whether or not there are still scenario channels that have not yet been confirmed (confirmed whether or not a scenario to be protected is registered).

In step S942, the CPU 42a confirms whether or not the scenario registered in the B area, that is, the scenario channel sCH(B), is a scenario to be protected. If it is a protected scenario, it is not deleted. On the other hand, if it is not a protected scenario, the scenario registered in the scenario channel sCH(B) is deleted in step S943.
Then, the variable B is incremented in step S944, and if B<64 in step S945, the process returns to step S942. If the variable B has reached 64, it means that the processing for all scenario channels sCH0 to sCH63 has been completed, so this all scenario deletion processing ends.
As described above, all the scenarios registered as the scenario registration information in the work are deleted except for the scenarios to be protected.

[10-3. Scenario update process]

Next, the scenario updating process performed in step S615 of the 16 ms process (FIG. 15) will be described. In the scenario update process, the main scenario and sub-scenarios are updated as described with reference to FIGS. 21 and 22. FIG.

First, the structure of scenario registration information will be described with reference to FIGS. 23 and 24. FIG. FIG. 23A shows the structure of scenario registration information as a main scenario and sub-scenarios. This scenario registration information is set using the work area of the RAM 42c.
As described above, in this embodiment, the scenario registration information has 64 channels of scenario channels sCH0 to sCH63. Scenarios registered in each scenario channel sCH can be executed simultaneously.

As shown in the figure, information that can be registered in each scenario channel sCH includes a sub-scenario timer (scTm) used in sub-scenario update processing, a sub-scenario execution line (scIx) indicating the execution line of the sound/motor sub-scenario table, and a lamp sub-scenario. sub-scenario execution line lmp (lmpIx) indicating the execution line of the table, main scenario timer (msTm) used for scenario update processing, main scenario execution line (mcIx) indicating the execution line of the main scenario table, main scenario number (mcNo), There are main scenario option (mcOpt), user option (userFn), waiting time (delay), and checksum (checkSum), which are optional data that can be added to the main scenario.

When the sound output by the speaker 30 (30a to 30d), the light emission by the LED on the LED board 48 and the like, and the driving of the movable body by the movable body driving section 102 are started, the waiting time (delay) and the main scenario number (scNo) are set. is registered in an empty scenario channel among scenario channels sCH0 to sCH63.
The waiting time (delay) indicates the time from registration to the scenario channel sCH to the start of the scenario. Note that this waiting time (delay) is subtracted by 1 every 16 ms processing. When the waiting time (delay) is 0, the process corresponding to the registered data is executed.

FIG. 25 shows examples of scenario numbers 1, 2, and 3 as part of the main scenario table. As a scenario for each scenario number, the value of the main scenario timer (msTm) is described as time data in each line of the scenario, and the sub-scenario number (scNo) and option (OPT) can be described. . That is, in the main scenario table, sub-scenarios (and optionally options) to be executed are specified as time by the main scenario timer (msTm). A scenario data end code D_SEEND or a scenario data loop code D_SELOP is written in the last line of the scenario.
Note that the value of the main scenario timer (msTm) is incremented by 1 from the start of the main scenario due to scenario update processing performed in 16 ms processing, so "1" indicates 16 ms. The scenario table for each scenario number advances to the next row when the time of the main scenario timer (msTm) in a certain row has passed. Time data in each line indicates the timing at which the line ends.
For example, in the case of scenario number 2, the operation of sub-scenario number 2 is specified as the time of 1500×16 ms, the operation of sub-scenario number 20 is specified as the time of 500×16 ms, and the operation of sub-scenario number 20 is specified as the time of 2000×16 ms. The action of scenario number 21 is specified. The next line is the scenario data end code D_SEEND. If the scenario data end code is D_SEEND, this scenario is deleted from the scenario registration information (work) (see step S1017 in FIG. 21 to be described later).

Next, the structure of the lamp data registration information will be described with reference to FIG. 23B. As the lamp data registration information, a scenario selected from the lamp sub-scenario table, that is, information indicating the effect operation (lighting pattern) by the LEDs of the LED board 48 and the first to third drum LEDs 50a to 50c is registered. This lamp data registration information is also set using the work area of the RAM 42c.
In this embodiment, the lamp data registration information has 16 channels of lamp channels dwCH0 to dwCH15. A priority is set for each of the ramp channels dwCH0 to dwCH15, and the priority increases in order from the ramp channels dwCH0 to dwCH15. Therefore, the scenario (ramp sub-scenario) registered in the ramp channel dwCH15 is executed with the highest priority. For example, if scenarios are registered in ramp channels dwCH3 and dwCH10, the scenario registered in ramp channel dwCH10 is preferentially executed.
Ramp channel dwCH0 is mainly used for ramp effects associated with BGM (Background Music), ramp channel dwCH15 is used for error-related ramp effects, and ramp channels dwCH1 to dwCH14 are used for normal effects.

Information that can be registered in each lamp channel dwCH includes a registered lighting number (lmpNew) indicating the number of a registered lighting pattern, an execution lighting number (lmpNo) indicating the number of a lighting pattern to be executed, and a lamp sub-scenario. There is an offset (offset) that indicates an execution line, an execution time (time), and a checksum (checkSum).

FIG. 26A shows examples of lamp sub-scenario numbers 1, 2, and 3 as part of the lamp sub-scenario table. As the lamp sub-scenario of each number, a value of time data (time) is described in each line (row) of the scenario, and a lamp channel and a lamp number indicating various lighting patterns are described. A lamp scenario data end code D_LSEND is written in the last line.

In this ramp sub-scenario table, the time data (time) of each line indicates the start time of that line after the sub-scenario started.
The main scenario timer (msTm) is compared with the time data in the table every 16 ms, and if they match, the lamp number of that line is registered in the lamp data registration information in FIG. 23B. The registered lamp channel dwCH is the channel indicated on the line.
For example, assume that scenario number 2 shown in FIG. 25 is registered and sub-scenario number 2 is referenced in a certain scenario channel sCH described above. In lamp sub-scenario number 2 shown in FIG. 26A, lamp channel 5 (dwCH5) and lamp number 5 are described with time data (time)=0 on the first line. In this case, when the main scenario timer (msTm)=0, first, the information of the first line is registered as the registration lighting number (lmpNew)=5 in the lamp channel dwCH5 of the lamp data registration information in FIG. 23B. The value of the sub-scenario execution line lmp (lmpIx) of the scenario registration information (FIG. 23A) is updated to the value of the next line (second line). This is a registration for executing the lighting pattern operation of lighting number 5 with a relatively low priority of lamp channel dwCH5.
As for the second line, the same processing is performed when it reaches 500×16 ms. That is, the registered lighting number (lmpNew)=6 (that is, the lighting pattern of the lighting number 6) is registered in the lamp channel dwCH5 of the lamp data registration information.
If the time data (time) is the same value for two consecutive lines, the processing for each line will be started at the same time.
In the above-described liquid crystal/LED processing (S618), LED driving data is created based on the lamp data registration information updated in this way.

Next, the structure of motor data registration information will be described with reference to FIG. 23C. Information indicating a scenario selected from a sound/motor sub-scenario table (described later in FIG. 26B) is registered as the motor data registration information. This motor data registration information is also set using the work area of the RAM 42c. Note that the motor here is an example of an actuator for driving the movable body that the movable body driving section 102 has.
In this embodiment, the motor data registration information has eight channels of motor channels mCH0 to mCH7.
Information that can be registered in each motor channel mCH includes the execution operation number (no), registered operation number (noNew), operation count (lcnt), excitation counter (tcnt), execution step (step), and operation line, as shown in the figure. (offset), parent (source)/child (destination) attribute (attribute), parent number (retNo), return address (retAddr), loop start point (roopAddr), loop count (roopCnt), error counter (errCnt) ), current input information (currentSw), software switch information (softSw), and software count (softCnt).

FIG. 24 shows sound data registration information. Information indicating a scenario selected from a sound/motor sub-scenario table (described later in FIG. 26B) is registered as the sound data registration information. This sound data registration information is also set using the work area of the RAM 42c.
In this embodiment, the sound data registration information has 16 sound channels aCH0 to aCH15. Each of these sound channels aCH0 to aCH15 corresponds to each of the input channels (same 16 channels) of the sound source IC 42d.
Information that can be registered in each sound channel aCH includes primary volume transition amount (frzVq), primary volume (frzVl), transition amount change (rsv2), volume change (rsv1), phrase change (rsv0), as shown in the figure. , stereo (frzSt), loop (frzLp), phrase number hi (frzHi), phrase number low (frzLo), and secondary volume (scdVl).

Here, the primary volume (first volume) is written in scenario data (BGM, SE1, SE2, error, which will be described later) that instructs the start of reproduction of a certain phrase, together with information on the phrase number of the phrase to be reproduced. volume information.
The secondary volume (second volume) is volume information that determines the final reproduction volume by multiplying it with the primary volume.
The difference between primary and secondary volumes is as follows.
The primary volume is also described in the scenario data instructing the start of playback of the phrase as described above, while the secondary volume is described in the scenario data of sound control (sound control information), which will be described later.
Further, in the case of this embodiment, depending on the primary volume, by combining with the information of the primary volume transition amount (frzVq), volume control for the phrase being reproduced is enabled, and the phrase is controlled by controlling the primary volume. fade-in reproduction/fade-out reproduction is possible. As will be described later, these fade-in reproduction/fade-out reproduction instructions are executed based on scenario data as sound control.
The secondary volume is normally set to a value that corresponds to the state of the volume switch provided on the back of the slot machine, and is set to a value different from the MAX value in the event of an error or when a desired phrase is to be muted, as will be described later. is set.
Instructions for changing the secondary volume can also be made by scenario data as sound control (this point will also be described later).

The primary volume transition amount frzVq is information representing the time (speed) at which the primary volume is changed.
The transition amount change rsv2 is information indicating whether or not to change the primary volume transition amount frzVq, and the volume change rsv1 is information indicating whether or not the primary volume is to be changed during phrase reproduction. Phrase change rsv0 is information indicating whether or not to rewrite the phrase number, stereo frzSt indicates either stereo playback or monaural playback, and loop frzLp indicates either infinite loop playback or no loop playback. information to represent.

As illustrated, the data size of the primary volume transition amount, primary volume, and secondary volume are each 1 byte (8 bits). Also, each information of transition amount change, volume change, phrase change, stereo, and loop is 1 bit. Furthermore, the phrase number hi is 3 bits, and the phrase number low is 1 byte. That is, the information of the phrase number consists of 11 bits, so that it is possible to designate up to 2048 phrases.

Here, in this example, in the case of stereo reproduction, two adjacent sound channels aCH are used. Specifically, the even-numbered sound channel aCHn and the next odd-numbered sound channel aCHn+1 are used.
Scenario data for instructing stereo reproduction includes phrase number information for designating a phrase to be reproduced in stereo (single phrase number common to Lch and Rch is used as designation information) and designation of stereo reproduction. Based on the scenario data, these phrase numbers and instruction information for stereo reproduction are registered in the even-numbered sound channel aCHn and the odd-numbered sound channel aCHn+1 in the sound data registration information (described above). phrase numbers hi, low and stereo frzSt).

FIG. 26B shows examples of sound/motor sub-scenario numbers 1 and 2 as part of the sound/motor sub-scenario table.
As the sound/motor sub-scenario of each number, the time data (time) value (ms) is described in each line (row) of the scenario, and BGM, SE1, SE2, error sound, sound control, motor, solenoid / User option information can be described. A scenario data end code D_SEEND is written in the last line.
Regarding this sound/motor sub-scenario table, when the value of the sub-scenario timer (scTm) reaches the value of the time data (time) described in a certain line in the sound/motor sub-scenario table (it is initially 0). ), the BGM, SE1, SE2, error sound, sound control, motor, solenoid/information according to the user option described in that line is registered in the sound data registration information and the motor data registration information.
The time data (time) of each line indicates the timing at which the line ends.

Here, the SEs (SE1 and SE2) in the sound/motor sub-scenario table mean sounds related to effects other than BGM and error sounds. A so-called sound for the announcement effect (announcement sound) is classified into this SE.
The distinction between SE1 and SE2 is made according to the appearance frequency of the effect that outputs the sound. For example, in the case of a notice sound, the distinction is made according to the appearance frequency (reliability) of the notice effect using that sound. In the case of this example, SE2 is a sound associated with an effect that appears less frequently than SE1.

Each piece of information of BGM, SE1, SE2, and error sound in the sound/motor sub-scenario table includes the phrase number and primary volume information.
Information on the BGM, SE1, SE2, and error sound described in these sound/motor sub-scenario tables is registered in any sound channel aCH in the sound data registration information. , SE1, SE2, and an error sound, the sound channel aCH for registering the information content is determined in advance.
Specifically, the BGM information described in the sound/motor sub-scenario table is registered in the sound channel aCH0 (additionally aCH1 in the case of stereo). Information on SE1 is registered in an empty channel among sound channels aCH2 to aCH9, and information on SE2 is registered in an empty channel among sound channels aCH10 to aCH14. Furthermore, the error sound information is registered in the sound channel aCH15.
As described above, in this embodiment, the correspondence relationship between the type of sound and the sound channel aCH for registering sound-related information about the sound is determined in advance.

The sound control information in the sound/motor sub-scenario table describes information for controlling the phrase being reproduced.
In the case of this embodiment, the sound control information consists of 4 bytes, the lower 3 bytes being information for designating the phrase to be controlled, and the upper 1 byte being control information (information representing the content of sound control). ing.

Here, in this embodiment, the correspondence between the type of sound and the sound channel aCH in which information about the sound is registered is defined as described above. In the case of stereo, aCH0 and aCH1) are reproduced, the phrase as SE1 is reproduced in any of the sound channels aCH2 to aCH9, the phrase as SE2 is reproduced in any of the sound channels aCH10 to aCH14, and the error sound is In other words, it is uniquely determined that the phrase is reproduced on the sound channel aCH15.
Therefore, when a predetermined type of sound (BGM/SE1/SE2/error sound) is to be controlled based on the sound control information, the sound control information should be registered for the sound channel aCH corresponding to the sound. Just do it.
In view of this point, in the sound control information of the present embodiment, the lower 3-byte information, that is, the information specifying the sound channel aCH is described as the information for specifying the phrase to be controlled. In other words, the sound channel aCH where the sound (phrase) to be controlled is reproduced (that is, aCH0 (and aCH1) corresponding to BGM/SE1/SE2/error sound/aCH2 to aCH9/aCH10 to aCH14/aCH15) The specified information is described.

The specific processing for registering the information of BGM, SE1, SE2, error sound, and sound control described in the sound/motor sub-scenario table in the work as the sound data registration information is shown in FIGS. 27 to 31. will be described later.

Here, as described above, in the present embodiment, the correspondence relationship between the type of sound and the sound channel aCH for registering information about the sound is determined in advance, so that a sound of a certain type can be reproduced. The sound channel aCH to be transmitted can be uniquely determined. As a result, when a certain type of sound being reproduced is to be controlled, it is sufficient to register control information for the sound channel aCH associated with that type of sound in the work, and the sound to be controlled is reproduced. It may not be necessary to search for the sound channel aCH in the middle.
Therefore, the control load related to the performance operation can be reduced by the amount of the search processing being omitted.

Further, as described above, in the present embodiment, sound control information for controlling the sound being reproduced consists of information representing the content of the control and information representing the sound channel aCH corresponding to the sound to be controlled. Combined information.
By making the sound control information such that it is possible to specify the sound channel aCH in which the control content information is registered, it is possible to eliminate the need to search for the sound channel aCH in which the sound to be controlled is being reproduced. That is, the fact that the sound control information is configured in this manner also contributes to the omission of the search process, that is, to the reduction of the control load related to the performance operation.

Returning to FIG. 26B.
In the sound/motor sub-scenario table, the motor data is structured such that one byte per motor indicates the motor operation pattern number.
This operation pattern number is set for the motor channel corresponding to the motor number.

In the sound reproduction process described as step S616 in FIG. 15, reproduction output is performed based on the sound data registration information updated by the scenario update process in FIGS.
Further, in the motor operation update process in step S703 of FIG. 16, motor drive data is created based on the motor data registration information updated in the scenario update process of FIGS.

Scenario update processing executed using each piece of information described so far will be described with reference to FIGS. 21 and 22. FIG.
In the scenario updating process of FIG. 21 executed as step S615 of the 16 ms process of FIG. 15, the CPU 42a performs steps S1000 to S1016 for each of the scenario channels sCH0 to sCH63 as loop process LP1. A scenario channel to be processed each time of the loop processing will be described as "sCHn".

The CPU 42a confirms whether or not the main scenario number of the scenario channel sCHn is 0 in step S1000. If the main scenario number is 0, the scenario channel sCHn is a channel sCH for which no main scenario has been registered in the scenario registration process of FIG. Therefore, in this case, the processing after step S1015 is executed and the processing ends. Specifically, the checksum of the scenario channel sCHn-related data is calculated and saved in step S1015, and then the scenario channel sCHn-related data is backed up and saved in step S1016. This completes one process for the scenario channel sCHn.

On the other hand, if it is determined in step S1000 that the main scenario number is not 0, the flow advances to step S1001 to check the waiting time (delay) of scenario channel sCHn. If the waiting time (delay) is not 0, the value of the waiting time (delay) is decremented by -1 in step S1002. Then, the processes of steps S1015 and S1016 are executed, and one process for the scenario channel sCHn is completed.

If it is confirmed in step S1001 that the waiting time (delay)=0, the CPU 42a advances to step S1003, where the main scenario number (mcNo) registered in the scenario channel sCHn and the main scenario execution line (mcIx) are displayed. Identify the address of the main scenario table corresponding to .
In step S1004, it is checked whether or not the execution line of a certain main scenario number in the main scenario table indicated by the specified address is the last line describing the end code D_SEEND (see FIG. 25).
If the end code matches the last line in which the end code is written, it means that the process to be executed in the scenario registered in the scenario channel sCHn has been completed. is deleted from the scenario registration information (work).
The deletion of the scenario registration in this case is normal deletion corresponding to the end of the scenario. It should be added that the scenario deletion described above with reference to FIG. 20 is a process of deleting, for example, an unfinished scenario other than the normal deletion from the scenario registration information (work).

After deleting the scenario in step S1017, the process proceeds to step S1015.

In step S1004, if the line of the main scenario table is not the end code, the CPU 42a proceeds to step S1005 and first sets the main scenario option (mcOpt) of the scenario channel sCHn to the option (OPT) of the line. Next, in step S1007, 0 is substituted for the user option (userFn).
Then, in step S1008, the sub-scenario specified by the scenario channel sCHn is updated. The updating of sub-scenarios will be described later with reference to FIG.

In step S1009, the CPU 42a increments the main scenario timer (msTm) by +1. Then, in step S1010, the value of the main scenario timer (msTm) is compared with the time data of the corresponding line in the main scenario table (see FIG. 25: described in msTm). As mentioned earlier, the time data of each line of the main scenario table defines the end timing of that line, so the value of the main scenario timer (msTm) is written in the line of the main scenario table. If it is equal to or greater than the time data, the processing of that line ends and the next line is processed. Therefore, if it is determined in step S1010 that the value of the main scenario timer (msTm) is greater than or equal to the time data described in the line of the main scenario table, the process advances to step S1011 to enter the main scenario execution line (mcIx) of scenario channel sCHn. ) is incremented by 1. In other words, next time, the next line is targeted.
Also, if it is determined in step S1010 that the value of the main scenario timer (msTm) is not greater than the time data described in the line of the main scenario table, the process proceeds to step S1015.

After the main scenario execution line (mcIx) of the scenario channel sCHn is incremented by 1 in step S1011, it is checked in step S1012 if the next line is a loop designation. In the scenario number 1 in the main scenario table of FIG. 25, an example is shown in which the final line is the scenario data loop code D_SELOP. mcIx) to set the loop line.
If it is determined in step S1012 that the next line is not a loop specification, the process proceeds to step S1014 without going through step S1013.

In step S1014, the CPU 42a performs a clear process according to the end of one line. Main scenario timer (msTm), sub-scenario timer (scTm), sub-scenario execution line (scIx), sub-scenario execution line lmp (lmpIx), main scenario option (mcOpt), user option (userFn), waiting time (delay) to clear.
Then, the checksum process in step S1015 and the backup process in step S1016 are performed, and one process for the scenario channel sCHn is completed.
As the scenario updating process, the above process is executed for each of the scenario channels sCH0 to sCH63 as the loop process LP1.

The sub-scenario update process performed in step S1008 is shown in detail in FIG. 22A.
Based on the main scenario timer (msTm), the scenario channel sCHn, and the sub-scenario number (scNo) described in the main scenario table, the sub-scenario update process of FIG. 22A is performed.

First, in step S1021, the CPU 42a confirms whether or not the scenario channel sCHn indicates any one of 0 to 63, that is, whether or not it is an appropriate value. If the scenario channel sCHn is 64 or more, the process of FIG. 22 is terminated assuming that the update process is impossible.
If the scenario channel sCHn is a proper value, the CPU 42a specifies the address of the lamp sub-scenario table (see FIG. 26A) corresponding to the sub-scenario number (scNo) and the sub-scenario execution line lmp (lmpIx) in step S1022.

The CPU 42a sets the lamp channel count value to 0 in step S1023. This lamp channel count value is a value managed by the CPU 42a to prevent the registration of lighting pattern numbers in the lamp data registration information from being performed an abnormal number of times exceeding the number of lamp channels dwCH (16). .

Then, in step S1024, the CPU 42a compares the main scenario timer (msTm) with the time data (time) of the lamp sub-scenario table. The time data (time) of the lamp sub-scenario table indicates the time (ms) at which the line (the line indicated by the sub-scenario execution line lmp (lmpIx)) is started. Therefore, if the time of the main scenario timer (actually msTm×16 ms) is longer than the time data (time), the line is processed. In that case, it is checked in step S1025 whether or not the lamp channel count value is normal (within "16" which is the number of lamp channels dwCH). If the value is abnormal, the process is terminated. If the value is normal, it is checked in step S1026 whether or not the current line is the line in which the lamp scenario data end code D_LSEND is described.

If the line does not describe the lamp scenario data end code D_LSEND, the CPU 42a acquires the lamp channel and lamp number described in the line in step S1027. Then, in step S1028, the lighting pattern number is registered.
FIG. 22B shows the lighting pattern number registration process. In this case, the CPU 42a first determines in step S1051 whether or not the value of the ramp channel dwCH described in the line is normal. If the value is not normal, the process ends without registration.
If the value is normal, it is determined in step S1052 whether or not the lamp number described in the line is normal. If the value is not normal, the process ends without registration.
If both the lamp channel dwCH and the lamp number are normal values, the registered lighting number (lmpNew) and the execution lighting number (lmpNo) are set in the area corresponding to the lamp channel dwCH in the lamp data registration information of the work in step S1053. do. That is, the lamp number acquired from the corresponding line of the lamp sub-scenario table is set as the registered lighting number (lmpNew), and "0" is set as the execution lighting number (lmpNo).
22B is performed in step S1028, the CPU 42a increments the value of the sub-scenario execution line lmp (lmpIx) by 1 in step S1029, increments the lamp channel count value by 1 in step S1030, and returns to step S1024.

When the time of the main scenario timer has not reached the time data (time) of the line indicated by the sub-scenario execution line lmp (lmpIx) in step S1024, and when the lamp scenario data end code D_LSEND is confirmed in step S1026. , the process of the CPU 42a proceeds to step S1031.

In step S1031, the sub-scenario number described in the main scenario table and the address of the sound/motor sub-scenario table corresponding to the sub-scenario execution line (scIx) registered in the currently processed scenario channel sCHn are specified. .
Then, in step S1032, it is confirmed whether or not the value of the sub-scenario timer (scTm) is greater than or equal to the value of the time data (time) in the table. That is, it checks whether the value of the sub-scenario timer (scTm) is equal to or greater than the value of the time data (time) of the line indicated by the sub-scenario execution line (sclx) registered in the scenario channel sCHn currently being processed. confirm.

In step S1032, if the value of the sub-scenario timer (scTm) is not equal to or greater than the value of the time data (time) in the table, the registration processing for the information described in that line should not be executed yet. Without registering the sound and motor, the process proceeds to step S1040, increments (+1) the value of the sub-scenario timer (scTm), and terminates the processing of FIG. 22A.

On the other hand, if the value of the sub-scenario timer (scTm) is equal to or greater than the value of the time data (time) of the table in step S1032, the CPU 42a advances the process to step S1033, and the sub-scenario number of the corresponding sound/motor sub-scenario number table. Confirm whether the line indicated by the scenario execution line (scIx) is the line in which the scenario data end code D_SEEND is described. If the line describes the scenario data end code D_SEEND, the process ends.
If the line does not contain the scenario data end code D_SEEND, the CPU 42a registers the sound in step S1035, and registers the motor in step S1036. As the registration processing in steps S1035 and S1036, the information of the corresponding line of the corresponding sub-scenario number in the sound/motor sub-scenario table shown in FIG. 26B is registered as the sound channel aCH of the sound data registration information in FIG. are registered in the motor channel mCH of the motor data registration information.
Note that the detailed processing contents of the sound registration executed in step S1035 will be described later (FIGS. 27 to 31).

Subsequently, in step S1037, the CPU 42a registers the solenoid/user option information described in the line in the scenario registration information or the like.
Then, in step S1038, the value of the next line is set as the value of the sub-scenario execution line (scIx). Further, in step S1040, the sub-scenario timer (scTm) is incremented and the process ends.

At step S615 in FIG. 15, the processes in FIGS. 21 and 22 are performed. In this process, the scenario registration information, lamp data registration information, motor data registration information, and sound data registration information on the workpiece are successively updated, and the production control is performed accordingly, thereby realizing the production operation according to the scenario. be.

Here, in the present embodiment, scenario registration information is set in the first work area (scenario channels sCH0 to sCH63) as effect data specifying the effect type. Specifically, a main scenario number (mcNo) is set to specify a sub-scenario on the main scenario table. Further, in the first work area, a sub-scenario execution line (scIx) indicating the execution line of the sound/motor sub-scenario table and a sub-scenario execution line lmp (lmpIx) indicating the execution line of the lamp sub-scenario table are set. The effect type is specified by these.
Operation data of the effect device corresponding to the effect to be executed is set in the second work area. Lamp channels dwCH1 to dwCH15 for setting lamp data registration information, motor channels mCH0 to mCH7 for setting motor data registration information, and sound channels aCH0 to aCH15 for setting sound data registration information are prepared as a second work area.
That is, in the present embodiment, overall performance data using various performance devices is set in the first work area, and action data is set in the second work area based on the performance data in the first work area. will be
In this case, in order to set various effects, it is preferable to relatively increase the number of effect data (the number of pieces of scenario registration information) that can be registered in the first work area. For example, you want to increase the number of registered channels for performance data. Therefore, 64 channels are prepared as scenario channels sCH0 to sCH63.
On the other hand, the number of pieces of motion data that can be registered may be relatively small, since it is only necessary to set the motion data that defines the motion of the effect device in the second work area. In particular, since the second work area is provided corresponding to each effect device of the lamp, motor, and sound, it is not necessary to increase the number of possible registrations for each device. Therefore, the second work area has 16 lamp channels (dwCH1 to dwCH15), 8 motor channels (mCH0 to mCH7), and 16 sound channels (aCH0 to aCH15). Since it suffices to set the operation data for one corresponding effect device, even if the number of registered channels is small, a sufficiently wide variety of effect operations can be handled.
Thus, if the number of channels in the first work area is N (for example, N=64) and the number of channels in the second work area is M (for example, M=16 or M=8), then N>M. Allocate storage as follows:
This keeps the memory from being consumed blindly while still allowing a variety of effects.

[10-4. Sound registration processing]

Next, the sound registration process executed in step S1035 of FIG. 22 will be described.
This sound registration process is a process of registering information corresponding to the description contents (sub-scenario data) of the sound/motor sub-scenario table illustrated in FIG. 26B in the sound channel aCH of the sound data registration information in FIG.

FIG. 27 shows the sound registration process.
First, in step S1100, the CPU 42a determines whether sound data exists in the sound/motor sub-scenario table. That is, it is determined whether or not any of the information of BGM/SE1/SE2/error sound/sound control exists as description information of the corresponding line of the corresponding sub-scenario number in the sound/motor sub-scenario table.
If these sound data do not exist, the processing ends.

On the other hand, if any of these sound data exists, the CPU 42a determines whether or not it is BGM in step S1101. If the sound data is BGM, the CPU 42a sets the sound data of the sound/motor sub-scenario table to the sound channel aCH0 in step S1106. That is, the BGM information described in the line corresponding to the sub-scenario number of the sound/motor sub-scenario table is registered in the sound channel aCH0 as the sound channel aCH associated with the BGM in the sound data registration information.
As described above, when the sound data is BGM, SE1, SE2, and error sound, the description contents (that is, scenario data) include at least the phrase number of the phrase to be reproduced and the information of the primary volume. Therefore, these information are registered in the sound data registration information.
It should be noted that the BGM can be reproduced in stereo, and in that case, the BGM information in the sound/motor sub-scenario table indicates this. As mentioned above, when BGM is reproduced in stereo, not only sound channel aCH0 but also sound channel aCH1 is used. In this case, in both of these sound channels aCH0 and aCH1, common phrase numbers described in the BGM information are registered as phrase numbers (frzHi, frzLo), and "1" is registered as stereo (frzSt) information. Described.

If BGM sound data is set in step S1106, or if the sound data is not BGM in step S1101, the CPU 42a determines in step S1102 whether or not the sound data is an error sound. At step S1107, the sound data of the sound/motor sub-scenario table is set to the sound channel aCH15. That is, information corresponding to the description content of the sub-scenario data is registered in the sound channel aCH15 as the sound channel aCH corresponding to the error sound.

If the sound data of an error sound is set in step S1107, or if the sound data is determined not to be an error sound in step S1102, the CPU 42a determines in step S1103 whether or not the sound data is SE1. In step S1108, SE1 setting processing is performed.
If SE1 setting processing is executed in step S1108, or if the sound data is not SE1 in step S1103, the CPU 42a determines in step S1104 whether or not the sound data is SE2. In step S1109, SE2 setting processing is performed.
Further, if SE2 setting processing is executed in step S1109, or if the sound data is not SE2 in step S1104, the CPU 42a determines in step S1105 whether or not the sound data is sound control. If so, sound control setting processing is performed in step S1110.
If the sound control setting process is executed in step S1110, or if the sound data is determined not to be sound control in step S1105, the CPU 42a finishes the process shown in FIG.

The contents of the SE1 setting process, the SE2 setting process, and the sound control setting process executed in steps S1108, S1109, and S1110 will be individually described below.

First, the contents of SE1 setting processing and SE2 setting processing executed in steps S1108 and S1109, respectively, will be described with reference to FIG.
Note that the contents of the setting processing of SE1 and the setting processing of SE2 are common except that the sound channel aCH (corresponding sound channel aCH) to be registered as sound data is different. and

First, in step S1201, the CPU 42a acquires the reproduction state of the corresponding sound channel aCH. As described above, in this embodiment, correspondence of sound channels aCH to be registered for each type of sound is determined. are corresponding sound channels aCH.
Therefore, when the process of step S1201 is executed as the SE1 setting process (S1108), it becomes the process of acquiring the playback status of the sound channels aCH2 to aCH9, and when executed as the SE2 setting process (S1109), the sound channel This is the process of acquiring the playback status of aCH10 to aCH14.
Acquisition of the reproduction state of each sound channel aCH, that is, acquisition of information as to whether or not a phrase is being reproduced is performed by obtaining the value of a reproduction state information storage register provided for each sound channel aCH in the sound source IC 42d. .

Next, in step S1202, the CPU 42a sets the setting sound channel aCH as the start sound channel aCH. Here, the set sound channel aCH means the sound channel aCH to be registered as sound data. The start sound channel aCH means the sound channel aCH with the smallest channel number among the corresponding sound channels aCH, and aCH2 corresponds to SE1, and aCH10 corresponds to SE2.
Through the processing of steps S1203 to S1211 below, empty channels are searched for in order from the start sound channel aCH, and the set sound channel aCH is set as the start sound channel aCH in step S1202 in order to register the sound data of the SE.

In step S1203, the CPU 42a determines whether or not the setting sound channel aCH is being reproduced. If the setting sound channel aCH is being reproduced, the setting sound channel aCH is incremented by 1 in step S1208, and it is determined in step S1209 whether or not the setting sound channel aCH is greater than the end channel. The end channel means the sound channel aCH with the largest channel number among the corresponding sound channels aCH, and therefore whether it is greater than the sound channel aCH9 in the case of SE1 or greater than the sound channel aCH14 in the case of SE2. It will be determined whether or not
If the set sound channel aCH is greater than the end channel, there is no free corresponding sound channel aCH, so the processing ends.
On the other hand, if the set sound channel aCH is not greater than the end channel, the process returns to step S1203 (that is, it is determined whether or not the next sound channel aCH is being reproduced).

If it is determined in step S1203 that the setting sound channel aCH is not being reproduced, the CPU 42a advances to step S1204 to determine whether or not there is sound data in the work of the setting sound channel aCH.
If there is sound data in the setting sound channel aCH, that is, if the setting sound channel aCH is not empty, the CPU 42a proceeds to step S1208. In other words, this causes a search for the next available channel within the corresponding sound channel aCH.

On the other hand, if there is no sound data in the setting sound channel aCH, that is, if the setting sound channel aCH is empty, the CPU 42a advances to step S1205 to determine whether or not there is a stereo request. That is, by referring to the information indicating whether or not stereo reproduction is required in the SE information in the table, it is determined whether or not the SE information is accompanied by a request for stereo reproduction. As described above, the scenario data requesting stereo reproduction does not describe separate phrase numbers for Lch and Rch, but describes one common phrase number.
If there is no stereo request, the CPU 42a advances to step S1210, sets the sound data of the table in the work area corresponding to the set sound channel aCH, and terminates the processing.

On the other hand, if there is a stereo request, the CPU 42a advances to step S1206 to determine whether or not the set sound channel aCH is an even channel. If the setting sound channel aCH is not an even channel, the CPU 42a advances to step S1208 to increment the setting sound channel aCH by one. That is, it searches for an empty channel after the next sound channel aCH.
Here, as described above, in this example, stereo reproduction is performed using the even-numbered sound channel aCHn and the next odd-numbered sound channel aCHn+1. should set the sound data such as the phrase number described in the scenario data to the even-numbered sound channel aCHn and the next odd-numbered sound channel aCHn+1. Therefore, if the set sound channel aCH is not an even-numbered channel, the next sound channel aCH and subsequent channels are searched for empty channels as described above.

On the other hand, if the setting sound channel aCH is an even numbered channel, the CPU 42a advances to step S1207 to determine whether the sound channel aCH next to the setting sound channel aCH is also an empty channel (including whether or not it is being reproduced). or not).
If the sound channel aCH following the set sound channel aCH is not a free channel, the process proceeds to step S1208. That is, it searches for the next available channel within the corresponding sound channel aCH.
On the other hand, if the sound channel aCH next to the setting sound channel aCH is an empty channel, the process advances to step S1211 to set the sound data in the table in the work areas corresponding to the setting sound channel aCH and the next sound channel aCH. and terminate the process.

By the above SE setting processing, the sound data of SE1 or SE2 described in the sub-scenario table is registered in an empty channel among the corresponding sound channels aCH in the sound data registration information.
If the information of SE1 or SE2 requests stereo reproduction of a phrase, the sound source IC 42d requests that the even channel and the next odd channel be used for stereo reproduction. , sound data can be appropriately registered in the even-numbered channel and the next odd-numbered channel in the corresponding sound channel aCH. In other words, this enables appropriate information registration according to the specifications of the sound source IC 42d.

Next, the sound control setting process executed in step S1110 of FIG. 27 will be described with reference to FIGS. 29 to 31. FIG.
FIG. 29 shows the sound control setting process in step S1110.
First, in step S1301, the CPU 42a confirms the value of the upper 1 byte of the sound control information.

FIG. 30 shows an example data structure of sound control information.
In the case of this embodiment, the sound control information consists of 4 bytes, the upper 1 byte describes the information (control type information) indicating the content of the sound control, and the lower 3 bytes describes the sound control target. Information for designating the sound channel aCH (information to be controlled) is described.
Depending on the control type information in the upper 1 byte, it is possible to instruct fade-in reproduction, fade-out reproduction, and secondary volume change.

As the control type information represented by the upper 1 byte as shown in the figure, 0x20 to 0x70 are fade-related information, and 0x80 and above are secondary volume change instruction information.
Specifically, as fade-related information from 0x20 to 0x70, 0x25 (SFO1M) is "fade out slowly mute", 0x35 (SFO2M) is "fade out normal mute", 0x45 (SFO3M) is "fade out quickly mute", 0x20 (SFO1) is "fade out slowly, low volume", 0x30 (SFO2) is "fade out normal, low volume", 0x40 (SFO3) is "fade out fast, low volume", 0x50 (SFI1) is "fade in slowly", 0x60 (SFI2) represents "fade-in normal", and 0x70 (SFI3) represents "fade-in fast".
Here, "slow", "normal", and "fast" mean volume transition speeds in fade control. The difference between "mute" and "low volume" in fade-out is whether or not the volume after transition is "0".

In addition, as the information of instruction to change the secondary volume of 0x80 or higher, 0x80 (SVO8), 0x81 (SVO0), 0x82 (SVO2), and 0x83 (SVO4) are secondary volumes = 0x80 (MAX) and 0x00 (0), respectively. , 0x20, 0x40. 0x90 (SVO8E) represents the secondary volume of all sound channels aCH (aCH0 to aCH14) other than errors = 0x80, and 0x91 (SVO0E) represents the secondary volume of all sound channels aCH other than errors = 0x00. .

The lower 3 bytes of the sound control information are 0x110000 (BG_T) for sound channel aCH0 (BGM), 0x220000 (YK1_T) for sound channels aCH2 to aCH9 (SE1), and 0x330000 (YK2_T) for sound channels aCH10 to aCH14 (SE2). ), 0x440000 (YKA_T) represents sound channels aCH2 to aCH14 (SE1+SE2=all SEs), and 0x00 ---- (other) represents the sound channel aCH reproducing the phrase indicated by "----".

In step S1301 of FIG. 29, the CPU 42a confirms the value of the upper 1 byte of the sound control information having the above data structure. Check which of the above is the case. This corresponds to confirming whether the control type is a fade system, a simple secondary volume change instruction, or a secondary volume change instruction accompanied by designation of a whole tone channel aCH other than an error.

If it is 80h or more and less than 90h, the CPU 42a sets the secondary volume of the sound channel aCH indicated by the lower 3 bytes of the sound/motor sub-scenario table (sound control information) to the volume value indicated by the upper 1 byte in step S1302. End the process.
If it is 90h or more, the CPU 42a sets the secondary volume of the sound channels aCH0 to aCH14 to the volume value indicated by the upper 1 byte in step S1303, and terminates the process.

On the other hand, if the upper 1 byte is less than 80h, the CPU 42a performs processing for converting control data according to the value of the upper 1 byte in step S1304, and then proceeds to step S1305 in the sound/motor sub-scenario table (sound control table). information) is set in the work area corresponding to the sound channel aCH indicated by the lower 3 bytes, and the process is terminated.

Here, the fade system control information whose upper 1 byte is less than 80h is information for identifying only the difference in control type, such as "slow fade-out mute" or "quick fade-in". Therefore, in step S1304, the control type information in the upper 1 byte is converted into information that allows the sound source IC 42d to execute the corresponding operation.

FIG. 31A shows the contents of the conversion processing in step S1304 of FIG.
First, in step S1401, the CPU 42a acquires a 2-byte value corresponding to the upper 1-byte value from the conversion table. Then, in step S1402, a 2-byte value is acquired based on the lower 3-byte value.
Then, in step S1403, the 2-byte values obtained in steps S1401 and S1402 are concatenated.

FIG. 31B is an explanatory diagram of the acquisition processing in steps S1401 and S1402 described above.
First, in the acquisition process in step S1401, a conversion table storing corresponding values (2 bytes) for each upper 2-byte value (0x25 to 0x70) of the fade system is used as shown in the drawing. The CPU 42a refers to the conversion table and acquires a 2-byte value corresponding to the upper 1-byte value.
Then, in the acquisition process of step S1402, based on the value of the lower 3 bytes of the sound control, if the control target is other than SE1 and SE2 (that is, other than aCH2 to aCH14: other than the notice sound), and in the case of SE1 and SE2, , each acquires a 2-byte value as shown in the figure. That is, it is 0xD000 for cases other than SE1 and SE2, and 0xC000 for SE1 and SE2.
As will be described later, the reason why the obtained values differ depending on whether the control target is either SE1 or SE2 is that the fade control for SE1 and SE2 is monaural. because there is
The 2-byte values thus obtained are concatenated in step S1403 to obtain 4-byte control data.

FIG. 31C exemplifies a correspondence relationship between fade-related information of sound control and control data obtained by the conversion processing of FIG. 31A according to the content (value) of the information.
Here, in the present embodiment, a total of 4 bytes of control data obtained by the conversion processing in FIG. 31A is set (registered) as it is in the sound data registration information. In this sense, in the drawing, the control data obtained by the conversion process of FIG. 31A is indicated as "data to be set in the sound data registration information".
According to FIG. 31C, the upper 1 byte = SFO1M (fade-out slow muting) and the lower 3 bytes = BG_T as fade-related sound control information, for example, are converted into control data "0x2000D000" by the above conversion processing. found to be converted. Further, for example, the upper 1 byte=SFO3M (quick fade-out, mute) and the lower 3 bytes=YK1_T for sound control information are converted into control data "0xFF00C000".

Referring to FIG. 24, in the sound data registration information, the 1st byte is "primary volume transition amount", the 2nd byte is "primary volume", and the 3rd byte is "transition amount change", "volume change", "phrase change". , ``stereo'', ``loop'' (each 1 bit so far) and ``phrase number hi'' (3 bits), and the 4th byte is ``phrase number low''.
As described above, in the present embodiment, the converted control data is set as it is in the sound data registration information, so for example, according to the control data (0x2000D000) of the sound control information of SFO1M+BG_T, the registration contents of the sound data registration information are ,
"Primary volume transition amount" = "0x20"
"primary volume" = "0x00"
"transition amount change" = "1"
"Volume change" = "1"
"phrase change" = "0"
"Stereo" = "1"
"loop" = "0"
"phrase number hi" = "000"
"phrase number low" = "0x00"
becomes.
Also, for example, according to the control data (0xFF00C000) of the above SFO3M+YK1_T sound control information, the registered contents of the sound data registration information are:
"Primary volume transition amount" = "0xFF"
"primary volume" = "0x00"
"transition amount change" = "1"
"Volume change" = "1"
"phrase change" = "0"
"stereo" = "0"
"loop" = "0"
"phrase number hi" = "000"
"phrase number low" = "0x00"
becomes.

As in the former example, when the control target is other than SE1 and SE2, "stereo" is set to "1" (stereo), and as in the latter example, the control target is SE1 (same for SE2). In this case, "stereo" is set to "0" (monaural). As can be understood from this point, the monaural specification for the SE fade control described above is realized.

As described above, in the present embodiment, regarding fade-type sound control information, information representing only the difference in fade control is simply described as the control type information, and this information is converted by the conversion process described above. The data is converted into data that can be registered in the sound data registration information (that is, data required for the sound source IC 42d to perform its fade control).
Here, fade control such as "slow fade-out mute" and "fade-in fast" may be realized by preparing sub-scenario data that gradually changes the volume over time. will hold the sub-scenario data for each hour, requiring a corresponding amount of memory capacity. On the other hand, according to the present embodiment in which the above-described conversion processing is performed, it is only necessary to describe information representing only the difference in fade control, such as "slow fade-out mute" and "fast fade-in", as sub-scenario data. , the number of sub-scenario data required for a kind of fade control can be reduced to one, and as a result, the memory capacity for holding the sub-scenario data can be reduced.

Further, if the above-described conversion processing is performed, even if the specifications of the sound source IC 42d are changed, it can be dealt with simply by changing the contents of the conversion table shown in FIG. 31B. There is no need to rewrite or rewrite the program. Therefore, it is possible to flexibly respond to changes in the specifications of the sound source IC 42d, and it is possible to reduce the work load for responding to the changes in the specifications of the sound source IC 42d.
Also, when changing specific volume transition amounts for fade-in/out, it is only necessary to change the contents of the conversion table shown in FIG. is not necessary, and the work load related to the change can be reduced.

Further, in the present embodiment, with respect to volume transition speed instruction information (primary volume transition amount) related to fade control, the gradation of the transition speed that can be instructed by the transition speed instruction information is set to the transition speed that can be realized by the sound source IC 42d. is less than the gradation of . Specifically, in this example, the volume transition speed information that is output and set to the sound source IC 42d is 8 bits (1 byte). On the other hand, the gradation of the transition speed that can be specified by the sound control information of the sub-scenario data is limited to the three gradations of "fast", "normal", and "slow" as described above.
In this way, by setting the gradation of the volume transition speed instruction information described in the sub-scenario data (production progress data) to be smaller than the gradation of the transition speed that can be realized by the sound source IC 42d, the volume transition speed instruction information described in the production progress data is reduced. The number of bits of the transition speed indication information can be reduced accordingly. Therefore, it is possible to reduce the data amount of the performance progress data, and to reduce the memory capacity for holding the performance progress data.

Note that the number of gradations that can be instructed by the volume transition speed instruction information should be less than the gradation of the transition speed that can be realized by the sound source IC 42d, and should not necessarily be limited to the three gradations illustrated above.

As described above, the sound control information describes fade-in and fade-out instruction information. This sound control information is stored in association with time information in the sub-scenario table as described above. information. In addition, the sub-scenario table stores not only information on such sound control but also information on phrases to be reproduced corresponding to time (“BGM,” “SE1,” “SE2,” and “BGM” in FIG. 26B). error tone”).
Here, as can be understood from this point, the sub-scenario table of the present embodiment includes "information specifying the sound to be output" (phrase reproduction instruction information) and "information for specifying the phrase being reproduced" corresponding to time. information for instructing fade-in and/or fade-out (sound control information).
According to the present embodiment, in which effect control related to sound is executed based on the information of such a sub-scenario table, the fade-in and fade-out of phrases are performed by describing the sound control information in the sub-scenario table (effect progression data). This is achieved by keeping Since fade-in and fade-out control changes the volume according to the passage of time, it is conceivable to write volume change instruction information for each time as production progress data. The amount of data tends to increase, leading to an increase in memory capacity. In addition, the amount of processing based on performance progress data also tends to increase, leading to an increase in control load.
On the other hand, according to this embodiment, the fade control of the phrase is realized by describing the sound control information for instructing fade-in and fade-out in the production progress data as described above. The amount can be reduced, and the control load can be reduced.

In this example, the sound control information for instructing fade-in and fade-out includes not only volume transition speed but also post-transition volume instruction information. , and post-transition volume indication information. That is, the information can include at least one of these pieces of information. For example, when using the tone generator IC 42d in which the post-transition volume is fixed at a predetermined value such as "0" or "MAX", the post-transition volume instruction information is unnecessary, and the transition speed is fixed at a predetermined value. In the case of using the sound source IC 42d provided with the sound source IC 42d, the transition speed instruction information is unnecessary.

Here, with reference to FIG. 32, an example of use of fade-type sound control information will be described.
In the example of FIG. 32, as the sub-scenario data of the sound/motor sub-scenario number 001 in the sound/motor sub-scenario table, the BGM is faded at time=0 in the mode of "fade out quickly, sound low" (SFO3+BG_T). , At time = 0 to 2000, SE1 phrase 0001 is played at volume 0x80, at time = 2000 to 5000, SE1 phrase 0002 is played in stereo at volume 0x80, and at time = 5000, the BGM is "fade in slowly" (SFI1 + BG_T). , exemplifies a case where information to be faded is described in the form of
As shown in the figure, the end timing of a phrase is the time when the sound data as the phrase ends.

By executing the scenario update processing, sub-scenario update processing, and sound data registration processing described with reference to FIGS. SFO3+BG_T) and SE1 information (0x00806001) described in the line of time=0 are set in the sound data registration information. For the sake of confirmation, according to the processing shown in FIGS. (set at once in the "sound registration process (S1035)" in FIG. 22).
By the sound reproduction processing (S616) in the main processing of FIG. 15, the information set in the sound data registration information is sequentially output to the sound source IC 42d, and sound output corresponding to the sub-scenario data is realized. As a result, the fade-out of the BGM and the reproduction of the phrase 0001 are realized as shown in the lower part of the figure.

In response to time=2000, the SE2 information (0x00807002) described in the time=2000 line is registered in the sound data registration information. , playback of phrase 0002 is started from time=2000 as shown in the lower part of the figure.
Further, when the time reaches 5000, control data corresponding to the sound control information (SFI1+BG_T) described in the line of time=5000 is registered in the sound data registration information. By sequentially outputting to the sound source IC 42d in the reproduction process, the fade-in of the BGM at time=5000 as shown in the figure is realized.

Here, depending on the sound control information, as described with reference to FIG. 30, it is also possible to issue an instruction to change the secondary volume of the phrase reproduced on the designated sound channel CHa.
With reference to FIG. 33, an example of volume control based on a secondary volume change instruction will be described.
FIG. 33 is an explanatory diagram of a control example of muting a predetermined type of sound by means of a secondary volume. An example of muting BGM by the next volume is shown.
In this example, there are two lines of time=0 in the sub-scenario table, and one line of time=0 describes "SVO0+BG_T" (see FIG. 30) as sound control information. On the other line with time=0, "0x0080700A" (stereo playback of phrase 0010 at primary volume 0x80) is described as SE1 information.
If there are two lines having the same time, the description information of those lines is sequentially converted into the sound data registration information by the processing shown in FIGS. will be registered with According to these pieces of registration information, muting of the BGM by the secondary volume as shown in the figure corresponding to time=0 and reproduction of phrase 0010 as SE1 are started.
Also, in this example, "SVO8 + BG_T" (secondary volume = 0x80) is written as sound control information on the line at time = 5000, and as a result, after time = 5000, the mute state of BGM is canceled as shown in the figure. be done.

According to this embodiment, in which it is possible to change the secondary volume of the designated sound channel aCH using sound control information in this way, when a certain type of sound is being reproduced, another high-priority sound is subsequently reproduced. When the sound of (1) is to be reproduced, it is possible to easily obtain a state in which only the high priority sound is reproduced and output without giving an instruction to stop the reproduction of the sound being reproduced. Therefore, sound priority control can be easily realized.

Here, although the priority control for BGM and other sounds has been exemplified above, in the present embodiment, SE sounds are classified into SE1 and SE2. Since they are treated as types, these SE1 and SE2 can similarly be realized with sound priority control by controlling the secondary volume based on the sound control information.
As described above, SE1 and SE2 are classified according to the appearance frequency of the effect in this example. Therefore, when the sound of SE1, which has a high appearance frequency (that is, has a low reliability), is being reproduced, and the sound of SE2, which has a low frequency of appearance (that is, has a high reliability), should be reproduced afterward. By controlling the secondary volume according to the sound control information in the same manner as in the example of (1) above, the sound of SE1 being reproduced can be muted, and the sound of SE2 can be preferentially output.

In addition, since volume control can be performed not only by the primary volume but also by the secondary volume, the muffling control as shown in FIG. 33 can be appropriately realized.
Here, when it is attempted to realize mute control of BGM as shown in FIG. It is conceivable to mute the BGM of
However, as described above, the primary volume is the volume value set in the sound source IC 42d together with the phrase number when playback of the phrase is started. For this reason, even if the sound is muted by the primary volume using the sound control information as described above, if the timing like "X" in FIG. If another scenario instructs to start playing back the BGM at the previous timing), the volume of the BGM is set to a required volume other than 0x00 at the point of "X", and the BGM is emitted. end up
On the other hand, according to the present embodiment, in which the volume control by the secondary volume is also possible, once the secondary volume of BGM is controlled to 0x00 by the sound control information, the secondary volume can be controlled as described in FIG. Even if the reproduction of new BGM is started and the primary volume is set to a volume other than 0x00 until sound control for restoring the next volume is performed, 0x00 can be maintained as the output volume. As a result, the volume control as shown in FIG. 33 can be properly realized.

Further, by enabling volume control by not only the primary volume but also the secondary volume, the control load related to volume control can be reduced.
That is, as can be understood from the explanation so far, the primary volume is volume information described in the scenario data (performance progress data). The scenario data registration process is always required, which tends to increase the load on the CPU 42a.
On the other hand, according to the present embodiment, which enables volume control by not only the primary volume but also the secondary volume, since the volume control can be performed without depending on the performance progress data, the volume control using only the primary volume is possible. Control, that is, the processing based on the performance progress data can be reduced in comparison with the case where the volume control is performed based only on the performance progress data. Therefore, it is possible to reduce the control load. In addition, since the amount of performance progress data to be held can be reduced, the memory capacity can be reduced.

In particular, in this embodiment, the volume control according to the operation (for example, the volume control according to the operation of the volume switch on the back side of the slot machine described above) is also performed using the secondary volume. As a result, it is possible to reduce the control load associated with the volume control according to the operation.
That is, if the volume control according to the operation is performed using only the primary volume, the primary volume is controlled according to the scenario each time according to the operation, which promotes an increase in the control load. As described above, according to the present embodiment, in which the volume control according to the operation is also performed using the secondary volume, the processing based on the scenario data can be omitted in the volume control according to the operation. can be reduced.

[10-5. Sound playback processing]

Next, the sound reproduction process executed as step S615 in FIG. 15 will be described.
As described above, the sound reproduction process is a process of causing the sound source IC 42d to output sound based on the information set in the work as the sound data registration information.

FIG. 34 is an explanatory diagram of sound reproduction processing.
First, as loop processing LP3, the CPU 42a performs steps S1500 to S1520 for each of the sound channels aCH0 to aCH15 of the sound data registration information. Hereinafter, the sound channel aCH to be processed will be described as "aCHn".

In step S1500, the CPU 42a checks the volume MAX error flag. The volume MAX error flag is a flag set in the error processing (see FIG. 8) in step S612. As described above, 0x5A indicates that a volume MAX error is Each indicates that it is not.
If the volume MAX error flag is 0x5A, the process advances to step S1521 to rewrite the secondary volume of the work to sound channels aCH0 to 14 (other than error sound)=0x00 and sound channel aCH15 (error sound)=0x80, and then to step S1501. move on.
On the other hand, if the volume MAX error flag is 0x00, the process advances to step S1501 without rewriting the secondary volume of the work in step S1521.

In step S1501, the CPU 42a outputs the secondary volume value to the target sound channel aCHn. That is, the secondary volume value set in the sound channel aCH of the sound data registration information is output to the secondary volume register for the sound channel aCHn in the sound source IC 42d.
As described above, the value of the secondary volume is normally set to the full tone channel aCH of the sound data registration information in accordance with the state of the volume switch. Alternatively, as a scenario, when sound control information instructing a change in the secondary volume of a certain sound channel aCH is described, the value of the secondary volume described in the sound control information is the sound data. It is set to the sound channel aCH indicated by the sound control information in the registration information. Further, if a volume MAX error is occurring, "0" is set in the sound channels aCH0 to 14 and the MAX value is set in the sound channel aCH15 by the processing of step S1521.

Next, the CPU 42a outputs the value "0x00" to the SUB volumes 0 and 1 in step S1502. That is, the value "0x00" is output to each of the "SUB volume 0" and "SUB volume 1" registers of the sound channel aCHn. As described above, the SUB volume is not used in this embodiment.

In step S1503, the CPU 42a determines whether or not there is sound data (sound data other than the secondary volume) in the work sound channel aCHn. If there is no sound data, the processing for the sound channel aCHn ends.

On the other hand, if there is sound data, the flow advances to step S1504 to determine whether or not there is a replacement request.
Here, in the present embodiment, a phrase replacement request can be made using the values of the upper two bytes (“primary volume transition amount” and “primary volume”) of the sound data registration information shown in FIG. ing. Specifically, if the upper two bytes of the sound data registration information are a predetermined value (for example, "0x5A5A" in this example), it is interpreted as a phrase replacement request.
In step S1504, it is determined whether or not the upper two bytes of the data set in the sound channel aCHn are a predetermined value "0x5A5A", thereby determining whether or not there is a phrase replacement request.

If it is a replacement request, the CPU 42a rewrites the phrase number in step S1505, and proceeds to step S1506. The phrase number is rewritten by outputting the values of "phrase number hi" and "phrase number low" of the data set in the sound channel aCHn to the phrase number register of the sound channel aCHn of the tone generator IC 42d.
On the other hand, if it is not a replacement request, the process proceeds to step S1506 without going through step S1505.

In step S1506, the CPU 42a determines whether or not there is a transition amount change request or a volume change request. That is, it is determined whether "1" is set to either the transition amount change frzVq or the volume change rsv1 of the sound channel aCHn.
Here, the value of the transition amount change frzVq in the sound data registration information is set to "1" when the sound registration processing (S1035) is executed based on the fade-type sound control information. If the sound registration process is executed based on sound control information (that is, secondary volume change instruction), BGM, SE1, SE2, and error sound information, "0" is set. .
On the other hand, the volume change rsv1 (whether or not to change the primary volume) is determined when the sound registration processing is executed based on the fade-type sound control information, and when the BGM, SE1, SE2, error sound information, and so on. "1" is set when the sound registration process is executed based on the fade-type sound control information. Then, when the sound registration processing is executed based on the sound control information other than the fade type, "0" is set.
As can be understood from these points, not only when sound data based on fade-type sound control information is registered, but also when sound data based on BGM, SE1, SE2, and error sound information are registered. Even if there is, information on the primary volume transition amount and the primary volume will be output to the sound source IC 42d in subsequent steps S1509 or S1511.

If there is a transition amount change request or a volume change request, the CPU 42a advances to step S1507 to determine whether or not the sound channel aCHn is for stereo reproduction, that is, whether or not the value of stereo frzSt is "1".
If the sound channel aCHn is not for stereo reproduction, the process advances to step S1509 to output the primary volume transition amount and the primary volume to the sound channel aCHn of the sound source IC 42d, and further to step S1510 to output the panpot to the sound channel aCHn of the sound source IC 42d. and proceed to step S1513.
Here, as the output of the panpot, values are output to the respective registers of "left/right panpot", "left/right panpot transition amount", "up/down panpot" and "up/down panpot transition amount" for the sound channel aCHn in the sound source IC 42d. do. In this example, the panning function of the sound source IC 42d is not used, so all "0" (0x00) is output in step S1510.

On the other hand, if the sound channel aCHn is for stereo reproduction, the flow advances to step S1508 to determine whether the sound channel aCHn is an even number.
If the sound channel aCHn is an even number, the process advances to step S1511 to output the primary volume transition amount and primary volume to the sound channels aCHn and aCHn+1, and panpots to the sound channels aCHn and aCHn+1 in step S1512. is output, and the process proceeds to step S1513.

Here, in the case of this embodiment, the registers of the "left and right panpot" of the even-numbered sound channel aCHn and the next odd-numbered sound channel aCHn+1 are used for the stereo reproduction instruction. Specifically, the sound source IC 42d in this case performs "right/left panpot" of the even-numbered sound channel aCHn (corresponding to the Lch side of stereo reproduction) and the next odd-numbered sound channel aCHn+1 (corresponding to the Rch side of stereo reproduction). By setting predetermined values in the respective registers, it is configured to recognize that the sound channel aCHn and the sound channel aCHn+1 are stereo reproduction. More specifically, the tone generator IC 42d in this case sets "0x81" in the "left/right panpot" register of the even-numbered sound channel aCHn, and sets the "left/right panpot" register of the next odd-numbered sound channel aCHn+1. is set to "0x82" to recognize that these sound channel aCHn and sound channel aCHn+1 are for stereo reproduction.
In response to this, in step S1512, as panpot output processing for sound channel aCHn and sound channel aCHn+1, "0x81" is set in the "left/right panpot" register of sound channel aCHn, and "left/right pan" of sound channel aCHn+1 is set. "0x82" is output to each "pot" register.
As described above, the panning function of the sound source IC 42d is not used in this embodiment, so in step S1512, the "left/right panpot transition amount", "up/down panpot", and "up/down panpot transition amount" other than the "left/right panpot" are set. "0x00" is output to each register.

If the sound channel aCHn is not an even number in step S1508, the process advances to step S1520 to clear the sound data of the work sound channel aCHn and terminate the processing for the sound channel aCHn.
That is, when the sound channel aCHn is for stereo reproduction and has an odd number, the phrase number registered in the sound channel aCHn is not output to the sound source IC 42d (note that the primary volume transition amount and the primary volume are even numbers). (already output in S1511 which is the processing for aCHn), the registered sound data of the sound channel aCHn is cleared. In this case, the sound source IC 42d specifies the phrase data for each of the Lch and Rch to be reproduced based on the phrase number set in the processing for the even-numbered sound channel aCHn. It is not necessary to indicate the phrase number to the tone generator IC 42d.

Also, in the previous step S1506, if there is no transition amount change request or volume change request, the CPU 42a skips the processing of steps S1507 to S1512 and proceeds to step S1513.

In step S1513, the CPU 42a determines whether or not there is a phrase change request, that is, whether or not the value of the phrase change rsv0 is "1".
If there is no phrase change request, the sound data of the sound channel aCHn is cleared in step S1520, and the processing for the sound channel aCHn ends. That is, when there is no phrase change request, the phrase number set in the work sound channel aCHn is not output to the sound source IC 42d (S1515).

On the other hand, if there is a phrase change request, it is determined in step S1514 whether or not the sound channel aCHn is stereo and odd. If the sound channel aCHn is stereo and has an odd number, the sound data of the sound channel aCHn is cleared in step S1520, and the processing for the sound channel aCHn ends.

If the sound channel aCHn is not stereo and odd in step S1514, the flow advances to step S1515 to output the phrase number to the sound channel aCHn. That is, the information of the phrase number consisting of the phrase number hi and the phrase number low registered in the sound channel aCHn of the work is output to the phrase number register for the sound channel aCHn of the sound source IC 42d.

In the next step S1516, the CPU 42a determines whether or not there is a loop request, that is, whether or not the value of the loop frzLp is "1". If there is a loop request, the loop count 0xFF (infinite loop) is output to the sound channel aCHn of the sound source IC 42d in step S1517, and the process proceeds to step S1519. (no loop) is output and the process proceeds to step S1519.

In step S1519, the CPU 42a instructs to reproduce and output the sound channel aCHn. That is, a reproduction instruction based on the data set in the sound channel aCHn is issued to the sound source IC 42d.
Next, the CPU 42a clears the sound data of the work sound channel aCHn in step S1520, and ends the processing for the sound channel aCHn.

The CPU 42a sequentially performs the processing of steps S1501 to S1520 described above for sound channels aCH0 to aCH15 by loop processing LP3. As a result, the sound reproduction processing in step S615 ends.
Through such sound reproduction processing, sound output based on the information registered in the sound data registration information is executed, and sound effects corresponding to the scenario are realized.

Here, as described above, in the present embodiment, it is assumed that a stereo reproduction instruction to the sound source IC 42d is performed by setting a predetermined value in the "left/right panpot" register of the even-numbered sound channel and the next odd-numbered sound channel aCH. However, as a result, stereo reproduction/monaural reproduction can be properly instructed without providing a register for instructing stereo reproduction/monaural reproduction in the sound source IC 42d. That is, the number of registers of the tone generator IC 42d can be reduced. At the same time, since the stereo reproduction/monaural reproduction instruction to the sound source IC 42d can be realized by the panpot output processing, there is no need to perform the stereo reproduction/monaural reproduction instruction processing separately, and the processing load can be reduced accordingly.

In the above example, the item "left/right panpot" is used to instruct stereo/monaural playback. volume control item), and thus the instruction for stereo/monaural reproduction serves as the output processing of the instruction information for the predetermined volume control item. can be made unnecessary, and the control load can be reduced.

Also, as can be understood from the above description, in the present embodiment, the tone generator IC 42d performs stereo reproduction based on phrase number information (playback phrase instruction information) set to the channel with the smaller number among the two consecutive channels. It is configured to acquire phrases on the Lch side and Rch side to be reproduced, and perform stereo reproduction of those phrases. Correspondingly, the CPU 42a sets the information of the phrase number for the channel with the smaller number together with the stereo reproduction instruction.
By adopting such a configuration, when realizing stereo reproduction of phrases, it is not necessary to output the reproduction phrase instruction information to the odd-numbered channel side (channels with lower numbers), thus further reducing the control load. be done.

Here, in the sound reproduction process of FIG. 34, the volume MAX error flag is checked each time at step S1500, and if a volume MAX error is occurring, the secondary volume of the work is rewritten at step S1521. That is, when a volume MAX error is occurring, the rewriting process of step S1521 is performed every 16 ms, and the secondary volume of the work (sound channel aCH other than the error sound) is set to "0x00" each time. set. As a result, during the volume MAX error, the sound channel aCH other than the error sound is maintained in a mute state.

<11. Vibration production of the embodiment>

In the slot machine of the present embodiment, a vibration presentation is performed by vibrating at least a part of the slot machine using the output sounds from the speakers 30c and 30d (speakers for medium and low sounds).
Specifically, in this example, in a memory that can be read by the sound source IC 42d, vibration phrase data is stored as SE phrase data, and the vibration phrase data is at least part of the slot machine. Sound data containing the frequency component of the natural frequency of the specific part is stored. More specifically, in this example, the vibrating effect is performed by vibrating the entire housing of the slot machine (the housing formed by the main body case 1 and the front panel 2) (that is, the specific part = housing As the phrase data for vibration, sound data containing the frequency component of the natural frequency of the housing is used.
In this example, the natural frequency of the housing of the slot machine is about 85 Hz.

Also, in this example, frequency-swept sound data is used as phrase data for vibration. Specifically, the phrase data for vibration in this example uses sound data whose frequency is swept within the range of 55 Hz to 100 Hz.
Further, a reciprocating sweep is performed as the sweep. Specifically, in this example, sound data whose frequency repeatedly rises and falls within the sweep range of 55 Hz to 100 Hz is used.
Here, the cycle of the reciprocating sweep, that is, the length of the reciprocating period until the frequency returns from 55 Hz to 100 Hz and then back to 55 Hz is set to 0.05 seconds or less. Specifically, the length of the reciprocating period is 0.03 seconds (the sum of 55 Hz→100 Hz=0.015 seconds and 100 Hz→55 Hz=0.015 seconds). Sound data obtained by repeating a reciprocating sweep with a period length for a predetermined number of seconds (for example, 1 second or 2 seconds) is used.

In this embodiment, the sound output for vibration includes frequency components of 55 Hz to 100 Hz as described above, but the lower limit frequency of the audible band is 20 Hz. A sound containing frequency components of

As described above with reference to FIG. 5 and the like, in the slot machine of this embodiment, at least a part of the rear sides of the speakers 30c and 30d are formed inside the main body case 1 when the front panel 2 is closed. Exposed in closed space. Therefore, by outputting sounds based on the phrase data for vibration as described above from the speakers 30c and 30d, the air in the closed space vibrates according to the sounds emitted from the rear side of the speakers 30c and 30d, It is possible to vibrate the entire housing of the slot machine.
Therefore, when the specific portion as the vibration target portion is the entire housing, there is no need to form a conduit for transmitting vibration from the rear surface of the speakers 30c and 30d to the specific portion or to provide a resonator. It is possible to simplify the configuration for vibrating the specific portion and reduce the cost.

Further, in the present embodiment, a frequency-swept sound is output, and by performing such a sweep, it is possible to adjust the amplitude of vibration, thereby facilitating the adjustment of the amplitude of vibration.
Furthermore, in the present embodiment, reciprocating sweeping is performed, which makes it possible to generate more stable vibration than in the case of one-sided sweeping on either the rising side or the falling side of the frequency.
In addition, in the present embodiment, the sound for vibration includes frequency components in the audible band. This makes it possible for the player to perceive low-pitched sound at the same time as the vibration, thereby increasing the impact of the vibration effect.

An example of the processing process of the CPU 42a relating to sound output for vibration will be described with reference to the flowchart of FIG.
First, the CPU 42a in the effect control board 42 receives the effect control command of the vibration opportunity in step F01. As an example of the effect control command for the vibration opportunity, the expectation effect command and the like described above can be cited. As described above, the expectation effect command is a command for instructing the content of the expectation effect to be executed at a predetermined timing during one game, such as at the start of the game.

Next, in step F02, the CPU 42a performs command analysis and command correspondence processing. That is, in this step F02, command analysis processing (step S614) and command correspondence processing (step S806) are performed for the vibration-initiated effect control command received in step F01 (see FIGS. 15, 17, and 18). At this time, each command process (S830: see FIG. 18A) for the effect control command of the vibration trigger includes the registration process of the scenario corresponding to the output of the vibration sound, and therefore the process of step F02 is executed. Thus, scenario data for reproducing and outputting vibration phrase data for a predetermined period of time at a predetermined timing is registered in the work of the RAM 42c.

In subsequent step F03, the CPU 42a performs processing for setting sound data registration information based on the registration scenario. That is, by executing the scenario update process (S615) and the sub-scenario update process (S1008) shown in FIGS. The information (FIG. 24) is set with sound data relating to the reproduction output of the phrase for vibration.
Here, in this example, the phrases for vibration are classified into sound types SE (which may be either SE1 or SE2). is set for the SE sound channel aCH (one of the sound channels aCH2 to aCH14 in this example).

Further, in the next step F04, the CPU 42a performs sound reproduction processing (S616: see FIGS. 15 and 34). As a result, the sound source IC 42d reproduces and outputs the phrase based on the sound data set in the sound data registration information. will be

Here, in reproducing and outputting the phrase for vibration as described above, in this example, the sound channel aCH other than the sound channel aCH of the error sound is masked. Specifically, the SE sound channel aCH (one of the sound channels aCH2 to aCH14: two channels for stereo reproduction) in which the sound data of the phrase for vibration is set, and the sound channel aCH of the error sound. Mask all sound channels aCH except sound channel aCH15. This mask can be realized by setting the secondary volume of the corresponding sound channel aCH in the work sound data registration information to "0x00".
Specifically, such a mask by the secondary volume is used as a sound/motor sub-scenario table (see FIG. 26) referenced from the scenario data instructing the sound output for vibration during the playback output period of the phrase for vibration. This can be realized by preparing a table storing sound control information for instructing that the secondary volume of the target sound channel aCH be set to "0x00" in synchronization.
Alternatively, setting the secondary volume for the mask is not limited to being based on the scenario as described above. For example, in the sound reproduction process of step S616, it is checked whether phrase data for vibration is being set in the sound data registration information. By providing processing to set "0x00" as the secondary volume of all sound channels aCH except sound channel aCH, sounds other than vibration sound and error sound are masked during playback output of phrase data for vibration. can be made
Here, for confirmation, the sound reproducing process in step S616 is a process that is repeatedly executed every 16 ms.
Note that it is not essential to mask the sound of the other sound channel aCH when outputting the vibration sound.

Further, in this example, when a volume MAX error occurs during playback output of the vibration phrase, all sound channels aCH other than the error sound, including the sound channel aCH of the vibration phrase, are masked. This is realized by providing the processing of steps S1500 and S1521 in the sound reproduction processing of step S616. Note that the details of the processing in steps S1500 and S1521 have already been explained, so overlapping explanations will be avoided.

Note that the form of masking the target sound channel aCH is not limited to the form of muting as exemplified above, but may be a form of low sound that lowers the volume to a volume other than "0x00".

Also, the masking of sounds other than the error sound when an error occurs can be realized by a scenario.
The flowchart of FIG. 36 represents the flow of processing of the CPU 42a in that case.
First, in step F11, the CPU 42a receives an effect control command for error notification, and in subsequent step F12, executes command analysis and command handling processing. Scenario registration of error sound output is performed by the process of step F12. In the case of this example, the scenario registration process for error notification when various errors occur is performed in the error process of step S612 (see FIG. 15). In this case, in the sound/motor sub-scenario table referred to by the registered scenario, sound data relating to the reproduction output of the phrase of the error sound and the sound channel aCH other than the error sound are synchronized with the output period of the error sound. The information of the sound control which sets the secondary volume of "0x00" is stored.

Next, in step F13, the CPU 42a performs processing for setting sound data registration information based on the registration scenario. As described above, the sound/motor sub-scenario table referenced from the scenario in this case stores sound control information in which the secondary volume of the sound channel aCH other than the error sound is set to "0x00". By performing the setting process of step F13, in the sound data registration information, "0x00" is set as the value of the secondary volume of the sound channel aCH other than the error sound, and the output sound is masked.

In subsequent step F14, the CPU 42a performs sound reproduction processing (S616). As a result, the error sound is reproduced and output as shown in step F15. At this time, the sound reproduction process is executed based on the sound data registration information described above, so that the sound channel aCH other than the error sound is muted.

<12. Summary and Modifications>

As described above, the gaming machine (slot machine) of the embodiment includes speaker units (speakers 30c and 30d) that emit sound, drive control means (effect control board 42) that controls driving of the speaker units, The drive control means drives and controls the speaker section based on a sound signal containing the frequency component of the natural frequency of the specific section, which is at least a part of the game machine, to vibrate the specific section.
As a result, since the speaker used for sound output can be used as a vibration source, there is no need to separately provide an actuator such as a motor as a vibration source.
Therefore, it is possible to reduce the number of parts and the associated cost.

Further, in the gaming machine of the embodiment, the drive control means drives and controls the speaker section based on the frequency-swept sound signal.
By sweeping the frequency of the vibration sound, it is possible to adjust the amplitude of the vibration.
Therefore, it is possible to facilitate the adjustment of the amplitude of vibration.

Furthermore, in the gaming machine of the embodiment, the drive control means drives and controls the speaker section based on the sound signal whose frequency is reciprocally swept.
As a result, frequency sweeping is performed in the form of a reciprocating sweep in which sweeping on the rising side and sweeping on the falling side of frequency are combined.
Therefore, stable vibration can be generated as compared with the case of one-side sweeping on either the rising side or the falling side of the frequency.

Furthermore, in the gaming machine of the embodiment, the driving control means drives and controls the speaker unit based on the sound signal in which the sweep is repeated with a reciprocating period of 0.05 seconds or less as the reciprocating sweep.
If the reciprocating period is lengthened (that is, the sweep speed is slowed down), the amplitude of vibration is increased, and if it is shortened (sweep speed is increased), the amplitude of vibration is decreased.
By appropriately setting the reciprocating period of the sweep, it is possible to optimize the magnitude of the vibration.

In addition, in the game machine of the embodiment, a box-shaped main body case (same 1) having an opening on the front side and a front panel (same 2) attached to the main body case so as to be openable and closable and closing the opening in the closed state (same 2) The speaker section is provided on the front panel so that at least a part of the rear side thereof is exposed to the closed space formed inside the main body case in the closed state.
As a result, the air in the closed space inside the main body case vibrates according to the sound emitted from the back side of the speaker unit, and the entire housing of the game machine can vibrate.
Therefore, when the specific portion as the vibration target portion is the entire housing, there is no need to form a conduit for transmitting vibration from the back surface of the speaker unit to the specific portion, or to provide a resonator. It is possible to simplify the configuration for vibrating the and reduce the cost.

Furthermore, in the gaming machine of the embodiment, the drive control means drives and controls the speaker section based on the sound signal containing the frequency component in the audible band to vibrate the specific section.
As a result, it is possible for the player to perceive the vibration and the low sound at the same time.
Therefore, it is possible to increase the impact of the vibration presentation.

Furthermore, in the game machine of the embodiment, the drive control means can simultaneously reproduce a plurality of sound signals, and includes a vibration sound that is a sound for vibrating the specific portion and an error sound that is a sound for notifying an error. A system used for reproduction is determined for each type of sound classified at least into a sound and a third sound that is a sound other than a vibration sound and an error sound, and the drive control means reproduces the sound signal of the vibration sound. When outputting, processing is performed to mask systems other than vibration sound and error sound among multiple systems.
As a result, it is possible to mask sounds other than the vibration sound while enabling the output of the notification sound when an error is detected.
Therefore, it is possible to reliably notify an error while emphasizing the vibration effect by the mask.

Further, in the gaming machine of the embodiment, when an error is detected, the drive control means carries out a process of masking all of the multiple systems excluding the error sound system.
This prevents the specific portion from vibrating when an error is detected.
Therefore, it is possible to prevent the occurrence of a situation in which the vibration for effect is performed despite the fact that the error notification is being performed, and it is possible to prevent the confusion of the player.

The present invention is not limited to the specific examples illustrated above, and various modifications and application examples are conceivable.
For example, in the above description, an example in which the present invention is applied to a slot machine has been shown, but the present invention can be widely and suitably applied to game machines having variable display means capable of displaying symbols by displacing them. The variable display means is not limited to the one provided with the rotating reel 4 described above, and may be configured to display an image as a design on a display screen such as a liquid crystal display so as to be displaceable.

The present invention can also be suitably applied to gaming machines other than slot machines, such as pachinko gaming machines.
In the case of a pachinko machine, the housing consists of a wooden outer frame and a front frame attached to the outer frame so that it can be freely opened and closed. It is difficult to employ a configuration in which the entire housing is vibrated based on the sound output from the speaker unit. In the case of a pachinko game machine, it is conceivable to employ a configuration in which not the entire housing but a specific part of the housing is vibrated. In that case, in order to improve the efficiency of vibration transmission, a conduit may be formed from the speaker section to the specific portion (specific section). Also, at this time, a resonator as disclosed in Patent Document 1 may be provided to selectively and efficiently vibrate only a specific portion.

In the above, an example of generating vibration with a sound signal containing frequency components in the audible band was given, but vibration can also be generated using a sound signal containing frequency components lower than the audible band. Also, frequency sweeping can be performed in such a manner that the frequency is changed from the audible band to the non-audible band, or from the non-audible band to the audible band.

1 body case,
2 front panel,
3 pattern rotation unit,
4a to 4c rotating reels (rotating drums),
16 max input button,
17 start lever,
18a-18c stop button,
30a-30d speakers,
40 main control board,
42 production control board,
42a CPU,
42b ROMs,
42c RAM,
42d sound source IC,
43 production interface board,
47 speaker relay board,
80 controller,
80a CPU,
80c RAM,
72a setting key switch;
72b reset switch

Claims (2)

A speaker unit that emits sound,
and drive control means for controlling the drive of the speaker unit,
The drive control means is
Driving and controlling the speaker unit based on a sound signal containing the frequency component of the natural frequency of the specific unit, which is at least a part of the game machine, to vibrate the specific unit and simultaneously reproduce sounds of multiple systems and
The plurality of sound systems are a vibration sound that can be output when vibrating the specific unit, an error sound that can be output when an error is notified, and a sound other than the vibration sound and the error sound. including at least three syllables and
The drive control means is
When reproducing and outputting the vibration sound, a process of muting or reducing the sound of the system other than the vibration sound and the error sound among the plurality of systems is performed.
game machine. A speaker unit that emits sound,
and drive control means for controlling the drive of the speaker unit,
The drive control means is
driving and controlling the speaker unit based on a sound signal containing the frequency component of the natural frequency of the specific unit, which is at least a part of the game machine, to vibrate the specific unit , and to the frequency-swept sound signal driving and controlling the speaker unit based on
game machine.

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