JP7253402B2 - Stacked semiconductor integrated circuit and manufacturing method thereof - Google Patents

Description

The present invention relates to a stacked semiconductor integrated circuit and its manufacturing method.

2. Description of the Related Art In order to increase the degree of integration of semiconductor integrated circuits, stacked semiconductor integrated circuits, which are formed by stacking a plurality of independently manufactured integrated circuits, have been put to practical use. For example, there is a laminated image sensor in which a light receiving portion and a signal processing circuit are laminated. The method of manufacturing a stacked semiconductor integrated circuit includes a method in which the upper and lower integrated circuits are aligned and joined, and then a through-silicon via that connects the upper and lower circuits is formed. Various manufacturing methods have been put into practical use, such as a method of aligning and bonding (hybrid bonding and bump bonding). For example, Patent Document 1 describes a solid-state imaging device in which two semiconductor substrates are bump-bonded. In the manufacturing process of this solid-state imaging device, the positioning of the exposure mask is performed by detecting the reflected light of the laser beam irradiated to the cross-shaped alignment mark.

Moreover, in a stacked semiconductor integrated circuit, multi-layer stacking of three or more layers is effective for further high integration. In general, stacking N layers requires (N−1) steps of aligning and bonding the integrated circuits. An example of alignment marks required for circuit alignment is shown in FIG. In this example, FIG. 5(a) shows the alignment mark 101 of the first layer, and FIG. 5(b) shows the alignment mark of the second layer. 5(d) is a cross-sectional view taken along line DD of FIG. 5(a), and FIG. 5(e) is a cross-sectional view taken along line EE of FIG. 5(b).

Alignment marks 101 made of the same metal material as the wiring are formed in the insulating layer 104 on the support substrate 103 in the circuit board of the first layer. Alignment mark 101 consists of four squares in plan view, and these four squares are arranged at four corners of a larger square as a whole. Alignment marks 102 made of the same metal material as the wiring are formed in the insulating layer 104 above (under in FIG. 5(e)) the support substrate 103 in the second layer circuit board. The alignment mark 102 has a cross shape in plan view.

Also, the insulating layers 104 having the alignment marks 101 and 102 formed thereon are opposed to each other, and as shown in FIG. The circuit boards are joined together by being adjusted so as to overlap. Note that overlapping in a plan view means that the alignment mark 102 is arranged in a gap area where the four squares forming the alignment mark 101 are not arranged in plan view. Here, FIG. 5(f) is a cross-sectional view taken along line FF of FIG. 5(c), and the thick broken line indicates the joint surface. Although the alignment marks 101 and 102 are often formed using the wiring of the integrated circuit, they may be formed by making irregularities on the insulating layer or the supporting substrate, if visible.

An example of the alignment method will be described with reference to FIGS. 6(a) to 6(c). Here, as shown in FIG. 6A, a coordinate system having the X-axis pointing rightward, the Z-axis pointing upward, and the Y-axis extending in the depth direction perpendicular to the XZ plane is assumed. For example, in the state shown in FIG. 6A, the camera 112 whose optical axis is aligned with the camera 111 photographs the alignment mark 102L formed in the left area of the substrate 106 fixed to the movable stage 108 arranged above. . A camera 113 whose optical axis coincides with that of the camera 114 photographs the alignment mark 101R formed in the right region of the substrate 105 fixed to the movable stage 107 arranged below. Further, in the state shown in FIG. 6B, for example, the camera 111 photographs the alignment mark 101L formed in the left area of the substrate 105 fixed to the movable stage 107 arranged below. Also, the camera 114 photographs the alignment mark 102R formed in the right region of the substrate 106 fixed to the movable stage 108 arranged above. Each camera is a visible light camera.

Using two sets of cameras (total of four cameras) with the same optical axis, the vertically arranged movable stages 107 and 108 are adjusted while moving in the XY directions. Center it in the camera's field of view. That is, the alignment mark 101L and the alignment mark 102L are arranged to face each other, and the alignment mark 101R and the alignment mark 102R are arranged to face each other. For example, the alignment mark 102L (or 102R) has a cross shape and is arranged so as to match the gap area where the four squares forming the alignment mark 101L (or 101R) are not arranged. Here, since the relative positions of the camera and the movable stage are known for each camera set, the two substrates 105 and 106 can be moved by moving the vertically arranged movable stages 107 and 108 by a desired distance in the X direction. can be aligned. After that, as shown in FIG. 6(c), the movable stage 108 arranged above is lowered in the Z direction to bond the two substrates 105 and 106 together.

JP 2014-157885 A

In a stacked semiconductor integrated circuit, in order to increase the number of stacked layers to three, as shown in FIG. The circuit and the integrated circuit of the third layer are bonded. However, when bonding the third layer integrated circuit onto the second layer integrated circuit, the alignment marks used for bonding the first and second layers cannot be used. This is because the visibility is very poor due to the overlapping of the upper and lower alignment marks. Therefore, as shown in FIG. 7B, alignment marks 122 for bonding the second and third layers are formed at different locations from the alignment marks 121 for bonding the first and second layers. need to keep The bonding of the fourth and subsequent layers is similar. For example, in order to bond N layers, it is necessary to form (N−1) sets of alignment marks at different locations. This hinders high integration of stacked semiconductor integrated circuits.

Specifically, as in an image sensor 131A shown in FIG. 8A, a silicon wafer 132A having a light receiving portion is stacked as a second layer on a first layer signal processing circuit (not shown). Assume the case of manufacturing an image sensor. In the case of the image sensor 131A, an alignment mark 135 having a size of several tens of μm to several hundreds of μm is arranged outside a pixel area 134 in which many pixels 133 of about 1 μm are arranged. Further, in the case of an image sensor, normally, a large number of electrode pads 136 are formed on the four sides of a silicon wafer 132A, wires 137 are joined to the electrode pads 136, and wiring is led out to the housing side (not shown).

On the other hand, the image sensor 131B shown in FIG. 8(b) has two layers of signal processing circuits (not shown) and a total of three layers of integrated circuits. In general, in order to improve the visibility of the alignment marks, wiring and circuits cannot be formed directly under the alignment marks. Therefore, in the conventional method of manufacturing a stacked semiconductor integrated circuit, it is necessary to form an alignment mark 135B at a location different from the alignment mark 135 on the silicon wafer 132B having the light receiving portion as the third layer. Therefore, in the conventional manufacturing method, as the number of stacked layers increases, the area occupied by the alignment marks increases in the limited area of the silicon wafer. This means that the area of the silicon wafer that cannot be used for circuit layout increases. As a result, in the conventional manufacturing method, it is difficult to improve the degree of integration. There are also manufacturing concerns such as lack of area for the electrode pads 136 and increased alignment marks interfering with wire bonding. Furthermore, if the size of the alignment mark itself is reduced, the precision of alignment by the camera will deteriorate, so there is a limit to reducing the size of the mark.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a stacked semiconductor integrated circuit in which the degree of integration of semiconductor circuits stacked in three or more layers is improved.

In order to solve the above problems, a stacked semiconductor integrated circuit according to a first aspect of the present invention has a semiconductor element and wiring formed in a predetermined region on a support substrate, and an alignment mark formed outside the predetermined region. A stacked semiconductor integrated circuit formed by bonding a predetermined number of integrated circuits of three or more in the plate thickness direction, wherein a first layer integrated circuit and the first layer integrated circuit are formed outside a predetermined region on the support substrate. a first alignment mark set consisting of alignment marks for alignment with a second layer integrated circuit laminated on the second layer integrated circuit; a second alignment mark set composed of alignment marks for aligning a third layer integrated circuit layered on the second layer; and a light shielding layer disposed below the second alignment mark set outside the predetermined region. , the second alignment mark set is arranged coaxially with respect to the first alignment mark set in the thickness direction, and the first alignment mark set is embedded in the upper surface of the first layer integrated circuit. a lower first-layer alignment mark; and an upper second-layer alignment mark embedded in the lower surface of the second-layer integrated circuit so as to face the lower first-layer alignment mark, wherein the second alignment mark The set includes a lower second-layer alignment mark embedded in the upper surface of the second-layer integrated circuit, and an upper upper surface embedded in the lower surface of the third-layer integrated circuit so as to face the lower second-layer alignment mark. and a third layer alignment mark, wherein the lower surface of the lower second layer alignment mark is bonded to the light shielding layer .
A stacked semiconductor integrated circuit according to a second aspect of the present invention has a semiconductor element and wiring formed in a predetermined region on a support substrate, and an alignment mark formed outside a predetermined region on the support substrate. A stacked semiconductor integrated circuit formed by joining a predetermined number of integrated circuits as described above in the plate thickness direction, wherein a first-layer integrated circuit and a first-layer integrated circuit are stacked on the first-layer integrated circuit outside the predetermined region. a second-layer integrated circuit, a first alignment mark set including alignment marks for aligning the positions of the second-layer integrated circuit, the second-layer integrated circuit outside the predetermined region, and three layers laminated on the second-layer integrated circuit a second alignment mark set comprising an alignment mark for aligning an eye integrated circuit; and a light shielding layer disposed below the second alignment mark set outside the predetermined region, wherein the second alignment mark The set is arranged coaxially with respect to the first alignment mark set in the plate thickness direction, and the material of the alignment mark is an embedded electrode that joins the integrated circuits and electrically connects the wirings. material is the same as

Further, a method for manufacturing a stacked semiconductor integrated circuit according to the present invention provides three or more semiconductor elements and wirings formed in predetermined regions on a supporting substrate and alignment marks formed outside the predetermined regions on the supporting substrate. A method for manufacturing a stacked semiconductor integrated circuit by bonding a predetermined number of integrated circuits in the thickness direction, comprising a preparation step of preparing a plurality of integrated circuits having semiconductor elements formed on a support substrate; A light-shielding layer forming step of forming a light-shielding layer under the region where the alignment mark is formed in a second-layer integrated circuit arranged on the integrated circuit; a pre-bonding alignment mark forming step of forming the alignment marks for each of the third-layer integrated circuit arranged thereabove, and forming the alignment mark on the light-shielding layer of the second-layer integrated circuit; , as a first alignment mark set for optically aligning the alignment marks formed on the first-layer integrated circuit and the alignment marks formed on the light-shielding layer of the second-layer integrated circuit so as to face each other. a first bonding step of bonding the first-layer integrated circuit and the second-layer integrated circuit; and a removal step of removing the support substrate from the second-layer integrated circuit bonded to the first-layer integrated circuit. a post-bonding alignment mark forming step of forming an alignment mark on the light shielding layer of the second layer integrated circuit from which the supporting substrate has been removed and which is coaxial with the first alignment mark set in the plate thickness direction; , as a second alignment mark set for optically aligning the alignment marks formed in the post-bonding alignment mark forming step and the alignment marks formed in the third-layer integrated circuit so as to face each other, and a second bonding step of bonding the second layer integrated circuit and the third layer integrated circuit.

ADVANTAGE OF THE INVENTION This invention has the outstanding effect shown below.
According to the laminated semiconductor integrated circuit, since the alignment mark sets are arranged coaxially, the area occupied by the alignment marks does not increase even if the number of laminated layers increases. Therefore, the stacked semiconductor integrated circuit can improve the degree of integration of semiconductor circuits stacked in three or more layers.
Further, according to the method for manufacturing a stacked semiconductor integrated circuit, it is possible to provide a stacked semiconductor integrated circuit in which the degree of integration of semiconductor circuits stacked in three or more layers is improved.

1 is a cross-sectional view schematically showing a stacked integrated circuit device according to an embodiment of the present invention; FIG. FIG. 4 is an explanatory diagram of alignment marks formed before lamination of integrated circuits, in which (a) to (c) schematically show the first layer integrated circuit, and (d) to (f) schematically show the second layer integrated circuit. ing. 1. It is sectional drawing which shows typically the manufacturing process of the laminated integrated circuit device of FIG. 1, (a) shows the joining process of a 2nd layer, (b) shows typically the thinning process. 2A is a cross-sectional view schematically showing the manufacturing process of the stacked integrated circuit device of FIG. 1, where (a) is a process of forming an alignment mark after lamination, and (b) is a schematic representation of an alignment mark of a third-layer integrated circuit. showing. (a) to (f) are explanatory diagrams schematically showing conventional alignment marks. (a) to (c) are explanatory diagrams schematically showing a conventional substrate bonding method. BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing which shows typically the conventional three-layer board|substrate joining method, (a) has shown the removal process of a supporting substrate, (b) has shown the joining process of the 3rd layer. It is a top view which shows the conventional image sensor typically, (a) has shown the type which laminated|stacked two integrated circuits, (b) has shown the type which laminated|stacked three integrated circuits.

[Structure of Stacked Semiconductor Integrated Circuit]
First, the configuration of a stacked semiconductor integrated circuit will be described with reference to FIG.
The stacked semiconductor integrated circuit 1 is formed by bonding three or more predetermined number of integrated circuits each having a semiconductor element and wiring formed in a predetermined region and an alignment mark formed outside the predetermined region in the plate thickness direction. . The stacked semiconductor integrated circuit 1 includes a first integrated circuit 201, a second integrated circuit 202 stacked on the first integrated circuit 201, and three layers stacked on the second integrated circuit 202. and an eye integrated circuit 203 .

This stacked semiconductor integrated circuit 1 includes a first alignment mark set 361, a second alignment mark set 362, and a light shielding layer 352 arranged below the second alignment mark set 362. 362 is arranged coaxially with respect to the first alignment mark set 361 in the plate thickness direction.

The first alignment mark set 361 consists of alignment marks 361A and 361B for aligning the first layer integrated circuit 201 and the second layer integrated circuit 202 .
The alignment mark 361A is configured similarly to the cross-shaped alignment mark 102 shown in FIG. 5(c). The alignment mark 361B is configured similarly to the alignment mark 101 consisting of four squares shown in FIG. 5(c). Alignment marks 361A and 361B are arranged to face each other.
The alignment mark 361B is arranged on the lower side in the first alignment mark set 361 and is embedded in the top surface of the first layer integrated circuit 201, so it is also called a lower first layer alignment mark.
The alignment mark 361A is arranged on the upper side in the first alignment mark set 361 and is embedded in the lower surface of the second layer integrated circuit 202, so it is also called an upper second layer alignment mark.

The second alignment mark set 362 consists of alignment marks 362A and 362B for aligning the positions of the second layer integrated circuit 202 and the third layer integrated circuit 203 .
The alignment mark 362A is configured similarly to the cross-shaped alignment mark 102 shown in FIG. 5(c). The alignment mark 362B is configured similarly to the alignment mark 101 consisting of four squares shown in FIG. 5(c). Alignment marks 362A and 362B are arranged to face each other.
The alignment mark 362B is arranged on the lower side in the second alignment mark set 362 and is embedded in the upper surface of the second layer integrated circuit 202, so it is also called a lower second layer alignment mark.
Since the alignment mark 362A is arranged on the upper side in the second alignment mark set 362 and is embedded in the lower surface of the third layer integrated circuit 203, it is also called an upper third layer alignment mark.

The first-layer integrated circuit 201 includes a transistor 331 as a semiconductor element, a wiring 341, a light-shielding layer 351, a lower first-layer alignment mark 361B, an embedded electrode 371B, and an insulating layer 381 on a first substrate 301. and have.
The second layer integrated circuit 202 includes a buried oxide film 322, a transistor 332 as a semiconductor element, a wiring 342, an upper second layer alignment mark 361A, a light shielding layer 352, a lower second layer alignment mark 362B, An embedded electrode 371A, an embedded electrode 372B, and an insulating layer 382 are provided.
The third layer integrated circuit 203 includes a third substrate 303, a transistor 333 as a semiconductor element, a wiring 343, a light blocking layer 353, an upper third layer alignment mark 362A, an embedded electrode 372A, an insulating layer 383, It has

The first substrate 301 is an SOI (Silicon on insulator) substrate and includes a support substrate 311 and a buried oxide film 321 . The third substrate 303 is also an SOI substrate and includes a support substrate 313 and a buried oxide film 323 . The buried oxide film 322 of the second-layer integrated circuit 202 is a member obtained by removing the support substrate from the second substrate, which is an SOI substrate, during the manufacturing process.

Transistor 331 is a fully depleted SOI transistor surrounded by insulating layer 381 and buried oxide film 321 . Transistor 332 is a fully depleted SOI transistor surrounded by insulating layer 382 and buried oxide layer 322 . Transistor 333 is a fully depleted SOI transistor surrounded by insulating layer 383 and buried oxide film 323 . Here, the transistors are assumed to be, for example, N-channel MOS transistors or P-channel MOS transistors. However, the structure of the transistor 331 and the like does not matter as long as the structure can exhibit the effects of the present invention.

As materials for the wirings 341 to 343, for example, metals such as Al, Cu, Au, and W can be used. As materials for the light shielding layers 351 to 353, for example, metals such as Al, Cu, Au, and W can be used. The material of the light shielding layer is preferably the same material as the wiring. As an example, it is assumed that the material of the wiring and the light shielding layer is Al. The light shielding layer 352 has an outer shape larger than the outer shape of the first alignment mark set 361 . The size of the light shielding layer 352 is preferably large enough to hide the entire area of the first alignment mark set 361 when the first alignment mark set 361 is viewed from above.

As materials for the alignment marks 361A, 361B, 362A, and 362B, for example, metals such as Cu and Au can be used. The material of the alignment marks is preferably the same as that of the embedded electrodes. As an example, it is assumed that the material of the alignment marks and embedded electrodes is Cu. The lower surface of the alignment mark 362B is bonded to the light shielding layer 352. As shown in FIG.

The embedded electrode 371 is an electrode formed by bonding an embedded electrode 371A and an embedded electrode 371B. The embedded electrode 371 joins the integrated circuits 201 and 202 together and electrically connects the circuit wirings 341 and 342 together. The embedded electrode 372 is an electrode formed by joining an embedded electrode 372A and an embedded electrode 372B. The embedded electrode 372 joins the integrated circuits 202 and 203 together and electrically connects the circuit wirings 342 and 343 together. As materials for the embedded electrodes 371 and 372, materials suitable for bonding, such as metals such as Cu and Au, can be used. As materials for the insulating layers 381, 382 and 383, oxide films such as SiO ₂ and Al ₂ O ₃ , Si ₃ N ₄ and MgF ₂ can be used.

[Manufacturing method of stacked semiconductor integrated circuit]
Next, a method of manufacturing the stacked semiconductor integrated circuit 1 will be described with reference to FIGS. The manufacturing method of the stacked semiconductor integrated circuit 1 includes a preparation process, a light shielding layer forming process, a pre-bonding alignment mark forming process, a first bonding process, a removal process, a post-bonding alignment mark forming process, and a second bonding. and a step.

(Preparation process)
The preparation step is a step of preparing a plurality of integrated circuits having semiconductor elements formed on a support substrate. In this step, an integrated circuit (first layer, second layer, third layer) including transistors, wiring, etc. is formed on the SOI substrate by a general semiconductor integrated circuit process.
As an example of the first-layer integrated circuit, FIG. 2A schematically shows a circuit board in which a transistor 331 and wiring 341 are formed on a first substrate 301 made of an SOI substrate. As an example of a second-layer integrated circuit arranged on the first-layer integrated circuit, FIG. is schematically shown. In addition, in FIGS. 2A and 2D, the cross sections of the circuits of the first layer and the second layer are drawn in the same manner, but generally the circuit layouts of these layers are different. Also, since the third-layer integrated circuit arranged on the second-layer integrated circuit has the same structure, it is not illustrated here.

(Light shielding layer forming step)
The light shielding layer forming step is a step of forming the light shielding layer 352 under the region where the alignment mark 361A is formed in the second layer integrated circuit. In this process, the size of the light shielding layer 352 is larger than the alignment mark 361B formed in the first layer integrated circuit and larger than the alignment mark 361A formed in the second layer integrated circuit in plan view. A light shielding layer 352 is formed as follows. The light shielding layer 352 is preferably formed of the same material as the wiring 342 at the same time as the step of forming the wiring 342 in the second layer integrated circuit. When a total of three layers of integrated circuits are stacked, the second integrated circuit requires a light shielding layer, but the other integrated circuits do not necessarily require a light shielding layer. However, since the light-shielding layer serves as an etching stop for holes for burying alignment marks in the integrated circuit of each layer, it is desirable to form the light-shielding layer in each layer. Here, the light shielding layer 351 is formed with the same material as the wiring 341 at the same time as the step of forming the wiring 341 in the first layer integrated circuit.

(Pre-bonding alignment mark forming process)
In the pre-bonding alignment mark forming step, as shown in FIGS. 2(b) and 2(c), alignment marks 361B are formed in the first layer integrated circuit, and the alignment marks 361B are formed in FIGS. 2(e) and 2(f). As shown, this is a step of forming alignment marks 361A on the light shielding layer 352 of the second layer integrated circuit. In addition, in this pre-bonding alignment mark forming process, an alignment mark is similarly formed on the third layer integrated circuit, but it is not illustrated here.

For example, the alignment marks 361B formed in the first-layer integrated circuit are preferably formed of the same material as the embedded electrodes 371B at the same time as the step of forming the embedded electrodes 371B. As shown in FIG. 2C, the insulating layer 381 is formed with embedded electrodes 371B connected to the wiring 341. As shown in FIG. At this time, as shown in FIGS. 2B and 2C, alignment marks 361B are formed at the same time. FIG. 2B is a plan view of the light shielding layer 351 and the alignment marks 361B.

Also, the alignment mark 361A formed in the second-layer integrated circuit is preferably formed of the same material as the embedded electrode 371A at the same time as the step of forming the embedded electrode 371A. As shown in FIG. 2( f ), embedded electrodes 371 A are formed in the insulating layer 382 so as to be connected to the wirings 342 . At this time, as shown in FIGS. 2(e) and 2(f), alignment marks 361A are formed at the same time. FIG. 2E is a plan view of the light shielding layer 352 and the alignment mark 361A.

Furthermore, as shown in FIG. 4B, it is preferable that the alignment marks 362A formed in the third-layer integrated circuit are also formed of the same material as the embedded electrodes 372A at the same time as the step of forming the embedded electrodes 372A. .
In integrated circuits of each layer, embedded electrodes and alignment marks are generally formed by the damascene method. Moreover, it is preferable to planarize the surface of the substrate on which the embedded electrodes are formed so that bonding can be performed in a subsequent step. Chemical mechanical polishing (CMP) or the like can be used as a planarization method.

(First joining step)
The first bonding step is a step of bonding the first layer integrated circuit and the second layer integrated circuit using the first alignment mark set 361 . In this step, as shown in FIG. 3A, the alignment mark 361B formed on the first layer integrated circuit and the alignment mark 361A formed on the light shielding layer 352 of the second layer integrated circuit are opposed to each other. Optically aligned, the first layer integrated circuit and the second layer integrated circuit are directly bonded. At this time, since the material (for example, Cu) of the alignment mark and the material (for example, Al) of the light shielding layer are different, the alignment mark can be easily visually recognized due to the difference in color and reflectance. In addition, in this embodiment, bonding is performed by a hybrid bonding method that simultaneously performs bonding between the insulating layer 381 and the insulating layer 382 and bonding between the embedded electrode 371B and the embedded electrode 371A.

(Removal process)
The removing step is, as shown in FIG. 3B, a step of removing the support substrate 312 from the second layer integrated circuit bonded to the first layer integrated circuit. As a method for removing the support substrate 312, a general removing method, that is, a method using grinding or polishing can be used.

(Post-bonding alignment mark forming process)
As shown in FIG. 4A, the post-bonding alignment mark forming step is a step of forming an alignment mark 362B on the light shielding layer 352 coaxially with respect to the first alignment mark set 361 in the plate thickness direction. be. The alignment mark 362B is preferably formed of the same material as the embedded electrode 372B at the same time as the step of forming the embedded electrode 372B. Since the method of forming alignment marks at this time is the same as the pre-bonding alignment mark forming process, further explanation is omitted.

(Second joining step)
The second bonding process is a process of bonding the second layer integrated circuit and the third layer integrated circuit using the second alignment mark set 362 . In the third-layer integrated circuit used here, as shown in FIG. 4B, embedded electrodes 372A and alignment marks 362A are separately formed in the insulating layer 383 on the third-layer substrate. It is. Note that here, the light shielding layer 353 is formed of the same material as the wiring 343 at the same time as the step of forming the wiring 343 in the third-layer integrated circuit. Then, in the second bonding step, as shown in FIG. 1, the alignment mark 362B formed on the second-layer integrated circuit and the alignment mark 362A formed on the third-layer integrated circuit are optically positioned to face each other. In addition, the second layer integrated circuit and the third layer integrated circuit are directly bonded. Thus, the three-layer stacked semiconductor integrated circuit 1 shown in FIG. 1 can be manufactured.

According to this embodiment, since the alignment mark sets 361 and 362 are all coaxially arranged, the area occupied by the alignment marks does not increase even if the number of layers of the integrated circuit increases, and the circuit can be effectively integrated. degree can be increased.
In addition, since the first alignment mark set 361 and the second alignment mark set 362 are arranged with the light shielding layer 352 interposed therebetween, the presence of the first alignment mark set 361 in the lower layer is difficult when aligning the multi-layer lamination. Visibility is not hindered by In addition, since the materials of the light shielding layer and the alignment marks are different, the alignment marks can be easily visually recognized.

Although the stacked semiconductor integrated circuits according to the embodiments of the present invention have been described above, the gist of the present invention is not limited to these descriptions, and should be broadly interpreted based on the description of the scope of claims. . In addition, it goes without saying that various changes and modifications based on these descriptions are also included in the gist of the present invention.
For example, arranging the alignment mark sets coaxially includes not only the case where the center points of the alignment mark sets are all aligned, but also the center points of the alignment marks are arranged to be shifted within a range in which the same effects of the present invention can be obtained. It also includes cases where

Also, although the wiring and the light shielding layer are illustrated and described as one layer for each integrated circuit, they may be multi-layered wiring. For example, in FIG. 4A, both the alignment mark 361A and the alignment mark 362B are in contact with the light blocking layer 352 of one layer. However, in the case of multi-layer wiring, a separate light shielding layer may be formed for each alignment mark. Specifically, when the multilayer wiring is a two-layer wiring, the second-layer integrated circuit has wiring in the in-plane direction instead of the wiring 342 in the in-plane direction. Equipped with wiring on the layer side. In this case, the second-layer integrated circuit includes, for example, a first-layer-side light-shielding layer and a second-layer-side light-shielding layer as the light-shielding layers 352 so as to correspond to this. Then, the light shielding layer on the first layer side contacts only the alignment mark 361A, and the light shielding layer on the second layer side contacts only the alignment mark 362B.

In addition, although the stacked semiconductor integrated circuit 1 having three layers is illustrated in FIG. 1, the stacked semiconductor integrated circuit may have four or more layers.
As an example, when the predetermined number of sheets is N and an integer of 4 or more and N or less is k (4≦k≦N), the N-layer stacked semiconductor integrated circuit includes the (k−1)th alignment mark set and the (k−1)th alignment mark set. k-1) a light shielding layer positioned under the alignment mark set. Here, the (k-1)th alignment mark set consists of alignment marks for aligning the positions of the (k-1)th layer integrated circuit and the kth layer integrated circuit. The (k-1)-th alignment mark set is arranged coaxially with the (k-2)-th alignment mark set in the plate thickness direction. Note that the integer k takes all integers from 4 to N in order.
Also, the light-shielding layer arranged under the (k-1)th alignment mark set has an outer shape larger than the outer shape of the (k-2)th alignment mark set.
The (k−1)th alignment mark set includes the lower (k−1)th layer alignment mark embedded in the upper surface of the (k−1)th layer integrated circuit and the lower (k−1)th layer alignment mark embedded in the lower surface of the kth layer integrated circuit. and an upper k-th layer alignment mark.

Further, by repeating the same steps as in the method of manufacturing the three-layer stacked semiconductor integrated circuit 1, a stacked semiconductor integrated circuit with four or more layers can be manufactured.
As an example, when the predetermined number is N and an integer between 4 and N is k (4≤k≤N), a method for manufacturing an N-layer stacked semiconductor integrated circuit can include the following steps. Note that the integer k takes all integers from 4 to N in order.
In the light-shielding layer forming step, the light-shielding layer is always formed under the region where the alignment mark is formed in the (k−1)-th layer integrated circuit.
In the pre-bonding alignment mark forming step, an alignment mark is formed on the light shielding layer of the (k−1)-th integrated circuit, and an alignment mark is formed for the N-th integrated circuit. In the (k-2)th bonding step, the alignment mark formed on the (k-2)th layer integrated circuit and the alignment mark formed on the essential light shielding layer of the (k-1)th layer integrated circuit and are used as a (k-2) alignment mark set for optical alignment by facing each other to join the (k-2)th layer integrated circuit and the (k-1)th layer integrated circuit.
In the removing step, the support substrate is removed from the (k-1)th layer integrated circuit joined to the (k-2)th layer integrated circuit.
In the post-bonding alignment mark forming step, alignment is performed on the light-shielding layer of the (k-1)-th integrated circuit from which the supporting substrate has been removed, coaxially with respect to the (k-2) alignment mark set in the plate thickness direction. form a mark.
In the (k−1)-th bonding step, the alignment mark formed in the immediately preceding post-bonding alignment mark forming step and the alignment mark formed in the k-th layer integrated circuit are optically positioned to face each other. The (k-1)-th layer integrated circuit and the k-th layer integrated circuit are joined by using the (k-1)th alignment mark set to be aligned.

1 stacked semiconductor integrated circuit device 201 first layer integrated circuit 202 second layer integrated circuit 203 third layer integrated circuit 301 first substrate 302 second substrate 303 third substrate 311-313 support substrate 321-323 buried oxide film 331- 333 transistors (semiconductor devices)
341 to 343 wiring 351 to 353 light shielding layer 361 first alignment mark set 361A alignment mark (upper second layer alignment mark)
361B Alignment mark (bottom first layer alignment mark)
362 second alignment mark set 362A alignment mark (upper third layer alignment mark)
362B Alignment mark (bottom second layer alignment mark)
371, 371A, 371B embedded electrodes 372, 372A, 372B embedded electrodes 381 to 383 insulating layer

Claims (9)

A laminated type in which a predetermined number of three or more integrated circuits, in which a semiconductor element and wiring are formed in a predetermined area on a supporting substrate and alignment marks are formed outside the predetermined area on the supporting substrate, are joined in the thickness direction. A semiconductor integrated circuit,
a first alignment mark set comprising alignment marks for aligning positions of a first layer integrated circuit and a second layer integrated circuit stacked on the first layer integrated circuit outside the predetermined region;
a second alignment mark set comprising alignment marks for aligning the positions of the second-layer integrated circuit and the third-layer integrated circuit stacked on the second-layer integrated circuit outside the predetermined region;
a light-shielding layer arranged under the second alignment mark set outside the predetermined region;
The second alignment mark set is arranged coaxially in the plate thickness direction with respect to the first alignment mark set,
The first alignment mark set includes:
a lower first-layer alignment mark embedded in the top surface of the first-layer integrated circuit;
an upper second-layer alignment mark embedded in the lower surface of the second-layer integrated circuit so as to face the lower first-layer alignment mark;
The second alignment mark set includes:
a lower second-layer alignment mark embedded in the upper surface of the second-layer integrated circuit;
an upper third-layer alignment mark embedded in the lower surface of the third-layer integrated circuit so as to face the lower second-layer alignment mark;
A stacked semiconductor integrated circuit, wherein a lower surface of the lower second layer alignment mark is bonded to the light shielding layer . A laminated type in which a predetermined number of three or more integrated circuits, in which a semiconductor element and wiring are formed in a predetermined area on a supporting substrate and alignment marks are formed outside the predetermined area on the supporting substrate, are joined in the thickness direction. A semiconductor integrated circuit,
a first alignment mark set comprising alignment marks for aligning positions of a first layer integrated circuit and a second layer integrated circuit stacked on the first layer integrated circuit outside the predetermined region;
a second alignment mark set comprising alignment marks for aligning the positions of the second-layer integrated circuit and the third-layer integrated circuit stacked on the second-layer integrated circuit outside the predetermined region;
a light-shielding layer arranged under the second alignment mark set outside the predetermined region;
The second alignment mark set is arranged coaxially in the plate thickness direction with respect to the first alignment mark set,
A laminated semiconductor integrated circuit, wherein the material of the alignment marks is the same as the material of embedded electrodes that join the integrated circuits and electrically connect the wirings. 2. The stacked semiconductor integrated circuit according to claim 1 , wherein the material of said alignment marks is the same as the material of embedded electrodes that join said integrated circuits together and electrically connect said wirings. 4. The stacked semiconductor integrated circuit according to claim 1, wherein said light shielding layer has an outer shape larger than an outer shape of said first alignment mark set. 5. The stacked semiconductor integrated circuit according to claim 1, wherein said light shielding layer is made of the same material as said wiring. A laminated type in which a predetermined number of three or more integrated circuits, in which a semiconductor element and wiring are formed in a predetermined area on a supporting substrate and alignment marks are formed outside the predetermined area on the supporting substrate, are joined in the thickness direction. A method for manufacturing a semiconductor integrated circuit, comprising:
a preparation step of preparing a plurality of integrated circuits having semiconductor elements formed on a support substrate;
a light-shielding layer forming step of forming a light-shielding layer under the region where the alignment mark is to be formed in the second-layer integrated circuit arranged on the first-layer integrated circuit;
forming the alignment marks for the first-layer integrated circuit and the third-layer integrated circuit arranged on the second-layer integrated circuit, and forming the light shielding layer of the second-layer integrated circuit; a pre-bonding alignment mark forming step of forming the alignment mark thereon;
Alignment marks formed on the first layer integrated circuit and alignment marks formed on the light shielding layer of the second layer integrated circuit are used as a first alignment mark set for optical alignment by facing each other. a first bonding step of bonding the first layer integrated circuit and the second layer integrated circuit;
a removing step of removing the supporting substrate from the second layer integrated circuit bonded to the first layer integrated circuit;
a post-bonding alignment mark forming step of forming an alignment mark on the light shielding layer of the second-layer integrated circuit from which the supporting substrate has been removed, the alignment mark being coaxial with the first alignment mark set in the board thickness direction;
The alignment marks formed in the post-bonding alignment mark forming step and the alignment marks formed in the third-layer integrated circuit are opposed to each other and used as a second alignment mark set for optically aligning the second alignment mark set. A method of manufacturing a stacked semiconductor integrated circuit, comprising: a second bonding step of bonding a first layer integrated circuit and the third layer integrated circuit. 7. The method of manufacturing a stacked semiconductor integrated circuit according to claim 6, wherein the light shielding layer formed on said second layer integrated circuit has an outer shape larger than the outer shape of said first alignment mark set. 8. The method according to claim 6, wherein the alignment marks are formed of the same material as the embedded electrodes at the same time as the step of bonding the integrated circuits to form embedded electrodes for electrically connecting the wirings. A method for manufacturing the stacked semiconductor integrated circuit described above. 9. The stacked semiconductor integrated circuit according to claim 6, wherein said light shielding layer is formed of the same material as said wiring at the same time as the step of forming wiring in said second layer integrated circuit. manufacturing method.

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