JP7253846B2 - Range image sensor and range image pickup device - Google Patents

Description

The present invention relates to a distance image sensor and a distance image pickup device.

Conventionally, the time of flight (Time of Flight, (hereinafter referred to as "TOF") type range image sensor has been realized. In a TOF-type range image sensor, a pulse of light (for example, near-infrared light) is irradiated to an object to be measured. The distance between the measuring instrument and the object is measured based on the difference from the arrival time, that is, the flight time of the light between the measuring instrument and the object.

At this time, when the background light in the environment of the measurement space is bright, when the distance to the object is short, or when the reflection coefficient of the surface of the object is large, the amount of reflected light input to the range image sensor increases. do.
In the TOF type distance image sensor, a photoelectric conversion element converts the amount of reflected light into electric charge, and an AD converter converts an analog voltage corresponding to the electric charge amount into a digital voltage.

However, when the intensity of the background light or the intensity of the reflected light from the object is high, the voltage corresponding to the charge amount is within the voltage range in which the analog voltage input to the AD converter (AD converter) can be converted into a digital value. may exceed the upper limit of the range (hereinafter simply the input range).
At this time. When an analog voltage equal to or higher than the upper limit value is input, it is clipped (limited) to the digital voltage corresponding to the upper limit value, and the time difference cannot be measured with high accuracy.
For the reasons described above, the distance measurement accuracy obtained from the time difference is lowered, and the distance measurement with high measurement accuracy cannot be performed when the background light is large or the intensity of the reflected light is high.

On the other hand, if the voltage input to the AD converter exceeds the input range of the AD converter, the range (output range) of the voltage output from the preceding circuit to the AD converter is adjusted to correspond to this input range. There is a method (for example, see Patent Document 1 and Patent Document 2).
Therefore, by applying the techniques of Patent Documents 1 and 2 to a TOF range image sensor, even if an analog voltage due to reflected light exceeding the upper limit is input, the digital voltage corresponding to the upper limit is clipped (limited). ), the time difference can be measured with high accuracy (see, for example, Patent Document 1).

JP 2017-108204 A JP 2011-242232 A

As described above, Patent Documents 1 and 2 convert the output range of the voltage supplied to the AD converter in accordance with the input range of the AD converter.
However, in Patent Document 1, in order to detect an input voltage to be AD-converted and correspond to the input range of the AD converter, a predetermined reference voltage is subtracted from the input voltage, and the voltage after this subtraction is sent to the AD converter. and supplies.
Further, in Patent Document 2, an amplifier circuit is provided in the front stage of the AD converter so that the input voltage to be AD-converted corresponds to the input range of the AD converter, and the gain and offset of this amplifier circuit are adjusted.

In Patent Documents 1 and 2, a predetermined amplifier circuit or the like is provided in the preceding stage of the AD converter in order to adjust the output range of the input voltage supplied to the AD converter so as to correspond to the input range of the AD converter. .
Therefore, in Patent Documents 1 and 2, in addition to the AD converter that performs AD conversion, an extra circuit such as an amplifier circuit that adjusts the input range is provided, resulting in a large circuit scale.

In particular, the TOF range image sensor performs AD conversion of voltage corresponding to the amount of charge for each column of pixel circuits arranged in a grid. A converter is provided.
Therefore, when the AD converters of Patent Documents 1 and 2 described above are used, the scale of the circuit for AD conversion of the range image sensor increases, and the range image sensor becomes larger (increases in chip area). Manufacturing costs rise.

In view of the above problems, even if the input voltage range exceeds the input range of the AD converter, there is no need to provide a circuit that changes the input voltage range in the front stage of the AD converter, and the resolution of the AD conversion of the input voltage is maintained. It is an object of the present invention to provide a distance image sensor and a distance image pickup device capable of AD-converting an input voltage with high precision.

In the distance image sensor of the present invention, light emitted from a predetermined light source to a measurement space, which is a space to be measured, is reflected by an object in the measurement space and a background in the environment of the measurement space. a photoelectric conversion element that receives light and generates charges corresponding to the received reflected light and the background light; and a charge storage unit that stores the charges when the irradiation light is applied in a frame period. a light-receiving pixel section having a pixel circuit for accumulating the charge in the charge accumulation section in synchronization with irradiation of the irradiation light; an AD converter; When AD-converting the input voltage corresponding to the charge amount obtained in each frame cycle, if the input voltage is not included in the input range of the AD converter, the arithmetic processing unit adjusts the voltage range of the input range to a predetermined range. an AD conversion circuit that adjusts the input range corresponding to the input voltage by shifting the shift voltage.

The distance image sensor of the present invention further includes a reference voltage generation unit that generates a reference voltage for controlling the voltage range of the input range of the AD conversion circuit corresponding to the shift voltage, and the arithmetic processing unit controls the input When the voltage is equal to or higher than the upper limit value of the input range of the AD converter, the shift voltage for shifting the voltage range of the input range is obtained, the shift voltage is supplied to the reference voltage generation unit, and the reference voltage generation unit generates the reference voltage corresponding to the shift voltage supplied from the arithmetic processing unit, supplies the reference voltage to the AD converter, and the AD converter supplies the shift voltage from the reference voltage generation unit. A reference voltage adjusts the voltage range of the input range.

In the distance image sensor of the present invention, when the input voltage exceeds the upper limit of the voltage range of the input range, the arithmetic processing unit shifts the input voltage by a preset shift voltage to a voltage side higher than the current voltage, and If the voltage is less than the lower limit of the voltage range of the input range, the voltage is shifted to the voltage side lower than the current time by a preset shift voltage.

The distance image sensor of the present invention includes the pixel circuit in which the irradiation light is light pulses of the same pulse width that are irradiated at a predetermined cycle, and the light receiving pixel portions are arranged in a two-dimensional lattice, and the AD A conversion circuit is provided for each column of the grid-like arrangement.

The distance image sensor of the present invention further includes a pixel drive circuit that outputs an accumulation drive signal, the charge accumulation section has a plurality of distributed charge accumulation sections, and the pixel drive circuit Synchronizing with the irradiation of the light pulse, the distribution accumulation drive signal is sequentially output to the distribution charge accumulation unit in the period as the accumulation drive signal, and the distance between the distance image sensor and the object is obtained. Therefore, each charge generated by the photoelectric conversion element according to the amount of light received during the period of the reflected light is distributed and accumulated in each of the distributed charge accumulation units.

In the distance image sensor of the present invention, the arithmetic processing unit shifts the voltage range of the input range in correspondence with the voltage corresponding to the amount of charge in the charge accumulation unit in which charge due to background light is accumulated. .

In the distance image sensor of the present invention, the AD converter is provided for each column of the charge storage section of each of the pixel circuits in the grid arrangement, and the arithmetic processing section is arranged in the distribution charge storage section. The input range of each of the AD converters is adjusted independently for each column.

In the distance image sensor of the present invention, the arithmetic processing unit generates the shift voltage of the input range used when the AD converter AD-converts the input voltage, in units of columns in the lattice arrangement. This is performed in accordance with the AD conversion result of the input voltage in the frame period.

In the distance image sensor of the present invention, the arithmetic processing unit generates the shift voltage of the input range used when the AD conversion circuit AD-converts the input voltage, and is arranged in the columns of the grid arrangement. Further, for each pixel circuit, it is performed according to the AD conversion result of the input voltage for each pixel circuit in the immediately preceding frame period.

The distance image sensor of the present invention is shifted by the predetermined shift voltage in response to a shift control signal supplied from an external device.

A range image pickup apparatus of the present invention includes any one of the range image sensors described above, a light source unit for irradiating a measurement space, which is a space to be measured, with irradiation light, and a predetermined fixed number of charge allocation times. and the distance image sensor based on the amount of charge accumulated in each of the plurality of distributed charge storage units in the charge storage unit and the voltage obtained by shifting the input range of the AD conversion circuit. and a distance image processing unit that obtains a distance to the object existing in the measurement space.

In the distance image pickup device of the present invention, the distance image processing unit adds the shift voltage obtained by shifting the input range to the converted voltage obtained by AD-converting the voltage corresponding to the amount of electric charge. Then, the distance between the distance image sensor and the object existing in the measurement space is calculated from the addition result.

The present invention adjusts the input range of the AD converter to the range of the input voltage even if the intensity of background light or reflected light input to the distance image sensor increases and the range of the input voltage exceeds the input range of the AD converter. Therefore, a distance image sensor and a distance image sensor capable of accurately AD-converting an input voltage while maintaining the resolution of AD conversion of the input voltage without providing a circuit for changing the range of the input voltage in the preceding stage of the AD converter. An image capture device is provided.

1 is a block diagram showing a schematic configuration of a distance image pickup device according to an embodiment of the present invention; FIG. 1 is a block diagram showing a schematic configuration example of a distance image sensor used in the distance image pickup device 1 of the embodiment of the present invention; FIG. 3 is a circuit diagram showing an example of a configuration of a pixel circuit 321 arranged in a light-receiving pixel section 320 of an imaging element (distance image sensor 32) used in the distance image pickup device 1 of the embodiment of the present invention; FIG. 4 is a timing chart showing the timing of driving the pixel circuits 321 arranged in the light-receiving pixel section 320 of the imaging element (distance image sensor 32) used in the distance image pickup device 1 of the embodiment of the present invention. 3 is a conceptual diagram showing a configuration example of an AD conversion circuit that AD-converts an input voltage supplied from a pixel signal processing circuit in the embodiment; FIG. FIG. 4 is a block diagram showing a configuration example of a column AD conversion circuit in a column AD conversion unit 329j according to the present embodiment; FIG. 4 is a diagram illustrating processing for shifting an input range in an AD converter; FIG. 4 is a diagram illustrating processing for shifting an input range in an AD converter; FIG. 4 is a diagram illustrating processing for shifting an input range in an AD converter; 5 is a flowchart showing an operation example of AD conversion and input range shift of a column conversion circuit; FIG. 7 is a conceptual diagram illustrating processing for shifting the input range of the AD converter shown in FIG. 6; FIG. 7 is a conceptual diagram illustrating processing for shifting the input range of the AD converter shown in FIG. 6; FIG. 5 is a diagram for explaining the effect of improving distance resolution by increasing the number of accumulation cycles in a frame cycle; FIG. 5 is a block diagram showing a schematic configuration of a distance image pickup device according to a second embodiment of the present invention; FIG. 13 shows a configuration example of a column AD conversion circuit 329j (CS1)' in the second embodiment; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of the distance image pickup device of this embodiment. Note that FIG. 1 also shows a subject S, which is a subject whose distance is to be measured by the distance image pickup device 1 .
A distance image pickup device 1 having the configuration shown in FIG.

Under the control of the range image processing unit 4, the light source unit 2 irradiates intermittent light pulses PO at a predetermined cycle to the space where the subject S whose distance is to be measured in the range image pickup device 1 exists. The light source unit 2 is, for example, a vertical cavity surface emitting laser (VCSEL: Vertical
It is a surface emitting semiconductor laser module such as a cavity surface emitting laser.

The light source device 21 is, for example, a light source that emits a laser beam in a near-infrared wavelength band (for example, a wavelength band of 850 nm to 940 nm) as a light pulse PO to irradiate the subject S. The light source device 21 is, for example, a semiconductor laser light emitting device. The light source device 21 emits pulsed laser light (optical pulse PO) under the control of the timing control section 41 .

The diffusion plate 22 is an optical component that diffuses the laser light in the near-infrared wavelength band emitted by the light source device 21 to a predetermined cross-sectional area for irradiating the measurement space P in which the object S is present. The pulsed laser light diffused by the diffusion plate 22 is emitted from the light source unit 2 as a light pulse PO, and the object S in the measurement space P is irradiated with the pulsed laser light.

The light receiving unit 3 receives the reflected light RL of the light pulse PO reflected by the subject S whose distance is to be measured in the distance image pickup device 1, and outputs a pixel signal corresponding to the received reflected light RL.

The lens 31 is an optical lens that guides the incident reflected light RL to the range image sensor 32 . The lens 31 emits the incident reflected light RL to the distance image sensor 32 side, and causes pixels provided in the light receiving area of the distance image sensor 32 to receive the light (incident).

The distance image sensor 32 is an image pickup device used in the distance image pickup device 1 . The distance image sensor 32 has a plurality of pixels in a two-dimensional light receiving area. Each pixel includes one photoelectric conversion element, a plurality of charge storage units corresponding to the one photoelectric conversion element, and each The imaging device has a distributing structure and is provided with a component for distributing the electric charge to the electric charge accumulating section. The distance image sensor 32 distributes the charges generated by the photoelectric conversion elements that make up the pixels to the respective charge storage units in accordance with the control from the timing control unit 41, and stores the charges according to the amount of charge distributed to the respective charge storage units. output the pixel signal.

In the distance image sensor 32, a plurality of pixels are arranged in a two-dimensional lattice (matrix), and pixel signals for one frame corresponding to each pixel are output.

The distance image processing unit 4 is a control unit that controls the entire distance image pickup device 1 and is also a calculation unit that calculates the distance to the subject S to be measured in the distance image pickup device 1 . The distance image processing section 4 includes a timing control section 41 and a distance calculation section 42 .

The timing control unit 41 controls the timing at which the light source unit 2 irradiates the subject S with the light pulse PO, the timing at which the distance image sensor 32 provided in the light receiving unit 3 receives the reflected light RL, and the like.

The distance calculation unit 42 outputs distance information obtained by calculating the distance between the distance image capturing device 1 and the subject S based on the pixel signals output from the distance image sensor 32 .

With such a configuration, in the distance image capturing device 1, the light receiving unit 3 receives the reflected light RL that is reflected by the subject S from the light pulse PO in the near-infrared wavelength band that the light source unit 2 irradiates the subject S, The distance image processing unit 4 outputs distance information obtained by measuring the distance to the subject S. FIG.

Although FIG. 1 shows the distance image pickup device 1 having a configuration in which the distance image processing unit 4 is provided inside, the distance image processing unit 4 is a component provided outside the distance image pickup device 1. may

Next, the configuration of the distance image sensor 32 used as an imaging device in the distance image pickup device 1 will be described. FIG. 2 is a block diagram showing a schematic configuration of an imaging device (distance image sensor 32) used in the distance image pickup device 1 of the embodiment of the present invention. 2, the distance image sensor 32 includes a light receiving area 320 in which a plurality of pixel circuits 321 are arranged, a control circuit 322, a vertical scanning circuit 323, a horizontal scanning circuit 324, a pixel signal processing circuit 325, and a pixel driving circuit 325. and circuit 326 . Note that the distance image sensor 32 shown in FIG. 2 shows an example of a light receiving region 320 in which a plurality of pixel circuits 321 are arranged in a two-dimensional grid pattern of 8 rows and 8 columns.

The control circuit 322 controls components provided in the distance image sensor 32 such as a vertical scanning circuit 323 , a horizontal scanning circuit 324 , a pixel signal processing circuit 325 and a pixel driving circuit 326 . For example, the control circuit 322 operates components provided in the range image sensor 32 according to control from the range image processing section 4 (more specifically, the timing control section 41) included in the range image capturing apparatus 1. to control. The control of the components provided in the distance image sensor 32 by the control circuit 322 may be performed directly by the distance image processing unit 4 (more specifically, the timing control unit 41), for example. In this case, the distance image sensor 32 may be configured without the control circuit 322 .

The pixel drive circuit 326 stores electric charges generated by photoelectric conversion elements (photoelectric conversion elements PD, which will be described later) included in the pixel circuits 321 arranged in a grid pattern, into a plurality of charge storage units (charge storage units, which will be described later) included in the pixel circuits 321. CS1, CS2, and CS3) and accumulate them (accumulation drive signals TX1, TX2, TX3 and a reset drive signal RSTD, which will be described later) are stored in columns of pixel circuits 321 arranged in a grid pattern in the light-receiving pixel portion 320. Output in units.
The vertical scanning circuit 323 controls each of the pixel circuits 321 arranged in the light-receiving pixel section 320 according to the control from the control circuit 322, and converts the incident light from each of the pixel circuits 321 into a charge amount. It is a drive circuit that outputs (reads out) a corresponding voltage signal (hereinafter referred to as “voltage signal”) to the corresponding vertical signal line 327 . The vertical scanning circuit 323 supplies control signals (selection drive signals SEL1, SEL2, and SEL3, which will be described later) for driving (controlling) and reading out the pixel circuits 321 to the pixel circuits 321 arranged in a grid pattern in the light receiving pixel portion 320. output line by line.
As a result, a voltage signal corresponding to the amount of charge distributed to each charge accumulation portion in the pixel circuit 321 is read out to each of the vertical signal lines 327 corresponding to each row of the light receiving pixel portion 320, and the pixel signal processing circuit 325.

In the light-receiving pixel portion 320, the pixel circuit 321 receives the reflected light RL that is reflected by the subject S from the light pulse PO emitted from the light source portion 2 to the subject S, and receives the reflected light RL according to the amount of received reflected light RL (the amount of received light). generate an electric charge. In each pixel circuit 321, the pixel drive circuit 326 outputs an accumulation drive signal, thereby distributing electric charge according to the light amount (light reception amount) of the received reflected light RL to one of the plurality of electric charge accumulation units. to accumulate. In the pixel circuit 321, the vertical scanning circuit 323 outputs a readout drive signal to output a voltage signal having a magnitude corresponding to the amount of charge accumulated in each charge accumulation portion. Output to the vertical signal line 327 . A detailed description of the configuration and driving (controlling) method of the pixel circuit 321 will be given later.

The pixel signal processing circuit 325 performs predetermined signal processing on the voltage signal output to the corresponding vertical signal line 327 from the pixel circuit 321 of each column according to the control from the vertical scanning circuit 323 . It is a signal processing circuit. The predetermined signal processing includes, for example, noise suppression processing for suppressing noise contained in the voltage signal by correlated double sampling (CDS).
The AD conversion circuit 329 AD-converts the analog voltage signals for each column supplied from the pixel signal processing circuit 325 via the vertical signal line 330 and converts them into digital values.

Note that the pixel signal processing circuit 325 may be a pixel signal processing circuit group including a plurality of pixel signal processing circuits corresponding to each column of the light receiving pixel section 320 . In this case, the pixel signal processing circuit 325 outputs a voltage signal after predetermined signal processing to the AD conversion circuit 329 via the vertical signal line 330 under the control of the control circuit 322 .
Then, the AD conversion circuit 329 outputs to the horizontal signal line 338 for each row of the light receiving pixel portion 320 under the control of the horizontal scanning circuit 324 .

The horizontal scanning circuit 324 converts a digital value obtained by AD-converting the voltage signal after signal processing, which is output from the AD conversion circuit 329 via the signal line 328, into a horizontal signal in accordance with the control of the control circuit 322. It is a driving circuit that sequentially outputs (reads out) to the line 338 . The horizontal scanning circuit 324 sequentially outputs to the pixel signal processing circuit 325 readout drive signals for causing the pixel circuits 321 in each column to output corresponding voltage signals. As a result, the voltage signals for one frame after signal processing output from the pixel signal processing circuit 325 are sequentially output to the outside of the distance image sensor 32 via the horizontal signal line 329 as pixel signals for one frame. be done. At this time, the distance image sensor 32 outputs the voltage signal after signal processing to the outside of the distance image sensor 32 as a pixel signal from an output circuit (not shown) such as an output amplifier.

In the following description, the pixel signal processing circuit 325 provided in the distance image sensor 32 performs noise suppression processing on the voltage signal output from the pixel circuit 321, and then the AD conversion circuit 329 performs A/D conversion processing. , that is, the voltage signal converted into a digital value is output from the horizontal signal line 338 .

Next, the configuration of the pixel circuit 321 arranged in the light receiving area 320 provided in the distance image sensor 32 will be described. FIG. 3 is a circuit diagram showing an example of the configuration of the pixel circuit 321 arranged in the light receiving area 320 of the imaging device (distance image sensor 32) used in the distance image pickup device 1 of the embodiment of the present invention. FIG. 3 shows an example of the configuration of one pixel circuit 321 among the plurality of pixel circuits 321 arranged in the light receiving region 320. As shown in FIG. The pixel circuit 321 is an example of a configuration including three pixel signal readout units.

The pixel circuit 321 includes one photoelectric conversion element PD, a drain gate transistor GD, and three pixel signal readout units RU for outputting voltage signals from corresponding output terminals O. As shown in FIG. Each pixel signal readout unit RU includes a readout gate transistor G, a floating diffusion FD, a charge storage capacitor C, a reset gate transistor RT, a source follower gate transistor SF, and a selection gate transistor SL. In each pixel signal readout unit RU, the floating diffusion FD and the charge storage capacitor C constitute a charge storage unit CS. The drain gate transistor GD, read gate transistor G, reset gate transistor RT, source follower gate transistor SF, and select gate transistor SL are N-channel MOS transistors.

In FIG. 3, three pixel signal readout units RU are distinguished by adding numerals "1", "2" or "3" after the symbol "RU" of the three pixel signal readout units RU. do. Similarly, each component provided in the three pixel signal readout units RU is also indicated by a numeral representing each pixel signal readout unit RU after the symbol, so that each component corresponds to the pixel signal readout unit. RUs are distinguished. In the pixel circuit 321 shown in FIG. 3, the pixel signal readout unit RU1 that outputs a voltage signal from the output terminal O1 includes a readout gate transistor G1, a floating diffusion FD1, a charge storage capacitor C1, a reset gate transistor RT1, and a source. It has a follower gate transistor SF1 and a select gate transistor SL1. In the pixel signal readout unit RU1, the charge storage unit CS1 is composed of the floating diffusion FD1 and the charge storage capacitor C1. The pixel signal readout unit RU2 and the pixel signal readout unit RU3 also have the same configuration.

The photoelectric conversion element PD is an embedded photodiode that photoelectrically converts incident light to generate charges and accumulate the generated charges. In addition, in the present invention, the structure of the photoelectric conversion element PD provided in the pixel circuit 321 is not particularly defined. Therefore, the photoelectric conversion element PD may be, for example, a PN photodiode having a structure in which a P-type semiconductor and an N-type semiconductor are joined together, or an I-type semiconductor sandwiched between the P-type semiconductor and the N-type semiconductor. It may be a PIN photodiode with a structure. Further, the photoelectric conversion element provided in the pixel circuit 321 is not limited to a photodiode, and may be, for example, a photogate type photoelectric conversion element.

The drain gate transistor GD is a transistor for discarding charge generated and accumulated by the photoelectric conversion element PD in response to a drive signal input from the pixel drive circuit 326 and not transferred to each pixel signal readout unit RU. is. In other words, the drain gate transistor GD is a transistor that resets charges generated by the photoelectric conversion element PD and not used for measuring the distance to the subject S.

The readout gate transistor G is a transistor for transferring the charge generated and accumulated by the photoelectric conversion element PD to the corresponding charge accumulation unit CS according to the drive signal input from the pixel drive circuit 326 . The charge transferred by the readout gate transistor G is held (accumulated) in the corresponding charge storage section CS.
Here, in the pixel signal readout unit RU1, the readout gate transistor G1 has a drain connected to the second terminal of the photoelectric conversion element PD, a gate connected to the signal line LTX1 that propagates the storage drive signal TX1, and a source floating. It is connected to the diffusion FD1 and the first terminal of the charge storage capacitor C1.
Similarly, in the pixel signal readout unit RU2, the readout gate transistor G2 has a drain connected to the second terminal of the photoelectric conversion element PD, a gate connected to the signal line LTX2 that propagates the accumulation drive signal TX2, and a source floating. It is connected to the diffusion FD2 and the first terminal of the charge storage capacitor C2.
Similarly, in the pixel signal readout unit RU3, the readout gate transistor G3 has a drain connected to the third terminal of the photoelectric conversion element PD, a gate connected to the signal line LTX3 that propagates the accumulation drive signal TX3, and a source. is connected to the floating diffusion FD3 and the first terminal of the charge storage capacitor C3.
Each of the accumulation drive signal TX1, the accumulation drive signal TX2, and the accumulation drive signal TX3 described above is supplied from the pixel drive circuit 326 via the signal line LTX1, the signal line LTX2, and the signal line LTX3, respectively.

The charge storage capacitor C is a capacitor that holds (accumulates) the charge transferred by the corresponding readout gate transistor G. As shown in FIG.

The reset gate transistor RT is a transistor for discarding the charge held in the corresponding charge storage section CS according to the drive signal input from the vertical scanning circuit 323 . That is, the reset gate transistor RT is a transistor that resets the charge held in the corresponding charge storage section CS.

The source follower gate transistor SF is a transistor for amplifying a voltage signal corresponding to the amount of charge accumulated in the charge storage section CS connected to the gate terminal and outputting it to the corresponding selection gate transistor SL.

The select gate transistor SL is a transistor for outputting a voltage signal amplified by the corresponding source follower gate transistor SF from the corresponding output terminal O according to the drive signal input from the vertical scanning circuit 323 .

With the above-described configuration, in the pixel circuit 321, charges generated by photoelectrically converting light incident on the photoelectric conversion element PD are distributed to each of the three charge storage units CS, and each charge corresponding to the charge amount of the distributed charges is distributed to each of the three charge storage units CS. voltage signal is output to the pixel signal processing circuit 325 .

The configuration of the pixels arranged in the range image sensor 32 is not limited to the configuration including the three pixel signal readout units RU as shown in FIG. The pixel may have any configuration as long as it includes a plurality of pixel signal readout units RU for distributing charges generated and accumulated by the element PD. That is, the number of pixel signal readout units RU (charge storage units CS) provided in the pixels arranged in the distance image sensor 32 may be two, or may be four or more.

Moreover, in the pixel circuit 321 having the configuration shown in FIG. However, the charge accumulating section CS should be composed of at least the floating diffusion FD. In other words, the pixel circuit 321 may be configured without the respective charge storage capacitors C. FIG. This configuration has the effect of increasing the charge detection sensitivity. However, considering widening the dynamic range in distance measurement in the distance image pickup device 1, a configuration that can hold (accumulate) more charges is superior. For this reason, in the pixel circuit 321, the pixel signal readout unit RU is provided with the charge storage capacitor C, and the charge storage unit CS is configured by the floating diffusion FD and the charge storage capacitor C, so that the charge storage unit CS can be read only by the floating diffusion FD. is configured to hold (accumulate) a larger amount of charge than in the case of configuring

In the pixel circuit 321 having the configuration shown in FIG. 3, an example of the configuration including the drain gate transistor GD is shown. Alternatively, the pixel arranged in the distance image sensor 32 may be configured without the drain gate transistor GD.

Next, a method (timing) for driving (controlling) the pixel circuits 321 in the distance image pickup device 1 will be described. FIG. 4 is a timing chart showing the timing of driving the pixel circuits 321 arranged in the light receiving area 320 of the imaging element (distance image sensor 32) used in the distance image pickup device 1 of the embodiment of the present invention. FIG. 4 shows the timing of the driving signal of the pixel circuit 321 when causing the distance image sensor 32 to output one frame of pixel signals, and the timing of the light pulse PO with which the light source unit 2 irradiates the object S. As shown in FIG.

First, regarding the driving (control) of the pixel circuit 321 during the charge accumulation period in which the charges generated and accumulated by the photoelectric conversion element PD according to the amount of received light (the amount of received light) are allocated to the respective pixel signal readout units RU. explain. During the charge accumulation period, the light source unit 2 irradiates the subject S with a light pulse PO. Then, by driving the pixel circuit 321 in synchronization with the timing of irradiation with the light pulse PO, charges corresponding to the received background light and the reflected light RL are distributed to the respective charge storage units CS. The pixel driving circuit 326 simultaneously drives all the pixel circuits 321 arranged in the light receiving region 320, i.e., so-called global shutter driving, so as to distribute electric charges to the respective electric charge storage units CS provided in all the pixel circuits 321. Accumulate. The time during which the light source device 21 emits the pulsed laser light, that is, the pulse width Tw of the light pulse PO is a predetermined very short time such as 10 nS. The reason is that the maximum measurable distance (hereinafter referred to as "maximum measurable distance") is determined by the pulse width Tw of the optical pulse PO in distance measurement by the pulse modulation method. When the pulse width Tw of the optical pulse PO described above is 10 nS, the maximum measurement distance is 1.5 m. Further, simply increasing the pulse width Tw of the optical pulse PO, that is, increasing the emission time of the laser light in the light source device 21 allows the photoelectric conversion element PD to receive more reflected light RL. The resolution of the distance to the object S to which the object S is focused is lowered. On the other hand, when the pulse width Tw of the light pulse PO is short, the amount of charge generated by photoelectric conversion by the photoelectric conversion element PD is also small. Therefore, in the distance image pickup device 1, irradiation of the light pulse PO and charge distribution are performed multiple times so that a sufficient amount of charge is accumulated in each charge accumulation unit CS during the charge accumulation period.
Here, a configuration in which each of the vertical scanning circuit 323 and the pixel driving circuit 326 drives (controls) the pixel circuit 321 will be described. In the following description, the control circuit 322 outputs clock signals CK1, CK2, CK3, and CKRSTD for generating accumulation drive signals TX1, TX2, and TX3 and reset drive signals RSTD to the pixel drive circuit 326, respectively. In addition, the control circuit 322 outputs clock signals for generating selection drive signals SEL1, SEL2, SEL3 and reset signals RST1, RST2, RST3 to the vertical scanning circuit 323, respectively.

The charge accumulation period of the timing chart shown in FIG. 4 shows the driving timing of the pixel circuits 321 when irradiation of the light pulse PO and distribution of charges in all the pixel circuits 321 are performed multiple times. Note that the light pulse PO in the charge accumulation period of the timing chart shown in FIG. )” level, the irradiation of the light pulse PO is stopped (the light source device 21 is turned off). Also, the timing chart shown in FIG. 4 will be described starting from a state where all pixel circuits 321 are reset, that is, no charge is accumulated in the photoelectric conversion element PD and the charge accumulation section CS.

In the following description, times tA1 to tA5 are accumulation cycles for charge distribution, and a plurality of accumulation cycles are repeated during the charge accumulation period. Also, for example, the time widths between times tA1, tA2, tA3, and tA4, that is, the pulse widths of the optical pulse PO and the accumulation drive signals TX1, TX2, and TX3 are the same Tw.

In the charge accumulation period, first, the pixel driving circuit 326 generates light generated by photoelectric conversion of the photoelectric conversion element PD from time tA1, which is the same time as the pulse width Tw at which the light source unit 2 irradiates the light pulse PO. Charge corresponding to the background light before irradiation with the pulse PO is transferred to and accumulated in the charge accumulation unit CS1 via the readout gate transistor G1.

Thereafter, from time tA2, which is the same as the timing at which the light source unit 2 irradiates the light pulse PO, the pixel drive circuit 326 reads out the charges generated according to the light photoelectrically converted by the photoelectric conversion element PD through the readout gate transistor G2. are transferred to the charge storage unit CS2 and stored therein. Here, the charge accumulated in the charge accumulation unit CS2 is the charge corresponding to the reflected light RL reflected by the subject S within the time of the pulse width Tw during which the light pulse PO is emitted. This charge includes, in addition to the charge corresponding to the background light, the charge corresponding to the reflected light RL incident with a small delay time proportional to the distance (absolute distance) to the subject S. More specifically, for example, when the object S is located near the object S, the irradiated light pulse PO is reflected by the object S in a short time and returns as the reflected light RL. , more charges corresponding to the reflected light RL reflected by the object S existing at a near position are included.

After that, the pixel driving circuit 326 transfers the charge generated according to the light photoelectrically converted by the photoelectric conversion element PD from time tA3, which is the same timing as the timing at which the light source section 2 stops the irradiation of the light pulse PO, to the readout gate transistor G3. to the charge storage unit CS3 for storage. Here, the charge accumulated in the charge accumulation unit CS3 is the charge corresponding to the reflected light RL reflected by the object S outside the pulse width Tw during which the light pulse PO is emitted. This charge includes, in addition to the charge corresponding to the background light, the charge corresponding to the reflected light RL that has entered with many delay times proportional to the distance (absolute distance) to the subject S. More specifically, for example, when the subject S exists at a distant position, the irradiated light pulse PO is reflected by the subject S for a longer time and returns as the reflected light RL. The portion CS3 contains more charges corresponding to the reflected light RL reflected by the object S existing at a distant position.

After that, the pixel drive circuit 326 starts the charge generated according to the light photoelectrically converted by the photoelectric conversion element PD from time tA4, which is the same time as the pulse width Tw at which the light source unit 2 irradiates the light pulse PO. , the charge not used for measuring the distance to the subject S is discarded via the drain gate transistor GD. In other words, the photoelectric conversion element PD is reset.

After that, the pixel driving circuit 326 cancels the reset of the photoelectric conversion element PD at time tA5, which is the same time as the pulse width Tw in which the light source unit 2 irradiates the next light pulse PO. Then, the pixel driving circuit 326, similarly to the timing from time tA1, controls the charge generated by the next photoelectric conversion of the photoelectric conversion element PD, that is, the background light before the next irradiation of the light pulse PO. The charge thus obtained is transferred to the charge storage section CS1 via the readout gate transistor G1 and stored therein.

After that, the pixel drive circuit 326 repeats driving of the pixel circuit 321 (hereinafter referred to as “charge distribution driving”) similar to that from time tA1 to time tA5. As a result, in the charge accumulation period, the charge amount corresponding to repeated charge distribution driving is accumulated and held in each of the charge accumulation units CS provided in all the pixel circuits 321 . Note that the maximum number of times the charge distribution drive is repeated in the charge accumulation period is determined by the period at which the distance image sensor 32 outputs (acquires) pixel signals for one frame. More specifically, the time that the distance image sensor 32 acquires pixel signals for one frame minus the pixel signal readout period is equal to the time that the light source device 21 emits pulsed laser light, that is, It is the number of quotients obtained by dividing by the pulse cycle time To of the optical pulse PO. In the distance image sensor 32, the greater the number of times the charge distribution drive is performed, the greater the amount of charge accumulated (integrated) in each charge accumulation section CS, resulting in higher sensitivity. Thereby, the distance image sensor 32 can improve the resolution of the distance to the object S to be measured.

Subsequently, after the end of the charge accumulation period, the pixel circuit arranged in the light receiving region 320 outputs a voltage signal corresponding to the amount of charge distributed to each charge accumulation section CS provided in each pixel signal readout section RU. The drive (control) of the pixel circuits 321 during the pixel signal readout period in which the pixel signals are sequentially output for each of the 321 rows will be described. In the pixel signal readout period, the pixel circuits 321 arranged in the light-receiving region 320 are driven row by row, i.e., so-called rolling driving, to accumulate ( It causes the pixel signal processing circuit 325 to output a voltage signal corresponding to the amount of charge accumulated and held in a row-sequential manner.

As described above, in the distance image sensor 32 , the pixel signal processing circuit 325 performs predetermined signal processing such as noise suppression processing on the voltage signal output from each pixel circuit 321 . Here, the correlated double sampling (CDS) processing performed by the pixel signal processing circuit 325 as noise suppression processing is a voltage signal (hereinafter referred to as " This is the process of taking the difference between the distance pixel voltage signal PS”) and the voltage signal corresponding to the amount of charge in the reset state of the charge storage section CS (hereinafter referred to as the “reset voltage signal PR”). be. Therefore, in the pixel signal readout period, each voltage signal of the distance pixel voltage signal PS and the reset voltage signal PR corresponding to each charge storage section CS provided in each pixel circuit 321 is row-sequentially subjected to pixel signal processing. Output to circuit 325 .

During the pixel signal readout period of the timing chart shown in FIG. (integer above) are arranged, the distance pixel voltage signal It shows the driving timing of the pixel circuit 321 when outputting voltage signals of PS(i) and reset voltage signal PR(i). Note that in the timing chart shown in FIG. 4, the charge storage unit CS1(i), the charge storage unit CS2(i), and the charge storage unit CS3(i) provided in each pixel circuit 321(i) are sequentially voltage signal is output.

In the pixel signal readout period, first, during the period from time tR1 to time tR2, the vertical scanning circuit 323 outputs the distance pixel voltage signal PS1(i) from the output terminal O1(i) to the pixel signal processing circuit via the vertical signal line. 325 output. Thereby, the pixel signal processing circuit 325 temporarily holds the distance pixel voltage signal PS1(i) output from the pixel signal readout unit RU1(i) via the vertical signal line.

After that, during the period from time tR3 to time tR4, the vertical scanning circuit 323 outputs the reset voltage signal PR1(i) from the output terminal O1(i) to the pixel signal processing circuit 325 via the vertical signal line. As a result, the pixel signal processing circuit 325 converts the previously held distance pixel voltage signal PS1(i) and the reset voltage signal PR1(i) output from the pixel signal reading unit RU1(i) through the vertical signal line into , that is, the noise included in the voltage signal corresponding to the amount of charge accumulated (integrated) and held in the charge accumulation unit CS1(i) is suppressed.

After that, during the period from time tR4 to time tR7, the vertical scanning circuit 323 outputs the distance pixel voltage signal PS2(i) and the reset voltage signal PR2(i) to the output terminal O2 as in the period from time tR1 to time tR4. From (i), it is output to the pixel signal processing circuit 325 via the vertical signal line. Furthermore, during the period from time tR7 to time tR10, the vertical scanning circuit 323 outputs the distance pixel voltage signal PS3(i) and the reset voltage signal PR3(i) to the output terminals, as in the period from time tR1 to time tR4. Output from O3(i) to the pixel signal processing circuit 325 via the vertical signal line.

Thereafter, the vertical scanning circuit 323 sequentially drives the pixel circuits 321 (hereinafter referred to as “pixel signal readout drive”) in the same manner as from time tR1 to time tR10 for each pixel arranged in another row of the light receiving region 320. The circuit 321 (for example, each pixel circuit 321 arranged in the (i+1)th row) is made to sequentially output each voltage signal from all the pixel circuits 321 arranged in the light receiving region 320 .

With such a drive (control) method (timing), the pixel drive circuit 326 reads out pixel signals of charges generated and accumulated by the photoelectric conversion elements PD in each of the pixel circuits 321 arranged in the light receiving region 320. Distribution to the partial RU is performed multiple times.
In addition, the vertical scanning circuit 323 sequentially outputs voltage signals corresponding to the amount of charge accumulated (integrated) in the charge accumulation unit CS provided in the pixel signal readout unit RU to the pixel signal processing circuit 325 via the vertical signal line. Let

Note that the AD conversion circuit 329 performs A/D conversion processing on each voltage signal whose noise is suppressed for each row. Then, the horizontal scanning circuit 324 sequentially outputs the voltage signals of each row after the A/D conversion processing by the AD conversion circuit 329 in the order of the columns of the light receiving area 320 via the horizontal signal line. Thus, the distance image sensor 32 outputs pixel signals of all the pixel circuits 321 for one frame to the outside. As a result, in the distance image capturing device 1, the pixel signals for one frame are output to the distance calculation section 42 in so-called raster order.

As can be seen from the drive (control) timing of the pixel circuit 321 shown in FIG. 4, each of the pixel signals for one frame has three pixel signal readout units RU (charge It contains three voltage signals corresponding to each of the storage portions CS). Based on one frame of pixel signals output from the distance image sensor 32, the distance calculator 42 calculates the distance to the subject S for each pixel signal, that is, for each pixel circuit 321. .

Here, a method of calculating the distance between the distance image pickup device 1 and the subject S in the distance calculation unit 42 will be described. Here, the amount of charge corresponding to the background light before being irradiated with the light pulse PO distributed to the charge accumulation unit CS1 of the pixel signal readout unit RU1 is assumed to be the amount of charge Q1. A charge amount Q2 is a charge amount corresponding to the reflected light RL incident with a short delay time from the background light distributed to the charge storage unit CS2 of the pixel signal readout unit RU2. A charge amount Q3 is a charge amount corresponding to the background light distributed to the charge storage unit CS3 of the pixel signal readout unit RU3 and the reflected light RL incident with a large delay time. The distance calculator 42 obtains the distance D between each pixel circuit 321 and the object S by the following formula (1).

D=(Q3-Q1)/(Q2+Q3-2Q1)×Dm (1)

In the above equation (1), Dm is the maximum distance (maximum measurement distance) that can be measured by irradiation with the light pulse PO. Here, the maximum measured distance Dm is represented by the following formula (2).

Dm=(c/2)Tw (2)

In the above equation (2), c is the speed of light and Tw is the pulse width of the optical pulse PO.

As described above, the distance image pickup device 1 obtains the distance D between itself and the subject S for each pixel circuit 321 arranged in the light receiving pixel section 320 of the distance image sensor 32 .

Note that, as described above, the configuration of the pixel circuits arranged in a grid pattern in the range image sensor 32 is limited to the configuration including the three pixel signal readout units RU1, RU2 and RU3 as shown in FIG. However, the pixel circuit 321 may be a pixel circuit 321 having a configuration including one photoelectric conversion element PD and two or more pixel signal readout units RU for distributing charges generated and accumulated by the photoelectric conversion element PD. In this case, that is, even in a range image sensor in which pixels having different numbers of pixel signal readout units RU are arranged, the driving (control) method (timing) of the pixels is the same as that of the range image capturing apparatus 1 shown in FIG. can be easily realized by considering the driving (control) method (timing) of the pixel circuit 321 in . More specifically, the charge is distributed to the pixels in a cycle that maintains the phase relationship so that the phases of the drive signals input to the readout gate transistor G and the drain gate transistor GD provided in each pixel signal readout unit RU do not overlap each other. By repeating the driving, similarly to the distance image sensor 32, the charge corresponding to the corresponding light can be accumulated (integrated) in the charge accumulation section CS provided in each pixel signal readout section RU. By sequentially outputting voltage signals from all the pixels by pixel signal readout driving, pixel signals for one frame can be output to the outside of the range image sensor 32 in the same manner as the range image sensor 32 . As a result, the distance calculation unit 42 similarly operates the distance image pickup device based on the pixel signals for one frame output from the distance image sensor in which the pixel signal readout unit RU and the number of pixels with different configurations are arranged. The distance D between 1 and the subject S can be obtained for each pixel signal (each pixel).

Normally, since the distance image sensor accurately measures the distance to the object, all the pixel circuits 321 in the light receiving pixel section 320 are driven at the same timing within the accumulation period in accordance with the global shutter method. . That is, each of the accumulation drive signals TX1, TX2, TX3, and the reset drive signal RSTD is supplied to all the columns of the pixel circuits 321 in the grid-like arrangement of the pixel circuits 321 at the same timing.

In FIG. 2, for each column of the pixel circuits 321, each of the four timing adjustment circuits 326C and the driver circuit 326D outputs the accumulation drive signals TX1, TX2, and TX3 and the reset drive signal RSTD to each pixel circuit in the column. 321 supplies.

The readout gate transistors G1, G2, and G3 shown in FIG. 3 are controlled by the storage driving signals TX1, TX2, and TX3, respectively. stored in
The vertical scanning circuit 323 causes the source follower gate transistors SF1, SF2, and SF3 to output to the pixel signal processing circuit 325 voltages corresponding to the charge amounts of the charges accumulated in the accumulation units CS1, CS2, and CS3, respectively.
The vertical scanning circuit 323 controls the select gate transistors SL1, SL2, SL3 by outputting select drive signals SEL1, SEL2, and SEL3, respectively. As a result, each of the select gate transistors SL1, SL2, and SL3 outputs a voltage corresponding to the amount of charge accumulated in the accumulation units CS1, CS2, and CS3 from the output terminals O1, O2, and O3 to the distance pixel voltage signals PS1, PS2, PS3 (hereinafter referred to as input voltages VA (CS1), VA (CS2), and VA (CS3) to clarify that they are analog voltages) are output to the pixel signal processing circuit 325 .

FIG. 5 is a conceptual diagram showing a configuration example of an AD conversion circuit that AD-converts an input voltage supplied from a pixel signal processing circuit according to the embodiment.
The AD conversion circuit 329 has a column AD conversion section 329j for each column j in the pixel circuits 321 arranged in a lattice. The vertical signal line 330 (FIG. 2) consists of three vertical signal lines. For example, the vertical signal line 330j corresponding to column j of the pixel circuits 321 arranged in a lattice has vertical signal lines 330j (CS1), 330j (CS2) and 330j (CS3).
The column AD conversion unit 329j is provided corresponding to each of the output terminals O1, O2, and O3 in the column j, and is connected via vertical signal lines 330j (CS1), 330j (CS2), and 330j (CS3), respectively. column AD conversion circuits 329j (CS1), 329j (CS2), and 329j (CS3).
From the pixel signal processing circuit 325 to each of the column AD conversion circuits 329j (CS1), 329j (CS2) and 329j (CS3) via the vertical signal lines 330j (CS1), 330j (CS2) and 330j (CS3) Analog voltages corresponding to the amount of charge accumulated in the charge accumulation unit CS1 after signal processing are supplied as input voltages VA (CS1), VA (CS2), and VA (CS3), respectively. Vertical signal lines 330j (CS1), 330j (CS2) and 330j (CS3) are respectively connected to output terminals O1, O2 and O3 in the pixel circuit 321 of FIG.
Each of the column AD conversion circuits 329j (CS1), 329j (CS2) and 329j (CS3) converts the input voltages VA (CS1), VA (CS2) and VA (CS3) into digital signals obtained by AD conversion. The converted voltages VD(CS1), VD(CS2), and VD(CS3) are respectively corrected and output as pixel signals of output digital values OD(CS1), OD(CS2), and OD(CS3).

FIG. 6 is a block diagram showing a configuration example of a column AD conversion circuit in the column AD conversion section 329j according to this embodiment. Each of the column AD conversion circuits 329j (CS1), 329j (CS2) and 329j (CS3) has the same configuration. Therefore, in FIG. 6, the column AD conversion circuit 329j (CS1) will be described as a representative.
The column AD conversion circuit 329j (CS1) includes an AD converter 3291, an arithmetic processing section 3292, and a reference voltage generation section 3293, respectively.

The AD converter 3291 inputs the voltage range of the input range set to itself as an input range (that is, the full scale range of the AD converter) with a resolution corresponding to a predetermined number of bits (for example, 16 bits). The input voltage VA (CS1) is AD-converted and output as an AD-converted value VD (CS1) of a digital value (digital value indicated by bit representation).
Arithmetic processing unit 3292 determines that AD conversion value VD(CS1) output from AD converter 3291 is the upper limit value of the convertible input range of AD converter 3291 (the maximum number of bits that can be indicated by the number of bits corresponding to the resolution of AD conversion). value, that is, full scale). Here, if the AD conversion value VD (CS1) is the upper limit value of the convertible input range of the AD converter 3291, the arithmetic processing unit 3292 performs shift control indicating a shift voltage α for shifting the input range to a higher voltage range. A voltage signal is output to the reference voltage generator 3293 . Then, the arithmetic processing unit 3292 adds the digital value αD corresponding to the shift voltage α to the AD conversion value VD (CS1) in the frame cycle following the frame cycle in which the control voltage signal is output, and outputs the output digital value. Output as OD(CS1). The digital value αD is the digital value of the shift voltage α corresponding to the resolution of the AD converter 3291. That is, the digital value αD is the same digital value (digital value represented by a bit representation) as the AD-converted value VD output when the AD converter 3291 AD-converts the shift voltage α.

Arithmetic processing unit 3292 determines that AD conversion value VD (CS1) output from AD converter 3291 is the lower limit value of the convertible input range (full scale range) of AD converter 3291 (bit corresponding to AD conversion resolution). A determination is made as to whether it is the smallest value that can be represented by a number, ie, 0). Here, when the AD conversion value VD (CS1) is the lower limit value of the convertible input range of the AD converter 3291, the arithmetic processing unit 3292 outputs a control voltage indicating a shift voltage α for shifting the input range to a lower voltage range. signal to the reference voltage generator 3293 . Then, the arithmetic processing unit 3292 adds the digital value αD, which is the digital value of the shift voltage α, to the AD conversion value VD (CS1) in the frame cycle next to the frame cycle in which the control voltage signal is output, and outputs Output as a digital value OD (CS1).
The reference voltage generator 3293 outputs to the AD converter 3291 a reference voltage shifted by the shift voltage α indicated by the control voltage signal supplied from the arithmetic processor 3292 .
In addition, the AD converter 3291 shifts the input range by the shift voltage α in accordance with the reference voltage supplied from the reference voltage generator 3293 . As a result, the AD converter 3291 AD-converts the input voltage VA within the input range corresponding to the voltage range of the input range shifted by the shift voltage α.

FIG. 7 is a diagram for explaining processing for shifting the input range in the AD converter. 7(a), 7(b) and 7(c), the vertical axis represents the input voltage VA, and the horizontal axis represents the charge accumulated in each of the charge storage units CS1, CS2 and CS3. The types of charge amounts Q1, Q2, and Q3 are shown. That is, each of FIGS. 7A, 7B, and 7C shows the charge amounts Q1, Q2, and Q3, respectively, and the input voltage VA (CS1) supplied from the pixel signal processing circuit 325. , VA(CS2), and VA(CS3). 7(a), 7(b) and 7(c), the dotted area indicates the amount of charge corresponding to the background light, and the shaded area indicates the amount of charge corresponding to the reflected light. showing quantity.
In FIG. 7A, the input range of the AD converter 3291 is set to a predetermined input range A1 (0[V]≦VA≦1.0[V]). In the case of FIG. 7A, each of the input voltages VA (CS1), VA (CS2) and VA (CS3) is included in the input range A1 (0[V]≤VA≤1.0[V]). ing. Therefore, the column AD converter circuits 329j (CS1), 329j (CS2), and 329 (CS3) in each of the column AD converter circuits 329j (CS1), 329j (CS2), and 329j (CS3) have an input voltage VA (CS1) , VA(CS2), and VA(CS3) are converted to the AD conversion values VD(CS1), VD(CS2), and VD(CS3) of digital values as voltages from the lower limit (0 V) of the voltage range of the input range. can be converted.

Similarly, in FIG. 7B as well, the input range of the AD converter 3291 is set to a predetermined input range A1 (0[V]≦VA≦1.0[V]). However, in the case of FIG. 7(b), the intensity of the background light is higher than that in FIG. 7(a), so the voltage of the input voltage VA (CS1) is higher than in FIG. 7(a). As a result, each of the input voltages VA (CS2) and VA (CS3) exceeds the upper limit of the input range A1 (0[V]≤VA≤1.0[V]). Therefore, the AD converters 3291 of the column AD conversion circuits 329j (CS2) and 329j (CS3) are configured such that the input voltages VA (CS2) and VA (CS3) are in the input range A1 (0 [V] ≤ VA ≤ 1.0). [V]), the result of AD conversion of the input voltages VA (CS2) and VA (CS3) is set as the upper limit value in the input range corresponding to its own resolution. That is, when the input voltage VA to be input exceeds the input range, the AD converter 3291 sets the AD conversion value VD as a voltage limited to the upper limit of the input range capable of AD conversion (saturated voltage in AD conversion). Output.

FIG. 7C shows the voltage range of the input range of the AD converter 3291 from the input range A1 (0 [V] ≤ VA ≤ 1.0 [V]) to the input range A2 (0.5 [V] ≤ VA ≤ 1.5 [V]) is shifted by 0.5 [V]. As a result, each of the input voltages VA (CS1), VA (CS2) and VA (CS3) is included in the input range A2 (0.5[V]≤VA≤1.5[V]). As a result, the column AD converter circuits 329j (CS1), 329j (CS2), and 329j (CS3) in each of the column AD converter circuits 329j (CS1), 329j (CS2), and 329j (CS3) have the input voltage VA (CS1) , VA (CS2), and VA (CS3) are set to voltages from the lower limit (0.5 [V]) of the voltage range of the input range without limiting each to the voltage value of the lower limit of the input range capable of AD conversion. , can be converted into AD conversion values VD(CS1), VD(CS2), and VD(CS3) of corresponding digital values.
In the case of FIG. 7A described above, since the shift voltage α is 0 [V], the arithmetic processing unit 3292 adds the digital value αD corresponding to 0 [V] to the AD conversion value VD, It is output as an output digital value OD (CS1).
In addition, in the case of FIG. 7B, as in the case of FIG. 7A, since the shift voltage α is 0 [V], the arithmetic processing unit 3292 A digital value αD corresponding to is added and output.
On the other hand, in the case of FIG. 7C, since the shift voltage α is 0.5 [V], the arithmetic processing unit 3292 calculates the digital value αD corresponding to 0.5 [V] for the AD conversion value VD. It is added and output as an output digital value OD (CS1).

In the case of FIG. 7C, when the resolution of the AD converter 3921 does not change and the shift voltage α is Vα1, the input voltage VA is AD-converted within the input range, so even if the input range is shifted, the AD-convertible voltage range does not change.
That is, by shifting the input range by the shift voltage α, the voltage obtained by subtracting the shift voltage α from the input voltage VA is substantially AD-converted in the range of 0 [V] ≤ VA ≤ 1.0 [V]. will do. For example, when the input voltage VA corresponding to Q2 in FIG. −0.5[V]=0.8[V] is AD-converted in the range of 0[V]≦VA≦1.0[V]. Therefore, in order to obtain the AD conversion result of the actual input voltage VA in the arithmetic processing unit 3921, the AD conversion value VD indicating 0.8 V output from the AD converter 3291 is converted to 0 as the shift voltage α. It is necessary to add the digital value αD corresponding to .5[V] to obtain the output digital value OD (CS1).

The example of FIG. 7 similarly uses 0.5 [V] as the shift voltage α for the AD converters 3291 in each of the column AD conversion circuits 329j (CS1), 329j (CS2) and 329j (CS3). . In this case, when any of the AD converters 3291 of the column AD converter circuits 329j (CS1), 329j (CS2) and 329j (CS3) outputs the upper limit value of the input range that can be AD converted, the column AD converter circuit 329j (CS1 ), 329j (CS2), and 329j (CS3), the input ranges of all the AD converters 3291 are shifted.

On the other hand, after setting the input range A2 (0.5[V]≤VA≤1.5[V]) shown in FIG. ), the input voltage VA due to the background light charge amount Q1 becomes less than the minimum value of the input range A2 (0.5 [V] ≤ VA ≤ 1.5 [V]), and the AD conversion result is It becomes the minimum value of the AD conversion of the AD converter 3291 (black sunken). In this case, an accurate AD conversion value VD corresponding to the input voltage VA due to the amount of charge Q1 due to background light cannot be obtained.
Therefore, when the AD conversion value VD output from the AD converter 3291 is the lower limit value of the input range in which the AD conversion of the AD converter 3291 is possible, the arithmetic processing unit 3292 performs processing to lower the input range to a lower voltage range. It outputs the shifted voltage α to the reference voltage generator 3293 .

For example, as described above, when the intensity of the background light decreases, the arithmetic processing unit 3292 sets the input range of the AD converter 3291 to the input range A2 (0.5 [V] ≤ VA ≤ 1.5 [V]). to the input range A1 (0 [V] ≤ VA ≤ 1.0 [V]), the shift voltage α of 0 [V] is output to the reference voltage generator 3293 .
As a result, the reference voltage generation unit 3293 can generate the shift voltage α indicated by the control voltage signal supplied from the arithmetic processing unit 3292, that is, 0.5 [V] compared to the case where the shift voltage α is 0.5 [V]. ] outputs the shifted reference voltage to the AD converter 3291 .
As a result, the AD converter 3291 changes the input range from the input range A2 (0.5 [V] ≤ VA ≤ 1.5 [V]) to the input range A1 (0 [V] ≤ VA ≤ 1.0 [V]). ) to lower the voltage range of the input range.

FIG. 8 is a diagram for explaining processing for shifting the input range in the AD converter. In FIG. 8, the vertical axis indicates the input voltage VA, and the horizontal axis indicates the types of charge amounts Q1, Q2, and Q3 of the charges accumulated in the charge storage units CS1, CS2, and CS3, respectively. That is, FIG. 8 shows the relationship between the charge amounts Q1, Q2, and Q3 of charges and the input voltages VA (CS1), VA (CS2), and VA (CS3) supplied from the pixel signal processing circuit 325 as in FIG. It shows correspondence. In the graph of FIG. 8, similarly to the graph of FIG. 7, the dotted area indicates the amount of charge corresponding to the background light, and the hatched area indicates the amount of charge corresponding to the reflected light.
In the case of FIG. 8, since the charge amount Q1 of the charges in the charge storage section CS1 is the background light, the voltage VA can fall within the range of the input range A1 (0[V]≦VA≦1.0[V]). This is reliable, and the column AD conversion circuit 329j (CS1) is formed only of the AD converter 3291 whose input range is fixed at the input range A1. Other column AD conversion circuits 329j (CS2) and (CS3) in the column AD conversion section 329j are formed of the column AD conversion circuits shown in FIG. 6 capable of shifting the input range.

The example of FIG. 8 similarly uses 0.5 [V] as the shift voltage α for the AD converter 3291 in each of the column AD conversion circuits 329j (CS2) and 329j (CS3). In this case, when at least one of the column AD conversion circuits 329j (CS2) and 329j (CS3) outputs the upper limit value of the input range that can be AD converted by the AD converter 3291, the column AD conversion circuits 329j (CS2) and 329j (CS3) CS3) shifts the input ranges of both AD converters 3291 .
Therefore, in order to obtain the output digital values OD (CS2) and OD (CS3) as the results of actual AD conversion, the AD It is necessary to add the digital value αD corresponding to the shift voltage α to the AD conversion values VD(CS2) and VD(CS3) output from the converter 3291 .

FIG. 9 is a diagram for explaining processing for shifting the input range in the AD converter. In FIG. 9, the vertical axis indicates the input voltage VA, and the horizontal axis indicates the types of charge amounts Q1, Q2, and Q3 of the charges accumulated in the charge storage units CS1, CS2, and CS3, respectively. That is, FIG. 9 shows the relationship between the charge amounts Q1, Q2, and Q3 of charges and the input voltages VA (CS1), VA (CS2), and VA (CS3) supplied from the pixel signal processing circuit 325 as in FIG. It shows correspondence. In the graph of FIG. 9, as in the graph of FIG. 7, the dotted area indicates the amount of charge corresponding to the background light, and the hatched area indicates the amount of charge corresponding to the reflected light.
In the case of FIG. 9, it is assumed that the input voltage VA corresponding to the charge amounts Q1, Q2, and Q3 of the charges in the charge storage units CS1, CS2, and CS3, respectively, does not fall within the range of the input range A1. . Therefore, each of the column AD conversion circuits 329j (CS1), 329j (CS2) and 329j (CS3) is formed of the column AD conversion circuit shown in FIG. 6 capable of shifting the input range.
In the case of FIG. 9, each of the column AD conversion circuits 329j (CS1), 329j (CS2) and 329j (CS3) independently shifts the input range with a different shift voltage α.

For example, in the column AD conversion circuit 329j (CS1), the arithmetic processing unit 3292 sets the input range to the input range A1 (0 [V] ≤ VA ≤ 1.0 [V]) to the input range A1 (0 [V] ≤ VA ≤ 1.0 [V]) is set to 0 [V] as the shift voltage α, and the reference voltage generation unit 3293 Output for
As a result, the reference voltage generator 3293 outputs to the AD converter 3291 a reference voltage shifted by the shift voltage α indicated by the control voltage signal supplied from the arithmetic processor 3292 . As a result, the AD converter 3291 maintains the input range at the input range A1 (0 [V] ≤ VA ≤ 1.0 [V]) even in the next frame period.
At this time, in the arithmetic processing unit 3921, in order to obtain the actual AD conversion result, the digital value αD corresponding to 0 [V] as the shift voltage α is applied to the AD conversion value VD output from the AD converter 3291. are added to obtain and output the output digital value OD (CS1).

In addition, in the column AD conversion circuit 329j (CS2), the arithmetic processing unit 3292 sets the input range to the input range A2 ( 1.0 [V] as the shift voltage α for shifting from 0.5 [V] ≤ VA ≤ 1.5 [V]) to the input range A3 (1.0 [V] ≤ VA ≤ 2.0 [V]) is output to the reference voltage generator 3293 .
As a result, the reference voltage generator 3293 outputs to the AD converter 3291 a reference voltage shifted by the shift voltage α indicated by the control voltage signal supplied from the arithmetic processor 3292 . As a result, the AD converter 3291 changes the input range in the next frame period from the input range A2 (0.5 [V] ≤ VA ≤ 1.5 [V]) to the input range A3 (1.0 [V] ≤ VA ≤ 2.0 [V]).
At this time, in the arithmetic processing unit 3921, in order to obtain the actual AD conversion result, a digital value corresponding to 1.0 [V] as the shift voltage α is applied to the AD conversion value VD output from the AD converter 3291. Add the value αD to obtain the output digital value OD(CS1).

In addition, in the column AD conversion circuit 329j (CS3), the arithmetic processing unit 3292 sets the input range to the input range A1 ( 0 [V] ≤ VA ≤ 1.0 [V]) to the input range A2 (0.5 [V] ≤ VA ≤ 1.5 [V]) as a shift voltage α of 0.5 [V], Output to the reference voltage generator 3293 .
As a result, the reference voltage generator 3293 outputs to the AD converter 3291 a reference voltage shifted by the shift voltage α indicated by the control voltage signal supplied from the arithmetic processor 3292 . As a result, the AD converter 3291 changes the input range in the next frame period from the input range A1 (0 [V] ≤ VA ≤ 1.0 [V]) to the input range A2 (0.5 [V] ≤ VA ≤ 1 .5 [V]).
At this time, in the arithmetic processing unit 3921, in order to obtain the actual AD conversion result, a digital value corresponding to 0.5 [V] as the shift voltage α is applied to the AD conversion value VD output from the AD converter 3291. Add the value αD to obtain the output digital value OD(CS1).

In the above-described embodiment, the arithmetic processing unit 3292 increases the shift voltage α by 0.5 [V]. An arbitrary voltage unit (for example, 0 .1 [V], etc.) to gradually increase the shift voltage α.

Further, the AD conversion circuit 3291 may have a shift voltage α table referred to by the arithmetic processing units 3292 of the column AD conversion circuits 329j (CS1), 329j (CS2), and 329j (CS3). This shift voltage α table is a table showing the correspondence relationship between the voltage range, the shift voltage α corresponding to this voltage range, and the digital value αD.
That is, when the AD conversion value VD output by the AD converter 3291 is the upper limit value of the input range in which AD conversion of AD conversion is possible, the arithmetic processing unit 3292 calculates the AD conversion value VD output by the AD converter 3291 and the shift voltage α. are added, and the shift voltage α table is searched for a voltage range that includes the addition result. Then, the arithmetic processing unit 3292 may read out the shift voltage α and the digital value αD corresponding to the searched voltage range, and use them as a new shift voltage α and digital value αD.

Also, the voltage corresponding to the charge amount Q1 of the background light in the charge storage section CS1 is set as the shift voltage α, and the input range when AD-converting the charge amount Q2 of the charge storage section CS2 and the charge amount Q3 of the charge storage section CS3 is A configuration in which the shift voltage is α may also be used. In this configuration, the arithmetic processing unit 3292 of the column AD conversion circuit 329j (CS1) applies the AD conversion value VD output from the AD converter 3291 to the arithmetic processing of each of the column AD conversion circuits 329j (CS2) and 329j (CS3). Output to the part 3292 as the shift voltage α.
Accordingly, in each of the column AD conversion circuits 329j (CS2) and 329j (CS3), the arithmetic processing unit 3292 converts the shift voltage α supplied from the arithmetic processing unit 3292 of the column AD conversion circuit 329j (CS1) into the reference voltage Output to the generation unit 3293 . The reference voltage generator 3293 outputs to the AD converter 3291 a reference voltage shifted by the shift voltage α supplied from the arithmetic processor 3292 . As a result, the AD converter 3291 shifts the input range in the next frame period by a voltage amount corresponding to the background light charge amount Q1 accumulated in the charge accumulation unit CS1. As a result, in each of the column AD conversion circuits 329j (CS2) and 329j (CS3), the AD converter 3291 outputs an AD conversion value VD corresponding to the voltage of only the reflected light from which the voltage of the background light is removed.
Then, the arithmetic processing unit 3292 does not add the digital value αD corresponding to the shift voltage α to the AD conversion value VD (or adds the digital value αD corresponding to 0 [V] as the shift voltage α). , to obtain and output an output digital value OD (CS1).

FIG. 10 is a flowchart showing an operation example of AD conversion and input range shift of the column conversion circuit. The flowchart of FIG. 10 will be described on the premise that each of the column AD conversion circuits 329j (CS1), 329j (CS2), and 329j (CS3) in the column AD conversion section 329j performs input range shift processing independently. In the following description, the operation of the column AD converter circuit 329j (CS1) will be described as a representative of the column AD converter circuits 329j (CS1), 329j (CS2) and 329j (CS3). Further, the processing of the flowchart of FIG. 10 is executed for each frame period as an example.

Step S101: In a frame cycle, when the charge accumulation processing in the light-receiving pixel portion 320 is completed, the input voltage VA is sequentially transferred from the pixel circuits 321 in each row in the grid-like arrangement via the pixel signal processing circuit 325 to the AD conversion circuit. 329.
Then, the column AD conversion circuit 329j (CS1) acquires, from the pixel signal processing circuit 325, the voltage corresponding to the charge amount Q1 on which predetermined signal processing has been performed as the input voltage VA.
Step S102: In the column AD conversion circuit 329j (CS1), the AD converter 3291 performs AD conversion processing corresponding to the currently set input range, converts the input voltage VA into an AD conversion value VD, and outputs the converted value VD. .
Then, the arithmetic processing unit 3292 adds the digital value αD corresponding to the shift voltage α stored inside to the AD conversion value VD, and outputs the result as an output digital value OD (CS1).

Step S103: The arithmetic processing unit 3292 determines whether the AD conversion value VD (CS1) supplied from the AD converter 3291 is the upper limit value of the input range in which the AD conversion of the AD converter 3291 is possible (or a predetermined whether or not it exceeds the upper limit threshold value that has a margin).
At this time, if the AD conversion value VD(CS1) is equal to or greater than the maximum value (greater than or equal to the upper limit threshold value), arithmetic processing unit 3292 advances the process to step S104.
On the other hand, if the AD conversion value VD(CS1) is less than the maximum value (less than the upper limit threshold value), arithmetic processing unit 3292 advances the process to step S105.

Step S104: The arithmetic processing unit 3292 adds a predetermined voltage to the shift voltage α currently supplied to the reference voltage generation unit 3293 .
Then, the arithmetic processing unit 3292 changes the shift voltage α to a higher voltage and supplies the changed shift voltage α to the reference voltage generation unit 3293 .
As a result, the reference voltage generation unit 3293 increases the reference voltage supplied to the AD converter 3291 in correspondence with the newly supplied shift voltage α, and shifts the voltage range of the input range of the AD converter 3291 to the higher side. Let

Step S105: The arithmetic processing unit 3292 determines whether the AD conversion value VD (CS1) supplied from the AD converter 3291 is the lower limit value of the input range in which the AD conversion of the AD converter 3291 is possible (or a predetermined is less than the lower limit threshold with a margin). Here, the lower limit threshold is, for example, approximately 5% of the upper limit.
At this time, if the AD conversion value VD(CS1) is the minimum value (less than or equal to the lower limit threshold value), arithmetic processing unit 3292 advances the process to step S106.
On the other hand, if the AD conversion value VD(CS1) exceeds the minimum value (exceeds the lower limit threshold), the arithmetic processing unit 3292 ends the processing in this flowchart.

Step S106: The arithmetic processing unit 3292 subtracts a preset predetermined voltage from the shift voltage α supplied to the reference voltage generation unit 3293 at this time.
Then, the arithmetic processing unit 3292 changes the shift voltage α to a lower voltage and supplies the changed shift voltage α to the reference voltage generation unit 3293 .
As a result, the reference voltage generator 3293 decreases the reference voltage supplied to the AD converter 3291 in correspondence with the newly supplied shift voltage α, and shifts the voltage range of the input range of the AD converter 3291 to the lower side. Let

FIG. 11 is a conceptual diagram illustrating processing for shifting the input range of the AD converter shown in FIG. FIG. 11 shows an example in which a single slope AD converter (hereinafter referred to as a single slope AD converter) is used as the AD converter 3291 . FIG. 11(a) shows a configuration example of a single-slope AD converter. FIG. 11B shows AD conversion processing when the shift voltage α is 0 [V] and the input range includes the input voltage VA. FIG. 11C shows AD conversion processing when the shift voltage α is 0 [V] and the input range does not include the input voltage VA. FIG. 11D shows AD conversion processing when the shift voltage α is Aα1 [V] and the input range includes the input voltage VA. 11B, 11C, and 11D, the vertical axis indicates the reference voltage VL, and the horizontal axis indicates the count number of the counter 304. In FIG. In each of the graphs of FIGS. 11(b), (c), and (d), the line indicating the input voltage VA is indicated by a solid line segment L_VA, and the line indicating the reference voltage VL is indicated by a broken line segment L_VL. ing.

As shown in FIG. 11A, the AD converter 3291 has a comparator 301, a clock generation circuit 302, a ramp voltage generation circuit 303 and a counter 304.
The comparator 301 compares the input voltage VA with the gradually increasing reference voltage VL. For example, when the reference voltage VL becomes equal to or higher than the input voltage VA, the output is changed from the 'L' level to the 'H' level. change.
The ramp voltage generation circuit 303 increases the reference voltage VL stepwise by a predetermined voltage unit each time a pulse as a clock signal is supplied from the clock generation circuit 302 (FIGS. 11(c) to 11( d) see).
The counter 304 increases the number of counts each time a pulse as a clock signal is supplied from the clock generation circuit 302 .
The counter 304 counts up (the upper limit of the input range, which is the full-scale range in which AD conversion is possible for AD conversion already described) is d (for example, 255), and the voltage range of the input range of the AD converter 3291 is is the voltage VA, the resolution is VA/256. The ramp voltage generation circuit 303 increases the reference voltage VL by VA/256, which is the resolution, each time a pulse is input, and outputs the reference voltage VL to the comparator 301 . The counter 304 counts pulses when the voltage of the signal supplied from the comparator 301 is at the 'L' level, and stops counting when it reaches the 'H' level. Therefore, the count number output from the counter 304 indicates the AD conversion value VD (the result of multiplying the resolution voltage by the count number).

In FIG. 11B, the input range A0 is, for example, a voltage range VW from 0 V to 0.5 V, and the count number of intersections of the line segment L_VL with the line segment L_VA is the AD-converted value VD obtained by AD-converting the input voltage VA. It is a numerical value that represents The shift voltage α at this point is 0 [V].
On the other hand, in FIG. 11(c), the input range A0 is the voltage range VW from 0V to 0.5V, and the line segment L_VL does not cross the line segment L_VA. In this case, the count number becomes the maximum value d counted up, and the count number indicating the input voltage VA cannot be obtained.
Therefore, as shown in FIG. 11D, information indicating Vα1 as the shift voltage α is supplied from the arithmetic processing unit 3292 to the reference voltage generation unit 3293 .
In the cases of FIGS. 11B and 11C, since the shift voltage α is 0 [V], the ramp voltage generation circuit 303 sets the reference voltage VL to It was supplied to the comparator 301 by increasing it step by step.
However, in the case of FIG. 11D, since the shift voltage α is Vα1, the ramp voltage generation circuit 303 increases the reference voltage VL stepwise within the voltage range VW from Vα1 to voltage 0.5 [V]+Vα1. , to the comparator 301 .

As shown in FIG. 11(d), the reference voltage VL starts from the voltage Vα1 and does not change within the voltage range VW of the input range, that is, from Vα1 to voltage 0.5 [V]+Vα1. The number of counts where the segment L_VL intersects the line segment L_VA indicates the result of AD conversion of the voltage value from the voltage Vα1, that is, the input voltage VA−voltage Vα1 (the value obtained by subtracting the voltage Vα1 from the input voltage VA). Therefore, as already described, the arithmetic processing unit 3292 adds the count number corresponding to the voltage Vα1 (the digital value αD corresponding to the shift voltage α) to the AD conversion value VD output from the AD converter 3291, An output digital value OD is calculated from the addition result. Then, the distance D is obtained using each of the obtained output digital values OD(CS1), OD(CS2), and OD(CS3) and equations (1) and (2).

FIG. 12 is a conceptual diagram illustrating processing for shifting the input range of the AD converter shown in FIG. FIG. 12 shows an example of using a cyclic AD converter (see Japanese Patent No. 3962788, for example) as the AD converter 3291 .
In FIG. 12, in order to shift the input range of AD converter 3291, shift voltage α is applied as reference voltage VCOM to be applied to inverting amplifier 200, capacitor C1, and the like. As a result, the voltage range of the input range of the AD converter 3291 is increased by the shift voltage α, as in the case described with reference to FIG.
Therefore, the digital values D1 and D2 (AD conversion value VD) obtained as a result of AD conversion of the input voltage VAN (corresponding to the input voltages VA (CS1) and VA (CS2)) by the AD converter 3291 are input voltage VA - shift It shows the voltage value of the voltage α.
Therefore, as shown in FIG. 11, the digital value corresponding to the shift voltage α is added to the digital values D1 and D2 to obtain the distance D using equations (1) and (2). It is necessary to calculate the digital value OD.

According to this embodiment, the intensity of the background light increases, and the charge amounts Q1, Q2, and Q3 of the charges accumulated in the charge accumulation units CS1, CS2, and CS3, respectively, are increased and supplied to the AD converter 3291. Even if the input voltages VA (CS1), VA (CS2), and VA (CS3) are large and are no longer included in the voltage range of the input range of the AD converter 3291, the voltage range of the input range can be shifted by the shift voltage α. is possible, and the distance D can be measured with high measurement accuracy even if the charge amounts Q1, Q2, and Q3 of the charges accumulated in the charge accumulation units CS1, CS2, and CS3 respectively fluctuate.

FIG. 13 is a diagram for explaining the effect of improving the distance resolution by increasing the number of accumulation cycles in the frame cycle. FIG. 13(a) shows three classifications #1, #2 and #3 of input voltages VA(CS1), VA(CS2) and VA(CS3). In FIG. 13(a), the vertical axis indicates the input voltage VA, and the horizontal axis indicates the input voltages VA (CS1) and VA (CS2) in each of the classifications #1, #2 and #3. , VA(CS3).
In the category #1, the input voltage VA (CS1) corresponding to the charge amount Q1 of the charge accumulated in the charge storage section CS1 is 0.58 [V], and the charge amount of the charge accumulated in the charge storage section CS2 is The input voltage VA (CS2) corresponding to Q2 is 0.8 [V], and the input voltage VA (CS3) corresponding to the charge amount Q3 of the charges accumulated in the charge accumulating section CS3 is 0.72 [V]. be.
In the category #2, the input voltage VA (CS1) corresponding to the charge amount Q1 of the charge accumulated in the charge storage section CS1 is 0.72 [V], and the charge amount of the charge accumulated in the charge storage section CS2 is The input voltage VA (CS2) corresponding to Q2 is 1.0 [V], and the input voltage VA (CS3) corresponding to the charge amount Q3 of the charges accumulated in the charge accumulating section CS3 is 0.89 [V]. be.
In the category #3, the input voltage VA (CS1) corresponding to the charge amount Q1 of the charge accumulated in the charge storage section CS1 is 0.85 [V], and the charge amount of the charge accumulated in the charge storage section CS2 is The input voltage VA (CS2) corresponding to Q2 is 1.19 [V], and the input voltage VA (CS3) corresponding to the charge amount Q3 of the charges accumulated in the charge accumulating section CS3 is 1.07 [V]. be.

Each of classifications #1, #2, and #3 shown in FIG. 13(a) has a constant background light intensity. However, the number of times charges are accumulated in each of the charge accumulation units CS1, CS2, and CS3, that is, the number of accumulation cycles (the number of distributions) is gradually increasing to 15,000, 19,000, and 23,000, respectively. Here, as the number of accumulation cycles increases, the charge amounts Q1, Q2, and Q3 of charges accumulated in the charge accumulation units CS1, CS2, and CS3 are gradually increased in the order of classification #1, classification #2, and classification #3. each increases. By performing the above-described shift of the input range corresponding to each increase of the charge amounts Q1, Q2 and Q3 for each of the classifications #1, #2 and #3, any of the classifications and the The distance D can be obtained even if

FIG. 13(b) is a table showing the correspondence between the number of accumulation cycles (the number of distributions) and the distance resolution (noise) for each of the classifications #1, #2, and #3.
The table in FIG. 13(b) has items of classification, shift voltage α, accumulation period number (distribution number), input voltage VA (charge amounts Q1, Q2, Q3), and distance resolution (noise) for each record. .
Classification is identification information for distinguishing combinations of input voltages VA (CS1), VA (CS2), and VA (CS3), and there are classifications #1, #2, and #3, respectively. A shift voltage α indicates a voltage value obtained by shifting the voltage range of the input range of the AD converter 3291 . In the column of input voltage VA (unit [V]), sub-columns are provided to indicate voltage values of VA (CS1), VA (CS2), and VA (CS3). Distance resolution (noise) indicates the resolution (ie, measurement error) obtained by increasing the number of charge accumulation cycles.
By increasing the number of accumulation cycles, the charge amounts Q1, Q2 and Q3 of charges accumulated in the charge accumulation units CS1, CS2 and CS3 are increased, respectively.
However, since each of the charge amounts Q1, Q2, and Q3, particularly each of the charge amounts Q2 and Q3, can be accumulated with higher accuracy as a charge amount corresponding to the distance, the resolution in distance measurement can be improved. can.

As shown in FIG. 13(b), by increasing the number of accumulation periods, even in the same measurement space and in the same measurement environment, the charge amounts Q1 and Q2 of the charges accumulated in the charge accumulation units CS1, CS2 and CS3 are , Q3 increase, and the input voltages VA (CS1), VA (CS2), and VA (CS3) increase.
Correspondingly, as the input voltage VA increases as the input voltages VA (CS1), VA (CS2), and VA (CS3), that is, as the accumulation cycle number (distribution number) increases, classification #1, #2 and #3, the distance resolution (noise) gradually decreased to 30.6 [mm rms], 22.7 [mm rms], and 18.2 [mm rms], and the measurement accuracy improved. I know. Here, the measured distance D contains an error of maximum +/- distance resolution (noise). Therefore, the smaller the distance resolution (noise) is, the more the distance D is measured with higher accuracy.
As described above, according to the present embodiment, the charge amounts Q1, Q2, and Q3 of the charges accumulated in the charge accumulation units CS1, CS2, and CS3 are increased, and the input voltages VA (CS1), VA (CS2), and VA Even if (CS3) increases, the input range of the AD converter 3291 can be easily shifted, so the number of accumulation cycles (the number of distributions) can be increased, and the resolution of distance measurement can be increased. , the measurement accuracy of the measured distance D can be improved.

Further, in the above-described embodiment, the input range of the AD converter 3291 is shifted for each column in the grid-like arrangement of the pixel circuits 321 in units of frame cycles. 321, and the voltage range of the input range of the AD converter 3291 may be shifted.
That is, in the lattice arrangement of the pixel circuits, each of the column AD conversion circuits 329j (CS1), 329j (CS2) and 329j (CS3) provided for each column stores the shift voltage α and the digital value αD. Each storage unit stores a shift voltage α and a digital value αD corresponding to the input voltages VA (CS1), VA (CS2), and VA (CS3) supplied from the pixel circuits 321 of each row in the column. Let me remember.
Here, the AD converter 3291 outputs an AD conversion value VD as a result of AD conversion of the input voltage VA of the row currently being processed to the arithmetic processing section 3292 .
After AD conversion value VD is output from AD converter 3921, arithmetic processing unit 3292 reads shift voltage α corresponding to the next row from the storage unit. The arithmetic processing unit 3292 outputs the read shift voltage α to the reference voltage generation unit 3293 to shift the voltage range of the input range of the AD converter 3291 .
Arithmetic processing unit 3292 also determines whether the AD conversion value VD of the row being processed at the present time is the upper limit value or the lower limit value of the input range. A corresponding digital value αD is obtained, and the digital value αD corresponding to the obtained shift voltage α is written and stored in the storage unit. The above process of shifting the voltage range of the input range of the AD converter 3291 corresponding to each of the pixel circuits 321 arranged in a lattice is performed by the column AD conversion circuits 329j (CS1), 329j (CS2) and 329j (CS3). Each is done independently.

With this configuration, in the pixel circuits 321 arranged in a grid pattern, the charge of the pixel circuits 321 is reduced when the background light is partially received or when the reflected light RL is received from the object S having a high reflectance. It is possible to flexibly shift the voltage range of the input range of the AD converter 3291 according to the charge amounts Q1, Q2, and Q3 of the charges accumulated in the accumulation units CS1, CS2, and CS3, respectively. 321 and the distance D between the object S in the measurement space P can be measured with high measurement accuracy.

<Second embodiment>
A second embodiment of the present invention will be described below with reference to the drawings. FIG. 14 is a block diagram showing a schematic configuration of a distance image pickup device according to the second embodiment of the present invention. Other configurations and operations of the distance image capturing apparatus 1' shown in FIG. 14 are the same as those of the first embodiment. Configurations and operations different from those of the first embodiment will be described below.
In the first embodiment, processing for shifting the input range of the AD converter 3291 is performed by the arithmetic processing unit 3292 comparing the AD conversion value VD with the upper and lower limits of the voltage range of the input range. .
In this embodiment, the process of shifting the voltage range of the input range is performed by a control signal supplied from the outside.

In FIG. 14, an input range control circuit 5 is provided in a distance image pickup device 1'. The input range control circuit 5 includes, for example, an optical sensor such as an illuminance sensor that measures the intensity of light.
The input range control circuit 5 converts the shift voltage α corresponding to the measured value of the light intensity in the measurement space P (that is, the light intensity of the background light) measured by the optical sensor and the digital value αD corresponding to the shift voltage to the above control information. , and is output to the distance image sensor 32'.
Here, the input range control circuit 5 may, for example, refer to a shift voltage α table provided therein to read out the shift voltage α and the digital value αD corresponding to the light intensity. The shift voltage α table is a table in which combinations of a plurality of light intensity ranges, shift voltages α corresponding to the intensity ranges, and digital values αD are set in advance. Therefore, the input range control circuit 5 refers to the shift voltage α table, searches for an intensity range that includes the light intensity measured by the photosensor, and shifts the shift voltage α and the digital value αD corresponding to this searched intensity range. is read from the shift voltage α table.

FIG. 15 shows a configuration example of the column AD conversion circuit 329j (CS1)' in the second embodiment. Hereinafter, the column AD converter circuit 329j (CS1)' shown in FIG. 15 will be described as an example. , and operates in the same way.
The column AD conversion circuit 329j (CS1)′ is supplied with the shift voltage α and the digital value αD from the input range control circuit 5 . Similarly, the shift voltage α and the digital value αD are supplied from the input range control circuit 5 to the column AD conversion circuits 329j (CS2)' and 329j (CS3)'.
Thereby, the arithmetic processing unit 3292' obtains the digital value αD of the shift voltage α corresponding to the background light. Also, the reference voltage generator 3293 acquires the shift voltage α corresponding to the background light.
The reference voltage generator 3293 outputs to the AD converter 3291 a reference voltage obtained by shifting the supplied shift voltage α, as in the first embodiment.
As a result, the AD converter 3291 shifts the voltage range of the input range according to the reference voltage supplied from the reference voltage generator 3293 . The AD converter 3291 AD-converts the input voltage VA (CS1) supplied from the pixel signal processing circuit 325, and outputs the AD-converted value VD (CS1) to the arithmetic processing section 3292'.
Further, the arithmetic processing unit 3292 ′ adds the shift voltage α supplied from the input range control circuit 5 to the AD conversion value VD(CS1) output from the AD converter 3291 . Then, the arithmetic processing unit 3292′ obtains the output digital value OD(CS1) as the addition result of the AD conversion value VD(CS1) and the digital value αD corresponding to the shift voltage α. The column AD conversion circuits 329j(CS2)' and 329j(CS3)' also perform the same processing as the column AD conversion circuit 329j(CS1)' to obtain the output digital values OD(CS2) and OD(CS3). Then, under the control of the horizontal scanning circuit 324, the AD conversion circuit 329 serially converts the output digital values OD (CS1), OD (CS2), and OD (CS3) of the column AD conversion section j into pixel signals for distance measurement. Output to the image processing unit 4 .
In this configuration, the simple configuration including the input range control circuit 5 allows the use of an arithmetic processing unit 3292' having a smaller circuit scale than the arithmetic processing unit 3292, and reduces the size of the distance image sensor 32'. 1, and adjusts the input range of the AD converter 3291 according to the light intensity of the background light in the environment of the measurement space P, as in the first embodiment. However, even when the light intensity of the background light is high or the light intensity of the reflected light RL from the object S is high, the distance D between the distance imaging device 1' and the object S can be measured with high measurement accuracy. becomes possible.

Further, in the second embodiment, the input range control circuit 5 may have an input means for inputting a numerical value indicating the shift voltage α by a user who is scanning the distance image pickup device 1'. As this input means, for example, any device such as a numerical input keyboard for inputting numbers or a volume knob for adjusting voltage can be used as long as a voltage value can be input.
The distance image pickup device 1' outputs a numerical value indicating the voltage input from the device as a shift voltage α to the distance image sensor 32'. In the distance image sensor 32', similarly to the configuration provided with the input range control circuit 5 described above, the reference voltage generator 3203 shifts the reference voltage supplied to the AD converter 3291 by the supplied shift voltage α.
Then, the AD converter 3291 performs AD conversion of the input voltage VA by changing the input range in accordance with the reference voltage shifted by the shift voltage α supplied from the reference voltage generation unit 3293, and outputs the AD conversion value VD. Output.
Further, the arithmetic processing unit 3292′ obtains the output digital value OD from the AD conversion value VD output from the AD converter 3291 and the digital value αD corresponding to the shift voltage α.
In the case of this configuration, when measuring the distance D from the distance imaging device 1' to the object S in the measurement space P, if the user feels that the light intensity of the background light in the environment of the measurement space P is strong. , the shift voltage α is adjusted by the input means while observing the distance image (image composed of pixels with gradation corresponding to the distance D) displayed by the distance image pickup device 1′.
As a result, the user can directly adjust the shift voltage α while observing the range image displayed by the range image pickup device 1' so as to eliminate 'brightness' and 'blackout'. , the distance D can be measured easily and with high measurement accuracy.

In addition, in the present embodiment, a configuration in which a column AD conversion circuit is provided for each column of pixel circuits arranged in a lattice pattern has been described. Alternatively, an AD conversion circuit capable of shifting the voltage range of the input range to be AD-converted in the present embodiment may be provided to AD-convert an analog voltage (input voltage VA) in parallel.
Further, in the row direction of the line sensor, an AD conversion circuit capable of shifting the voltage range of the input range for AD conversion according to the present embodiment is provided. A configuration may be adopted in which AD conversion of the output analog voltage (input voltage VA) is sequentially performed.
Further, in the present embodiment, the light source device 21 emits, for example, a laser beam in a near-infrared wavelength band that becomes a light pulse PO to be irradiated onto the subject S, and a light pulse generated by a pulse transmission operation is used as the laser beam. explained. However, the configuration for shifting the voltage range of the input range for the above-mentioned AD conversion uses laser light other than pulse light, for example, sinusoidal laser light (irradiation light) by continuous emission of constant light (CW: continuous wave). This embodiment can also be applied to a distance image pickup apparatus that measures a distance from a shift in intensity modulation using a distance image pickup apparatus in the same manner as in the processing of AD-converting an analog voltage (input voltage VA) output by a pixel circuit.
In addition, instead of the analog voltage output by the pixel circuit, the analog voltage generated by the photovoltaic force of the photodiode, LED (light emitting diode), solar cell, etc., and the analog voltage waveform in signal processing in communication etc. Also, when measuring with high resolution, it is possible to apply the AD conversion circuit according to the present embodiment, in which the voltage range of the input range for AD conversion can be shifted.

Although the embodiments of the present invention have been described in detail above with reference to the drawings, the specific configuration is not limited to these embodiments, and designs and the like are included within the scope of the gist of the present invention.

DESCRIPTION OF SYMBOLS 1, 1'... Range image pick-up device 2... Light source part 3... Light receiving part 4... Range image processing part 5... Input range control circuit 21... Light source device 22... Diffusion plate 31... Lens 32, 32'... Range image sensor 41... Timing control unit 42 Distance calculation unit 320 Light receiving pixel unit 321 Pixel circuit 322 Control circuit 323 Vertical scanning circuit 324 Horizontal scanning circuit 325 Pixel signal processing circuit 326 Pixel driving circuit 329 AD conversion circuit 329j AD Conversion section 329j (CS1), 329j (CS1)', 329j (CS2), 329j (CS3)...AD conversion circuit 3291...AD converter 3292, 3292'...Arithmetic processing section 3293...Reference voltage generation section C...Charge storage capacitor CS Charge storage section FD... Floating diffusion G... Readout gate transistor GD... Drain gate transistor O... Output terminal P... Measurement space PD... Photoelectric conversion element PO... Light pulse RL... Reflected light RT... Reset gate transistor RU... Pixel signal readout section S … Object SF … Source follower gate transistor SL … Selection gate transistor

Claims (12)

Irradiation light emitted from a predetermined light source to a measurement space, which is a space to be measured, receives reflected light reflected by an object in the measurement space and background light in the environment of the measurement space. a photoelectric conversion element that generates charges according to the reflected light and the background light; and a charge storage unit that stores the charges when the irradiation light is applied in a frame cycle, the a light-receiving pixel section having a pixel circuit that synchronously accumulates the charge in the charge accumulation section;
An AD converter and an arithmetic processing unit are provided, and when an input voltage corresponding to the amount of charge accumulated in the charge accumulation unit is AD-converted for each frame period, the input voltage is within the input range of the AD converter. an AD conversion circuit that adjusts the input range corresponding to the input voltage by shifting the voltage range of the input range by a predetermined shift voltage by the arithmetic processing unit when the input range is not included in the range image sensor. further comprising a reference voltage generator for generating a reference voltage for controlling the voltage range of the input range of the AD conversion circuit corresponding to the shift voltage;
When the input voltage is equal to or higher than the upper limit value of the input range of the AD converter, the arithmetic processing unit obtains the shift voltage for shifting the voltage range of the input range, and sends the shift voltage to the reference voltage generation unit. supply and
the reference voltage generating unit generates the reference voltage corresponding to the shift voltage supplied from the arithmetic processing unit, and supplies the reference voltage to the AD converter;
The distance image sensor according to claim 1 , wherein the AD converter adjusts the voltage range of the input range with the reference voltage supplied from the reference voltage generator. When the input voltage exceeds the upper limit of the voltage range of the input range, the arithmetic processing unit shifts the input voltage to the voltage side higher than the current voltage by a preset shift voltage so that the input voltage is the voltage of the input range. 3. The range image sensor according to claim 1 , wherein if the range is less than the lower limit, the range is shifted to a lower voltage side than the present time by a preset shift voltage. The irradiation light is a light pulse with the same pulse width that is irradiated at a predetermined cycle,
The pixel circuit in which the light-receiving pixel portion is arranged in a two-dimensional grid,
3. The range image sensor according to claim 1 , wherein the AD conversion circuit is provided for each column of the grid array. A pixel drive circuit that outputs an accumulation drive signal is further provided,
The charge storage unit has a plurality of distributed charge storage units,
The pixel drive circuit sequentially outputs a distribution accumulation drive signal to the distribution charge accumulation unit as the accumulation drive signal in the cycle in synchronization with irradiation of the light pulse, and the distance image sensor and the 5. The distance image according to claim 4 , wherein each of the electric charges generated by the photoelectric conversion element according to the amount of light received during the period of the reflected light is distributed to and accumulated in each of the distributed charge accumulation units in order to obtain the distance to the object. sensor. 6. The distance image according to claim 5 , wherein the arithmetic processing unit shifts the voltage range of the input range in accordance with the voltage corresponding to the amount of charge in the charge accumulation unit in which charge due to background light is accumulated. sensor. An AD converter is provided for each column of the charge storage section of each of the pixel circuits in the grid arrangement,
7. The distance image sensor according to claim 5 , wherein the arithmetic processing section adjusts the input range of each of the AD converters independently for each of the columns of the distributed charge storage section. The arithmetic processing unit generates the shift voltage of the input range used when the AD converter AD-converts the input voltage, for each column in the grid array, AD of the input voltage in the immediately preceding frame period. 8. The range image sensor according to any one of claims 4 to 7 , wherein the conversion is performed in response to the result of the conversion. The arithmetic processing unit generates the shift voltage of the input range used when the AD conversion circuit AD-converts the input voltage, for each of the pixel circuits arranged in the columns of the lattice arrangement, immediately before the shift voltage. 9. The distance image sensor according to any one of claims 4 to 8, wherein the range image sensor according to any one of claims 4 to 8 , wherein the input voltage is AD-converted for each pixel circuit in the frame period of . 2. The distance image sensor according to claim 1, wherein the shift by the predetermined shift voltage is performed by a shift control signal supplied from an external device. a distance image sensor according to any one of claims 1 to 10 ;
a light source unit that irradiates a measurement space, which is a space to be measured, with irradiation light;
A charge amount, which is the amount of the charge distributed by a predetermined fixed number of times of charge distribution and accumulated in each of the plurality of distributed charge accumulation units in the charge accumulation unit, and the input range in the AD conversion circuit. and a distance image processing unit that obtains a distance between the distance image sensor and the object existing in the measurement space based on the shifted voltage. The distance image processing unit adds the shift voltage obtained by shifting the input range to the converted voltage obtained by AD-converting the voltage corresponding to the amount of electric charge, and the distance image is obtained by the addition result. 12. The distance imaging device according to claim 11 , wherein the distance between the sensor and the object existing in the measurement space is calculated.

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