JP7269564B2 - Circuit design device and circuit design method - Google Patents

Description

The present invention relates to a circuit design apparatus and a circuit design method using the same, which efficiently create a database of existing circuit assets and design a circuit with high efficiency.

In recent years, with the increasing variety of products and the shortening of product cycles due to mass customization, there is a demand for short TAT and high efficiency in circuit design and verification. On the other hand, there are cases where the above needs cannot be met due to a shortage of circuit designers, especially skilled people. Therefore, there is an increasing demand for advanced circuit design support systems and design automation.

On the other hand, in Patent Document 1, when a circuit is designed by CAD, input of circuit narrowing-down conditions by a designer is accepted, and based on the circuit narrowing-down conditions, the circuit topology of the circuit to be designed is changed. A circuit design support system is described that obtains recommended circuits by searching a database unit that stores component data and circuit data, and displays a list of recommended circuits on a display.

In addition, Patent Document 2 discloses an automatic design support technique for analog circuits that performs circuit design while appropriately evaluating the yield and performance of analog circuits, which have trade-offs. The automatic design support method generates one or more design variable value sets for a predetermined design variable, generates a plurality of parameter value sets for parameters that are assumed to vary due to manufacturing or environment for each design variable value set, A circuit simulation is performed for a circuit configuration for each combination of these, a performance item value set of a predetermined performance item is obtained as the result of the circuit simulation, and a performance item value set for each parameter value set for each design variable value set is obtained for each combination. A parameter generated for the design variable value set by identifying a combination of the design variable value set and the parameter value set that has performance item values superior to or identical to the performance item value for all predetermined performance items It is stated that the yield rate is calculated by the ratio of the number of specified combinations to the number of value sets.

JP 2009-122718 A JP 2011-180866 A

Patent Literatures 1 and 2 disclose a method of improving design efficiency by utilizing past design resources in a design support system. In order to share past assets, these methods create a database of circuit diagrams, component performance, costs, etc., and provide methods, tools, and systems that are easy for designers to access.

Generally, when creating a database of circuits, each circuit in the past is registered in the database, so circuits with the same configuration but using different parts must be registered as separate circuits, especially when the circuit scale is large. There is a problem that the registration work becomes complicated and the database also becomes enormous.
For example, FIGS. 20A and 20B are simple amplifier circuit diagrams using operational amplifiers, both of which have the same configuration of non-inverting amplification, inverting amplification, and non-inverting amplification. Although the non-inverting amplifier parts have compatible pin assignments and the same specifications and functions, they are made by different manufacturers and have different performances, so they are judged to be different parts, and the two circuits are different. It is centrally registered in the database as a circuit.

On the other hand, when a designer designs a circuit and extracts a past asset circuit that meets the required specifications from the database, if the desired circuit is not registered, there is a problem that the optimum circuit cannot be obtained. For example, as shown in Fig. 20(C), the input is single input and the output is differential output, but there is no single input and differential output circuit registered in the database. do.

There is also the problem that as the database becomes more complex, the designer's operations on the GUI (Graphical User Interface) become more complicated.
Here, a simplified example is shown for easy explanation of the problem, but in actual circuit design, there are more complex circuits and a huge amount of circuits.

Creating a database of such a complex and huge amount of circuits, including differences in the parts used, is a daunting task. This is a major obstacle to improving efficiency.

Therefore, in order to utilize existing design assets and improve design efficiency, it is necessary to have an efficient configuration method for the circuit database, flexibility of the database that can be used when designing new circuits, and an easy-to-use user interface for designers. GUI) is important.

On the other hand, in both Patent Documents 1 and 2, it is proposed to build a database without imposing a heavy burden on the designer, and to efficiently search for existing assets that are likely to be useful for new designs. is not considered.

The present invention solves the above-described problems of the prior art, enables the existing circuit assets to be utilized with high efficiency, and automatically or semi-automatically generates the optimum circuit configuration plan for the given circuit requirement specifications. It is an object of the present invention to provide a circuit design apparatus and a circuit design method using the same that realize short TAT (Turn Around Time) and high efficiency in design and verification.

In order to solve the above problems, in a preferred example of the circuit design apparatus of the present invention, a circuit topology, which is a circuit unit having a primitive function, is extracted from a conventional circuit asset, and the layout positions of circuit components contained therein are extracted. A circuit topology DB that registers circuit topology data with a hole in the circuit topology, and a circuit component DB that registers each circuit component that has the same function and is compatible in pin assignment that can be replaced with the hole in the circuit topology. , a user interface for accepting the information requested by the user, inputting the required specifications of the circuit to be designed, selecting and instructing the circuit topology, circuit parts, and simulation analysis method, and each information of the circuit topology and circuit parts selected and instructed by the user. a combinational circuit generation unit that searches the circuit topology DB and the circuit part DB, reads the corresponding circuit topology data and the circuit part data, and generates combinational circuit data from the data; A simulation execution unit for executing a circuit simulation, and a result comparison unit for comparing the simulation result with the required specifications and selecting a combinational circuit satisfying the required specifications as a candidate circuit to be designed.

Further, in order to solve the above-mentioned problems, in the circuit design apparatus of the present invention, when the circuit to be designed is composed of a circuit topology with a plurality of stages, the user interface is configured to include the required specifications of the circuit to be designed and the circuits at each stage. User input is divided into specifications, and a screen configuration for selecting and instructing circuit topology and circuit components for each stage is displayed, and user selection and instruction input are accepted, and candidate circuit generation unit corresponds to circuit topology for each stage. The combinational circuit generator in the candidate circuit generator corresponding to each stage generates the combinational circuit data for each stage from the circuit topology and circuit component data for each stage selected and instructed by the user. , a simulation execution unit in the candidate circuit generation unit corresponding to each stage executes a simulation of each combinational circuit generated in correspondence with each stage, and a result comparison unit in the candidate circuit generation unit corresponding to each stage executes a simulation of each combinational circuit. Comparing the result of the simulation executed for each stage with the circuit specifications of each stage, outputting a combinational circuit corresponding to each stage that satisfies the circuit specifications as a candidate circuit for each stage to be designed, and generating each candidate circuit. a multistage combinational circuit generation unit that generates a multistage combinational circuit by inputting the candidate circuit of each stage output from the multistage combinational circuit, and a simulation of each of the generated multistage combinational circuits, and a simulation result of each of the multistage combinational circuits; a computing unit that compares the required specifications with the required specifications and selects a multistage combinational circuit that satisfies the required specifications as a candidate circuit to be designed.

In order to solve the above problems, in a preferred example of the circuit design method of the present invention, a circuit topology, which is a circuit unit having a primitive function, is extracted from a conventional circuit asset, and the circuit components contained therein are extracted. A circuit topology DB in which circuit topology data whose placement positions are holes are registered, and each circuit component having the same function and compatibility in pin allocation that can be replaced by the holes in the circuit topology is registered. a circuit part DB, presenting a user interface to a user to receive from the user input of required specifications of a circuit to be designed, and information for selecting and instructing a circuit topology, circuit parts, and a simulation analysis method; searches the circuit topology DB and the circuit component DB from each information of the circuit topology and circuit components selected and instructed by , reads out the corresponding circuit topology data and circuit component data, and retrieves all combinable data from those data. a step of generating combinational circuit data; a step of simulating each of the generated combinational circuits; and comparing the simulation result with the required specifications to select a candidate circuit to be designed that satisfies the required specifications. It is implemented so as to have a step of

According to the present invention, by efficiently creating a database of existing circuit assets, it becomes possible to utilize them with high efficiency, and it is possible to automatically or semi-automatically generate an optimal circuit configuration plan for a given circuit specification.・ Short TAT and high efficiency of verification can be realized.

In addition, according to the present invention, a database can be easily created from existing circuit design resources, and an optimal circuit configuration proposal can be automatically or semi-automatically generated by combining circuit topologies and circuit components on a user interface. An optimum circuit configuration plan can be generated regardless of proficiency.

1 is a block diagram showing an overall schematic configuration of a circuit design apparatus according to Example 1 of the present invention; FIG. 1 is a block diagram showing a detailed configuration of a circuit design device according to Example 1 of the present invention; FIG. 1 is a diagram showing a physical configuration of a circuit design device according to each embodiment of the present invention; FIG. FIG. 10 is an explanatory diagram of extracting a circuit topology and circuit components from a conventional circuit asset and registering them in a circuit topology DB and a circuit component DB; 4 is a flow chart for implementing circuit design using the circuit design apparatus of Example 1 of the present invention. FIG. 4 is a diagram illustrating examples of a circuit topology DB, a circuit component DB, and a combinational circuit generator according to Example 1 of the present invention; FIG. 4 is a diagram for explaining an example of SPICE netlist representation of (a) circuit topology, (b) hole-filling parts, and (c) additional parts. FIG. 4 is a diagram illustrating an example of a circuit topology DB, a circuit component DB, and a simulation setup generator according to Example 1 of the present invention; FIG. 2 is an image diagram showing a screen configuration of a user interface according to Example 1 of the present invention; FIG. 4 is an image diagram showing a design result according to Example 1 of the present invention; FIG. 3 is a block diagram showing a schematic configuration of the entire circuit design apparatus according to Example 2 of the present invention; FIG. 5 is a block diagram showing a detailed configuration of a circuit design device according to Example 2 of the present invention; FIG. 10 is a flow chart for performing circuit design using the circuit design apparatus of Example 2 of the present invention; FIG. FIG. 11 is a block diagram showing the detailed configuration of a circuit design device according to Example 3 of the present invention; FIG. 10 is a flow chart for performing circuit design using the circuit design apparatus of Example 3 of the present invention; FIG. FIG. 10 is an image diagram showing a screen configuration of a user interface according to Examples 2 and 3 of the present invention; FIG. 10 is a diagram illustrating an example of candidate circuit generators 1 to 4 and a multi-stage combinational circuit generator according to Example 2 of the present invention; FIG. 10 is a diagram illustrating a process of obtaining candidate circuit outputs in the multi-stage combinational circuit DB according to Example 2 of the present invention; It is a reference diagram showing a simulation result of a candidate circuit according to Example 2 of the present invention. FIG. 10 is a reference diagram for explaining an example of circuit data in a conventional circuit database;

This embodiment relates to highly efficient circuit design using conventional circuit resources, automatic circuit design method and system, a highly efficient circuit database construction method, a circuit database simulation method, and a user-friendly display method of user interface. , to provide a highly efficient design of a circuit equipped with a method of narrowing down a circuit that satisfies the circuit specifications, an automatic design method of the circuit, and an apparatus therefor.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail based on the drawings. In principle, the same reference numerals are given to the same parts in all the drawings for explaining the embodiments, and the repeated explanation thereof will be omitted.

1 to 10, a circuit design method and apparatus 100 for designing a circuit with high efficiency using existing circuit resources according to the first embodiment of the present invention will be described.

[Circuit database]
A characteristic feature of this embodiment is that the conventional circuit asset (circuit diagram) 401 is registered in advance in the circuit DB 302 shown in FIG. In the registration process, for example, as shown in FIG. 4, a circuit topology, which is a circuit configuration extracted as a circuit unit having a known primitive function that constitutes a conventional circuit, is extracted and registered in the circuit topology DB 303. . Here, each extracted circuit topology is a circuit within the circuit topology such that each circuit component contained therein can be replaced with other circuit components (other components with compatible pin assignments and the same function). An identification ID and a name are added to the extracted circuit topology and registered in the circuit topology DB 303 as data in which the component placement positions are blank (holes). For example, circuit topologies include inverting amplifiers, non-inverting amplifiers, I/V conversion amplifiers, and third-order active LPFs.

In parallel with the registration of the circuit topology, as shown in FIG. Each circuit part in the conventional circuit that can be replaced as a circuit part is classified as a part with compatible pin assignments and the same function, and further classified according to the difference in various performance values caused by different manufacturers, etc. An identification ID and a name are added to each circuit component (fill-in-the-blank component) that is different in classification, and registered in the circuit component DB 304 . For example, circuit components (blank filling components) include operational amplifier ICs, differential amplifier ICs, switches, and resistors.

Different circuit data are registered such that the circuit topology registered in the circuit topology DB 303 and the circuit component (blank-filling component) registered in the circuit component DB 304 are each given a unique identification ID. In this embodiment, the registration means is not specified. Circuit topology data and circuit component data are created in advance from the conventional circuit asset (circuit diagram) 401 and downloaded to the circuit topology DB 303 and circuit component DB 304 .

[Circuit design device configuration]
FIG. 1 is a block diagram showing the overall schematic configuration of a circuit design apparatus 100 that efficiently designs a circuit using a database according to this embodiment. A circuit design apparatus 100 according to the present embodiment includes a user interface (GUI: Graphical User Interface) 101, a computing unit 201 that executes circuit simulations, etc., an object database (DB) 301 that holds circuit DBs registered from conventional circuit resources 401, and so on. , and a candidate circuit generator 601 for generating a combinational circuit to be a candidate circuit from the circuit DB. Circuit topology/component selection control data 502 is sent from the user interface 101 to the object DB 301 , and circuit diagram data 511 is sent from the object DB 301 to the user interface 101 . Requirement specification data 501 is sent from the user interface 101 to the computing unit 201 , and conversely, simulation results 504 and candidate circuit simulation results 503 are sent from the computing unit 201 to the user interface 101 . A simulation result 504 is sent from the calculation unit 201 to the object DB 301 , and combinational circuit data 505 is sent from the object DB 301 to the calculation unit 201 . A candidate circuit generation unit 601 is composed of the object DB 301 and the calculation unit 201 .

FIG. 2 is a diagram for explaining the schematic configuration of FIG. 1 in more detail. A user interface (GUI) 101 comprises a required specification input unit 102, a circuit topology/parts/analysis selection unit 103, a circuit topology/parts combination simulation result display unit 107, and an optimum candidate circuit and simulation result display unit 108. . The required specification input unit 102 receives input of required specifications 501 such as the gain and bandwidth of the circuit to be designed by the user, the number of candidate circuits P to be displayed on the GUI after analysis, and the like. The circuit topology/components/analysis selection unit 103 is composed of a circuit topology selection unit 104, a circuit components selection unit 105, and a simulation analysis selection unit 106. The circuit topology selection unit 104 accepts the user's selection of the circuit topology of the circuit to be designed. , The circuit component selection unit 105 accepts user selection of components used in the circuit to be designed, and the simulation analysis selection unit 106 selects a simulation analysis method for the circuit to be designed (for example, AC analysis, DC analysis, transient analysis, distortion analysis, noise analysis etc.) and outputs a circuit topology/parts/analysis control signal 502 . The circuit topology/component combination simulation result display unit 107 has a function of displaying the circuit topology/component/analysis 502 and the simulation result 504 used in the designed circuit. The optimum candidate circuit and simulation result display unit 108 has a function of displaying the specified number of candidate circuits satisfying the required specifications 501 among the designed circuits and the simulation result.

The object DB 301 is composed of a circuit DB 302 and a combinational circuit DB 307 , and the combinational circuit DB 307 is composed of a combinational circuit generation unit 305 , a simulation result storage unit 306 and a simulation setup generation unit 308 .

As described above, the circuit DB 302 is composed of the circuit topology DB 303 and the circuit component DB 304 in which the conventional circuit assets (circuit diagrams) 401 are registered. Both the circuit topology data registered in the circuit topology DB 303 and the circuit component data registered in the circuit component DB 304 are databased in, for example, a SPICE netlist format or a transfer function format.

The circuit topology and circuit components in the circuit DB 302 are selected by the circuit topology/component/analysis control signal 502 from the circuit topology/component/analysis selection unit 103 of the user interface 101, and the circuit topology/component 506 data (for example, SPICE) is selected. net list) to the combinational circuit generator 305 . The combinational circuit generation unit 305 generates circuits of all combinations of the circuit topology/parts 506 and outputs them as data of the combinational circuit 505 (for example, a SPICE netlist of combinational circuits). A simulation result accumulation unit 306 associates a simulation result 504 (for example, AC analysis, DC analysis, transient analysis, distortion analysis, noise analysis, etc.) of the combinational circuit 305 with the combinational circuit 505 and accumulates and saves it.

The calculation unit 201 is composed of a simulation execution unit 202 and a result comparison unit 203 . In the simulation execution unit 202, the combinational circuit 505 sent from the combinational circuit generation unit 305 and the preset simulation setup (for example, setup for AC analysis, DC analysis, transient analysis, distortion analysis, noise analysis, etc.) The simulation results 504 are sent to the simulation result accumulation unit 306 of the object DB 301, the circuit topology and component combination simulation result display unit 107 of the user interface 101, and the result comparison unit 203 of the calculation unit 201, respectively. The result comparison unit 203 compares the required specification 501 received from the required specification input unit 102 of the user interface 101 with the simulation result 504, and selects the one that satisfies the required specification 501 and has a large margin with respect to the required specification 501. Only the number P of candidate circuits is selected, and the candidate circuit simulation result 503 is sent to the optimum candidate circuit and simulation result display unit 108 to display the result. Also, the candidate circuit data 512 is sent to and recorded in the circuit DB 302 .

FIG. 3 is a diagram showing a physical configuration of the circuit design apparatus 100 shown in FIGS. 1 and 2. As shown in FIG. In this embodiment, a computer 120 having a processor (CPU) 121, a memory 122, an auxiliary storage device 123, and a communication interface (communication I/F) 124 is used for the circuit design device 100. FIG. This computer may be, for example, a general-purpose computer such as a personal computer (PC).

The processor 121 executes programs stored in the memory 122 . The computer 120 may have multiple processors 121 . The memory 122 includes ROM, which is a non-volatile storage element, and RAM, which is a volatile storage element. The ROM stores immutable programs (eg, BIOS) and the like. RAM is a high-speed and volatile memory device such as DRAM (Dynamic Random Access Memory), and temporarily stores programs executed by processor 121 and data used during program execution.

The auxiliary storage device 123 is, for example, a large-capacity, non-volatile storage device such as a magnetic storage device (HDD) or flash memory (SSD), and stores programs executed by the processor 121 and data used when the programs are executed. do. In this embodiment, the circuit design support program is read from the auxiliary storage device 123, loaded into the memory 122, and executed by the processor 121 to realize each functional unit.

Communication interface 124 is a network interface device that controls communication with other devices according to a predetermined protocol.

Computer 120 also has an input interface (input I/F) 125 and an output interface (output I/F) 128 . The input interface 125 is an interface to which a keyboard 126, a mouse 127, etc. are connected and receives input from an operator. The output interface 128 is an interface that is connected to a display device 129, a printer, etc., and outputs the result of execution of the program in a form that can be visually recognized by the operator.

Also, the circuit design support program executed by the processor 121 and the circuit topology data and circuit component data created from the conventional circuit asset (circuit diagram) 401 are provided to the computer 120 via a computer-readable storage medium or network. and stored in the auxiliary storage device 123, which is a non-temporary storage medium. A computer-readable storage medium is a non-transitory computer-readable medium, such as a non-volatile removable medium such as a CD-ROM or flash memory. Therefore, the computer 120 preferably has an interface for reading data from removable media.

Also, as another embodiment, part or all of each functional unit may be implemented using hardware such as FPGA or ASIC.

FIG. 5 shows a flowchart for performing circuit design using the circuit design apparatus 100. As shown in FIG.
In step S101, user input of required specifications of the designed circuit is accepted.
In step S102, user selection of circuit topology/circuit components/simulation analysis method is accepted.
At step S103, a circuit netlist for the selected circuit topology and circuit component is selected from the circuit DB 302. FIG.
In step S104, a circuit topology and a combinational circuit of circuit components are generated.
At step S105, a simulation setup for which the analysis method was specified at S102 is generated.
In step S106, the combinational circuit generated in S104 is put into the simulation setup generated in S105 to perform a combinational simulation.
In step S108, the simulation result is saved in the object DB301.
In step S111, the simulation result and combinational circuit are displayed on the user interface.
In step S107, the required specifications are compared with the simulation results, and in step S109, candidate circuits that satisfy the required specifications are extracted.
In step S110, the candidate circuits are DBized in the object DB301.
In step S112, the candidate circuits and simulation results are displayed on the GUI.

[Configuration of circuit database and combinational circuit generator]
FIG. 6 shows an embodiment of the circuit topology DB 303, the circuit component DB 304, and the combinational circuit generator 305. In FIG. The circuit topology DB 303 illustrates that the circuit topologies of inverting amplifiers and non-inverting amplifiers are stored. The circuit topology DB 303 stores the amplifier topology as a SPICE netlist, for example, as shown in FIG. : X_U5 1 2 3 VP VN OPA_open), composed only of peripheral circuits. As an example, the input terminals on the netlist are 1 for inverting input, 2 for non-inverting input, 3 for output, + power supply as VP, and - power supply as VN. In the circuit topology, the input terminal is in and the output terminal is out.

The circuit component DB 304 stores filling components to be inserted into holes and additional components to be added to the circuit topology, for example, as shown in FIG. 7(b) and FIG. 7(c) in SPICE net lists. The blank-filling components are two op-amp ICs, OPA a and OPA b, which are assigned 1 for the inverting input, 2 for the non-inverting input, and 3 for the output in accordance with the terminal numbers of the circuit topology. One resistor Rc is shown as an example of the additional part, and in order to connect to the output terminal out of the circuit topology, for example, one terminal of the resistor in the net list shown in FIG. there is

From the user interface (GUI) 101, selection information of the two types of circuit topologies selected by the user, two types of filling components, and one additional component is sent to the circuit DB section 302, and the circuit topology DB 303 and circuit The netlist read out from the component DB 304 is sent to the combinational circuit generator 305, and the following combinational circuit generation processing is executed.

In the combinational circuit generator 305, four types (2×2=4) of combinational circuits in which terminal numbers are aligned and two types of hole-filling parts are inserted into the holed portions of the two types of circuit topologies, and the four types of circuits are further generated. A total of 8 types (2×2+2×2×1=8) of 4 types of circuits are generated by inserting the output resistor Rc as an additional component into the circuit of (1) with the same terminal numbers. Since the added part is connected to the output part of the circuit topology, for example, the terminal 4, which is the output of the circuit topology on the netlist, is changed to the terminal out after the connection.

In this way, if there are L circuit topologies in the circuit topology DB 303, M blank filling components in the circuit component DB 304, and N additional components, the number of combinational circuits to be generated is (L×M+L×M×N). . However, if there are O parts such as input resistors added to the in terminal of the circuit topology as additional parts, the number of combination circuits generated is (L×M+L×M×N+L×M×O+L×M×N×O ), the number of combinational circuits generated varies depending on the number of additional parts and connection points. In any case, circuit diagrams and, for example, SPICE netlists are generated for all combinations as shown in this embodiment (FIG. 6).

FIG. 8 shows another embodiment of the circuit topology DB 303 and the circuit component DB 304 and an embodiment of the simulation setup generator 308 . In the embodiment of FIG. 6, the circuit topology of the circuit topology DB 303 is a single-stage circuit of an amplifier circuit, but the circuit topology may be a multi-stage circuit, or may include a circuit with a function different from that of the amplifier circuit. The example in FIG. 8 is a four-stage circuit, and in addition to the amplifier, filters (LPF) with different functions are included, and the parts used are perforated.

The circuit component DB 304 may store filter components in addition to amplifiers as filling components, and additional components may include amplifier circuits, such as non-inverting OPAMPs. Also, in this embodiment, the circuit topology is only an amplifier and a filter, but it is not limited to this, and various circuits such as a switch, an attenuator, and an adder may be used.

The simulation setup generation unit 308 is automatically generated according to the configuration of the combinational circuit and the type of analysis method specified by the user interface, and is generated from the signal source, drive power supply, load, and probes that measure current and voltage. In this embodiment, a case of single output (setup A) and a case of differential output (setup B) are described as examples, but the simulation setup is not limited to this.

[Configuration of Circuit Topology/Components/Analysis Selection Unit 103 and Combination Simulation Result Display Unit 107 of Circuit Topology and Components]
FIG. 9 shows a configuration example of a screen displayed on the screen of the display device 129 by the circuit topology/parts/analysis selection unit 103 on the GUI.
The screen displayed by the circuit topology selection unit 104 shows an example of a screen for selecting an amplifier topology, and an inverting amplifier, a non-inverting amplifier, an I/V (current-voltage) conversion amplifier, a differential amplifier, etc. can be selected on the GUI. It is possible.
The screen displayed by the circuit component selection unit 105 shows an example of a screen for selecting a filling component to be inserted into a hole in the circuit topology and an additional component to be added to the circuit topology. The filling components are OPAa, OPAb, OPAc, and OPAd. The four types are configured so that additional parts can be selected from output resistances of 50Ω and 100Ω and input resistances of 50Ω and 100Ω.
The screen displayed by the simulation analysis selection unit 106 is used to select analysis methods such as DC analysis and AC analysis, as well as detailed settings for the simulation (for example, drive power supply voltage range, frequency range, load impedance, probe position for observing voltage and current, etc.). It is possible.

When selecting circuit topologies, parts, and analyses, the display should be easy for the user to understand, such as putting a check mark in the selected circuit topology or parts. As an example shown in FIG. 9, the circuit topology selection unit 104 selects an inverting amplifier and a non-inverting amplifier, and the circuit component selection unit 105 selects OPAa, OPAb, OPAc, and OPAd as filling components and a damping resistor (dump R) as an additional component. Select an output resistance of 50Ω for In this case, a total of (circuit topology types 2 x OPAMP types 4 + topology types 2 x OPAMP types 4 x output resistance types 1) = 16 types of combinational circuits are generated, and if AC analysis and DC analysis are performed for each, 32 types of simulations are generated. results will be obtained.

The circuit topology/parts/analysis selection unit 103 accepts user selections and setting inputs on the GUI, and sends circuit topology/parts/analysis information 502 to the circuit DB 302 of the object DB 301 .

FIG. 10 shows an example using a sub-burst chart as a display example in which the circuit topology and parts combination simulation result display unit 107 on the GUI displays the simulation result on the screen of the display device 129 . Place an inverting amplifier and a non-inverting amplifier as the circuit topology on the innermost circumference, place four types of OPAMPs to be used toward the outside, then place output resistance (dump R) with/without, and analysis results on the outermost circumference. By arranging AC analysis and DC analysis as , all 32 types of simulation results are arranged on the outermost circumference. Follow this with the cursor, for example, non-inverting amplification, OPAd, with output resistance (dump R), AC analysis, and when the cursor is stopped at the AC analysis, the simulation result is displayed. Such a display allows the user to easily see the characteristics of each circuit configuration and quickly determine which characteristics are good, thereby shortening the design time. This embodiment is an example of a GUI, and for example, the circuit topology of the sub-burst chart and the arrangement of components are not limited to this.

In this embodiment, the circuit topology and circuit components are specified in advance on the user interface, and combinational circuit generation and simulation are performed only for the specified combination. A simulation is automatically performed at power-on, etc., and the result and the combinational circuit are stored in the combinational circuit DB 307. For the combination specified by the user through the user interface at the time of designing, the corresponding combinational circuit and the simulation result are retrieved from the combinational circuit DB 307. may be used.

As described above, according to this embodiment, existing circuit assets can be efficiently put into a database, and can be utilized with high efficiency. It is possible to achieve short TAT and high efficiency of design and verification.

In addition, according to this embodiment, a DB can be easily created from existing circuit design resources, and an optimal circuit configuration proposal can be automatically or semi-automatically generated by combining circuit topologies and components on a user interface. An optimum circuit configuration plan can be generated regardless of proficiency.

11 to 13 and 16 to 19, a circuit design method and apparatus for efficiently designing a circuit using existing circuit assets according to the second embodiment of the present invention will be described.

[Device configuration]
FIG. 11 is a block diagram showing an overall schematic configuration of a circuit design apparatus 150 that efficiently designs a circuit using a database according to this embodiment. The circuit design apparatus 150 according to this embodiment is a circuit design apparatus for easily designing a multi-stage circuit having a large number of circuit stages and a large number of circuit types. It consists of a user interface (GUI: Graphical User Interface) 101, a candidate circuit generation block 602, and a multistage combinational circuit DB 701. FIG.

The candidate circuit generation block 602 is composed of N stages of candidate circuit generation units 601-1 to 601-N corresponding to the candidate circuit generation unit 601 in the first embodiment (FIG. 1). The N-stage circuit topology/component selection control data 502 sent from the user interface 101 (GUI) is input to the N-stage candidate circuit generators 601-1 to 601-N, respectively. The circuit specification data 507-1 to 507-N are input to the N-stage candidate circuit generators 601-1 to 601-N, respectively. Each candidate circuit generator executes a simulation to extract one or more candidate circuits, and these candidate circuits are sent as candidate circuit data 512 to the multi-stage combinational circuit DB 701 . A simulation result 504 of each candidate circuit generator is sent to the user interface 101 and displayed.

As an example, when the number of stages is N=4, four candidate circuits are generated for the first stage circuit, and one candidate circuit is generated for each of the second to fourth stage circuits, the candidate circuit data 512 is 4+1+1+1=7 circuit data. . The multistage combinational circuit DB 701 generates combinational circuits from the first stage to the fourth stage. In the above example, 4×1×1×1=4 types of combinational circuits are generated, the four types of circuits are simulated, and the simulation results are compared with the requirement specifications 501 sent from the user interface 101. . A predetermined number of candidate circuits P of combinational circuits are selected from the comparison results in descending order of performance.

FIG. 12 is a diagram for explaining the schematic configuration of FIG. 11 in more detail. In this embodiment, for the sake of explanation, a four-stage circuit with N=4 will be explained as an example. The GUI 101 includes a required specification input unit 102, circuit specification input units 109-1 to 109-4 for inputting the required specifications by dividing them into single-stage circuit specifications for a four-stage configuration, and a circuit topology/parts/analysis selection unit 103-1. . Note that in the case of an N-stage configuration, there are N circuit specification input units and N circuit topology/parts/analysis selection units, respectively.

The required specification input unit 102 accepts required specifications 501 such as the gain and bandwidth of the circuit to be designed input by the user. Circuit specification input units 109-1 to 109-4 input circuit specifications 507-1 to 507 such as the gain and bandwidth of each stage circuit when the required specification 501 received by the required specification input unit 102 has a four-stage configuration. - 4 divided and accepted.

The circuit topology/parts/analysis selection units 103-1 to 103-4 allow the user to select the circuit topology of each stage of the circuit to be designed, the parts used in the circuit to be designed, and the simulation analysis method of the circuit to be designed. It receives and outputs control signals 502-1 to 502-4 for selecting the circuit topology/parts/analysis of each stage.
The circuit topology/component combination simulation result display unit 107 has a function of displaying circuit topologies/components 502-1 to 502-4 and simulation results 504-1 to 504-4 used for each designed four-stage circuit. The circuit and simulation result display unit 108 has a function of displaying a circuit that satisfies the required specifications 501 and a simulation result among circuits designed by combining four stages of individual circuits, which will be described later.

The candidate circuit generation block 602 is composed of candidate circuit generation units 601-1 to 601-4, each of which has the number of design circuit stages (N=4). Candidate circuit generators 601-1 to 601-4 each comprise the object DB 301 and the arithmetic unit 201 shown in the first embodiment (FIG. 2), and operate in the same manner as the candidate circuit generator 601 described in FIG. .
The circuit DBs 302-1 to 302-4 have different DB configurations (for example, circuit DBs 302-1, 302- 2, 302-4 is an amplifier database, circuit DB 302-3 is a filter database, etc.), or the same database containing various circuit functions.
Circuit specification data 507-1 to 507-4 of each stage are input to candidate circuit generation units 601-1 to 601-4, and candidate circuits 512-1 to 512-4 are compared with internal simulation results 504. (For example, as an example, if four candidate circuits are generated for the first stage candidate circuits and one candidate circuit is generated for each of the second to fourth stage candidate circuits, each of the candidate circuit data 512-1 to 512-4 is four 1, 1, 1, 1 circuit data), and input to the multi-stage combinational circuit DB 701 respectively.

The multistage combinational circuit DB 701 is composed of a multistage combinational circuit generation section 702 , an arithmetic section 703 , and a candidate circuit DB 704 .
The multistage combinational circuit generator 702 generates a combinational circuit of each of the candidate circuits 512-1 to 512-4. In the case of the above embodiment, 4.times.1.times.1.times.1=4 types of combinational circuits are generated and input to the arithmetic unit 703 as the multistage combinational circuit data 509. FIG.
The calculation unit 703 executes simulation of the input four types of circuits and compares the simulation results with the required specifications 501 sent from the user interface 101 . Candidate circuits of the multi-stage combinational circuit of the number P of candidate circuits which are specified in advance in order of performance satisfying the required specifications are extracted from the comparison result, the candidate circuit 513 is stored in the candidate circuit DB 704, and the candidate circuit/Sim result/circuit diagram is stored. It is sent to the user interface 101 as data 510 and displayed on the user interface.

FIG. 13 shows a flow chart for performing circuit design using the circuit design device 150. As shown in FIG.
In step S201, user input of the required specifications of the circuit to be designed, the number of circuit stages N, and the number of candidate circuits P is accepted.
In step S202, the required specifications are divided into N stages of circuit specifications and user input is accepted.
In step S203, the user's selection of the circuit topology/parts/simulation analysis method for each stage is accepted.
In step S204, candidate circuits that satisfy the circuit specifications for each stage are generated. The processing in the candidate circuit generation unit is the same as the processing contents shown in S103-S107 and S109 of FIG.
In step S205, N stages of combinational circuits are generated from the candidate circuits generated in each stage.
At step S206, a simulation setup for which the analysis method was specified at S203 is generated.
In step S207, a simulation of the N-stage combinational circuit is performed.
At step S209, the simulation result is saved.
In step S208, the required specifications and simulation results are compared.
In step S210, a predetermined number P of candidate circuits satisfying the required specifications and in descending order of performance are extracted.
In step S211, the extracted candidate circuits are put into a database.
In step S212, the candidate circuits and simulation results are displayed on the GUI. On the GUI, it is also possible to display together the candidate circuits and simulation results of each stage obtained in S204, the simulation results of the N-stage combination in S209, and the N-stage circuits.

FIG. 14 shows a third embodiment, which is a derived example of the second embodiment. The basic configuration is the same as the configuration of FIG. 12 of the second embodiment, but the candidate circuit generation block 602 is used as a single candidate circuit generation unit, and N stages of circuit topology/component selection data 502-1 to 502- 4 are all input to candidate circuit generation block 602 . The circuit topology/component selection data 502-1 to 502-4 may be processed simultaneously, or the circuit topology/component selection data 502-1 to 502-4 may be processed sequentially in a time division manner. Other configurations and operations are the same as those of the second embodiment shown in FIG.

FIG. 15 shows a flow chart of this embodiment. It is the same as the flowchart of FIG. 13 of the second embodiment except that step S204 is changed to step S213. In step S213, candidate circuits for each stage are generated by time-division operation. The internal operation repeats the same processing as shown in steps S103 to S107 and S109 in the flow chart of FIG. N-stage combinational circuits are generated from the candidate circuits generated in the stages.

[Example of GUI input screen for selection of required specifications, number of candidate circuits, circuit topology/parts/analysis method]
FIG. 16 shows an example screen displayed by the required specification input unit 102 on the GUI 101 in the second and third embodiments, an example screen for inputting the number of candidate circuits, and an example screen displayed by the circuit specification input units 109-1 to 109-4. 4 shows examples of screens displayed by the circuit topology/parts/analysis selection units 103-1 to 103-4.

As for the required specifications, the required specifications of the entire design circuit, such as noise, bandwidth, gain, etc., are entered along with the number of circuit stages to achieve these specifications. Also, input the number of candidate circuits P=1 to be displayed on the GUI as a result. Input the circuit specifications for the specified number of circuit stages (for example, 4 stages), and specify the circuit topology, filling parts, and additional parts to be used at each stage. As an example, the first stage selects a non-inverting amplifier from the amplifier DB for the circuit topology, selects OPAa, OPAb, OPAc, and OPAd as the blanking parts, selects the non-inverting amplifier from the amplifier DB for the second stage circuit topology, Select OPAb and OPAc as the filling parts, select LPF (low-pass filter) from the filter DB for the circuit topology on the third stage, select LPFa and LPFb as the filling parts, and select the amplifier for the circuit topology on the fourth stage. A differential amplifier is selected from DB, and OPABa and OPABb are selected as hole-filling components. AC analysis and noise analysis are selected as the simulation analysis method. When selecting circuit topologies, parts, and analysis methods, the display is made easy for the user to understand by, for example, putting a check mark in the selected analysis topology or parts.

FIG. 17 shows an example of the candidate circuit generators 601-1 to 601-4 of Example 2 when the above settings are made. Candidate circuit generator 1 (601-1) configures four types of combinational circuits by combining netlists of non-inverting amplifiers as circuit topologies and four types of OPAMPs as fill-in parts. Candidate circuit generator 2 (601-2) configures two types of combinational circuits by combining netlists of a non-inverting amplifier as a circuit topology and two types of OPAMP as blanking parts. Candidate circuit generator 3 (601-3) constructs two types of combinational circuits by combining netlists of filters as circuit topologies and two types of LPFs as fill-in components. Candidate circuit generator 4 (601-4) configures two types of combinational circuits by combining netlists of differential amplifiers as circuit topologies and two types of OPAMPs as blanking parts.

By simulating each combinational circuit in each of the candidate circuit generators 601-1 to 601-4, the combinational circuit of the circuit topology and filling parts that satisfy the circuit specifications 507-1 to 507-4 is determined by the candidate circuit generator 1 (601-1 ) outputs four types, and the candidate circuit generators 601-2 to 601-4 output one type.

The multistage combinational circuit generated by the multistage combinational circuit generation unit 702, which receives the candidate circuit data 512-1 to 512-4 output from each of the candidate circuit generation units 601-1 to 601-4, has four types ( Only OPAMPs in the first stage are four types of OPAa, OPAb, OPAc, and OPAd).

FIG. 18 shows an example of simulation performed by the arithmetic unit 703 as combinational circuits A1, A2, A3, and A4. Since the combinational circuit A3 does not meet the required specifications for noise and band, and the combinational circuit A2 does not meet the required specifications for gain, one candidate is selected from the combinational circuits A1 and A4. Here, the evaluation index E(Ak) of circuit plan Ak is calculated using the following equation (1).
(Formula 1) E(Ak)=ΣWx・|Ak(x)-O(x))|
where Wx is the weight of each performance (ΣWx=1.0, can be specified by the user), x=1 is noise, X=2 is bandwidth, X=3 is gain, and Ak(x) is the proposed circuit. performance, O(x) indicates the required specification.

A larger evaluation index E(Ak) indicates a larger circuit margin, and the magnitude of E(Ak) was compared between combinational circuits A1 and A4. As a result, the margin of the combinational circuit A1 is large, and the circuit diagram of the combinational circuit A1 and the simulation result are displayed on the optimum candidate circuit and simulation result display section 108 on the user interface 101 as a circuit plan (candidate circuit for multistage combinational circuit) output. .
FIG. 19 shows SPICE simulation results of the noise, bandwidth and gain of the combinational circuits A1, A2, A3 and A4.

As described above, according to this embodiment, existing circuit assets can be efficiently put into a database, and can be utilized with high efficiency. It is possible to achieve short TAT and high efficiency of design and verification.

In addition, according to this embodiment, a DB can be easily created from existing circuit design resources, and an optimal circuit configuration proposal can be automatically or semi-automatically generated by combining circuit topologies and components on a user interface. An optimum circuit configuration plan can be generated regardless of proficiency.

Although the invention made by the present inventor has been specifically described above based on the embodiments, it goes without saying that the invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. stomach.

100 circuit design device 101 user interface (GUI: Graphical User Interface)
102 Requirement specification input unit 103 Circuit topology/component/analysis selection unit 104 Circuit topology selection unit 105 Circuit component selection unit 106 Simulation analysis selection unit 107 Combination simulation result of circuit topology and components Display unit 108 .. optimal candidate circuit and simulation result display units 109-1 to 4 .. circuit specification input units 1 to 4
150 Circuit design apparatus of second and third embodiments 201 Operation unit 202 Simulation execution unit 203 Result comparison unit 301 Object database 302 Circuit DB
303 circuit topology DB
304 Circuit component DB
305... Combinational circuit generation unit 306... Simulation result storage unit 307... Combinational circuit DB
308...Simulation setup generator 401...Conventional circuit assets 501...Required specifications 502...Circuit topology/parts/analysis (control signal)
503 Candidate circuit simulation result 504 Simulation result 505 Combination circuit 506 Circuit topology/parts 507-1 to N Circuit specification 509 Multistage combination circuit 510 Candidate circuit Sim result Circuit diagram 511 Circuit diagram 512 Candidate circuit 513 Candidate circuit 601 Candidate circuit generators 601-1 to 4 Candidate circuit generators 1 to 4
602 Candidate circuit generation block 701 Multistage combinational circuit DB
702 Multi-stage combinational circuit generation unit 703 Operation unit 704 Candidate circuit DB

Claims (9)

A circuit topology DB in which a circuit topology, which is a circuit unit having a primitive function, is extracted from a conventional circuit asset, and circuit topology data is registered in which the layout positions of the circuit components included in the circuit topology are registered as holes;
A circuit component DB in which each circuit component having the same function and having compatibility in assignment of pins that can be replaced with the perforated portion of the circuit topology is registered;
a user interface that accepts information that a user inputs required specifications of a circuit to be designed, and selects and instructs circuit topology, circuit components, and simulation analysis method;
The circuit topology DB and the circuit component DB are searched from the circuit topology and circuit component information selected and instructed by the user, the relevant circuit topology data and circuit component data are read, and combinational circuit data is obtained from these data. a combinational circuit generator to generate;
a simulation executing unit that executes a simulation of each of the generated combinational circuits;
a result comparison unit that compares the simulation results with the required specifications and selects a combinational circuit that satisfies the required specifications as a candidate circuit to be designed;
with
The result comparison unit compares the simulation result of each combinational circuit with the required specifications, and selects as many as the number of candidate circuits specified by the user combinational circuits that satisfy the required specifications and have a large margin with respect to the required specifications. is a candidate circuit to be designed,
The circuit design apparatus , wherein the user interface displays the candidate circuit selected by the result comparison unit and the simulation result on the user interface . The combinational circuit generation unit generates, for the readout circuit topology data, all combinations according to all combinations different from each other in combinations of all the readout circuit part data that can be replaced with the perforated portion. 2. The circuit design apparatus according to claim 1, wherein circuit data is generated. In the circuit topology DB, each circuit topology data is configured and registered by an identification ID, a name, and data in a netlist format or a transfer function format in which the circuit parts of the circuit with holes are not connected. 2. The circuit design apparatus according to claim 1, characterized by: 2. The circuit component DB according to claim 1, wherein each circuit component data is configured by an identification ID, a name, and data in a netlist format or a transfer function format for the circuit component and registered therein. Circuit design device. When the circuit under design is composed of circuit topologies of multiple stages, the user interface receives user input by dividing the required specifications of the circuit under design and the circuit specifications of each stage, and the circuit topology and circuit of each stage. Displays the screen configuration for selecting and instructing parts, accepts user's selection and instruction input,
A plurality of candidate circuit generators are generated corresponding to the circuit topology of each stage,
A combinational circuit generator in the candidate circuit generator corresponding to each stage generates combinational circuit data for each stage from the circuit topology and circuit component data for each stage selected and instructed by the user,
a simulation execution unit in the candidate circuit generation unit corresponding to each stage executes a simulation of each combinational circuit generated corresponding to each stage;
A result comparison unit in the candidate circuit generation unit corresponding to each stage compares the result of the simulation executed corresponding to each stage with the circuit specifications of each stage, and designs a combinational circuit corresponding to each stage that satisfies the circuit specifications. Output as a candidate circuit for each stage of interest,
a multi-stage combinational circuit generation unit that receives the candidate circuits of each stage output from each of the candidate circuit generation units and generates a multi-stage combinational circuit;
A computing unit that executes a simulation of each of the generated multistage combinational circuits, compares the simulation result of each of the multistage combinational circuits with the required specifications, and selects a multistage combinational circuit that satisfies the required specifications as a candidate circuit to be designed. 2. The circuit design apparatus according to claim 1, further comprising: and. When the circuit under design is composed of circuit topologies of multiple stages, the user interface receives user input by dividing the required specifications of the circuit under design and the circuit specifications of each stage, and the circuit topology and circuit of each stage. Displays the screen configuration for selecting and instructing parts, accepts user's selection and instruction input,
A single candidate circuit generator is generated for generating a candidate circuit for each stage based on circuit topology for each stage and selection data for circuit components,
A combinational circuit generation unit in the candidate circuit generation unit generates combinational circuit data for each stage from the circuit topology and circuit component data for each stage selected and instructed by the user,
A simulation execution unit in the candidate circuit generation unit executes a simulation of each combinational circuit of each stage generated,
A result comparison unit in the candidate circuit generation unit compares the simulation result of each combinational circuit at each stage with the circuit specification at each stage, and selects a combinational circuit satisfying the circuit specification at each stage. Output as a stage candidate circuit,
a multi-stage combinational circuit generation unit that receives the candidate circuits of each stage output from the candidate circuit generation unit and generates a multi-stage combinational circuit;
A computing unit that executes a simulation of each of the generated multistage combinational circuits, compares the simulation result of each of the multistage combinational circuits with the required specifications, and selects a multistage combinational circuit that satisfies the required specifications as a candidate circuit to be designed. and,
2. The circuit design apparatus according to claim 1, further comprising: A circuit topology DB in which a circuit topology, which is a circuit unit having a primitive function, is extracted from a conventional circuit asset, and circuit topology data is registered in which the layout positions of the circuit components included in the circuit topology are registered as holes, and a circuit component DB in which each circuit component having the same function and compatible pin allocation that can be replaced with a hole in the circuit topology is registered;
a step of presenting a user interface to a user and accepting from the user input of required specifications of a circuit to be designed, and information for selecting and instructing a circuit topology, circuit components, and a simulation analysis method;
Searching the circuit topology DB and the circuit component DB from each information of the circuit topology and circuit components selected and instructed by the user, reading out the corresponding circuit topology data and circuit component data, and all possible combinations from those data generating combinational circuit data of
performing a simulation of each combinational circuit generated;
a step of comparing the simulation result with the required specifications and selecting a combinational circuit satisfying the required specifications as a candidate circuit to be designed;
has
The step of selecting a combinational circuit that satisfies the required specifications as a candidate circuit to be designed includes comparing a simulation result of each combinational circuit with the required specifications, and finding a combination that satisfies the required specifications and has a large margin with respect to the required specifications. A step of selecting circuits by the number of candidate circuits specified by a user and setting them as candidate circuits to be designed,
A circuit design method , further comprising the step of displaying the selected candidate circuit and the simulation result on a user interface . When the circuit to be designed is composed of circuit topologies of multiple stages, the user interface receives user input by dividing the required specifications of the circuit to be designed and the circuit specifications of each stage, and the circuit topology and circuit components of each stage. a step of displaying a screen configuration for selecting and instructing and accepting a user's selection and instruction input;
generating a plurality of candidate circuit generators corresponding to the circuit topology of each stage;
a step in which a combinational circuit generator in the candidate circuit generator corresponding to each stage generates combinational circuit data for each stage from the circuit topology and circuit component data for each stage selected and instructed by the user;
a step in which a simulation execution unit in the candidate circuit generation unit corresponding to each stage executes a simulation of each combinational circuit generated corresponding to each stage;
A result comparison unit in the candidate circuit generation unit corresponding to each stage compares the result of the simulation executed corresponding to each stage with the circuit specifications of each stage, and designs a combinational circuit corresponding to each stage that satisfies the circuit specifications. a step of outputting as a candidate circuit for each stage of interest;
a multistage combinational circuit generation unit receiving the candidate circuits of each stage output from each of the candidate circuit generation units to generate a multistage combinational circuit;
A computing unit executes a simulation of each of the generated multistage combinational circuits, compares a simulation result of each of the multistage combinational circuits with the required specifications, and selects a multistage combinational circuit satisfying the required specifications as a candidate circuit to be designed. and
8. The circuit design method according to claim 7, further comprising: When the circuit to be designed is composed of circuit topologies of multiple stages, the user interface receives user input by dividing the required specifications of the circuit to be designed and the circuit specifications of each stage, and the circuit topology and circuit components of each stage. a step of displaying a screen configuration for selecting and instructing and accepting a user's selection and instruction input;
a step of generating a single candidate circuit generator for generating a candidate circuit for each stage from the circuit topology for each stage and selection data for circuit components;
a step in which a combinational circuit generator in the candidate circuit generator generates combinational circuit data for each stage from data for circuit topology and circuit components for each stage selected and instructed by a user;
a step in which a simulation execution unit in the candidate circuit generation unit executes a simulation of each of the generated combinational circuits at each stage;
A result comparison unit in the candidate circuit generation unit compares the simulation result of each combinational circuit at each stage with the circuit specification at each stage, and selects a combinational circuit satisfying the circuit specification at each stage. outputting as a stage candidate circuit;
a multistage combinational circuit generation unit receiving the candidate circuits of each stage output from the candidate circuit generation unit to generate a multistage combinational circuit;
A computing unit executes a simulation of each of the generated multistage combinational circuits, compares a simulation result of each of the multistage combinational circuits with the required specifications, and selects a multistage combinational circuit satisfying the required specifications as a candidate circuit to be designed. and
8. The circuit design method according to claim 7, further comprising:

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