JP7269743B2 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device and its manufacturing method.

Patent Document 1 discloses a semiconductor device including an LDMOS (Lateral Double-diffused MOS) type transistor.
This semiconductor device includes a p-type semiconductor substrate, an n-type semiconductor layer formed on the semiconductor substrate, a p-type drain offset region formed on the surface of the semiconductor layer, and a drain offset region extending through the drain offset region. an n-type body region formed on the surface of a semiconductor layer, a p-type source region formed on the surface of the body region, a p-type drain region formed apart from the body region, and a source A gate insulating film formed on the drain offset region so as to cross the body region from the end of the region on the drain region side, and a thick insulating film formed on the drain offset region between the gate insulating film and the drain region ( LOCOS oxide film) and a gate electrode formed on the gate insulating film. In this configuration, the boundary between the body region and the semiconductor layer is in contact with the gate insulating film.

JP 2011-243919 A

In Patent Document 1, a LOCOS oxide film is inserted below the gate electrode. The on-resistance decreases as the length of the LOCOS oxide film in the direction from the drain region to the source region is shortened.
However, there is a limit to reducing the length of the LOCOS oxide film. This is because, due to the resolution limit of the exposure machine used when forming the LOCOS oxide film, if the pattern is too thin, the resolution will be poor and the pattern cannot be formed. As a result, there is a possibility that the LOCOS oxide film cannot be formed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can reduce the on-resistance as compared with the prior art.

A semiconductor device according to one embodiment of the present invention comprises a first conductivity type semiconductor layer having an element main surface, a second conductivity type body region formed on the element main surface of the semiconductor layer, and the body region. and a source region of a first conductivity type formed in said semiconductor layer and spaced apart from the periphery of said body region; and a source region formed in said main surface of said semiconductor layer and spaced from said body region. a first conductivity type drain region, a gate insulating film facing a channel region between the source region and the periphery of the body region, and a gate electrode facing the channel region through the gate insulating film; a field insulating film formed on the element main surface of the semiconductor layer between the gate insulating film and the drain region and having a greater thickness than the gate insulating film; In a plan view of the element main surface of the semiconductor layer viewed from the normal direction, along the first direction from the drain region to the source region, a first length and a second length shorter than the first length are provided. has a length of

According to this configuration, the field insulating film has a portion having a relatively short second length in the first direction. As a result, the cell pitch is reduced, so that the on-resistance per unit area can be reduced.
In the semiconductor device according to one embodiment of the present invention, the end portion of the field insulating film on the drain region side includes, in the plan view, a ridge projecting in a direction toward the drain region and a ridge continuing to the ridge. and a trough recessed in a direction away from the drain region, one end point of the first length is set at the top of the ridge, and the second One end point of the length may be set at the bottom of the valley.

In the semiconductor device according to one embodiment of the present invention, the end portion of the field insulating film on the source region side may be formed linearly in the section facing the peak portion and the valley portion.
In the semiconductor device according to one embodiment of the present invention, the end portion of the field insulating film on the source region side includes, in the plan view, a mountain portion protruding in a direction toward the source region and a peak portion continuing to the mountain portion. , and a trough recessed in a direction away from the source region.

In the semiconductor device according to one embodiment of the present invention, in the first direction, the peak portion on the drain region side of the field insulating film and the peak portion on the source region side of the field insulating film are opposed to each other, and The valley portion of the insulating film on the drain region side and the valley portion on the source region side may face each other.
A semiconductor device according to one embodiment of the present invention includes an interlayer insulating film formed on the semiconductor layer, and a drain contact penetrating through the interlayer insulating film in a thickness direction and connected to the drain region. The drain contact may be arranged at a portion adjacent to the valley portion of the end portion of the field insulating film on the drain region side in the plan view.

According to this configuration, since the drain contact is arranged in a relatively wide portion in the drain region, flexibility can be given to the design rule and the cell pitch can be reduced.
In the semiconductor device according to one embodiment of the present invention, the end portion of the field insulating film on the source region side includes, in the plan view, a mountain portion protruding in a direction toward the source region and a peak portion continuing to the mountain portion. and a trough recessed in a direction away from the source region, one end point of the first length is set at the top of the peak, and the second One end point of the length may be set at the bottom of the valley.

In the semiconductor device according to one embodiment of the present invention, the end portion of the field insulating film on the drain region side may be formed linearly in the section facing the peak portion and the valley portion.
In the semiconductor device according to one embodiment of the present invention, the first length may be 0.4 μm to 0.7 μm, and the second length may be 0.2 μm to 0.5 μm.

In the semiconductor device according to one embodiment of the present invention, the field insulating film may include a LOCOS (LOCal Oxidation of Silicon) oxide film.
A method of manufacturing a semiconductor device according to an embodiment of the present invention comprises the steps of: applying a photoresist onto a semiconductor layer of a first conductivity type having an element main surface; placing on the photoresist a mask having an edge portion including a plurality of selectively protruding protrusions and recesses between the plurality of protrusions in a planar view; exposing and developing the photoresist to have a wavy edge including peaks corresponding to the protrusions of the mask and valleys corresponding to the recesses of the mask; and oxidizing the element main surface of the semiconductor layer exposed from a hard mask formed using the photoresist after the patterning as a mask, thereby forming ridges corresponding to the ridges of the photoresist. forming a field insulating film having a wave-shaped first end portion including a trough portion corresponding to the trough portion of the photoresist; and a second end portion opposite to the first end portion. and removing the hard mask to form a first region which is the device main surface of the semiconductor layer on the first end side of the field insulating film and the first region on the second end side of the field insulating film. forming a first conductivity type drain region in the first region of the semiconductor layer; and forming a gate insulating film in the second region of the semiconductor layer. forming a gate electrode on the gate insulating film; forming a body region of a second conductivity type in the second region of the semiconductor layer; forming source regions of the first conductivity type in the body region such that they are spaced apart from each other.

Further, a method of manufacturing a semiconductor device according to another embodiment of the present invention includes the steps of: applying a photoresist on a semiconductor layer of a first conductivity type having an element main surface; disposing on the photoresist a mask having an end portion including a plurality of selectively protruding protrusions and recesses between the plurality of protrusions in plan view in a line direction; exposing and developing the photoresist with a patterning the photoresist; and oxidizing the element main surface of the semiconductor layer exposed from a hard mask formed using the patterned photoresist as a mask, thereby corresponding to the peaks of the photoresist. forming a field insulating film having a corrugated first end portion including a ridge portion corresponding to the trough portion of the photoresist and a trough portion corresponding to the trough portion of the photoresist; and a second end portion opposite to the first end portion. and removing the hard mask to form a first region, which is the element main surface of the semiconductor layer on the first end side of the field insulating film, and the second end of the field insulating film. selectively forming a gate insulating film in the first region of the semiconductor layer; and forming a gate electrode on the gate insulating film. forming a body region of a second conductivity type in the first region of the semiconductor layer; and forming a source region of the first conductivity type in the body region so as to be spaced apart from a peripheral edge of the body region. and forming a first conductivity type drain region in the second region of the semiconductor layer.

The semiconductor device described above can be manufactured by the manufacturing method described above. Also, in this manufacturing method, the photoresist is exposed using a mask having edges that include protrusions and recesses. Therefore, due to diffraction and interference phenomena of light, the convex portions and concave portions are smoothed, and the photoresist is resolved as a wavy end pattern including peaks and valleys. Therefore, even if the dimension of the area including the concave portion of the mask is below the resolution limit of the exposing machine, it is possible to prevent poor resolution. As a result, even if an exposure tool with a relatively high resolution limit is used, a second length of the field insulating film that is below the resolution limit of the exposure tool in the first direction from the drain region to the source region is achieved. be able to.

In the method of manufacturing a semiconductor device according to one embodiment and another embodiment of the present invention, the mask has an edge formed linearly on the opposite side of the edge including the protrusion and the recess. may be
A method of manufacturing a semiconductor device according to another embodiment of the present invention includes the steps of: applying a photoresist on a semiconductor layer of a first conductivity type having an element main surface; placing a mask on the photoresist, the mask having a plurality of patterns spaced apart from each other by less than 0.5 μm in a plan view from the top; exposing the photoresist using the mask; patterning the photoresist so as to have an end portion including valleys corresponding to gaps between the adjacent patterns and peaks corresponding to the pattern by developing the photoresist after the patterning; By oxidizing the element main surface of the semiconductor layer exposed from a hard mask formed using a resist as a mask, a peak corresponding to the peak of the photoresist and a valley corresponding to the photoresist are formed. forming a field insulating film having a corrugated first end and a corrugated second end including, respectively, valleys; and removing the hard mask to form the first end of the field insulating film. a step of exposing a first region that is the device main surface of the semiconductor layer on the second end side of the field insulating film and a second region that is the device main surface on the second end side of the field insulating film; forming a drain region of a first conductivity type in a first region; selectively forming a gate insulating film in the second region of the semiconductor layer; and forming a gate electrode on the gate insulating film. forming a body region of the second conductivity type in the second region of the semiconductor layer; and forming a source region of the first conductivity type in the body region so as to be separated from a peripheral edge of the body region. and a step.

Also by this manufacturing method, the above-described semiconductor device can be manufactured.

FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the invention. FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG. 1, showing a cross section taken along the line II--II in FIG. FIG. 3 is a diagram showing a part of the manufacturing process of the semiconductor device shown in FIGS. 1 and 2. FIG. FIG. 4 is a diagram showing the next step of FIG. FIG. 5 is a diagram showing the next step of FIG. FIG. 6 is a diagram showing the next step of FIG. FIG. 7 is a diagram showing the next step of FIG. FIG. 8 is a diagram showing the next step of FIG. FIG. 9 is a diagram showing the next step of FIG. FIG. 10 is a diagram showing the next step of FIG. FIG. 11 is a diagram showing the next step after FIG. FIG. 12 is a diagram showing the next step after FIG. FIG. 13 is a diagram showing the next step after FIG. FIG. 14 is a diagram showing the next step after FIG. FIG. 15 is a diagram showing the next step after FIG. FIG. 16 is a diagram showing the next step after FIG. FIG. 17 is a diagram showing the next step after FIG. FIG. 18 is a diagram showing the next step after FIG. FIG. 19A is a diagram showing steps related to exposure and development of a photoresist. FIG. 19B is a diagram showing steps related to exposure and development of a photoresist. FIG. 20 is a schematic plan view of a semiconductor device according to the second embodiment of the invention. FIG. 21 is a schematic plan view of a semiconductor device according to the third embodiment of the invention. FIG. 22 is a schematic plan view of a semiconductor device according to a fourth embodiment of the invention. FIG. 23A is a diagram (fifth embodiment) showing steps related to exposure and development of a photoresist. FIG. 23B is a diagram (fifth embodiment) showing steps related to exposure and development of a photoresist.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
<First embodiment>
FIG. 1 is a schematic plan view of a semiconductor device 1 according to a first embodiment of the invention. FIG. 2 is a cross-sectional view of the semiconductor device 1 shown in FIG. 1, showing a cross section taken along the line II--II of FIG.
The semiconductor device 1 is, for example, a semiconductor device including an LDMOS (Lateral Double-diffused Metal Oxide Semiconductor) region having a drain-source voltage _VDS of about 5V to 30V.

A semiconductor device 1 includes a semiconductor substrate 2, an epitaxial layer 3, a field insulating film 4, a body region 5, a source region 6, a drain region 7, a gate insulating film 8, a gate electrode 9, and an interlayer insulating film. 10 , a source contact 11 , a drain contact 12 , a source electrode 13 and a drain electrode 14 .
The semiconductor substrate 2 has a main surface 15 and a back surface 16 facing away from the main surface 15 in the thickness direction of the semiconductor substrate 2 . Main surface 15 is a surface in contact with epitaxial layer 3 . The back surface 16 is entirely exposed to the outside of the semiconductor device 1 .

The semiconductor substrate 2 is composed of a silicon (Si) substrate in this embodiment, but may be a substrate composed of other materials (for example, silicon carbide (SiC), etc.). The semiconductor substrate 2 is p-type in this embodiment. Semiconductor substrate 2 has an impurity concentration of, for example, 1×10 ¹⁴ cm ⁻³ to 5×10 ¹⁸ cm ⁻³ . Moreover, the thickness of the semiconductor substrate 2 is, for example, 500 μm to 800 μm before grinding.

The epitaxial layer 3 is in contact with the semiconductor substrate 2 and laminated on the semiconductor substrate 2 . Epitaxial layer 3 has an element main surface 17 and a junction surface 18 facing away from element main surface 17 in the thickness direction of epitaxial layer 3 . The element main surface 17 is the surface on which the aforementioned LDMOS region is formed. The bonding surface 18 is a surface in contact with the main surface 15 of the semiconductor substrate 2 . Although not shown, the LDMOS region may be partitioned by forming a p-type device isolation well having a closed annular shape in plan view from the device main surface 17 of the epitaxial layer 3 to reach the semiconductor substrate 2 . there is That is, the LDMOS region is a region surrounded by the p-type semiconductor substrate 2 and the p-type isolation well (not shown).

The epitaxial layer 3 is composed of silicon (Si) in this embodiment, but may be composed of other materials (for example, silicon carbide (SiC), etc.).
The epitaxial layer 3 has a conductivity type opposite to that of the semiconductor substrate 2 and is n-type in this embodiment. Epitaxial layer 3 has an impurity concentration of, for example, 5×10 ¹⁴ cm ⁻³ to 1×10 ¹⁷ cm ⁻³ . Moreover, the thickness of the epitaxial layer 3 is, for example, 3 μm to 20 μm.

Field insulating film 4 is formed on element main surface 17 of epitaxial layer 3 . The field insulating film 4 selectively covers the element main surface 17 of the epitaxial layer 3, and uses a part of the element main surface 17 as a first region 19 and a second region 20, respectively, for a first opening 21 and a second region. 2 are exposed from the opening 22 .
The first region 19 and the second region 20 are separated from each other and surrounded by the field insulating film 4 as shown in FIG. FIG. 1 shows a state in which the second region 20 is sandwiched between a pair of first regions 19, but as another form, the device main surface 17 of the epitaxial layer 3 has the first region 19 and the second region 19. A plurality of regions 20 may be alternately arranged.

In FIG. 1, the peripheral portion of the field insulating film 4 surrounding the first region 19 and the second region 20 is indicated by a thick solid line. That is, in FIG. 1, the area except for the first area 19 and the second area 20 surrounded by the thick solid line is the area covered with the field insulating film 4 .
As shown in FIG. 1, the portion sandwiched between the first opening 21 and the second opening 22 of the field insulating film 4 is the first Along the first direction D1 from the region 19 to the second region 20, it has a first length L1 and a second length L2 shorter than the first length L1. Such a difference between the first length L1 and the second length L2 can be explained by the following structure.

For example, in this embodiment, the portion of the field insulating film 4 surrounding the first region 19 includes a pair of straight portions 23 facing each other and a pair of curved portions 24 connecting the ends of the straight portions 23 . More specifically, the pair of linear portions 23 are linear extending in the first direction D<b>1 and constitute sides of the first region 19 in the short direction. On the other hand, the pair of curved portions 24 extend in a second direction D2 orthogonal to the first direction D1 and constitute sides of the first region 19 in the longitudinal direction.

In addition, the pair of curved portions 24 has a wave shape including a peak portion 25 projecting toward the inside of the first region 19 and a valley portion 26 that is continuous with the peak portion 25 and recessed in a direction away from the first region 19. formed. Furthermore, for a pair of curved portions 24 that face each other, peaks 25 face each other and valleys 26 face each other. Thus, the first region 19 is the third length L3 between the valleys 26 and the length between the peaks 25 in the first direction D1, and a fourth length L4 that is shorter than the third length L3.

On the other hand, the portion of the field insulating film 4 surrounding the second region 20 includes a pair of straight portions 27 facing each other and a pair of curved portions 28 connecting the ends of the straight portions 27 . More specifically, the pair of linear portions 27 are linear and extend in the second direction D2, and constitute sides of the second region 20 in the longitudinal direction. On the other hand, the pair of curved portions 28 has a semicircular shape that bulges in the second direction D2, and constitutes the sides of the second region 20 in the short direction.

That is, the curved portion 24 and the straight portion 27 of the field insulating film 4 extending in the second direction D2 face each other. As a result, the distance between the peak portion 25 of the curved portion 24 and the straight portion 27 is set as a relatively long first length L1, and the distance between the bottom portion of the valley portion 26 of the curved portion 24 and the straight portion 27 is set to be relatively long. A distance is set as a second length L2 that is relatively shorter than the first length L1. In this embodiment, the first length L1 is for example between 0.4 μm and 0.7 μm and the second length L2 is for example between 0.2 μm and 0.5 μm.

The field insulating film 4 is composed of silicon oxide (SiO ₂ ), more specifically LOCOS (LOCal Oxidation of Silicon) oxide film in this embodiment, but other insulating materials (for example, silicon nitride (SiN)). etc.). Moreover, the field insulating film 4 may be composed of a laminated structure of a plurality of materials, for example, silicon oxide and silicon nitride.

Further, as shown in FIG. 2, field insulating film 4 includes a first portion 29 and a second portion 30 as a cross-sectional structure. More specifically, the second portion 30 is the portion of the field insulating film 4 surrounding the first region 19 and the second region 20, and at least the portion of the field insulating film 4 surrounding the first region 19 and the second region 20. constitutes the periphery. On the other hand, the first portion 29 occupies most of the field insulating film 4 excluding the second portion 30 and is separated from the first region 19 and the second region 20 with the second portion 30 interposed therebetween. .

As for thickness, the first portion 29 of the field insulating film 4 has a constant thickness. On the other hand, the second portion 30 of the field insulating film 4 has a thickness that gradually decreases from the first portion 29 toward the first opening 21 and the second opening 22 . In other words, the second portion 30 has a tapered shape in which the thickness decreases from the first portion 29 toward the first opening 21 and the second opening 22 when viewed in cross section.

Body region 5 is formed in second region 20 of device main surface 17 of epitaxial layer 3 . Body region 5 is spaced inwardly from the peripheral edge of field insulating film 4 surrounding second region 20 and has an annular outer peripheral edge 31 along the peripheral edge of field insulating film 4 . The annular region sandwiched between the outer peripheral edge 31 of the body region 5 and the peripheral edge portion of the field insulating film 4 and constituted by part of the epitaxial layer 3 is a semiconductor region 35 of the same conductivity type as the epitaxial layer 3 . be.

Body region 5 is a p-type semiconductor region in this embodiment. Body region 5 has an impurity concentration of, for example, 1×10 ¹⁶ cm ⁻³ to 1×10 ¹⁸ cm ⁻³ . The depth of body region 5 is deeper than the bottom position of field insulating film 4 as shown in FIG. 2, and is, for example, 0.5 μm to 4.0 μm.
Source region 6 is formed inwardly of body region 5 in second region 20 of element main surface 17 of epitaxial layer 3 . Source region 6 is spaced inwardly from outer peripheral edge 31 of body region 5 and has an annular outer peripheral edge 32 along outer peripheral edge 31 of body region 5 . The annular region sandwiched between the outer peripheral edge 31 of the body region 5 and the outer peripheral edge 32 of the source region 6 and constituted by the body region 5 forms a channel when an appropriate voltage is applied to the gate electrode 9 . A channel region 33 is formed.

The source region 6 is an n-type semiconductor region in this embodiment. Source region 6 has an impurity concentration of, for example, 1×10 ¹⁹ cm ⁻³ to 5×10 ²¹ cm ⁻³ . The conductivity type of source region 6 may be defined as n ⁺ type in consideration of the difference in impurity concentration from epitaxial layer 3 .
The depth of source region 6 is shallower than that of body region 5, and is, for example, 0.2 μm to 1.0 μm. Therefore, in a cross-sectional view, source region 6 is integrally covered with body region 5 at its side and bottom portions.

Drain region 7 is formed in first region 19 of device main surface 17 of epitaxial layer 3 . The drain region 7 has an outer peripheral edge 34 substantially coinciding with the peripheral edge of the field insulating film 4 surrounding the first region 19 . Therefore, drain region 7 has a shape corresponding to peaks 25 and valleys 26 of field insulating film 4 . The drain region 7 may partially overlap the field insulating film 4 by locating the outer peripheral edge 34 below the field insulating film 4 . In this case, drain region 7 does not have a shape corresponding to peaks 25 and valleys 26 of field insulating film 4 .

The drain region 7 is an n-type semiconductor region in this embodiment. Drain region 7 has an impurity concentration of, for example, 1×10 ¹⁹ cm ⁻³ to 5×10 ²¹ cm ⁻³ . The conductivity type of drain region 7 may be defined as n ⁺ type in consideration of the difference in impurity concentration from epitaxial layer 3 .
The depth of drain region 7 is, for example, 0.2 μm to 2.0 μm. For example, drain region 7 may have the same depth as source region 6 .

Gate insulating film 8 is formed in second region 20 of device main surface 17 of epitaxial layer 3 . More specifically, in the second region 20, it is formed in a region extending from the outer peripheral edge 32 of the source region 6 to the peripheral edge of the field insulating film 4, is integrated with the field insulating film 4, and is integrated with the channel region 33 and the semiconductor. It covers area 35 .
The gate insulating film 8 is made of silicon oxide (SiO ₂ ) in this embodiment, but may be made of other insulating materials (for example, silicon nitride oxide (SiON)). The thickness of gate insulating film 8 is thinner than field insulating film 4, for example, 2 nm to 55 nm.

A gate electrode 9 is formed on the gate insulating film 8 . Gate electrode 9 faces channel region 33 and semiconductor region 35 with gate insulating film 8 interposed therebetween, and extends continuously from gate insulating film 8 to first portion 29 of field insulating film 4 . Thereby, the gate electrode 9 covers the second portion 30 and the first portion 29 (a portion) of the field insulating film 4 .
In this embodiment, the gate electrode 9 is the hatched area in FIG. That is, it is formed in an annular shape covering both the inside and the outside of the peripheral portion of the field insulating film 4 surrounding the first region 19 of the epitaxial layer 3 . Source region 6 may be formed, for example, in self-alignment with the inner peripheral edge of gate electrode 9 . Gate electrode 9 is, for example, polysilicon doped with an impurity.

Interlayer insulating film 10 is formed over the entire element main surface 17 of epitaxial layer 3 . Interlayer insulating film 10 covers body region 5 , source region 6 , drain region 7 and gate electrode 9 . The interlayer insulating film 10 is composed of silicon oxide (SiO ₂ ) in this embodiment, but may be composed of other insulating materials (for example, silicon nitride (SiN) or the like). Moreover, the interlayer insulating film 10 may be composed of a laminated structure of a plurality of materials, for example, silicon oxide and silicon nitride. Further, the thickness of interlayer insulating film 10 is, for example, 0.3 μm to 2.0 μm.

Source contact 11 is embedded in interlayer insulating film 10 . More specifically, a source contact hole 36 for selectively exposing the source region 6 is formed in the interlayer insulating film 10 . Source contact 11 is arranged in source contact hole 36 and connected to source region 6 . A plurality of source contacts 11 may be provided at intervals along the longitudinal direction of the second region 20 of the epitaxial layer 3, as shown in FIG.

Also, the source contact 11 is made of tungsten (W) in this embodiment, but may be made of another conductive material (eg, aluminum (Al), copper (Cu), etc.). At that time, it goes without saying that a barrier film such as TiN may be used.
Drain contact 12 is embedded in interlayer insulating film 10 . More specifically, a drain contact hole 37 for selectively exposing the drain region 7 is formed in the interlayer insulating film 10 . The drain contact 12 is arranged in the drain contact hole 37 and connected to the drain region 7 . A plurality of drain contacts 12 may be provided at intervals along the longitudinal direction of the first region 19 of the epitaxial layer 3, as shown in FIG.

In this embodiment, the drain contact 12 is arranged in a region between the valleys 26 of the field insulating film 4 in plan view. With this configuration, in the drain region 7, the drain contact 12 is sandwiched between the valleys 26 and is arranged in a relatively wide portion, so that flexibility can be given to the design rule. A cell pitch can be reduced.

Also, the drain contact 12 is made of tungsten (W) in this embodiment, but may be made of other conductive materials (eg, aluminum (Al), copper (Cu), etc.). At that time, it goes without saying that a barrier film such as TiN may be used.
Source electrode 13 and drain electrode 14 are formed on the surface of interlayer insulating film 10 . Source electrode 13 and drain electrode 14 cover source contact 11 and drain contact 12 and are connected to source contact 11 and drain contact 12, respectively. As a result, the source electrode 13 and the drain electrode 14 are electrically connected to the source region 6 and the drain region 7, respectively.

The source electrode 13 and the drain electrode 14 are made of aluminum (Al) in this embodiment, but may be made of other conductive materials (for example, copper (Cu), etc.). The source electrode 13 and the drain electrode 14 may be referred to as a source wiring and a drain wiring, respectively, depending on their shape (pattern).
Although not shown in FIGS. 1 and 2, a conductive layer such as a gate wiring electrically connected to the gate electrode 9 is formed on the interlayer insulating film 10 .

In this semiconductor device 1, for example, the source electrode 13 is grounded, a positive voltage (drain voltage) is applied to the drain electrode 14, and the potential of the gate electrode 9 is controlled. A channel can be formed in the vicinity of the interface between the source region 6 and the drain region 7 so that a current can flow between the source region 6 and the drain region 7 .
3 to 18 are diagrams showing the steps of manufacturing the semiconductor device 1 shown in FIGS. 1 and 2 in order of steps. 19A and 19B are diagrams showing steps related to exposure and development of the photoresist 38. FIG. Note that in FIGS. 19A and 19B, part of the configuration of the semiconductor device 1 after manufacture is indicated by dashed lines in order to facilitate understanding of the manufacturing process (the same applies to FIGS. 23A and 23B, which will be described later).

First, as shown in FIG. 3, the n-type epitaxial layer 3 is formed on the main surface 15 of the semiconductor substrate 2 by an epitaxial method. As the n-type impurity, for example, P (phosphorus), As (arsenic), Sb (antimony), etc. can be applied (the same applies hereinafter).
Next, as shown in FIG. 4, a base insulating film 52 (eg, 5 nm to 50 nm thick) is formed on the device main surface 17 of the epitaxial layer 3 by, eg, thermal oxidation. The base insulating film 52 is composed of silicon oxide (SiO ₂ ) in this embodiment. Next, a mask insulating film 53 (for example, 80 nm to 200 nm thick) is deposited on the base insulating film 52 by a method such as low pressure CVD.

Next, as shown in FIG. 5, a photoresist 38 is applied onto the mask insulating film 53 . Photoresist 38 is applied using, for example, a spin coater or a spray coater. Photoresist 38 is a positive photoresist in this embodiment.
Next, as shown in FIG. 6, a photomask 39 is placed on the photoresist 38 .
The photomask 39 is formed with a pattern having openings in areas other than the hatched area in FIG. 19A. More specifically, an opening pattern 40 is provided in a portion of the element main surface 17 of the epitaxial layer 3 facing the region where the field insulating film 4 is formed.

The peripheral portion of the opening pattern 40 has a first side portion 41 and a second side portion 42 facing each other in a plan view of the element main surface 17 of the epitaxial layer 3 viewed from the normal direction.
The first side portion 41 includes a plurality of selectively projecting protrusions 43 and recesses 44 between the protrusions 43 . The convex portions 43 and the concave portions 44 are alternately arranged so that the convex portions 43 and the convex portions 43 face each other and the concave portions 44 and the concave portions 44 face each other.

The convex portion 43 is formed in a substantially square shape having a flat top portion and substantially right-angled corner portions at both ends of the top portion. The concave portion 44 is formed in a substantially square shape having a flat bottom portion and substantially right-angled corner portions at both ends of the bottom portion.
As a result, the first side portion 41 of the opening pattern 40 has a ninety-nine fold shape in which the first straight portion 45 along the longitudinal direction and the second straight portion 46 along the direction perpendicular to the longitudinal direction are alternately continuous. be. On the other hand, the second side portion 42 of the opening pattern 40 is formed linearly in the section facing the convex portion 43 and the concave portion 44 .

At this time, the photomask 39 has a fifth length L5 and a sixth length L6 shorter than the fifth length L5 between the first side portion 41 and the second side portion . are doing. More specifically, the distance between the top of the convex portion 43 and the second side portion 42 (straight line portion) is set as a fifth length L5, and the distance between the bottom portion of the concave portion 44 and the second side portion 42 is relatively long. (straight line portion) is set as a sixth length L6 relatively shorter than the fifth length L5. In this embodiment, the fifth length L5 is for example between 0.3 μm and 0.6 μm and the sixth length L6 is for example between 0.1 μm and 0.4 μm.

Then, as shown in FIG. 6, the photoresist 38 is exposed to light (for example, ultraviolet rays) through such a photomask 39 .
Excess portions of the photoresist 38 are then removed by immersing the exposed wafer (semiconductor substrate 2 and structures thereon) in a developer. In this embodiment, since the photoresist 38 is of positive type, the portion of the photoresist 38 exposed through the opening pattern 40 is removed.

As a result, an opening pattern 47 corresponding to the opening pattern 40 of the photomask 39 is formed in the photoresist 38, as shown in FIGS. 7 and 19B. In this embodiment, the photoresist 38 is not exposed so that the shapes of the projections 43 and the recesses 44 of the photomask 39 are completely matched due to light diffraction and interference phenomena, and the shapes of the projections 43 and the recesses 44 are different from each other. It is exposed in a smoothed state. As a result, the opening pattern 47 of the photoresist 38 after development has a wavy first side portion 50 and a wavy second side portion 48 including peaks 48 corresponding to the convex portions 43 and valley portions 49 corresponding to the concave portions 44 . It will have a linear second side portion 51 corresponding to 42 .

As a result, the photoresist 38 has a seventh length L7 shorter than the fifth length L5 and a length longer than the sixth length L6 between the first side portion 50 and the second side portion 51. and an eighth length L8. More specifically, the distance between the top portion of the peak portion 48 and the second side portion 51 (straight line portion) is set as a seventh length L7 that is relatively long, and the bottom portion of the valley portion 49 and the second side portion 51 (straight line portion) is set as an eighth length L8 that is relatively shorter than the seventh length L7. In addition, in FIG. 19B, the photoresist 38 remaining after the development is indicated by hatching.

Next, as shown in FIG. 8, the mask insulating film 53 exposed from the opening pattern 47 of the photoresist 38 is selectively removed by a method such as reactive ion etching (RIE). be. As a result, a hard mask 55 made of the mask insulating film 53 having the same opening pattern 54 as the opening pattern 47 of the photoresist 38 is formed. After that, the photoresist 38 is removed by a known method.

Next, as shown in FIG. 9, by thermally oxidizing the portion of the epitaxial layer 3 exposed from the opening pattern 54 of the hard mask 55, the base insulating film 52 is thickened, and the element main surface 17 of the epitaxial layer 3 is exposed. , a field insulating film 4 is selectively formed. At this time, the peripheral pattern of the opening pattern 54 is taken over by the field insulating film 4 . As a result, field insulating film 4 is formed in a shape including curved portion 24 (first end portion) including peak portion 25 and valley portion 26 and straight portion 27 (second end portion). Also, the portion intruded into the interface between hard mask 55 and epitaxial layer 3 is formed as second portion 30 of field insulating film 4 .

After that, as shown in FIG. 10, the hard mask 55 is removed by a method such as sulfuric acid etching. Next, the base insulating film 52 below the hard mask 55 is removed by etching with, for example, hydrogen fluoride water. As a result, the portions covered with the hard mask 55 are exposed as the first region 19 and the second region 20 of the element main surface 17 of the epitaxial layer 3 .

Next, as shown in FIG. 11, a gate insulating film 8 (for example, 2 nm to 55 nm thick) is formed on the element main surface 17 of the epitaxial layer 3 exposed from the field insulating film 4 by a method such as thermal oxidation. is formed.
Next, polysilicon is deposited on the entire surface of the element main surface 17 of the epitaxial layer 3 by, for example, a low-pressure CVD method or the like. is formed.

Next, as shown in FIG. 13, p-type impurity ions are selectively implanted into the second region 20 of the element main surface 17 of the epitaxial layer 3 . As the p-type impurity, for example, B (boron), Al (aluminum), Ga (gallium), or the like can be applied.
Next, as shown in FIG. 14, the epitaxial layer 3 is heat treated to diffuse the impurity ions implanted in the process of FIG. Thus, p-type body region 5 is formed.

Next, as shown in FIG. 15, n-type impurity ions are implanted into first region 19 and second region 20 of element main surface 17 of epitaxial layer 3 .
Next, as shown in FIG. 16, the epitaxial layer 3 is heat-treated to diffuse the impurity ions implanted in the process of FIG. Thereby, n-type source region 6 and drain region 7 are formed. Although the source region 6 and the drain region 7 are formed in the same step in this embodiment, they may be formed through separate ion implantation steps and heat treatment steps.

Next, as shown in FIG. 17, interlayer insulating film 10 is formed by, for example, CVD to cover the entire surface of element main surface 17 of epitaxial layer 3 .
Next, as shown in FIG. 18, the interlayer insulating film 10 is selectively etched to form a source contact hole 36 and a drain contact hole 37. Next, as shown in FIG. Although the source contact hole 36 and the drain contact hole 37 are formed in the same step in this embodiment, they may be formed in separate etching steps.

Thereafter, source contact 11, drain contact 12, source electrode 13 and drain electrode 14 are formed to obtain semiconductor device 1 shown in FIGS.
As described above, according to this embodiment, as shown in FIG. 19A, the photoresist 38 is exposed using the photomask 39 having the opening pattern 40 including the protrusions 43 and the recesses 44 . Therefore, the photoresist 38 is exposed with the shapes of the projections 43 and the recesses 44 smoothed by light diffraction and interference phenomena. As a result, the opening pattern 47 of the photoresist 38 after development has a wavy first side portion 50 and a wavy second side portion 48 including peaks 48 corresponding to the convex portions 43 and valley portions 49 corresponding to the concave portions 44 . It will have a linear second side portion 51 corresponding to 42 .

Therefore, even if the sixth length L6 whose end point is the bottom of the concave portion 44 of the photomask 39 is below the resolution limit of the exposing machine, the convex portion 43 and the concave portion 44 are smoothed, resulting in poor resolution. can be prevented. As a result, even if an exposure device with a relatively high resolution limit (for example, a resolution limit of 6 μm or the like) is used, the second thickness of the field insulating film 4 is below the resolution limit of the exposure device in the first direction D1. A length L2 can be realized.

According to the semiconductor device 1 having the second length L2, the field insulating film 4 has a portion having the second length L2 that is relatively short in the first direction D1. As a result, the cell pitch is reduced, so that the on-resistance per unit area can be reduced.
<Second embodiment>
FIG. 20 is a schematic plan view of a semiconductor device 61 according to the second embodiment of the invention.

In the above-described embodiments, the drain contact 12 is arranged in the region between the valleys 26 of the field insulating film 4 in plan view. In contrast, in the semiconductor device 61 according to this embodiment, the drain contact 12 is formed in the region between the peaks 25 of the field insulating film 4 and the region between the valleys 26 of the field insulating film 4 . are placed in both As a result, the number of drain contacts 12 is increased compared to the above-described embodiment, so the contact resistance to the drain region 7 can be reduced.
<Third Embodiment>
FIG. 21 is a schematic plan view of a semiconductor device 71 according to the third embodiment of the invention.

In this semiconductor device 71 , the portion of the field insulating film 4 surrounding the second region 20 includes a pair of curved portions 72 facing each other and a pair of curved portions 73 connecting the ends of the curved portions 72 . More specifically, the pair of curved portions 72 have a semicircular shape that bulges in the second direction D<b>2 and form sides of the second region 20 in the short direction. On the other hand, the pair of curved portions 73 extend in the second direction D2 and constitute sides of the second region 20 in the longitudinal direction.

In addition, the pair of curved portions 73 has a wave shape including a peak portion 74 that protrudes toward the inside of the second region 20 and a valley portion 75 that is continuous with the peak portion 74 and recessed in a direction away from the second region 20. formed. Furthermore, with respect to the pair of curved portions 73 that face each other, the peak portions 74 face each other and the valley portions 75 face each other. Thus, the second region 20 is the third length L3 between the peaks 74 and the length between the valleys 75 in the first direction D1, and a fourth length L4 longer than the third length L3.

On the other hand, the portion of the field insulating film 4 surrounding the first region 19 includes a pair of straight portions 76 facing each other and a pair of straight portions 77 connecting the ends of the straight portions 76 . More specifically, the pair of linear portions 76 are linear extending in the second direction D<b>2 and constitute sides of the first region 19 in the longitudinal direction. On the other hand, the pair of linear portions 77 are linear extending in the first direction D<b>1 and constitute sides of the first region 19 in the short direction. Thereby, the first region 19 is formed in a rectangular shape in plan view.

That is, the curved portion 73 and the straight portion 76 of the field insulating film 4 extending in the second direction D2 face each other. As a result, the distance between the top of the peak portion 74 of the curved portion 73 and the straight portion 76 is set as a relatively long first length L1, and the distance between the bottom of the valley portion 75 of the curved portion 73 and the straight portion 76 is set to be relatively long. A distance is set as a second length L2 that is relatively shorter than the first length L1.

In order to manufacture such a semiconductor device 71, as a process different from the manufacturing process of the first embodiment, in the process shown in FIG. A photomask 39 having an opening pattern 40 in which the portions 41 are linearly formed in the sections facing the convex portions 43 and the concave portions 44 may be used.
<Fourth Embodiment>
FIG. 22 is a schematic plan view of a semiconductor device 81 according to the fourth embodiment of the invention.

In this semiconductor device 81 , the portion of the field insulating film 4 surrounding the second region 20 of the semiconductor device 1 described above has a pair of curved portions 82 facing each other instead of the pair of straight portions 27 .
The pair of curved portions 82 are formed in a wavy shape including peak portions 83 projecting toward the inside of the second region 20 and valley portions 84 that are continuous with the peak portions 83 and recessed in a direction away from the second region 20. ing.

In the first direction D1, the peak portion 83 and the valley portion 26 face each other, and the valley portion 84 and the peak portion 25 face each other. Thereby, the distance between the top of the peak 83 and the bottom of the valley 26 is set as the first length L1, and the distance between the bottom of the valley 84 and the top of the peak 25 is set as the second length L2. is set as The first length L1 and the second length L2 are the same length. Therefore, according to the semiconductor device 81 of this embodiment, the distance between the first region 19 and the second region 20 can be shortened throughout the second direction D2.
<Fifth Embodiment>
23A and 23B are diagrams (fifth embodiment) showing steps related to exposure and development of the photoresist 38. FIG.

While the photomask 39 having a single pattern was used in the above embodiment, a photomask 92 having a plurality of patterns 91 is used in this embodiment. More specifically, as shown in FIG. 23A, in a photomask 92, each of the plurality of patterns 91 is formed in a rectangular shape in plan view. Each pattern 91 has a ninth length L9 in the first direction D1.

Also, the plurality of patterns 91 are arranged at intervals of less than 0.5 μm from each other. A plurality of patterns 91 are arranged at intervals in the region where the field insulating film 4 is to be formed.
Also, in this embodiment, the photoresist 38 is a negative photoresist.
Then, the photoresist 38 is exposed by irradiating the photoresist 38 with light (for example, ultraviolet rays or the like) through the photomask 92 .

Excess portions of the photoresist 38 are then removed by immersing the exposed wafer (semiconductor substrate 2 and structures thereon) in a developer. In this embodiment, because of the negative photoresist 38, the portion of the photoresist 38 covered by the pattern 91 and not exposed is removed. Furthermore, since the interval between the patterns 91 is less than 0.5 μm, exposure of the gaps 93 between the adjacent patterns 91 can be prevented by using an exposure machine with a resolution limit equal to or greater than the interval.

As a result, as shown in FIG. 23B, the opening pattern 47 of the photoresist 38 has peaks 94 corresponding to both ends of the gap 93 between the adjacent patterns 91 and valleys 95 corresponding to both ends of the pattern 91 . It will have a wavy first side portion 50 and a second side portion 51 including a . At least the gap portion 93 between adjacent patterns 91 can be resolved with a second length L2 shorter than the ninth length L9 of the pattern 91 of the photomask 92 .

Although the embodiments of the present invention have been described above, the present invention can also be implemented in other forms.
For example, the photoresist 38 used in the first embodiment may be a negative photoresist, and the photoresist 38 used in the fifth embodiment may be a positive photoresist. The patterns of the photomask 39 and the photomask 92 may be appropriately changed according to the type of photoresist (positive type, negative type).

In addition, various design changes can be made within the scope of the matters described in the claims.

REFERENCE SIGNS LIST 1 semiconductor device 2 semiconductor substrate 3 epitaxial layer 4 field insulating film 5 body region 6 source region 7 drain region 8 gate insulating film 9 gate electrode 10 interlayer insulating film 11 source contact 12 drain contact 13 source electrode 14 drain electrode 15 main surface 16 back surface 17 element main surface 18 joint surface 19 first region 20 second region 21 first opening 22 second opening 23 straight portion 24 curved portion 25 crest portion 26 valley portion 27 straight portion 28 curved portion 29 first portion 30 second portion 31 Outer edge 32 Outer edge 33 Channel region 34 Outer edge 35 Semiconductor region 36 Source contact hole 37 Drain contact hole 38 Photoresist 39 Photomask 40 Opening pattern 41 First side 42 Second side 43 Convex 44 Concave 45 First straight line Part 46 Second straight part 47 Opening pattern 48 Peak part 49 Valley part 50 First side part 51 Second side part 52 Base insulating film 53 Mask insulating film 54 Opening pattern 55 Hard mask 61 Semiconductor device 71 Semiconductor device 72 Curved part 73 Curved line Portion 74 Peak 75 Valley 76 Straight portion 77 Straight portion 81 Semiconductor device 82 Curved portion 83 Peak 84 Valley 91 Pattern 92 Photomask 93 Gap 94 Peak 95 Valley

Claims (13)

a first conductivity type semiconductor layer having an element main surface;
a body region of a second conductivity type formed on the element main surface of the semiconductor layer;
a first conductivity type source region formed in the body region and spaced apart from the periphery of the body region;
a first conductivity type drain region formed on the element main surface of the semiconductor layer and spaced apart from the body region;
a gate insulating film facing a channel region between the source region and the periphery of the body region;
a gate electrode facing the channel region through the gate insulating film;
a field insulating film formed on the element main surface of the semiconductor layer between the gate insulating film and the drain region and having a thickness greater than that of the gate insulating film ;
an interlayer insulating film formed on the semiconductor layer;
a drain contact penetrating through the interlayer insulating film in the thickness direction and connected to the drain region ;
The field insulating film has a first length and a first a second length that is less than the length of
The semiconductor device , wherein the second length is set to a portion adjacent to the drain contact in the first direction . The end portion of the field insulating film on the side of the drain region includes, in the plan view, a mountain portion projecting in a direction toward the drain region and a valley portion continuous with the mountain portion and recessed in a direction away from the drain region. is formed into a waveform containing and
2. One end point of said first length is set at the top of said peak, and one end point of said second length is set at the bottom of said valley. The semiconductor device according to . 3. The semiconductor device according to claim 2, wherein the end of said field insulating film on the source region side is formed linearly in a section facing said peak and said valley. The end portion of the field insulating film on the source region side includes, in the plan view, a mountain portion projecting in a direction toward the source region and a valley portion continuous with the mountain portion and recessed in a direction away from the source region. 3. The semiconductor device according to claim 2, wherein the semiconductor device is formed into a corrugated shape including and. a first conductivity type semiconductor layer having an element main surface;
a body region of a second conductivity type formed on the element main surface of the semiconductor layer;
a first conductivity type source region formed in the body region and spaced apart from the periphery of the body region;
a first conductivity type drain region formed on the element main surface of the semiconductor layer and spaced apart from the body region;
a gate insulating film facing a channel region between the source region and the periphery of the body region;
a gate electrode facing the channel region through the gate insulating film;
a field insulating film formed on the element main surface of the semiconductor layer between the gate insulating film and the drain region and having a thickness greater than that of the gate insulating film;
The field insulating film has a first length and a first a second length that is less than the length of
The end portion of the field insulating film on the side of the drain region includes, in the plan view, a mountain portion projecting in a direction toward the drain region and a valley portion continuous with the mountain portion and recessed in a direction away from the drain region. is formed into a waveform containing and
One end point of the first length is set at the top of the peak, and one end point of the second length is set at the bottom of the valley,
The end portion of the field insulating film on the source region side is, in the plan view, a mountain portion protruding in a direction toward the source region, and is continuous with the mountain portion on the source region side and separated from the source region. A semiconductor device formed into a corrugated shape including valleys recessed in a direction. In the first direction, the peak portion of the field insulating film on the drain region side faces the peak portion on the source region side, and the valley portion of the field insulating film on the drain region side is opposed to the peak portion on the source region side. 6. The semiconductor device according to claim 4, wherein said valley on said source region side is opposed to said valley. 5. The drain contact according to any one of claims 2 to 4 , wherein the drain contact is arranged in a portion adjacent to the valley at the end of the field insulating film on the drain region side in the plan view. semiconductor device. 8. The semiconductor device according to claim 1, wherein said first length is 0.4 μm to 0.7 μm and said second length is 0.2 μm to 0.5 μm. . 9. The semiconductor device according to claim 1 , wherein said field insulating film includes a LOCOS (LOCal Oxidation of Silicon) oxide film. a step of applying a photoresist onto a semiconductor layer of a first conductivity type having a main surface of an element;
A mask having an edge including a plurality of selectively projecting protrusions and recesses between the plurality of protrusions in a plan view of the element main surface of the semiconductor layer in the normal direction is formed by the photomask. placing on the resist;
Exposing and developing the photoresist using the mask to have wavy edges including peaks corresponding to the protrusions of the mask and valleys corresponding to the recesses of the mask. patterning the photoresist to
By oxidizing the element main surface of the semiconductor layer exposed from a hard mask formed using the patterned photoresist as a mask, the peak portions corresponding to the peak portions of the photoresist and the forming a field insulating film having a corrugated first end including a valley corresponding to the valley and a second end opposite the first end;
By removing the hard mask, a first region which is the element main surface of the semiconductor layer on the first end side of the field insulating film and the element on the second end side of the field insulating film are formed. exposing the second region, which is the main surface;
forming a drain region of a first conductivity type in the first region of the semiconductor layer;
selectively forming a gate insulating film in the second region of the semiconductor layer;
forming a gate electrode on the gate insulating film;
forming a body region of a second conductivity type in the second region of the semiconductor layer;
forming a source region of the first conductivity type in the body region so as to be spaced apart from the periphery of the body region ;
forming an interlayer insulating film on the element main surface of the semiconductor layer;
By selectively etching the interlayer insulating film, a drain contact hole for selectively exposing the drain region is formed in a portion adjacent to the valley in a first direction from the drain region to the source region. A method of manufacturing a semiconductor device, comprising : a step of applying a photoresist onto a semiconductor layer of a first conductivity type having a main surface of an element;
A mask having an edge including a plurality of selectively projecting protrusions and recesses between the plurality of protrusions in a plan view of the element main surface of the semiconductor layer in the normal direction is formed by the photomask. placing on the resist;
Exposing and developing the photoresist using the mask to have wavy edges including peaks corresponding to the protrusions of the mask and valleys corresponding to the recesses of the mask. patterning the photoresist to
By oxidizing the element main surface of the semiconductor layer exposed from a hard mask formed using the patterned photoresist as a mask, the peak portions corresponding to the peak portions of the photoresist and the forming a field insulating film having a corrugated first end including a valley corresponding to the valley and a second end opposite the first end;
By removing the hard mask, a first region which is the element main surface of the semiconductor layer on the first end side of the field insulating film and the element on the second end side of the field insulating film are formed. exposing the second region, which is the main surface;
selectively forming a gate insulating film in the first region of the semiconductor layer;
forming a gate electrode on the gate insulating film;
forming a body region of a second conductivity type in the first region of the semiconductor layer;
forming a source region of the first conductivity type in the body region so as to be spaced apart from the periphery of the body region;
forming a first conductivity type drain region in the second region of the semiconductor layer ;
forming an interlayer insulating film on the element main surface of the semiconductor layer;
By selectively etching the interlayer insulating film, a drain contact hole for selectively exposing the drain region is formed in a portion adjacent to the valley in a first direction from the drain region to the source region. A method of manufacturing a semiconductor device, comprising : 12. The method of manufacturing a semiconductor device according to claim 10 , wherein said mask has an end portion formed in a straight line opposite to the end portion including said projection and said recess. a step of applying a photoresist onto a semiconductor layer of a first conductivity type having a main surface of an element;
disposing on the photoresist a mask having a plurality of patterns spaced apart from each other by less than 0.5 μm in a plan view of the device principal surface of the semiconductor layer;
By exposing and developing the photoresist using the mask, the photo resist is formed so as to have an edge including valleys corresponding to gaps between the adjacent patterns and peaks corresponding to the patterns. patterning the resist;
By oxidizing the element main surface of the semiconductor layer exposed from a hard mask formed using the patterned photoresist as a mask, the peak portions corresponding to the peak portions of the photoresist and the forming a field insulating film having a wavy first end and a wavy second end each including a valley corresponding to the valley;
By removing the hard mask, a first region which is the element main surface of the semiconductor layer on the first end side of the field insulating film and the element on the second end side of the field insulating film are formed. exposing the second region, which is the main surface;
forming a drain region of a first conductivity type in the first region of the semiconductor layer;
selectively forming a gate insulating film in the second region of the semiconductor layer;
forming a gate electrode on the gate insulating film;
forming a body region of a second conductivity type in the second region of the semiconductor layer;
and forming a source region of the first conductivity type in the body region so as to be spaced apart from a peripheral edge of the body region.

Images