JP7271264B2 - LATCH ARRAY CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - Google Patents

Description

The present invention relates to latch array circuits and semiconductor integrated circuits.

In a system in which data from a plurality of blocks are output using a common bus, a circuit is provided to prevent bus logic conflicts caused by simultaneous data output from a plurality of blocks. This circuit includes, for example, a buffer (for example, a tristate buffer) that outputs data to a bus, a control circuit that outputs a control signal for controlling the buffer, and a control signal that is output from the control circuit and is supplied to the buffer. and a plurality of flip-flops as storage elements.

In such a circuit, when the system power is turned on, the output of the flip-flop may become unstable because the flip-flop has not received the control signal from the control circuit. Therefore, a flip-flop with a reset terminal is used as the flip-flop, and a power-on reset signal is input to each reset terminal when power is turned on. Inputting a power-on reset signal to the power-on reset terminal fixes the output of the flip-flop to a predetermined value.

When flip-flops with reset terminals are used, each flip-flop must have a built-in reset function, resulting in a large circuit scale and a large chip occupation area. Therefore, in order to reduce the chip area, flip-flops without reset terminals are used instead of flip-flops with reset terminals to form circuits. In this circuit, a reset clock generation circuit is provided to generate a reset clock signal, and a reset clock signal is input to the clock terminal of a flip-flop that does not have a reset terminal immediately after the power is turned on. fetches a control signal (for example, Patent Document 1).

Japanese Patent No. 3368815

However, the power-on reset signal and the reset clock signal supplied to the flip-flops as in the conventional technology rise reflecting the rise of the power supply voltage, so they have to rise with some delay from the rise of the power supply voltage. Therefore, the output value of the flip-flop becomes unstable until the power-on reset signal or reset clock signal rises. Therefore, it is impossible to completely eliminate the period during which the internal circuit is not reset (initialized).

Depending on the type of internal circuit, the presence of such an uninitialized period poses a serious problem. For example, in semiconductor integrated circuits and electronic equipment, in addition to normal functions open to users, test functions are often built in advance for use only by designers, manufacturers, and product suppliers. The test function is installed for the purpose of facilitating analysis of failure occurrence, understanding of operating limits, and selection of manufacturing defects before product shipment. As circuits become larger in scale, more multifunctional, and more complex, test functions tend to become more and more diverse. For this reason, in a semiconductor integrated circuit with a built-in test function, a test mode latch circuit including a memory element group and its control circuit for centrally switching and holding information for setting and canceling the test function is provided as an internal circuit. often

Further, the large-scale semiconductor integrated circuit incorporates a power supply circuit that generates an internal power supply potential based on the external power supply potential and supplies it to internal circuits such as a test mode latch circuit. In such a configuration, in order to analyze the failure of the internal circuit, grasp the operating limit, and sort out manufacturing defects before shipment, the cause derived from the built-in power supply circuit and the cause derived from the internal circuit itself must be separated. Separable test methods are essential. In order to implement such a test method, for example, a test function is provided that includes a function that allows a pseudo internal power supply potential to be separately supplied from the outside in parallel with a normal external power supply potential and a function that forcibly stops the built-in power supply circuit. It is conceivable to install it in advance as These test functions are held by a dedicated latch provided in the test mode latch circuit by receiving the supply of the internal power supply potential, and a power-on reset signal is used to ensure that unintended test functions are not activated when the power is turned on. need to be transformed.

However, as in the above prior art, the output value of the flip-flop becomes undefined until the power-on reset signal or reset clock signal rises, and the test mode latch circuit cannot be initialized. Whether or not it becomes is also uncertain. If the test mode is set to test mode by mistake, the internal power supply potential will not rise due to the power supply circuit stopping, unlike the original operation in which a power-on reset signal is generated based on the rise in the internal power supply potential. A power-on reset signal is not generated for a long time, and normal operation cannot be started.

Such a power-on reset failure at power-on can occur regardless of whether the test function is used or not, and regardless of whether the product is shipped before or after it is shipped. Depends on whether "H" level or "L" level is output by chance, it appears as a troublesome problem that is irregular and has no reproducibility.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a latch array circuit that can prevent the occurrence of a period in which the output of a memory element is unstable.

A latch array circuit according to the present invention comprises a plurality of latch circuits arranged in a matrix and a first timing signal that transitions at a first timing synchronized with the rise of a power-on reset signal. and a second timing signal that transitions at a second timing later than the first timing. and a data supply unit for fixing each data input to a predetermined value for each row or column of the plurality of latch circuits , wherein the clock control unit is arranged for each row or column of the plurality of latch circuits. a first logic gate circuit group comprising a plurality of logical sum circuits each provided for each and receiving the external clock signal and the first timing signal and outputting the logical sum of the external clock signal and the first timing signal; controlling the clock input of the plurality of latch circuits for each row or column based on the first timing signal until the first timing, based on the outputs of the plurality of OR circuits; After the first timing, clock inputs to the plurality of latch circuits are controlled row by row or column by column based on the external clock signal.

According to the latch array circuit of the present invention, it is possible to avoid a state in which the output of the memory element becomes unstable before the power-on reset signal rises.

3 is a block diagram showing the configuration of the latch array circuit of Example 1; FIG. 3 is a block diagram showing a configuration example of a power-on reset circuit used together with the latch array circuits of Examples 1 to 3; FIG. FIG. 3 is a waveform diagram of Examples 1 to 3 showing the rise of the internal power supply potential and the input potential VRC shown in FIG. 2 when the power is turned on; FIG. 10 is a waveform diagram of Examples 1 to 3 showing the operation of the power-on reset circuit when the power is turned on; FIG. 10 is a waveform diagram of Examples 1 to 3 showing the operation of the latch array circuit of the present example when power is turned on; FIG. 10 is a waveform diagram of Examples 1 to 3 showing the operation of the latch array circuit of the present example when power is turned on; FIG. 11 is a block diagram showing the configuration of a latch array circuit of Example 2; FIG. 11 is a block diagram showing a configuration example of a power-on reset circuit of Example 2; FIG. 11 is a block diagram showing the configuration of a latch array circuit of Example 3;

Preferred embodiments of the present invention are described in detail below. In the following description of each embodiment and the attached drawings, substantially the same or equivalent parts are denoted by the same reference numerals.

FIG. 1 is a block diagram showing the configuration of a latch array circuit 100 of this embodiment. The latch array circuit 100 is mounted on an IC chip. Latch array circuit 100 includes a plurality of latch circuits L00, L01, . . . , L0n, L10, L11, . , Lm1, . . . , Lmn (hereinafter collectively referred to as latch circuits L00 to Lmn).

Each of latch circuits L00 to Lmn is a transparent type D latch circuit having no reset terminal. That is, each of the latch circuits L00 to Lmn responds to the input signal input to the data input terminal D while the clock signal input to the clock terminal CK is at the "H" level (that is, the logic value is "1"). Output data reflecting the value is output from the output terminal Q. On the other hand, each of the latch circuits L00 to Lmn maintains the previous state regardless of the value of the input signal input to the data input terminal D during the period when the clock signal is at the "L" level (that is, the logic value is "0"). The output data holding the value is continuously output from the output terminal Q.

Latch array circuit 100 also includes a delay circuit DLY. The delay circuit DLY receives the input of the inverted preceding power-on reset signal PORB and delays it to output the inverted subsequent power-on reset signal POR2B. The inverted preceding power-on reset signal PORB is supplied from a power-on reset circuit provided outside the latch array circuit 100 .

Latch array circuit 100 also includes (m+1) AND gate circuits AN0, AN1, . Each of the AND gate circuits AN0, AN1, . . . , ANm is a 2-input AND circuit. AND gate circuits AN0, AN1, .

External input data signals DI<0>, DI<1>, . An inverted subsequent power-on reset signal POR2B is commonly input to the other input terminals of the AND gate circuits AN0, AN1, . . . , ANm. AND gate circuit AN0 outputs a signal obtained by ANDing external input data signal DI<0> and inverted subsequent power-on reset signal POR2B as internal input data signal D0. Similarly, AND gate circuits AN1-ANm output logical product signals of external input data signals DI<1>-DI<m> and inverted subsequent power-on reset signal POR2B as internal input data signals D1-Dm.

The internal input data signal D0, which is the output signal of the AND gate circuit AN0, is input to the data input terminal D of each of the latch circuits L00 to L0n arranged in the first row among the latch circuits L00 to Lmn. Similarly, internal input data signals D1 to Dm common to each row are supplied to the data input terminals D of the latch circuits L10 to L1n, . is entered.

Latch array circuit 100 also includes an inverter INV0. Inverter INV0 receives an input of inverted preceding power-on reset signal PORB, and outputs a preceding power-on reset signal POR1 by inverting this.

Latch array circuit 100 also includes (n+1) OR gate circuits OR0, OR1, . Each of the OR gate circuits OR0, OR1, . . . , ORn is a two-input logical sum circuit. The OR gate circuits OR0, OR1, .

External clock signals CKI<0>, CKI<1>, . The preceding power-on reset signal POR1 is commonly input to the other input terminals of the OR gate circuits OR0, OR1, . . . , ORn. The external clock signals CKI<0>, CKI<1>, .

OR gate circuit OR0 outputs a signal obtained by ORing external clock signal CKI<0> and preceding power-on reset signal POR1 as internal clock signal CK0. Similarly, the OR gate circuits OR1, . . Since the external clock signals CKI<0>, CKI<1>, . . . , CKI<n> are pulse clock signals, the internal clock signals CK0, CK1, . clock signal.

The internal clock signal CK0, which is the output signal of the OR gate circuit OR0, is input to the clock terminal CK of each of the latch circuits L00 to Lm0 arranged in the first column among the latch circuits L00 to Lmn. Similarly, internal clock signals CK1 to CKn common to each column are input to clock terminals CK of latch circuits L01 to Lm1, . be. The latch circuits L00 to Lmn are configured as pulse latch circuits that operate in response to pulsed internal clock signals CK0, CK1, . . . , CKn.

Latch circuit L00 outputs an output signal Q00 from output terminal Q. FIG. Similarly, latch circuits L01-Lmn output output signals Q01-Qmn, respectively. The output signal from each of the latch circuits L00 to Lmn has a value reflecting the value of the internal input data signal input to the clock terminal D while the internal clock signal input to the clock terminal CK is at "H" level. , the previous value is held while the internal clock signal is at the "L" level.

FIG. 2 is a circuit diagram showing a configuration example of the first power-on reset circuit PRC1 that generates the inverted preceding power-on reset signal PORB. The first power-on reset circuit PRC1 is provided inside the IC chip and outside the latch array circuit 100 . The first power-on reset circuit PRC1 receives an internal power supply potential Vdd from an internal power supply circuit (not shown) provided inside the IC chip, and receives an internal power-on reset signal POR and an inverted preceding power-on reset signal PORB. to generate The first power-on reset circuit PRC1 is composed of, for example, a resistive element R1, a capacitive element C1, an inverter INV1 and an inverter INV2.

Resistance element R1 and capacitance element C1 are connected in series between a node receiving internal power supply potential Vdd and a ground node. That is, the internal power supply potential Vdd is supplied to one end of the resistance element R1, the ground potential is supplied to one end of the capacitance element C1, and the other ends of the resistance element R1 and the capacitance element C1 are connected to each other.

An input terminal of the inverter INV1 is connected to a connection node between the resistance element R1 and the capacitance element C1. The inverter INV1 outputs a signal obtained by inverting the input potential VRC, which is the potential of the connection node, as the internal power-on reset signal POR.

The input end of the inverter INV2 is connected to the output end of the inverter INV1. The inverter INV2 outputs an inverted preceding power-on reset signal PORB obtained by inverting the internal power-on reset signal POR.

FIG. 3A is a waveform diagram showing temporal changes in the internal power supply potential Vdd and the input potential VRC when the power of the first power-on reset circuit PRC1 is turned on. FIG. 3B is a waveform diagram showing temporal changes of the internal power-on reset signal POR and the inverted preceding power-on reset signal PORB at that time.

First, when an external power supply (not shown) provided outside the IC chip is turned on, the internal power supply potential Vdd starts to rise after a short delay after the external power supply potential starts to rise. Here, the time at which the internal power supply potential Vdd starts rising is indicated as time t0. At this time, due to the presence of the resistance element R1 and the capacitance element C1, the input potential VRC rises with a delay from the internal power supply potential Vdd.

Assuming that the time at which internal power supply potential Vdd reaches logic threshold VTH of inverter INV1 is time t1, input potential VRC has not yet reached logic threshold VTH at time t1. Therefore, the inverter INV1 outputs the "H" level internal power-on reset signal POR. This "H" level value continues to rise as the internal power supply potential Vdd rises.

Assuming that the time at which the input potential VRC reaches the logic threshold value VTH of the inverter INV1 is time t2, the inverter INV1 outputs the internal power-on reset signal POR at "L" level after time t2. The period from time t1 to time t2 is the power reset period TRST.

The inverted preceding power-on reset signal PORB is a signal obtained by inverting the internal power-on reset signal POR, and is at "L" level until time t2 and at "H" level after time t2. Since internal power supply potential Vdd is still rising near time t2, inverted preceding power-on reset signal PORB rises as internal power supply potential Vdd rises. Then, as the internal power supply potential Vdd reaches a predetermined saturation potential, the potential of the inverted preceding power-on reset signal PORB also becomes constant.

Although the potential of the internal power-on reset signal POR is unstable while the internal power supply potential Vdd is low, it is almost the same potential as the internal power supply potential Vdd, and the input of the inverter INV2 becomes "H" level. Therefore, there is no reason for the current from the internal power supply potential Vdd to consistently flow into the output terminal of the inverter INV2. Therefore, the inverted preceding power-on reset signal PORB is relatively early and stably maintained at the ground potential level. At least, even during an unstable period while internal power supply potential Vdd is rising, inverted preceding power-on reset signal PORB is reliably maintained at "L" level.

Next, the operation of the latch array circuit 100 of this embodiment will be described with reference to FIGS. 4A and 4B.

FIG. 4A is a waveform diagram showing temporal changes of the preceding power-on reset signal POR1 and the inverted subsequent power-on reset signal POR2B. Here, the leading power-on reset signal POR1 is indicated by a solid line, and the inverted subsequent power-on reset signal POR2B is indicated by a dashed line.

The preceding power-on reset signal POR1 is a signal output by inverting the inverted preceding power-on reset signal PORB from the inverter INV0, and is a signal obtained by inverting the internal power-on reset signal POR twice. Therefore, the signal waveform of the leading power-on reset signal POR1 is substantially the same as the signal waveform of the internal power-on reset signal POR shown in FIG. 3B. However, since the preceding power-on reset signal POR1 is output via the inverter INV2 of the first power-on reset circuit PRC1 and the inverter INV0 of the latch array circuit 100, the signal level changes from "H" level slightly after time t2. It transitions to "L" level.

The inverted late power-on reset signal POR2B is a signal obtained by delaying the inverted early power-on reset signal PORB by the delay circuit DLY. Therefore, the signal waveform of the inverted subsequent power-on reset signal POR2B shifts in parallel from the signal waveform of the inverted preceding power-on reset signal PORB shown in FIG. The waveform becomes In FIG. 4A, the delay amount by the delay circuit DLY is indicated as "Tdelay".

In this embodiment, the time t3 at which the inverted subsequent power-on reset signal POR2B rises from the "L" level to the "H" level is delayed so as to be the time after the internal power supply potential Vdd finishes rising and becomes saturated. It sets the amount Tdelay. Therefore, unlike the inverted preceding power-on reset signal PORB shown in FIG. 3B, the inverted subsequent power-on reset signal POR2B shown in FIG. 4A does not have a period during which it rises together with the internal power supply potential Vdd.

4B is a waveform diagram showing temporal changes of internal clock signals CK0, CK1, . . . , CKn, internal input data signals D0, D1, . is. Here, internal clock signals CK0, CK1, . . . , CKn are indicated by solid lines, internal input data signals D0, D1, . there is

The internal clock signals CK0, CK1, . . . , CKn are supplied to a pair of input terminals of the OR gate circuits OR0, OR1, . <1>, . Therefore, the internal clock signals CK0, CK1, . Become.

On the other hand, during the period after the preceding power-on reset signal POR1 transitions to "L" level (that is, the period on the right side of the drawing), the internal clock signals output from the OR gate circuits OR0, OR1, . CK0, CK1, . . . , CKn are at the same logic level as the external clock signals CKI<0>, CKI<1>, .

FIG. 4B shows signal waveforms assuming that external clock signals CKI<0>, CKI<1>, . . . , CKI<n> are all at the "L" level. In this case, the internal clock signals CK0, CK1, . . . , CKn have signal waveforms that uniformly transition to "L" level following the fall of the preceding power-on reset signal POR1.

The internal input data signals D0, D1, . . . , Dm are applied to a pair of input terminals of AND gate circuits AN0, AN1, . >, DI<1>, . . . , DI<m>. Therefore, during the period in which the potential of the inverted subsequent power-on reset signal POR2B is near the ground potential (that is, the period before time t3), the internal input data signals D0, D1, . be the level.

On the other hand, during the period after the inverted subsequent power-on reset signal POR2B transitions to the "H" level near time t3, the internal input data signals D0, which are the outputs of the AND gate circuits AN0, AN1, . The signal levels of D1, . . . , Dm are the same logic levels as the external input data signals DI<0>, DI<1>, .

FIG. 4B shows signal waveforms assuming that external input data signals DI<0>, DI<1>, . . . , DI<m> are all at "H" level. In this case, the internal input data signals D0, D1, . If an "L" level signal is included in the external input data signals DI<0>, DI<1>, . Since it is maintained at the L" level, it becomes a signal waveform that sticks to the vicinity of the ground potential and never rises.

Output signals Q00, Q01, . . . , Qmn correspond to output signals of latch circuits L00, L01, . Therefore, during the period in which the internal clock signals CK0, CK1, . It is reflected as an output value as it is. As described above, the internal input data signals D0, D1, . becomes "L" level.

On the other hand, in the period after the internal clock signals CK0, CK1, . , Dm transition to the "H" level, the output signals Q00, Q01, . Therefore, in this period, the output signals Q00, Q01, . . . , Qmn are uniformly at "L" level.

, CKn transition to "L" level and internal input data signals D0, D1, . At the same time, internal clock signals CK0, CK1, . . . , CKn and internal input data signals D0, D1, . level may occur. During that period, the "H" level of the internal input data signals D0, D1, . A malfunction may occur in which Qmn transitions to "H" level.

To prevent this, the inverted subsequent power-on reset signal POR2B must be reliably maintained at "L" level until the preceding power-on reset signal POR1 finishes transitioning to "L" level. The delay circuit DLY of this embodiment is provided for this purpose. That is, the delay circuit DLY delays the inverted preceding power-on reset signal PORB by a period corresponding to "Tdelay" in FIG. One of the signals supplied to the AND gate circuits AN0, AN1, . can be maintained.

With the above configuration, in the latch array circuit 100 of this embodiment, it is possible to initialize the output signals Q00, Q01, .

After time t3, the power-on operation of the first power-on reset circuit PRC1 shown in FIG. 2 is completed. The subsequent power-on reset signal POR2B is fixed at the "H" level. Therefore, the internal clock signals CK0, CK1, . . . , CKn always have values reflecting the external clock signals CKI<0>, CKI<1>, . In addition, the internal input data signals D0, D1, . .

Thus, during normal operation, values to be written to the latch array circuit 100 are input in advance as external input data signals DI<0>, DI<1>, . , CKI<1>, . It is possible to simultaneously write to the latch circuit group in the column corresponding to the "H" level external clock signal (that is, the latch circuit group receiving the internal clock signal corresponding to the external clock signal).

For example, by setting the external clock signals CKI<1>, . Data values input as <0>, DI<1>, . , are reflected in the output signals Q00, Q10, . . . , Qm0.

In this manner, the latch array circuit 100 of this embodiment can also realize the normal operation of a general latch array circuit. The reason why one of the external clock signals CKI<0>, . This is to provide a timing margin so that the period during which <0>, DI<1>, . . . , DI<m> must be controlled can be shortened.

As described above, according to the latch array circuit 100 of the present embodiment, it is possible to avoid a state in which the output signal becomes an undefined value in the period immediately after power-on and before the internal power-on reset signal POR rises. Become. This makes it possible to safely initialize the memory element when the power is turned on, even for applications where the output of an undefined value poses a particular problem.
For example, in the test mode, the internal power supply circuit in the IC chip is forcibly stopped, and a pseudo internal power supply potential is separately supplied from the outside. Thus, it is possible to safely initialize the memory element when the power is turned on, even for an internal circuit for which even an output of an indefinite value for a short period of time cannot be tolerated.

In the latch array circuit 100 of this embodiment, the initialization is not triggered by a signal transition like the clock input of the flip-flop, but the initialization is performed immediately by the input of the logic value like the input of the reset signal to the flip-flop with reset. can be made.

In addition, since the flip-flop with reset and the latch with reset occupy a relatively large area, the chip area tends to be large and the cost tends to be high, especially in applications where a large amount of stored data is handled. On the other hand, in the latch array circuit 100 of this embodiment, the reset function is not individually incorporated in each memory element as in these circuits, but as shown in FIG. AN1, . . . , ANm and OR gate circuits OR0, OR1, . In the latch array circuit 100 of this embodiment, as shown in FIG. 1, the latch circuits arranged in the row direction (horizontal direction in FIG. 1) have a common internal input data input signal. Further, the internal clock signal of each latch circuit arranged in the column direction (vertical direction in FIG. 1) is common. Therefore, since the number of signal wirings and the number of drivers for driving the signals can be reduced, the occupied area can be reduced.

In addition, the latch array circuit 100 of this embodiment has a configuration and operation that can be easily used together with a so-called "pulse latch technology" that operates a latch circuit using a pulse type clock, and occupies a smaller area than a flip-flop. It is possible to realize a timing margin close to the loop. Therefore, according to the latch array circuit 100 of this embodiment, it is possible to achieve both a reduction in the area occupied and a timing margin.

In addition, in the latch array circuit 100 of the present embodiment, even if the control of the test function for forcibly stopping the internal power supply circuit has a great influence on the entire internal circuit, it is built into the internal circuit. be able to. Therefore, in a general semiconductor integrated circuit in which the internal power supply potential is lower than the external power supply potential, such a circuit that is used only in the test mode can be configured with only low-voltage elements, thereby reducing the chip area. can contribute.

Next, Example 2 of the present invention will be described. FIG. 5 is a block diagram showing the configuration of the latch array circuit 200 of the second embodiment. The latch array circuit 200 of this embodiment differs from the latch array circuit 100 of the first embodiment in that it does not have the delay circuit DLY shown in FIG. Other configurations are common to the latch array circuit 100 of the first embodiment.

In this embodiment, the inverted subsequent power-on reset signal POR2B is supplied from outside the latch array circuit 200 and inside the IC chip. Specifically, in the IC chip of this embodiment, in addition to the first power-on reset circuit for generating the inverted preceding power-on reset signal PORB as shown in FIG. A second power-on reset circuit is provided for.

FIG. 6 is a circuit diagram showing the configuration of the second power-on reset circuit PRC2. The second power-on reset circuit PRC2 receives an internal power supply potential Vdd from an internal power supply circuit (not shown) provided inside the IC chip, and receives a subsequent power-on reset signal POR2 and an inverted subsequent power-on reset signal POR2B. to generate

In the second power-on reset circuit PRC2, the resistance element R1 of the first power-on reset circuit PRC1 shown in FIG. are replaced with the inverter INV4. Resistive element R2 has a resistance value greater than that of resistive element R1. Also, the capacitive element C2 has a larger capacitance value than the capacitive element C1.

According to such a configuration, the rise in the potential of the input potential VRC2 (that is, the input potential of the inverter INV3), which is the potential of the connection node between the resistance element R2 and the capacitive element C2, immediately after the power is turned on, corresponds to the input potential in FIG. It becomes slower than the rise of the potential of VRC.

As a result, the time at which the input potential VRC2 reaches the logic threshold VTH of the inverter INV3 (ie, the time corresponding to time t2 in FIG. 3A) is delayed, so that the rise of the output signal of the inverter INV4 is also delayed. In this embodiment, this output signal becomes the inverted subsequent power-on reset signal POR2B.

According to the second power-on reset circuit PRC2 of this embodiment, by setting the resistance value of the resistance element R2 and the capacitance value of the capacitance element C2 to appropriate values, the delay difference shown as "Tdelay" in FIG. A corresponding delay difference can be stably generated after the internal power supply potential Vdd rises to some extent.

The second power-on reset circuit PRC2 supplies the inverted subsequent power-on reset signal POR2B to the AND gate circuits AN0, AN1, . . . ANm of the latch array circuit 200 of FIG. The inverted preceding power-on reset signal PORB is supplied to the inverter INV0 of the latch array circuit 200 from the first power-on reset circuit PRC1 shown in FIG. The operation of each part of the latch array circuit 200 of this embodiment is the same as that of the parts other than the delay circuit DLY of the latch array circuit 100 of the first embodiment.

As described above, according to this embodiment, the delay circuit DLY can be omitted from the latch array circuit 200, so that the area can be further reduced as compared with the latch array circuit 100 of the first embodiment.

Further, in the case where a plurality of power-on reset circuits are originally used corresponding to a plurality of internal power supply potentials, the output thereof can be diverted to generate the inverted subsequent power-on reset signal POR2B. , the chip area can be reduced without the need to provide the delay circuit DLY.

Next, Example 3 of the present invention will be described. FIG. 7 is a block diagram showing the configuration of the latch array circuit 300 of the third embodiment. The latch array circuit 300 of the present embodiment has an OR gate circuit OR00 instead of the AND gate circuit AN0 shown in FIG. 1, and additionally has an inverter INV5 and its output signal POR2. different from

The inverter INV5 receives the inverted late power-on reset signal POR2B, which is the output signal of the delay circuit DLY, and inverts it to output the late power-on reset signal POR2.

An external input data signal DI<0> is input to one of the input terminals of the OR gate circuit OR00. The subsequent power-on reset signal POR2 is input to the other input terminal of the OR gate circuit OR00. OR gate circuit OR00 outputs a logical sum signal of external input data signal DI<0> and subsequent power-on reset signal POR2 as internal input data signal D0. The output internal input data signal D0 is input to each data input terminal D of the latch circuits L00, L01, .

The OR gate circuit OR00 constitutes an input data supply section 31 that supplies internal input data to the latch circuits L00 to Lmn together with the AND gate circuits AN1 to ANm.

Next, the operation of the latch array circuit 300 of this embodiment will be described. Since the subsequent power-on reset signal POR2 is a signal obtained by inverting the inverted subsequent power-on reset signal POR2B, the potential follows the internal power supply potential Vdd after time t0 (see FIG. 3A) when the internal power supply Vdd starts to rise. Rise. The subsequent power-on reset signal POR2 is inverted around time t3 (see FIG. 4A) at which the inverted subsequent power-on reset signal POR2B rises from the "L" level to the "H" level, and thereafter is fixed at the ground potential. .

The internal input data signal D0 corresponds to the output of an OR gate circuit OR00 whose one input is the subsequent power-on reset signal POR2. Therefore, the potential of the internal input data signal D0 rises following the internal power supply potential Vdd after time t0, and is maintained at the "H" level until time t3.

The latch circuits L00, L01, . It continues to capture the value of the internal input data signal D0 to be input. Therefore, of the output signals Q00, Q01, . . . , Qmn, only the output signals Q00, Q01, . Immediately reflecting the value of D0, it rises together with the internal power supply potential Vdd to attain "H" level.

Thus, according to the configuration of the latch array circuit 300 of this embodiment, the output signals Q00, Q01, . Early and relatively stable initialization to "H" level becomes possible.

The latch circuits whose output signals are initialized to "H" level are not limited to the latch circuits L00, L01, . . Further, the output signals of all the latch circuits L00 to Lmn may be uniformly initialized to "H" level.

It should be noted that the present invention is not limited to those shown in the above embodiments. For example, in the above embodiment, the latch circuits L00 to Lmn are arranged in a matrix of (m+1) rows×(n+1) columns. For example, fewer than (n+1) latch circuits may be arranged in some rows, and fewer than (m+1) latch circuits may be arranged in some columns.

Further, in the above-described embodiment, the input data supply section is composed of a plurality of AND gate circuits, and the inverted subsequent power-on reset signal POR2B and the external input data signals DI<0>, DI<1>, . . . , DI<m > is supplied as the internal input data signals D0 to Dm to the latch circuits L00 to Lmn. However, the circuit configuration is not limited to this. It is only necessary to supply the internal input data of "L" level to the latch circuit (excluding the latch circuit).

In the above embodiment, the external clock signals CKI<0>, CKI<1>, . . . , CKI<n> and the internal clock signals CK0, CK1, . , and the case where it is assumed to be used together with the so-called pulse latch technique has been described as an example. However, when it is easy to secure a timing margin during normal operation, for example, in applications where high-speed operation is not required, the clock signal need not be limited to a pulse form.

In the first and third embodiments, the delay circuit DLY is arranged inside the latch array circuit. You can

100, 200, 300 Latch array circuits 11, 31 Input data supply unit 12 Clock supply units L00 to Lmn Latch circuits AN0 to ANm AND gate circuits OR0 to ORn OR gate circuits INV0 to INV5 Inverter DLY Delay circuit PRC1 First power-on reset circuit R1, R2 Resistance elements C1, C2 Capacitance element PRC2 Second power-on reset circuit OR00 OR gate circuit

Claims (9)

a plurality of latch circuits arranged in a matrix;
Based on a first timing signal that transitions at a first timing synchronized with the rise of a power-on reset signal, each clock input of each row or column of the plurality of latch circuits is controlled until the first timing. a clock controller that fixes a logic value;
a data supply unit that fixes each data input to a predetermined value for each row or column of the plurality of latch circuits based on a second timing signal that transitions at a second timing that is later than the first timing;
has
The clock control unit is provided for each row or column of the plurality of latch circuits, and receives an external clock signal and the first timing signal as inputs, and calculates a logical sum of the external clock signal and the first timing signal. including a first logic gate circuit group consisting of a plurality of OR circuits that output,
Based on the outputs of the plurality of OR circuits, clock inputs to the plurality of latch circuits are controlled row by row or column by column based on the first timing signal until the first timing; After the timing of (1), the clock input to the plurality of latch circuits is controlled row by row or column by column based on the external clock signal. 2. The latch array circuit according to claim 1, wherein each of said plurality of latch circuits is a latch circuit having no reset terminal . 2. The latch array circuit according to claim 1, wherein said second timing signal is a signal obtained by delaying a signal based on said power-on reset signal. 4. The latch array circuit according to claim 3, wherein the delay time of said second timing signal is longer than the hold time of each of said plurality of latch circuits. The data supply unit is provided for each row or column of the plurality of latch circuits, each of which receives external data and the second timing signal and outputs a logical product of the external data and the second timing signal. including a second logic gate circuit group consisting of a plurality of AND circuits that
Based on the outputs of the plurality of AND circuits, data input to the plurality of latch circuits is controlled row by row or column by column based on the second timing signal until the second timing; 5. The latch array circuit according to any one of claims 1 to 4 , wherein data input to said plurality of latch circuits is controlled row by row or column by column based on said external data after the timing of . The second logic gate, wherein the data supply unit fixes data input of at least one row or column of the plurality of latch circuits to a value different from the predetermined value until the second timing. 6. The latch array circuit of claim 5 , comprising at least one logic gate circuit different from the logic gate circuits of the circuit group. 7. The clock controller according to any one of claims 1 to 6 , wherein the clock controller supplies a pulse-shaped clock signal as a clock input to the plurality of latch circuits in a period after the first timing. Latch array circuit. a latch array circuit according to any one of claims 1 to 7 ;
an internal power supply circuit that generates an internal power supply voltage based on the external power supply voltage;
including
A semiconductor integrated circuit, wherein at least one of the outputs of the plurality of latch circuits of the latch array circuit is a signal used to control a test mode function for forcibly stopping the operation of the internal power supply circuit. a latch array circuit according to any one of claims 1 to 7 ;
a plurality of power-on reset circuits that generate a plurality of power-on reset signals that transition at different timings;
including
The semiconductor integrated circuit according to claim 1, wherein the clock control section and the data supply section of the latch array circuit use the plurality of power-on reset signals as the first timing signal and the second timing signal.

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