JP7294083B2 - Semiconductor device and its manufacturing method - Google Patents

Description

The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the same.

A semiconductor substrate of a semiconductor device is divided into a cell region in which a switching structure is formed and a termination region provided around the cell region and in which a termination breakdown voltage structure is formed. A guard ring structure or a RESURF structure is exemplified as the termination withstand voltage structure. In this type of semiconductor device, it is desired to improve the breakdown voltage by alleviating the electric field at the periphery of the cell region. For this reason, as disclosed in Patent Document 1, in this type of semiconductor device, between the p-type body region of the cell region and the termination breakdown voltage structure of the termination region, the depth from the top surface of the semiconductor substrate is greater than the body region. A technique for forming a deep p-type deep p region has been developed.

JP 2014-49695 A

By the way, in order to realize a semiconductor device with a high withstand voltage, research is being conducted to adopt silicon carbide as a material for a semiconductor substrate. In general, such a semiconductor substrate employing silicon carbide is often formed by preparing a base substrate of silicon carbide and epitaxially growing an epitaxial layer of silicon carbide on the base substrate. As is well known, an epitaxial layer of silicon carbide has threading dislocations inherited from a base substrate and extended. According to studies by the present inventors, it has been found that the following problems occur when such threading dislocations are formed so as to penetrate the forming range of the deep p region.

The deep p region is formed by activating ion-implanted p-type impurities by annealing. In order to form the deep p-region deeply, boron, which is a p-type impurity with large thermal diffusion, is used as the p-type impurity for forming the deep p region.

It is known that the thermal diffusion of boron, which is a p-type impurity, is proportional to the carbon vacancy density. That is, when the carbon vacancy density is high, boron can diffuse thermally widely. A portion where threading dislocations exist has a high carbon vacancy density. Therefore, if threading dislocations are formed to penetrate the formation range of the deep p region, boron diffuses at an accelerated rate along the threading dislocations during the annealing process, and a part of the lower surface of the deep p region protrudes. It is formed like this. Such a projecting portion on the lower surface of the deep p region concentrates an electric field, generates a leakage current, and causes a decrease in breakdown voltage. Therefore, the present specification provides a technique for suppressing the formation of protrusions on part of the bottom surface of the deep p region.

A semiconductor device disclosed in this specification can include a silicon carbide semiconductor substrate, an upper electrode arranged on the upper surface of the semiconductor substrate, and a lower electrode arranged on the lower surface of the semiconductor substrate. Thus, the semiconductor device disclosed in this specification is a vertical semiconductor device. The type of semiconductor device is not particularly limited, and examples include MOSFET and IGBT. The semiconductor substrate is divided into a cell region in which a switching structure is formed and a termination region provided around the cell region and in which a termination breakdown voltage structure is formed. The semiconductor substrate includes: an n-type drift region provided across the cell region and the termination region; a p-type body region provided on the drift region of the cell region; a p-type deep p region provided on the drift region between the body region and the termination breakdown voltage structure of the termination region and having a depth from the upper surface of the semiconductor substrate deeper than that of the body region; A diffusion suppressing region, which is provided in contact with the lower surface of the deep p region and spreads in the plane direction to suppress diffusion of the p-type impurity, can be provided. A p-type impurity contained in the deep p-region is boron. The diffusion suppression region has a lower carbon vacancy density than the surrounding semiconductor region. In this semiconductor device, a diffusion suppression region having a low carbon vacancy density is provided so as to be in contact with the lower surface of the deep p region. Therefore, in this semiconductor device, formation of a protruding portion on a part of the lower surface of the deep p region is suppressed.

In the above semiconductor device, the diffusion suppression region may have a higher carbon concentration than the surrounding semiconductor region. A high carbon concentration means a low carbon vacancy density. Therefore, in this semiconductor device, formation of a protruding portion on a part of the lower surface of the deep p region is suppressed.

The present specification can provide a method for manufacturing the above semiconductor device. This manufacturing method comprises the steps of: forming the diffusion suppressing region at a position in contact with the lower surface of the formation range of the deep p region of the semiconductor substrate; and introducing a p-type impurity into the formation range of the deep p region of the semiconductor substrate. and activating the p-type impurity by annealing to form the deep p-region. Thus, in this manufacturing method, the diffusion suppressing region is formed prior to annealing the deep p region. Therefore, in this manufacturing method, it is possible to suppress the formation of a protrusion on a part of the lower surface of the deep p region.

The step of forming the diffusion suppressing region of the manufacturing method includes forming a mask on the upper surface of the semiconductor substrate and implanting carbon ions through an opening in the mask to form the diffusion suppressing region. may have. Thus, in this manufacturing method, carbon ions can be implanted prior to the annealing treatment of the deep p region to reduce the carbon vacancy density and form the diffusion suppressing region. Further, in this case, the step of introducing the p-type impurity may include the step of ion-implanting the p-type impurity from the opening of the mask formed in the step of forming the diffusion suppressing region. . According to this manufacturing method, the mask for forming the diffusion suppressing region and the deep p region can be used in common. The order of the step of ion-implanting carbon to form the diffusion suppressing region and the step of ion-implanting p-type impurities to form the deep p-region is not particularly limited.

The step of forming the diffusion suppression region in the above manufacturing method includes epitaxially growing a lower portion of the drift region, and ion-implanting carbon into a portion of the upper surface of the lower portion of the drift region to form the diffusion suppression region. and epitaxially growing an upper portion of the drift region. Thus, in this manufacturing method, by forming the diffusion suppressing region when the drift region is epitaxially grown, the diffusion suppressing region can be formed prior to the annealing treatment of the deep p region. . Therefore, in this manufacturing method, it is possible to suppress the formation of a protrusion on a part of the lower surface of the deep p region.

1 schematically shows a plan view of a semiconductor device; FIG. FIG. 2 is a cross-sectional view of a main part of the semiconductor device, schematically showing a cross-sectional view corresponding to line II-II of FIG. 1 ; FIG. 4 schematically shows cross-sectional views of essential parts in the process of manufacturing a semiconductor device. FIG. 4 schematically shows cross-sectional views of essential parts in the process of manufacturing a semiconductor device. FIG. 4 schematically shows cross-sectional views of essential parts in the process of manufacturing a semiconductor device. FIG. 4 schematically shows cross-sectional views of essential parts in the process of manufacturing a semiconductor device. FIG. 4 schematically shows cross-sectional views of essential parts in the process of manufacturing a semiconductor device. FIG. 4 schematically shows cross-sectional views of essential parts in the process of manufacturing a semiconductor device. FIG. 4 schematically shows cross-sectional views of essential parts in the process of manufacturing a semiconductor device of a comparative example. FIG. 4 schematically shows cross-sectional views of essential parts in the process of manufacturing a semiconductor device. FIG. 4 schematically shows cross-sectional views of essential parts in the process of manufacturing a semiconductor device. FIG. 4 schematically shows cross-sectional views of essential parts in the process of manufacturing a semiconductor device. FIG. 4 schematically shows cross-sectional views of essential parts in the process of manufacturing a semiconductor device. FIG. 4 schematically shows cross-sectional views of essential parts in the process of manufacturing a semiconductor device. FIG. 4 schematically shows cross-sectional views of essential parts in the process of manufacturing a semiconductor device.

As shown in FIGS. 1 and 2, the semiconductor device 1 is a type of power semiconductor device called a MOSFET, and is configured using a semiconductor substrate 10. As shown in FIG. Silicon carbide is adopted as the material of semiconductor substrate 10 .

As shown in FIG. 1, two source electrodes 32 and a plurality of signal electrodes 36 are provided on the upper surface 10a of the semiconductor substrate 10. As shown in FIG. The source electrode 32 is arranged near the central portion of the upper surface 10 a of the semiconductor substrate 10 . As shown in FIG. 2, the source electrode 32 is in contact with the upper surface 10a of the semiconductor substrate 10. As shown in FIG. Around the contact area 32a between the source electrode 32 and the semiconductor substrate 10, the upper surface 10a of the semiconductor substrate 10 is covered with an insulating film 50 or the like. A semiconductor region overlapping with the contact area 32a when the semiconductor substrate 10 is viewed from above is called a cell region 100A. A switching structure is formed in the cell region 100A as will be described later. A semiconductor region around the cell region 100A is called a termination region 100B. A termination breakdown voltage structure is formed in the termination region 100B, as will be described later.

A drain electrode 34 is arranged on the lower surface 10 b of the semiconductor substrate 10 . The drain electrode 34 is in contact with the entire lower surface 10b of the semiconductor substrate 10 across the cell region 100A and the termination region 100B.

A plurality of trenches are formed in the upper surface 10a of the semiconductor substrate 10 in the cell region 100A. The inner surface of each trench is covered with a gate insulating film 42 . A gate electrode 44 is arranged in each trench. The gate electrode 44 is insulated from the semiconductor substrate 10 by the gate insulating film 42 . An upper surface of the gate electrode 44 is covered with an interlayer insulating film 46 . The interlayer insulating film 46 is covered with the source electrode 32 . An interlayer insulating film 46 insulates the gate electrode 44 from the source electrode 32 .

A drain region 11 , a drift region 12 , a body region 13 , a source region 14 , a deep p region 15 , a RESURF region 16 and a termination contact region 17 are formed in the semiconductor substrate 10 .

The drain region 11 is an n-type layer containing a high concentration of n-type impurities. The drain region 11 is provided across the cell region 100A and the termination region 100B, and is provided at a position exposed to the lower surface 10b of the semiconductor substrate 10. As shown in FIG. The drain region 11 is in ohmic contact with the drain electrode 34 over the entire lower surface 10b. The drain region 11 is also a base substrate for epitaxially growing the drift region 12 .

The drift region 12 is an n-type layer having a lower n-type impurity concentration than the drain region 11 . The drift region 12 is provided across the cell region 100A and the termination region 100B.

Body region 13 is a p-type layer. Body region 13 is arranged in cell region 100</b>A, is arranged above drift region 12 , and is in contact with drift region 12 . The body region 13 has a body contact region 13a and a low concentration body region 13b.

Body contact region 13a is a p-type layer containing a high concentration of p-type impurities. Body contact region 13 a is provided at a position exposed on upper surface 10 a of semiconductor substrate 10 . Body contact region 13 a is in ohmic contact with source electrode 32 .

The low-concentration body region 13b is a p-type layer having a p-type impurity concentration lower than that of the body contact region 13a. Low-concentration body region 13 b is arranged between body contact region 13 a and drift region 12 .

Source region 14 is an n-type layer containing a high concentration of n-type impurities. The source region 14 is arranged in the cell region 100A, is arranged on the side of the body contact region 13a, and is provided at a position exposed on the upper surface 10a of the semiconductor substrate 10. As shown in FIG. Source region 14 is in ohmic contact with source electrode 32 . Source region 14 is insulated from drift region 12 by body region 13 .

The source region 14 is in contact with the gate insulating film 42 at the upper end of the trench. The low-concentration body region 13 b is in contact with the gate insulating film 42 below the source region 14 . Drift region 12 is in contact with gate insulating film 42 below low-concentration body region 13b.

In this manner, the switching structure is formed in the cell region 100A by the drain region 11, the drift region 12, the body region 13, the source region 14, the gate electrode 44, and the like.

A deep p region 15 , a resurf region 16 and a termination contact region 17 are provided in the termination region 100</b>B of the semiconductor substrate 10 .

Deep p region 15 is a p-type layer, is arranged above drift region 12 , is provided between body region 13 and RESURF region 16 , and is provided at a position exposed to upper surface 10 a of semiconductor substrate 10 . It is The deep p region 15 is arranged adjacent to the outer peripheral side surface of the body region 13 so as to make a circuit around the cell region 100A. The deep p region 15 extends from the upper surface 10 a of the semiconductor substrate 10 to a position deeper than the body region 13 , more specifically, a position deeper than the trench filled with the gate insulating film 42 and the gate electrode 44 .

The RESURF region 16 is a p-type layer having a p-type impurity concentration lower than that of the deep p region 15 , is arranged above the drift region 12 , and is provided at a position exposed to the upper surface 10 a of the semiconductor substrate 10 . The resurf region 16 is also arranged adjacent to the outer peripheral side surface of the deep p region 15 so as to make a circuit around the cell region 100A. The RESURF region 16 is arranged in a shallower range than the deep p region 15 . The RESURF region 16 is an example of a termination breakdown voltage structure. Instead of the RESURF region 16, a guard ring structure may be provided as the termination breakdown voltage structure.

Termination contact region 17 is an n-type layer containing a high concentration of n-type impurities, is provided above drift region 12 , and is provided at a position exposed to upper surface 10 a of semiconductor substrate 10 . The termination contact region 17 is arranged so as to circle around the periphery of the semiconductor substrate 10 . The termination contact region 17 is fixed at the same potential as the drain electrode 34 .

A diffusion suppression region 60 is further provided in the termination region 100B of the semiconductor substrate 10 . Diffusion suppression region 60 is provided in contact with the lower surface of deep p region 15 and spreads in the planar direction. The diffusion suppression region 60 is a region with a lower carbon vacancy density than the surrounding semiconductor region.

As will be described later in the manufacturing method, the provision of such a diffusion suppressing region 60 suppresses formation of a protruding portion on a part of the lower surface of the deep p region 15 . If such a projecting portion were to be formed on the bottom surface of the deep p region 15, it would concentrate the electric field, generate a leak current, and cause a decrease in breakdown voltage. Therefore, since the semiconductor device 1 is provided with the diffusion suppressing region 60, formation of a protruding portion in a part of the lower surface of the deep p region 15 is suppressed, and the semiconductor device 1 can have high breakdown voltage characteristics. .

Next, operation of the semiconductor device 1 will be described. When a potential higher than the threshold is applied to the gate electrode 44 , a channel is formed in the body region 13 adjacent to the gate insulating film 42 . When the potential of the drain electrode 34 becomes higher than that of the source electrode 32 while the channel is formed, the semiconductor device 1 is turned on and current flows between the source electrode 32 and the drain electrode 34 . When the voltage applied to the gate electrode 44 is lowered below the threshold, the channel disappears, the semiconductor device 1 is turned off, and the current flowing between the source electrode 32 and the drain electrode 34 is cut off. Thus, the semiconductor device 1 can operate as a switching element that controls the current flowing between the source electrode 32 and the drain electrode 34 .

Next, a method of forming the deep p region 15 in the method of manufacturing the semiconductor device 1 will be described. A method for forming other semiconductor regions is omitted.

(First manufacturing method)
First, as shown in FIG. 3, a drain region 11, which is a base substrate of silicon carbide, is prepared. As shown, this drain region 11 has threading dislocations TD.

Next, as shown in FIG. 4, the drift region 12 is crystal-grown from the upper surface of the drain region 11 using an epitaxial growth technique. Thereby, the semiconductor substrate 10 in which the drain region 11 and the drift region 12 are laminated is prepared. As shown, the drift region 12 has threading dislocations TD inherited from the drain region 11 of the base substrate and extended.

Next, as shown in FIG. 5, a mask 72 is formed on the upper surface 10a of the semiconductor substrate 10. Next, as shown in FIG. The mask 72 has an opening 72a corresponding to the formation range 15a of the deep p region.

Next, as shown in FIG. 6, using an ion implantation technique, carbon ions are implanted into the semiconductor substrate 10 through the openings 72a of the mask 72 to form diffusion suppressing regions 60. Next, as shown in FIG. The diffusion suppressing region 60 is formed at a position in contact with the lower surface of the deep p region formation range 15 a of the semiconductor substrate 10 . Carbon introduced by ion implantation has a concentration profile with a peak in the thickness direction of the semiconductor substrate 10 . This peak concentration of carbon is adjusted to a concentration at which defects are not generated by ion implantation of carbon.

The diffusion suppression region 60 is formed as a region with a higher carbon concentration than the surrounding semiconductor region. A threading dislocation TD is a region with a high carbon vacancy density. When the diffusion suppression region 60 is formed for such threading dislocations TD, the introduced carbon can fill the carbon vacancies. Therefore, the carbon vacancy density is reduced in the threading dislocation TD where the diffusion suppression region 60 overlaps.

Next, as shown in FIG. 7, using an ion implantation technique, boron ions are implanted as p-type impurities into the semiconductor substrate 10 through the openings 72a of the mask 72. Next, as shown in FIG. After implanting boron ions, the mask 72 is removed. Boron is introduced in multiple steps into the formation range 15a of the deep p region. In this way, carbon ion implantation for forming diffusion suppressing region 60 and boron ion implantation for forming deep p region 15 can be performed using common mask 72 . The order of the step of implanting carbon ions to form the diffusion suppressing region 60 and the step of implanting boron ions to form the deep p region 15 is not particularly limited. For example, carbon ions may be implanted to form the diffusion suppressing region 60 after boron ions are implanted to form the deep p region 15 .

Next, as shown in FIG. 8, after forming a carbon cap layer 74 on the upper surface 10a of the semiconductor substrate 10, the boron is activated by annealing to form the deep p region 15. Next, as shown in FIG. By this annealing treatment, the introduced boron thermally diffuses toward the deep part of the semiconductor substrate 10 . At this time, since the diffusion suppression region 60 is provided, the thermal diffusion of boron toward the deep portion is suppressed by the diffusion suppression region 60 .

Here, FIG. 9 shows a comparative example in which the diffusion suppressing region 60 is not formed. Thermal diffusion of boron is known to be proportional to carbon vacancy density. A portion where threading dislocations TD exist has a high carbon vacancy density. Therefore, if the threading dislocation TD is formed to penetrate the formation range of the deep p region, boron diffuses at an accelerated rate along the threading dislocation TD during the annealing treatment, and the lower surface of the deep p region 15 is partially exposed. is formed to protrude. The projecting portion 15b on the lower surface of the deep p region 15 concentrates an electric field, generates a leakage current, and causes a decrease in breakdown voltage. On the other hand, as shown in FIG. 8, in the manufacturing method of the present embodiment, since the diffusion suppressing region 60 is formed prior to the annealing treatment of the deep p region 15, the protruding portion is partially formed on the lower surface of the deep p region 15. 15b is suppressed.

(Second manufacturing method)
First, as shown in FIG. 3, a drain region 11, which is a base substrate of silicon carbide, is prepared. As shown, this drain region 11 has threading dislocations TD.

Next, as shown in FIG. 10, an epitaxial growth technique is used to crystal-grow the lower portion 12A of the drift region 12 from the surface of the drain region 11. Next, as shown in FIG. As shown, the lower portion 12A of the drift region 12 has threading dislocations TD inherited from the drain region 11 of the base substrate and extended.

Next, as shown in FIG. 11, a mask 76 is formed on the upper surface of the lower portion 12A of the drift region 12. As shown in FIG. The mask 76 is formed with an opening 76a corresponding to the forming range 60a of the diffusion suppressing region.

Next, as shown in FIG. 12, using an ion implantation technique, carbon ions are implanted into the semiconductor substrate 10 through the openings 76a of the mask 76 to form the diffusion suppressing regions 60. Next, as shown in FIG. After the carbon ion implantation, mask 76 is removed.

Next, as shown in FIG. 13, the drift region 12 is formed by crystal-growing the upper portion 12B of the drift region 12 from the upper surface of the lower portion 12A of the drift region 12 using an epitaxial growth technique. Thereby, the semiconductor substrate 10 in which the drain region 11 and the drift region 12 are laminated is prepared.

Next, as shown in FIG. 14, a mask 78 is formed on the upper surface 10a of the semiconductor substrate 10. Next, as shown in FIG. The mask 78 has an opening 78a corresponding to the formation range 15a of the deep p region.

Next, as shown in FIG. 15, using an ion implantation technique, boron ions are implanted as p-type impurities into the semiconductor substrate 10 through the openings 78a of the mask 78. Next, as shown in FIG. After implanting boron ions, the mask 78 is removed. Boron is introduced in multiple steps into the formation range 15a of the deep p region.

The subsequent steps are the same as the steps shown in FIG. Also in this manufacturing method, the diffusion suppressing region 60 is formed prior to the annealing treatment of the deep p region 15, so formation of the projecting portion 15b on a part of the lower surface of the deep p region 15 is suppressed.

Although the embodiments have been described in detail above, they are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or in the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

Reference Signs List 1: semiconductor device 10 : semiconductor substrate 11 : drain region 12 : drift region 13 : body region 13a : body contact region 13b : low concentration body region 14 : source region 15 : deep p region 16 : resurf region 17 : termination contact region 32 : source electrode 34 : drain electrode 42 : gate insulating film 44 : gate electrode 46 : interlayer insulating film 50 : insulating film 60 : diffusion suppression region 100A : cell region 100B : termination region

Claims (7)

A semiconductor device,
a silicon carbide semiconductor substrate;
an upper electrode provided on the upper surface of the semiconductor substrate;
a lower electrode provided on the lower surface of the semiconductor substrate, wherein the semiconductor substrate includes a cell region in which a switching structure is formed, and a termination breakdown structure formed around the cell region. and a termination region defined by
The semiconductor substrate is
an n-type drift region provided across the cell region and the termination region;
a p-type body region provided on the drift region of the cell region;
A p-type deep p provided on the drift region between the body region of the cell region and the termination breakdown voltage structure of the termination region and having a depth from the upper surface of the semiconductor substrate deeper than that of the body region. area and
a diffusion suppression region provided in contact with the lower surface of the deep p region and extending in a planar direction to suppress diffusion of the p-type impurity,
the p-type impurity contained in the deep p region is boron;
the diffusion suppression region has a lower carbon vacancy density than the surrounding semiconductor region;
The semiconductor device , wherein a carbon concentration peak of the diffusion suppressing region in the thickness direction of the semiconductor substrate is located below a lower surface of the deep p region. 2. The semiconductor device according to claim 1, wherein said diffusion suppression region has a higher carbon concentration than the surrounding semiconductor region. A method for manufacturing a semiconductor device according to claim 1 or 2,
forming the diffusion suppressing region at a position in contact with the lower surface of the formation range of the deep p region of the semiconductor substrate;
introducing a p-type impurity into a formation range of the deep p region of the semiconductor substrate;
and activating the p-type impurity by annealing to form the deep p-region. The step of forming the diffusion suppression region includes:
forming a mask on the top surface of the semiconductor substrate;
4. The method of manufacturing a semiconductor device according to claim 3, further comprising implanting carbon ions through the opening of the mask to form the diffusion suppressing region. The step of introducing the p-type impurity includes
5. The method of manufacturing a semiconductor device according to claim 4, further comprising the step of ion-implanting a p-type impurity through said opening of said mask formed in said step of forming said diffusion suppressing region. The step of forming the diffusion suppression region includes:
epitaxially growing a lower portion of the drift region;
ion implanting carbon into a portion of the upper surface of the lower portion of the drift region to form the diffusion suppression region;
4. The method of manufacturing a semiconductor device according to claim 3, further comprising the step of epitaxially growing an upper portion of said drift region. a silicon carbide semiconductor substrate;
an upper electrode provided on the upper surface of the semiconductor substrate;
a lower electrode provided on the lower surface of the semiconductor substrate;
the semiconductor substrate is divided into a cell region in which a switching structure is formed and a termination region provided around the cell region and in which a termination breakdown voltage structure is formed;
The semiconductor substrate is
an n-type drift region provided across the cell region and the termination region;
a p-type body region provided on the drift region of the cell region;
A p-type deep p provided on the drift region between the body region of the cell region and the termination breakdown voltage structure of the termination region and having a depth from the upper surface of the semiconductor substrate deeper than that of the body region. area and
a diffusion suppression region provided in contact with the lower surface of the deep p region and extending in a planar direction to suppress diffusion of the p-type impurity,
the p-type impurity contained in the deep p region is boron;
A method for manufacturing a semiconductor device, wherein the diffusion suppression region has a lower carbon vacancy density than the surrounding semiconductor region,
forming the diffusion suppressing region at a position in contact with the lower surface of the formation range of the deep p region of the semiconductor substrate;
introducing a p-type impurity into a formation range of the deep p region of the semiconductor substrate;
activating the p-type impurity by annealing to form the deep p-region;
The step of forming the diffusion suppression region includes:
epitaxially growing a lower portion of the drift region;
ion implanting carbon into a portion of the upper surface of the lower portion of the drift region to form the diffusion suppression region;
and a step of epitaxially growing an upper portion of the drift region.

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