JP7296002B2 - Semiconductor light emitting device and method for manufacturing semiconductor light emitting device - Google Patents

Description

The present invention relates to a semiconductor light emitting device and a method for manufacturing a semiconductor light emitting device.

A light-emitting device for deep ultraviolet light has an aluminum gallium nitride (AlGaN)-based n-type clad layer, an active layer, and a p-type clad layer that are sequentially stacked on a substrate. An n-side electrode having a laminated structure of Ti/Al/Ti/Au, for example, is formed on the n-type clad layer. It is known that the contact resistance between the n-type clad layer and the n-side electrode increases as the AlN mole fraction of the n-type clad layer increases, making good ohmic contact more difficult. In order to reduce the contact resistance of the n-side electrode, annealing treatment at 700° C. or higher is required (see, for example, Patent Document 1).

Japanese Patent No. 5594530

If the n-side electrode is annealed at a temperature exceeding the melting point of aluminum (Al) (approximately 660° C.), the flatness of the annealed n-side electrode may be degraded, and the ultraviolet light reflectance of the n-side electrode may be degraded.

The present invention has been made in view of these problems, and one of its exemplary purposes is to improve the reliability and output characteristics of semiconductor light emitting devices.

A semiconductor light emitting device according to one aspect of the present invention includes an n-type semiconductor layer made of an n-type aluminum gallium nitride (AlGaN) based semiconductor material, an n-side electrode provided in a partial region on the n-type semiconductor layer, and an n-type semiconductor layer. and an active layer of an AlGaN-based semiconductor material provided in a region different from the upper partial region. The n-side electrode includes a first layer containing titanium (Ti) on the n-type semiconductor layer, a second layer containing aluminum (Al) on the first layer, and titanium nitride (TiN) on the second layer. and a third layer.

According to this aspect, by covering the second layer containing Al with the third layer containing TiN, it is possible to prevent oxidation and corrosion of the Al surface in the annealing process and the lithography process. This makes it possible to provide an n-side electrode with excellent flatness and reflectance, and improve the reliability and output characteristics of the semiconductor light emitting device.

The arithmetic mean roughness (Ra) of the upper surface of the n-side electrode may be 5 nm or less.

The third layer may include a TiN layer with a thickness of 10 nm or more.

The thickness of the first layer may be 5 nm or less, and the thickness of the second layer may be 300 nm or more.

The third layer may include a Ti layer on the second layer and a TiN layer on the Ti layer.

The TiN layer may be formed by subjecting the surface of the Ti layer to ammonia (NH ₃ ) gas plasma treatment.

The n-type semiconductor layer may have a molar fraction of aluminum nitride (AlN) of 20% or more, and the active layer may be configured to emit ultraviolet light with a wavelength of 350 nm or less.

Another aspect of the invention is a method for manufacturing a semiconductor light emitting device. This method includes the steps of forming an active layer of an AlGaN-based semiconductor material on an n-type semiconductor layer of an n-type aluminum gallium nitride (AlGaN)-based semiconductor material; a first layer containing titanium (Ti), a second layer containing aluminum (Al) and titanium (Ti) on a partial region of the n-type semiconductor layer. _A step of sequentially forming a third layer containing a Annealing the three layers at a temperature of 500° C. or more and 650° C. or less to form an n-side electrode.

According to this aspect, by covering the second layer containing Al with the TiN layer, it is possible to prevent oxidation and corrosion of the Al surface in the annealing process and the lithography process. A TiN layer having excellent flatness can be formed by forming the TiN layer by ammonia gas plasma treatment. This makes it possible to provide an n-side electrode with excellent flatness and reflectance, and improve the reliability and output characteristics of the semiconductor light emitting device.

The step of forming the TiN layer on the surface of the third layer may be done at a temperature below 300°C.

forming a protective metal layer on the TiN layer of the n-side electrode; forming a protective insulating layer covering the n-type semiconductor layer and the protective metal layer; and part of the protective insulating layer on the n-side electrode. and forming a pad electrode on the protective metal layer exposed by partially removing the protective insulating layer.

According to the present invention, reliability and output characteristics of a semiconductor light emitting device can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing which shows roughly the structure of the semiconductor light-emitting device which concerns on embodiment. 4 is a graph showing the relationship between the thickness of a Ti layer and the reflectance of ultraviolet light. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. FIG. 10 is a cross-sectional view schematically showing the configuration of a semiconductor light emitting device according to a modification; FIG. 10 is a cross-sectional view schematically showing the configuration of a semiconductor light emitting device according to another modified example;

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the description, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted as appropriate. Also, in order to facilitate understanding of the explanation, the dimensional ratio of each component in each drawing does not necessarily match the dimensional ratio of the actual light emitting element.

FIG. 1 is a cross-sectional view schematically showing the configuration of a semiconductor light emitting device 10 according to an embodiment. The semiconductor light emitting element 10 is an LED (Light Emitting Diode) chip configured to emit "deep ultraviolet light" with a center wavelength λ of approximately 360 nm or less. In order to output deep ultraviolet light with such a wavelength, the semiconductor light emitting device 10 is made of an aluminum gallium nitride (AlGaN) based semiconductor material with a bandgap of about 3.4 eV or more. In this embodiment, a case of emitting deep ultraviolet light having a center wavelength λ of approximately 240 nm to 350 nm will be described.

As used herein, "AlGaN-based semiconductor material" refers to a semiconductor material containing at least aluminum nitride (AlN) and gallium nitride (GaN), and a semiconductor material containing other materials such as indium nitride (InN). shall include Therefore, the “AlGaN-based semiconductor material” referred to in this specification is, for example, a composition of In _1-xy Al _x Ga _y N (0≦x+y<1, 0<x<1, 0<y<1). and includes aluminum gallium nitride (AlGaN) or indium aluminum gallium nitride (InAlGaN). The "AlGaN-based semiconductor material" of the present specification is, for example, AlN and GaN each having a molar fraction of 1% or more, preferably 5% or more, 10% or more, or 20% or more.

In order to distinguish materials that do not contain AlN, they are sometimes referred to as "GaN-based semiconductor materials". "GaN-based semiconductor material" includes GaN and InGaN. Similarly, the term "AlN-based semiconductor material" may be used to distinguish materials that do not contain GaN. The "AlN-based semiconductor material" includes AlN and InAlN.

The semiconductor light emitting device 10 includes a substrate 20, a buffer layer 22, an n-type cladding layer 24, an active layer 26, an electron blocking layer 28, a p-type cladding layer 30, an n-side electrode 32, and a p-side electrode 42. , an n-side protective metal layer 39 , a p-side protective metal layer 49 , a protective insulating layer 50 , an n-side pad electrode 56 and a p-side pad electrode 58 .

_The substrate 20 is a substrate having translucency to deep ultraviolet light emitted by the semiconductor light emitting device 10, and is, for example, a sapphire ( _Al2O3 ) substrate. The substrate 20 has a first major surface 20a and a second major surface 20b opposite the first major surface 20a. The first main surface 20a is one main surface that serves as a crystal growth surface for growing each layer above the buffer layer 22 . The second main surface 20b is one main surface that serves as a light extraction surface for extracting deep ultraviolet light emitted from the active layer 26 to the outside. Alternatively, the substrate 20 may be an aluminum nitride (AlN) substrate or an aluminum gallium nitride (AlGaN) substrate.

A buffer layer 22 is formed on the first main surface 20 a of the substrate 20 . The buffer layer 22 is a base layer (template layer) for forming each layer above the n-type cladding layer 24 . The buffer layer 22 is, for example, an undoped AlN layer, and more specifically, an AlN (HT-AlN; High Temperature AlN) layer grown at a high temperature. The buffer layer 22 may include an undoped AlGaN layer formed on the AlN layer. In a modification, if the substrate 20 is an AlN substrate or an AlGaN substrate, the buffer layer 22 may be composed of only an undoped AlGaN layer. That is, the buffer layer 22 includes at least one of an undoped AlN layer and an AlGaN layer.

The n-type cladding layer 24 is an n-type semiconductor layer formed on the buffer layer 22 . The n-type cladding layer 24 is an n-type AlGaN-based semiconductor material layer, for example, an AlGaN layer doped with silicon (Si) as an n-type impurity. The composition ratio of the n-type cladding layer 24 is selected so as to transmit the deep ultraviolet light emitted by the active layer 26. For example, the molar fraction of AlN is 25% or more, preferably 40% or more or 50% or more. is formed as The n-type cladding layer 24 has a bandgap greater than the wavelength of deep ultraviolet light emitted from the active layer 26, and is formed to have a bandgap of 4.3 eV or more, for example. The n-type cladding layer 24 is preferably formed so that the molar fraction of AlN is 80% or less, that is, the band gap is 5.5 eV or less, and the molar fraction of AlN is 70% or less (that is, the band gap is 5.5 eV or less). It is more desirable that the gap be 5.2 eV or less). The n-type cladding layer 24 has a thickness of about 1 μm to 3 μm, for example, about 2 μm.

The n-type cladding layer 24 is formed so that the concentration of silicon (Si), which is an impurity, is 1×10 ¹⁸ /cm ³ or more and 5×10 ¹⁹ /cm ³ or less. The n-type cladding layer 24 is preferably formed so that the Si concentration is 5×10 ¹⁸ /cm ³ or more and 3×10 ¹⁹ /cm ³ or less, and 7×10 ¹⁸ /cm ³ or more and 2×10 ¹⁹ /cm 3 or more. It is preferably formed so as to be cm ³ or less. In one embodiment, the Si concentration of the n-type cladding layer 24 is around 1×10 ¹⁹ /cm ³ and ranges from 8×10 ¹⁸ /cm ³ to 1.5×10 ¹⁹ /cm ³ .

The active layer 26 is composed of an AlGaN-based semiconductor material, and is sandwiched between the n-type cladding layer 24 and the electron blocking layer 28 to form a double heterojunction structure. The active layer 26 may have a single-layer or multi-layer quantum well structure, for example, a laminate of a barrier layer made of an undoped AlGaN-based semiconductor material and a well layer made of an undoped AlGaN-based semiconductor material. It may consist of a body. The active layer 26 is configured to have a bandgap of 3.4 eV or more in order to output deep ultraviolet light with a wavelength of 355 nm or less. For example, the AlN composition ratio is selected so as to output deep ultraviolet light with a wavelength of 310 nm or less. be done. The active layer 26 is formed on the first upper surface 24a of the n-type cladding layer 24 and is not formed on the second upper surface 24b adjacent to the first upper surface 24a. That is, the active layer 26 is not formed over the entire surface of the n-type clad layer 24, but is formed only in a partial region of the n-type clad layer 24. As shown in FIG.

An electron blocking layer 28 is formed over the active layer 26 . The electron block layer 28 is an undoped AlGaN-based semiconductor material layer, and is formed, for example, so that the molar fraction of AlN is 40% or more, preferably 50% or more. The electron blocking layer 28 may be formed such that the molar fraction of AlN is 80% or more, or may be formed of an AlN-based semiconductor material that does not contain GaN. The electron blocking layer has a thickness of about 1 nm to 10 nm, for example, a thickness of about 2 nm to 5 nm. The electron block layer 28 may be a p-type AlGaN-based semiconductor material layer.

The p-type cladding layer 30 is a p-type semiconductor layer formed on the electron blocking layer 28 . The p-type cladding layer 30 is a p-type AlGaN-based semiconductor material layer, for example, an AlGaN layer doped with magnesium (Mg) as a p-type impurity. The p-type cladding layer 30 has a thickness of approximately 300 nm to 700 nm, for example, approximately 400 nm to 600 nm. The p-type cladding layer 30 may be made of a p-type GaN-based semiconductor material that does not contain AlN.

The n-side electrode 32 is formed on the second upper surface 24b of the n-type cladding layer 24. As shown in FIG. The n-side electrode 32 includes a first layer 34 , a second layer 36 and a third layer 38 . The first layer 34 is provided on and in contact with the n-type cladding layer 24 and contains titanium (Ti). The first layer 34 may be a Ti layer containing substantially only Ti. The second layer 36 is provided on and in contact with the first layer 34 and contains aluminum (Al). The second layer 36 may be an Al layer containing substantially only Al. The third layer 38 includes a titanium (Ti) layer 38a and a titanium nitride (TiN) layer 38b. The Ti layer 38 a is provided on and in contact with the second layer 36 . The TiN layer 38b is provided on the Ti layer 38a so as to cover the surface of the Ti layer 38a.

The thickness of the first layer 34 is about 1 nm to 10 nm, preferably 5 nm or less, more preferably 2 nm or less. By reducing the thickness of the first layer 34, the ultraviolet light reflectance of the n-side electrode 32 viewed from the n-type cladding layer 24 can be increased. The thickness of the second layer 36 is about 100 nm to 1000 nm, preferably 200 nm or more, more preferably 300 nm or more. By increasing the thickness of the second layer 36, the ultraviolet light reflectance of the second layer 36 can be increased. The thickness of the third layer 38 is about 20 nm to 500 nm, preferably 30 nm or more, more preferably 50 nm or more. By increasing the thickness of the third layer 38 , the surface of the second layer 36 can be suitably covered and oxidation of Al can be prevented during annealing of the n-side electrode 32 .

FIG. 2 is a graph showing the relationship between the thickness of the first layer 34 (Ti layer) and the ultraviolet light reflectance. showing change. As shown in the figure, the reflectance of the n-side electrode 32 tends to decrease after heating compared to before heating, and particularly after annealing at 700° C., which exceeds the melting point of Al, the ultraviolet light reflectance decreases significantly. I understand. Moreover, it is found that the n-side electrode 32 having a higher ultraviolet light reflectance can be obtained by setting the thickness of the Ti layer to 5 nm or less or 2 nm or less.

It is preferable that the n-side electrode 32 does not contain gold (Au), which may cause a decrease in ultraviolet light reflectance.

Returning to FIG. 1, the p-side electrode 42 is provided on and in contact with the p-type cladding layer 30 . The p-side electrode 42 is made of transparent conductive oxide (TCO) such as tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (ITO). The thickness of the transparent electrode layer 42 is about 20 nm to 500 nm, preferably 50 nm or more, more preferably 100 nm or more.

The n-side protective metal layer 39 is provided on the n-side electrode 32 and is in contact with the third layer 38 (TiN layer 38b). The p-side protective metal layer 49 is provided on the p-side electrode 42 and is in contact with the p-side electrode 42 . The protective metal layers 39 and 49 are made of a metal material having high adhesion to the protective insulating layer 50, and are composed of a single metal film or a metal laminated film. The protective metal layers 39 and 49 function as stop layers in the dry etching process for forming the n-side opening 52 and the p-side opening 54, and are preferably made of a metal material that is highly resistant to etching gases. As a material of the protective metal layers 39 and 49, for example, a platinum group metal can be used, and palladium (Pd) can be used. The thickness of the protective metal layers 39 and 49 is preferably 50 nm or more, preferably 100 nm or more.

The protective insulating layer 50 is provided to cover the n-side protective metal layer 39 and the p-side protective metal layer 49 and the exposed surfaces of the second upper surface 24 b of the n-type cladding layer 24 and the p-type cladding layer 30 . . The protective insulating layer 50 is made of an insulating material such as silicon oxide (SiO ₂ ), silicon oxynitride (SiON), or silicon nitride (SiN). The thickness of the protective insulating layer 50 is about 20 nm to 500 nm, preferably 50 nm or more, and preferably 100 nm or more.

The protective insulating layer 50 is provided with an n-side opening 52 through which a portion of the n-side protective metal layer 39 is exposed and a p-side opening 54 through which a portion of the p-side protective metal layer 49 is exposed. The n-side pad electrode 56 is provided in the n-side opening 52 on the n-side protective metal layer 39 and is in contact with the n-side protective metal layer 39 . The p-side pad electrode 58 is provided in the p-side opening 54 on the p-side protective metal layer 49 and is in contact with the p-side protective metal layer 49 .

The n-side pad electrode 56 and the p-side pad electrode 58 are portions that are bonded when the semiconductor light emitting device 10 is mounted on a package substrate or the like. The n-side pad electrode 56 and the p-side pad electrode 58 are configured to contain gold (Au) from the viewpoint of corrosion resistance, such as nickel (Ni)/Au, titanium (Ti)/Au or Ti/platinum ( Pt)/Au laminated structure. If the pad electrodes 56, 58 are bonded with gold tin (AuSn), the pad electrodes 56, 58 may include an AuSn layer for the bonding.

Next, a method for manufacturing the semiconductor light emitting device 10 will be described. 3 to 9 are diagrams schematically showing manufacturing steps of the semiconductor light emitting device 10. FIG. In FIG. 3, first, a buffer layer 22, an n-type cladding layer 24, an active layer 26, an electron blocking layer 28, and a p-type cladding layer 30 are formed on the first major surface 20a of the substrate 20 in this order.

The substrate 20 is a sapphire (Al ₂ O ₃ ) substrate and a growth substrate for forming an AlGaN-based semiconductor material. For example, the buffer layer 22 is formed on the (0001) plane of the sapphire substrate. The buffer layer 22 includes, for example, a high temperature grown AlN (HT-AlN) layer and an undoped AlGaN (u-AlGaN) layer. The n-type clad layer 24, the active layer 26, the electron block layer 28, and the p-type clad layer 30 are layers formed of an AlGaN-based semiconductor material, an AlN-based semiconductor material, or a GaN-based semiconductor material, and are formed by metalorganic chemical vapor deposition. It can be formed using well-known epitaxial growth methods such as the (MOVPE) method and the molecular beam epitaxy (MBE) method.

Next, a first mask 12 is formed on the p-type cladding layer 30 except for the exposed region W1. The first mask 12 is patterned using photolithography, for example. Subsequently, portions of the p-type cladding layer 30, the electron blocking layer 28, the active layer 26 and the n-type cladding layer 24 in the exposed region W1 where the first mask 12 is not formed are removed. Thereby, the second upper surface 24b (exposed surface) of the n-type cladding layer 24 is formed in the exposed region W1. Each layer can be removed by dry etching 14 in the step of forming the exposed surface of the n-type cladding layer 24 . For example, reactive ion etching by turning etching gas into plasma can be used, for example, inductive coupled plasma (ICP) etching can be used. After that, the first mask 12 is removed.

Next, as shown in FIG. 4, a second mask 16 is formed except for the n-side electrode region W2 on the second upper surface 24b (exposed surface) of the n-type cladding layer 24. Next, as shown in FIG. The n-side electrode region W2 is a region narrower than the exposed region W1 of the second upper surface 24b. The second mask 16 is patterned using photolithography, for example. Subsequently, a first layer 34, a second layer 36 and a Ti layer 38a are laminated in order on the second upper surface 24b of the n-type cladding layer 24 in the n-side electrode region W2. Each of the first layer 34, the second layer 36 and the Ti layer 38a can be formed by a sputtering method or an electron beam (EB) evaporation method. At this point, the TiN layer 38b has not yet been formed. In other words, the TiN layer 38b is not formed by sputtering or electron beam (EB) evaporation. After that, the second mask 16 is removed.

Subsequently, as shown in FIG. 5, the surface of the Ti layer 38a is treated with ammonia (NH ₃ ) gas plasma 40 to supply nitrogen (N) atoms to the surface of the Ti layer 38a, thereby reducing the surface of the Ti layer 38a. Nitriding. Thereby, a TiN layer 38b is formed on the surface of the Ti layer 38a. The temperature of the plasma treatment for forming the TiN layer 38b is preferably below the melting point of Al (approximately 660.degree. C.), more preferably below 300.degree. When the TiN layer 38b is formed by plasma treatment at such a relatively low temperature, the flatness of the original surface of the Ti layer 38a is maintained. The arithmetic mean roughness (Ra) of the surface of the TiN layer 38b immediately after the plasma treatment is 5 nm or less, for example 2 nm or less or 1 nm or less. The thickness of the TiN layer 38b is preferably 5 nm or more, preferably 10 nm or more. Note that the TiN layer 38b may be formed on at least part of the side surface 32b of the n-side electrode 32 .

Subsequently, the n-side electrode 32 is annealed. The annealing treatment of the n-side electrode 32 is performed at a temperature below the melting point of Al (approximately 660° C.), preferably at a temperature of 500° C. or higher and 650° C. or lower. By performing the annealing treatment at such a temperature, the contact resistance of the n-side electrode 32 can be reduced to 0.1 Ω·cm ² or less, and the flatness and ultraviolet light reflectance of the n-side electrode 32 can be improved. By performing the annealing treatment while the second layer 36 (Al layer) is covered with the third layer 38, the oxidation of the Al layer due to the annealing treatment can be prevented, and the flatness of the n-side electrode 32 can be further improved. be able to. Specifically, the arithmetic average roughness (Ra) of the upper surface 32a of the n-side electrode 32 can be set to 5 nm or less, and a surface roughness of about 1 nm to 3 nm can be achieved, for example.

Subsequently, as shown in FIG. 6, a third mask 18 is formed except for the p-side electrode region W3 on the p-type cladding layer 30. Then, as shown in FIG. The p-side electrode region W3 is a region narrower than the upper surface of the p-type cladding layer 30 . The third mask 18 is patterned using photolithography, for example. Subsequently, a p-side electrode 42 is formed on the p-type cladding layer 30 in the p-side electrode region W3. The p-side electrode 42 can be formed by a sputtering method or an electron beam (EB) vapor deposition method. After that, the third mask 18 is removed.

Next, as shown in FIG. 7, a fourth mask 19 is formed except for protection regions W4n and W4p corresponding to the n-side electrode region W2 and the p-side electrode region W3. The fourth mask 19 is patterned using photolithography, for example. The protection regions W4n and W4p of the fourth mask 19 may exactly match the n-side electrode region W2 and the p-side electrode region W3, or partially overlap the n-side electrode region W2 and the p-side electrode region W3. It may be shifted as much as possible. Subsequently, an n-side protective metal layer 39 is formed on the n-side electrode 32 (TiN layer 38b) in the protective region W4n, and a p-side protective metal layer 49 is formed on the p-side electrode 42 in the protective region W4p. . The protective metal layers 39 and 49 can be formed using a sputtering method or an electron beam (EB) vapor deposition method. After that, the fourth mask 19 is removed.

Subsequently, as shown in FIG. 8, a protective insulation layer 50 is formed. A protective insulating layer 50 is formed to cover the entire upper surface of the device structure. Protective insulating layer 50 covers n-side protective metal layer 39 and p-side protective metal layer 49 , and also covers second upper surface 24 b of n-type cladding layer 24 and p-type cladding layer 30 .

Next, as shown in FIG. 9, an n-side opening 52 and a p-side opening 54 are formed by removing part of the protective insulating layer 50 . The protective insulating layer 50 can be dry-etched using a CF-based etching gas, for example, hexafluoroethane (C ₂ F ₆ ) can be used. In this dry etching step, the n-side protective metal layer 39 and the p-side protective metal layer 49 function as stop layers to prevent damage to the underlying n-side electrode 32 and p-side electrode 42 .

Subsequently, an n-side pad electrode 56 is formed in the n-side opening 52 on the n-side protective metal layer 39 and a p-side pad electrode 58 is formed in the p-side opening 54 on the p-side protective metal layer 49 . The pad electrodes 56 and 58 can be formed, for example, by first depositing a Ni layer or a Ti layer and then depositing an Au layer thereon. Another metal layer may be provided on the Au layer, for example, a Sn layer, an AuSn layer, and a Sn/Au layered structure may be formed.

Through the above steps, the semiconductor light emitting device 10 shown in FIG. 1 is completed. According to the present embodiment, oxidation of the upper surface 32a of the n-side electrode 32 can be prevented by covering the upper surface 32a of the n-side electrode 32 with the TiN layer 38b when the n-side electrode 32 is annealed. In addition, since no oxide is formed on the upper surface 32a of the n-side electrode 32, corrosion of the oxide by chemicals used in the subsequent photolithography process for forming the third mask 18 and the fourth mask 19 can be prevented. As a result, deterioration of the flatness due to oxidation or corrosion of the upper surface 32a of the n-side electrode 32 can be suitably prevented.

For example, in the comparative example in which the Ti layer 38a and the TiN layer 38b are not provided on the second layer 36 of the n-side electrode, aluminum (Al) contained in the second layer 36 is oxidized during annealing to form aluminum oxide. and subsequent photolithography steps can erode the aluminum oxide. In the comparative example in which only the Ti layer 38a is provided on the second layer 36 of the n-side electrode and the TiN layer 38b is not provided, the surface of the Ti layer 38a is oxidized during annealing to form titanium oxide. Titanium oxide may corrode in subsequent photolithographic steps. In any of the comparative examples, the top surface of the n-side electrode may be oxidized or corroded, so that the flatness of the electrode surface is reduced and the arithmetic mean roughness (Ra) of the electrode surface exceeds 5 nm. If the flatness of the upper surface of the n-side electrode exceeds 5 nm, the insulating properties of the protective insulating layer and the contact with the pad electrode become poor, which may cause a problem that the semiconductor light emitting device does not light up.

On the other hand, according to the present embodiment, since the n-side protective metal layer 39, the protective insulating layer 50 and the n-side pad electrode 56 are formed on the upper surface 32a of the n-side electrode 32 with high flatness, poor insulation and poor contact are prevented. Such troubles can be suitably prevented. Therefore, according to the present embodiment, the reliability of semiconductor light emitting device 10 can be enhanced. Further, by realizing the n-side electrode 32 with high reflectance, the output characteristics of the semiconductor light emitting device 10 can be improved.

According to this embodiment, the flatness of the upper surface 32a of the n-side electrode 32 can be improved by forming the TiN layer 38b by plasma processing. As a method for forming the TiN layer, a film forming technique such as a sputtering method is also conceivable. However, when the TiN film is formed by sputtering, a grain structure is formed on the surface, which may deteriorate the flatness. As a result, it becomes difficult to achieve an arithmetic mean roughness (Ra) of 5 nm or less. On the other hand, according to the present embodiment, after forming a Ti metal film with high flatness, nitridation can be performed while maintaining the flatness of the surface, so that the n-side electrode 32 with excellent flatness can be realized.

The present invention has been described above based on the examples. Those skilled in the art will understand that the present invention is not limited to the above-described embodiments, and that various design changes and modifications are possible, and that such modifications are within the scope of the present invention. It is about to be done.

FIG. 10 is a cross-sectional view schematically showing the configuration of a semiconductor light emitting device 110 according to a modification. This modification differs from the above embodiment in that the third layer 138 of the n-side electrode 132 is provided so as to cover the side surfaces of both the first layer 34 and the second layer 36 . The third layer 138 includes a Ti layer 138a and a TiN layer 138b. The Ti layer 138 a is provided so as to cover the side surfaces of the first layer (Ti layer) 34 and the second layer (Al layer) 36 and the upper surface of the second layer 36 . The TiN layer 138b is provided so as to cover the surface of the Ti layer 138a, that is, the side and top surfaces of the Ti layer 138a. Also in this modified example, it is possible to obtain the same effect as the above-described embodiment.

FIG. 11 is a cross-sectional view schematically showing the configuration of a semiconductor light emitting device 210 according to another modification. The n-side electrode 232 according to this modification includes a first layer 234 containing Ti, a second layer 236 containing Al, a third layer 238 containing Ti, and a nitride layer 240 . A first layer 234 , a second layer 236 and a third layer 238 are laminated in order on the second upper surface 24 b of the n-type cladding layer 24 . The nitride layer 240 is provided to cover the top and side surfaces of the n-side electrode 232, and has a first portion covering the side surfaces of the first layer 234, a second portion covering the side surfaces of the second layer 236, and and a third portion covering the side and top surfaces of the third layer 238 . A first portion of nitride layer 240 is a TiN layer, a second portion of nitride layer 240 is an AlN layer, and a third portion of nitride layer 240 is a TiN layer. Nitride layer 240 can be formed by nitriding the respective surfaces of first layer 234, second layer 236 and third layer 238 with an ammonia gas plasma treatment. Also in this modified example, it is possible to obtain the same effect as the above-described embodiment.

10 and 11, the n-side protective metal layer 39 may be provided between the n-side electrodes 132 and 232 and the n-side pad electrode 56 as well. A p-side protective metal layer 49 may be provided between the p-side electrode 42 and the p-side pad electrode 58 .

In the above embodiments and modifications, the case where the third layer of the n-side electrode is composed of a laminated structure of a Ti layer and a TiN layer has been described. In a further modification, the third layer of the n-side electrode may consist essentially of a TiN layer. For example, a Ti layer having a thickness smaller than that of the TiN layer of the third layer may remain, and substantially no Ti layer may be included. In this case, the TiN layer of the third layer may have a thickness of 5 nm or more or 10 nm or more, while the Ti layer of the third layer may have a thickness of less than 10 nm or less than 5 nm (for example, about 1 nm to 3 nm).

DESCRIPTION OF SYMBOLS 10... Semiconductor light emitting element, 24... n-type clad layer, 26... active layer, 32... n-side electrode, 34... first layer, 36... second layer, 38... third layer, 38a... Ti layer, 38b... TiN Layer, 42... p-side electrode, 50... protective insulating layer.

Claims (12)

an n-type semiconductor layer of an n-type aluminum gallium nitride (AlGaN) based semiconductor material;
an n-side electrode provided in a partial region on the n-type semiconductor layer;
an n-side protective metal layer provided on the n-side electrode;
an active layer of an AlGaN-based semiconductor material provided in a region different from the partial region on the n-type semiconductor layer;
The n-side electrode includes a first layer containing titanium (Ti) on the n-type semiconductor layer, a second layer containing aluminum (Al) on the first layer, and titanium nitride ( and a third layer containing TiN). 2. The semiconductor light emitting device according to claim 1, wherein said n-side protective metal layer contains a platinum group metal. 3. The semiconductor light emitting device according to claim 1, wherein said n-side protective metal layer is composed of a metal laminated film. 4. The semiconductor light emitting device according to claim 1, wherein the third layer is provided so as to cover an upper surface and side surfaces of the laminated structure of the first layer and the second layer. . an n-type semiconductor layer of an n-type aluminum gallium nitride (AlGaN) based semiconductor material;
an n-side electrode provided in a partial region on the n-type semiconductor layer;
an active layer of an AlGaN-based semiconductor material provided in a region different from the partial region on the n-type semiconductor layer;
The n-side electrode includes a first layer containing titanium (Ti) on the n-type semiconductor layer, a second layer containing aluminum (Al) on the first layer, and titanium nitride ( and a third layer containing TiN), wherein the third layer covers the upper surface and side surfaces of the laminated structure of the first layer and the second layer. The third layer comprises a Ti layer covering the upper surface and the side surfaces of the laminated structure of the first layer and the second layer, and a TiN layer covering the upper surface and side surfaces of the Ti layer. 6. The semiconductor light emitting device according to claim 4 or 5. 7. The semiconductor light emitting device of claim 1, wherein the third layer comprises aluminum nitride (AlN) in contact with the second layer. forming an active layer of an AlGaN-based semiconductor material on an n-type semiconductor layer of an n-type aluminum gallium nitride (AlGaN)-based semiconductor material;
removing a portion of the active layer and the n-type semiconductor layer so as to expose a partial region on the n-type semiconductor layer;
forming an n-side electrode on the partial region of the n-type semiconductor layer;
The step of forming the n-side electrode includes forming a first layer containing titanium (Ti) on the n-type semiconductor layer and forming a second layer containing aluminum (Al) on the first layer. and forming a third layer containing titanium nitride (TiN) on the second layer. The step of forming the third layer comprises a step of forming a Ti layer on the second layer, and a step of subjecting the surface of the Ti layer to an ammonia gas plasma treatment to form a TiN layer. 9. The method for manufacturing a semiconductor light emitting device according to claim 8. 10. The manufacturing of the semiconductor light emitting device according to claim 9, wherein the step of forming the third layer further comprises the step of applying the ammonia gas plasma treatment to the surface of the second layer to form an AlN layer. Method. 11. The semiconductor light emitting device according to claim 9, wherein the step of forming the third layer further comprises the step of applying the ammonia gas plasma treatment to the surface of the first layer to form a TiN layer. manufacturing method. 12. The method of manufacturing a semiconductor light emitting device according to claim 8, further comprising forming an n-side protective metal layer on the n-side electrode.

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