JP7305052B2 - Delay update device, processing system and program - Google Patents

Description

The present disclosure relates to multicore processor systems.

As described in Patent Literature 1, conventionally, in order to speed up processing, there has been proposed a technology related to a multicore processor system that executes parallel processing using a multicore processor having a plurality of cores. Also, in order to improve the processing performance of a multi-core processor system, a technology is known in which a plurality of cores share a cache.

In a multi-core processor system, if all programs are cached, the multi-core processor can execute programs efficiently.

However, if the entire program cannot be stored in the cache due to software bloat or the like, the program that cannot be stored in the cache is loaded into the cache each time a cache miss occurs. Therefore, the execution efficiency of the multicore processor may decrease.

On the other hand, as a parallel processing method, data parallel processing is known in which a plurality of cores execute the same processing on a plurality of data in parallel.

JP 2008-191949 A

For multi-core processor systems, it is desirable to be able to take advantage of multi-core processors.

Therefore, the present disclosure has been made in view of the above points, and an object thereof is to provide a technology that enables effective use of a multi-core processor.

One aspect of a program creation device is a program creation device that creates a program to be executed by the multi-core processor of a multi-core processor system comprising a multi-core processor including a plurality of cores and a shared cache shared by the plurality of cores, a specifying unit for specifying a target partial program, which is a target partial program to be converted into a data parallel program in which data parallel processing is described, in the processing target program; Execution including the data parallel program obtained by converting the target partial program into the data parallel program describing the data parallel processing whose timing is delayed from the processing start timing of other cores. and a generator for generating the target program.

Further, one aspect of the delay amount updating device is a delay amount for updating the delay amount of the processing start timing in the part of the cores in the data parallel processing described in the data parallel program created by the program creating device. An update device, comprising: an acquisition unit that acquires execution state information indicating an execution state of the data parallel processing in the multi-core processor; and an update unit that updates the delay amount based on the execution state information.

Further, one aspect of the processing system includes the above program creation device and the above delay amount updating device.

Further, one aspect of the program is a program for creating a program to be executed by the multi-core processor of a multi-core processor system comprising a multi-core processor including a plurality of cores and a shared cache shared by the plurality of cores, specifying, in a computer device, a target partial program that is a target partial program to be converted into a data parallel program in which data parallel processing is described in a processing target program; converting the target partial program into the data parallel program in which the data parallel processing is described such that the processing start timing of the other cores is delayed from the processing start timing of the other cores, and the data parallel program obtained thereby and a step of generating an execution target program including

Further, one aspect of the program is a program for updating the delay amount of the processing start timing in the part of the cores in the data parallel processing described in the data parallel program created by the program creation device. a step of obtaining execution state information indicating an execution state of the data parallel processing in the multi-core processor; and a step of updating the delay amount based on the execution state information. is.

Effective use of a multi-core processor can be achieved.

Objects, features, aspects and advantages of the present disclosure will become more apparent with the following detailed description and accompanying drawings.

It is a block diagram which shows an example of a structure of a processing system. It is a block diagram which shows an example of a structure of a program creation apparatus. 1 is a block diagram showing an example of the configuration of a program writing device; FIG. It is a block diagram which shows an example of a structure of a program creation apparatus. It is a flowchart which shows an example of operation|movement of a program creation apparatus. FIG. 4 is a diagram showing an example of the operation of a multicore processor; FIG. FIG. 4 is a diagram showing an example of the operation of a multicore processor; FIG. It is a figure which shows an example of a for sentence. It is a figure which shows an example of a delayed data parallel program. It is a block diagram which shows an example of a structure of a delay amount update apparatus. It is a flowchart which shows an example of operation|movement of a delay amount update apparatus. FIG. 4 is a diagram showing an example of the operation of a multicore processor; FIG. FIG. 4 is a diagram showing an example of the operation of a multicore processor; FIG. It is a figure which shows an example of a designation|designated description. It is a figure which shows an example of a structure of a part of engineering tool. It is a block diagram which shows an example of an update part. It is a flowchart which shows an example of operation|movement of a delay amount update apparatus.

Embodiment 1.
FIG. 1 is a block diagram showing an example of the configuration of a processing system 1 according to this embodiment. A processing system 1 comprises a multi-core processor system 2 and an engineering tool 3 . The engineering tool 3 creates programs to be executed by the multicore processor system 2 . The engineering tool 3 then writes the created program to the multicore processor system 2 .

<Configuration example of multi-core processor system>
A multi-core processor system 2 (simply referred to as a processor system 2) is installed in built-in devices such as home appliances and IoT (Internet of Things) devices. The processor system 2 may be installed in a device other than an embedded device.

As shown in FIG. 1, the processor system 2 includes, for example, a multi-core processor 20 having a plurality of cores 21, a shared cache 22 shared by the plurality of cores 21, and a shared memory 23 shared by the plurality of cores 21. and Each core 21 is a kind of arithmetic circuit and can execute a program. A plurality of cores 21 can execute a common program independently of each other. A plurality of cores 21 are accommodated, for example, in one package. The multi-core processor 20 can be said to be a kind of CPU (Central Processing Unit), for example.

The shared memory 23 (simply called memory 23) is a storage circuit that stores various data such as programs. The memory 23 is also called main memory. Programs in the memory 23 are executed by the multicore processor 20 . The memory 23 stores a main program 230, an update program 231 and a delay amount 232, for example. The main program 230 is, for example, a program in which various types of processing to be executed by an embedded device in which the processor system 2 is installed are described. The delay amount 232 is a parameter that is referenced when the main program 230 is executed, as will be described later. The update program 231 is a program in which processing for updating the delay amount 232 is described. The memory 23 is composed of, for example, a ROM (Read Only Memory). The memory 23 may be composed of a flash ROM, or may be composed of a memory other than the flash ROM.

The shared cache 22 (simply referred to as cache 22) is a storage circuit that temporarily stores various data such as programs. The storage capacity of cache 22 is smaller than the storage capacity of memory 23 . Also, the speed of the cache 22 is faster than the speed of the memory 23 . The cache 22 is composed of, for example, a RAM (Random Access Memory). The cache 22 may be composed of SRAM (Static Random Access Memory), or may be composed of memory other than SRAM.

When executing a program, each core 21 reads the data to be processed from the cache 22 if the data to be processed (including the program) exists in the cache 22 . The presence of data to be processed (in other words, necessary data) in the cache 22 is called a cache hit. On the other hand, when the data to be processed does not exist in the cache 22 , each core 21 reads the data to be processed from the shared memory 23 and temporarily stores it in the cache 22 . Then, each core 21 reads data to be processed from the cache 22 . The absence of data to be processed in the cache 22 is called a cache miss.

<Engineering tool configuration example>
As shown in FIG. 1, the engineering tool 3 includes a program creation device 30 (simply referred to as creation device 30) and a program writing device 35 (simply referred to as writing device 35). The creating device 30 can create the main program 230 that the multicore processor 20 executes. The writing device 35 can write the main program 230 created by the creating device 30 into the memory 23 . Note that the creation device 30 may create the update program 231 . In this case, the writing device 35 may write the update program 231 created by the creating device 30 into the memory 23 .

FIG. 2 is a block diagram showing an example of the hardware configuration of the creation device 30. As shown in FIG. The creation device 30 is a kind of computer device. The creation device 30 may be a personal computer or another computer device. As shown in FIG. 2, the creation device 30 includes, for example, a processing circuit 300, a storage device 301, a communication device 302, an input device 303, and a display device 304 as hardware.

Processing circuitry 300 comprises, for example, at least one processor. The processing circuit 300 includes, for example, a CPU, which is a type of processor. The processing circuit 300 may include multiple CPUs or at least one DSP (Digital Signal Processor). The processing circuit 300 can also be called a processing unit 300 .

Note that at least part of the processing circuit 300 may be implemented by a hardware circuit that does not require software to implement its functions. In this case, at least part of the processing circuit 300 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit) and an FPGA (field-programmable gate). array).

The storage device 301 includes non-temporary recording media such as ROM and RAM, which are readable by a processor such as a CPU. The storage device 301 may comprise a non-temporary computer-readable recording medium other than ROM and RAM. The storage device 301 may include, for example, an HDD (Hard Disk Drive) or an SSD (Solid State Drive).

The storage device 301 stores a program 301 a for controlling the program creating device 30 . The program 301a includes, for example, an OS (Operating System). Various functions of the processing circuit 300 are realized by the processor of the processing circuit 300 executing the program 301a.

The display device 304 can display various types of information such as characters, symbols, and graphics. The display device 304 may be a liquid crystal display device or another type of display device. The input device 303 can accept input from the user. Input device 303 includes, for example, a keyboard and a mouse. Input device 303 may include a touch sensor. In this case, the display device 304 may be a touch panel display having a touch sensor included in the input device 303 . Input device 303 may comprise a microphone.

The communication device 302 can communicate with devices external to the creation device 30 . The communication device 302 can also be said to be a communication circuit. The communication device 302 can communicate with the writing device 35, for example. The communication device 302 performs wired communication directly with the writing device 35, for example. The communication device 302 may perform wireless communication with the writing device 35 . Also, the communication device 302 may communicate with the writing device 35 through a network including the Internet.

Note that the hardware configuration of the creation device 30 is not limited to the above example. For example, the creation device 30 may include devices other than the processing circuitry 300 , the storage device 301 , the communication device 302 , the input device 303 and the display device 304 .

FIG. 3 is a block diagram showing an example of the hardware configuration of the writing device 35. As shown in FIG. The writing device 35 is a kind of computer device. As shown in FIG. 3, the writing device 35 includes, for example, a processing circuit 350, a storage device 351, a communication device 352, and a communication device 353 as hardware.

Processing circuitry 350 includes, for example, at least one processor. The processing circuitry 350 includes, for example, a CPU, which is a type of processor. The processing circuitry 350 may comprise multiple CPUs and may comprise at least one DSP.

Note that at least part of the processing circuit 350 may be implemented by a hardware circuit that does not require software to implement its functions. In this case, at least a portion of processing circuitry 350 may comprise, for example, single circuits, multiple circuits, programmed processors, parallel programmed processors, ASICs, and/or FPGAs.

The storage device 351 includes, for example, non-temporary recording media such as ROM and RAM that are readable by a processor such as a CPU. As with the storage device 301, the storage device 351 may include a non-temporary computer-readable recording medium other than ROM and RAM.

The storage device 351 stores a program 351a for controlling the writing device 35. FIG. Various functions of the processing circuit 350 are realized by the processor of the processing circuit 350 executing the program 351a.

The communication device 352 can communicate with the communication device 302 of the creation device 30 . Communication device 353 is capable of communicating with processor system 2 . Processor system 2 includes a communication device that communicates with communication device 353 . The communication device 353 may communicate directly with the processor system 2 or may communicate with the processor system 2 through a network including the Internet. The communication device 353 may perform wired communication or wireless communication.

Note that the hardware configuration of the writing device 35 is not limited to the above example. For example, writing device 35 may comprise devices other than processing circuitry 350 , storage device 351 , communication device 352 and communication device 353 . For example, writing device 35 may comprise an input device capable of accepting input from a user.

In the engineering tool 3 having the hardware configuration example as described above, the processing circuit 300 of the creation device 30 creates the main program 230 . The communication device 302 of the creating device 30 then transmits the main program 230 created by the processing circuit 300 to the communication device 352 of the writing device 35 . In the writing device 35 , the processing circuit 350 inputs the main program 230 received by the communication device 352 to the communication device 353 . The communication device 353 writes the input main program 230 into the memory 23 through the communication device of the processor system 2 .

Note that the writing device 35 does not have to be always connected to the processor system 2 . For example, if the writing device 35 is connected to the processor system 2 through a network, the writing device 35 may be disconnected from the network after the main program 230 is written into the memory 23 .

In the above example, the writing device 35 writes the program to the memory 23 mounted on the processor system 2, but writing the program to the memory 23 not mounted on the processor system 2 good. In this case, the writing device 35 comprises a holding part, for example a socket, holding the memory 23 . Then, the processing circuit 350 of the writing device 35 writes the program to the memory 23 held in the holding component. A memory 23 in which a program is written is installed in the processor system 2 .

<Example of functional block configuration of programming device>
FIG. 4 is a diagram showing an example of the functional block configuration of the creation device 30. As shown in FIG. As shown in FIG. 4, the creation device 30 includes a program description unit 310, a specification unit 320, a generation unit 330, and a compilation unit 340 as functional blocks. Each of the program description unit 310, the specifying unit 320, the generating unit 330, and the compiling unit 340 is composed of, for example, functional blocks realized by the processing circuit 300 when the processing circuit 300 executes the program 301a. Note that when at least part of the processing circuit 300 is realized by a hardware circuit that does not require software to realize its functions, at least one of the program description unit 310, the identification unit 320, the generation unit 330, and the compilation unit 340 One may be implemented by a hardware circuit that does not require software to implement its functions.

The program description unit 310 can describe the first text format program 401 based on the input from the user received by the input device 303 . The user can use the function of the program writing unit 310 to write the first text format program 401 on the program creation device 30 . The program description unit 310 creates the first text format program 401 based on user input received by the input device 303 .

The program description unit 310 can describe processing in units of threads, for example. The program description unit 310 can describe, for each thread, which core 21 executes the thread in the first text format program 401 according to the user's instruction.

The program description unit 310 is realized by executing an OS included in the program 301a in the processing circuit 300, for example. The OS includes, for example, a text editor, which is a type of program, and the program description unit 310 is realized by executing the text editor. The first text format program 401 created by the program description unit 310 is displayed on the display device 304, for example. As a result, the user can advance the description of the first text format program 401 while watching the first text format program 401 being created displayed on the display device 304, for example.

The identification unit 320 identifies a partial program to be converted into a data parallel program describing data parallel processing in the first text format program 401 . Hereinafter, the partial program may be called a conversion target partial program.

Here, data parallel processing is processing in which a plurality of cores execute the same processing in parallel on a plurality of data (or a plurality of data sets). In other words, data parallel processing means that multiple cores perform parallel processing on multiple data (or multiple data sets) using a common program (in other words, the same program). The plurality of cores 21 of the processor system 2 can parallelly execute the same processing on a plurality of independent data (or a plurality of data sets) that are independent of each other. Data parallelism is sometimes called data parallelism. Hereinafter, processing executed by individual cores in data parallel processing may be referred to as parallel individual processing. The operation of the identification unit 320 will be described later in detail.

The generation unit 330 generates the second text format program 402 from the first text format program 401 based on the identification result of the identification unit 320 . Specifically, the generation unit 330 performs data parallel processing (delayed data parallel processing) such that the processing start timing of some cores 21 is delayed from the processing start timing of other cores 21 among the plurality of cores 21 . process) is described (also called delayed data parallel program). The processing start timing can also be said to be the processing start time. The generation unit 330 then generates the second text format program 402 including the delayed data parallel program. The second text format program 402 is obtained by replacing the conversion target partial program in the first text format program 401 with a delayed data parallel program. As will be described later, the second text format program 402 can be said to be a program to be executed because it is executed by the multi-core processor 20 after being compiled. The operation of the generator 330 will be described later in detail.

The compiling unit 340 compiles the second text format program 402 and converts the second text format program 402 into the executable format program 403 . The executable program 403 is written into the memory 23 by the writing device 35 as the main program 230 .

As can be understood from the above description, the main program 230 includes a delayed data parallel program (more specifically, a delayed data parallel program converted into executable form). In the delayed data parallel processing described in this delayed data parallel program, the start timing of the parallel individual processing executed by some cores 21 is delayed from the start timing of the parallel individual processing executed by the other cores 21. .

Hereafter, parallel individual processing may be called a job. In the delayed data parallel processing, a parallel individual process whose start timing is later than other parallel individual processes may be called a delayed parallel individual process or a delayed job. Also, in the delayed data parallel processing, a parallel individual process whose start timing is earlier than other parallel individual processes may be called a preceding parallel individual process or a preceding job.

The delay amount 232 in the memory 23 indicates the delay amount of the start timing of the delayed parallel individual processing (delayed job) with respect to the start timing of the preceding parallel individual processing (preceding job). The delay amount 232 is referenced by the core 21 executing the delayed job during execution of the delayed data parallel program included in the main program 230 . When the core 21 executing the delayed data parallel program refers to the delay amount 232, if the delay amount 232 is stored in the cache 22, the delay amount 232 is read from the cache 22 and referred to. On the other hand, if the delay amount 232 is not stored in the cache 22 , the core 21 reads the delay amount 232 from the memory 23 and temporarily stores it in the cache 22 . The core 21 then reads the delay amount 232 from the cache 22 and refers to it.

FIG. 5 is a flow chart showing an example of the operation of the engineering tool 3. As shown in FIG. As shown in FIG. 5, in step s1, the program description unit 310 describes and creates a first text format program 401 based on user input. Next, at step s2, the identification unit 320 identifies a partial program to be converted into a data parallel program, that is, a partial program to be converted, in the first text format program 401. FIG. Next, in step s3, the generation unit 330 converts the conversion target partial program into a delayed data parallel program, and generates the second text format program 402 including the delayed data parallel program thus obtained. Next, in step s4, the compiling section 340 compiles the second text format program 402 to generate the executable program 403. FIG. Then, in step s5, the writing device 35 writes the executable program 403 to the memory 23 as the main program 230. FIG. Various functions of the embedded device are implemented by executing the main program 230 in the memory 23 during actual operation of the embedded device on which the processor system 2 is mounted. During execution of the main program 230, for example, delayed data parallel processing is repeatedly executed. Note that the first text format program 401 may be created by a device other than the program creating device 30 .

As described above, in data parallel processing, a plurality of cores 21 perform parallel processing on a plurality of data using a common program. can do.

FIG. 6 is a diagram showing an example of the operation of the multicore processor 20 when the multicore processor 20 executes the data parallel processing 50. As shown in FIG. In the example of FIG. 6, the multiple cores 21 are composed of four cores 21a to 21d. In the data parallel processing 50, the cores 21a-21d execute parallel individual processing 51-54, respectively. Also, the data parallel processing 50 is not delayed data parallel processing, and the start timings of the plurality of parallel individual processings 51 to 54 are set to be the same. The data to be processed are different among the plurality of parallel individual processes 51 to 54, but the processing contents are the same.

In the example of FIG. 6 , the core 21 a performs serial processing 55 before parallel individual processing 51 and serial processing 56 after parallel individual processing 51 . In data parallel processing 50 , the same processing is executed in parallel on multiple data sets obtained in serial processing 55 . The core 21 a performs serial processing 56 on the multiple data sets obtained by the data parallel processing 50 .

The cores 21b-21d also execute low-priority processes 57-59, respectively. The low priority processes 57 to 59 are processes with processing priorities lower than those of the data parallel processing 50, serial processing 55 and serial processing 56. FIG. The low-priority processes 57-59 are independent processes unrelated to the data parallel process 50, the serial process 55 and the serial process 56, for example.

In the example of FIG. 6, core 21a initiates sequential processing 55, and cores 21b-21d initiate low-priority processing 57-59, respectively. Once the serial processing 55 is completed, the data parallel processing 50 can be performed. The core 21 a executes the parallel individual processing 51 after executing the serial processing 55 . The core 21b suspends execution of the low-priority process 57 and executes the parallel individual process 52 of high priority. Similarly, the core 21c suspends execution of the low-priority process 58 and executes the parallel individual process 53, and the core 21d suspends execution of the low-priority process 59 and executes the parallel individual process . When the high-priority data parallel processing 50 is completed, the cores 21b-21d resume the suspended low-priority processing 57-59, respectively, and the core 21a executes the serial processing 56. FIG.

By executing the data parallel processing 50 in this way, it is possible to shorten the completion time of the entire high-priority processing.

FIG. 7 is a diagram showing an example of the operation of the multicore processor 20 when the multicore processor 20 executes the delayed data parallel processing 150. As shown in FIG. In the example of FIG. 7, the multiple cores 21 are composed of four cores 21a to 21d. In the delayed data parallel processing 150, the cores 21a-21d execute parallel individual processing 51-54, respectively. In the delayed data parallel processing 150 shown in FIG. 7, for example, the start timing of the parallel individual processes 52 to 54 executed by the cores 21b to 21d is delayed from the start timing of the parallel individual process 51 executed by the core 21a. . In the delayed data parallel processing 150, the parallel individual processing 51 is the preceding job, and the parallel individual processings 52-54 are the delayed jobs. The start timings of the parallel individual processes 52 to 54 are delayed from the start timing of the parallel individual process 51 by a delay amount 232 .

In the example of FIG. 7, as in the example of FIG. 6, the core 21a starts the sequential process 55 and the cores 21b-21d start the low priority processes 57-59, respectively. Once the serial processing 55 is completed, the delayed data parallel processing 150 can be executed. The core 21 a starts the parallel individual processing 51 after executing the serial processing 55 . When the parallel individual processing 52 starts after the parallel individual processing 51 has started, the core 21 b interrupts the low priority low priority processing 57 and starts the high priority parallel individual processing 52 . Similarly, the core 21 c interrupts the low-priority processing 58 and starts the parallel individual processing 53 at the start timing of the parallel individual processing 53 . Similarly, the core 21 d interrupts the low-priority processing 59 and starts the parallel individual processing 54 at the start timing of the parallel individual processing 54 . When the high-priority delayed data parallel processing 150 is completed, the cores 21b-21d resume the suspended low-priority processing 57-59, respectively, and the core 21a executes the serial processing 56. FIG.

In the example of FIG. 6, when the multi-core processor 20 executes the data parallel processing 50, the cores 21a to 21d execute a common data parallel program in which the data parallel processing 50 is written. If the data parallel program is not present in cache 22, the data parallel program must be loaded into cache 22 from memory 23. FIG. A latency of the multi-core processor 20 occurs while the data parallel program is being loaded into the cache 22 . In the data parallel processing 50, since the start timings of the plurality of parallel individual processes 51-54 are the same, the same waiting time for loading the data parallel program to the cache 22 occurs in all of the cores 21a-21d.

On the other hand, in the delayed data parallel processing 150 shown in FIG. 7, the start timings of the parallel individual processings 52 to 54 are delayed from the start timing of the parallel individual processing 51 . As a result, the cores 21b-21c can execute processes other than the parallel individual processes 52-54 while the delayed data parallel processing 150 is being executed. In the example of FIG. 7, the cores 21b-21c are executing the low-priority processes 57-59 during the execution of the delayed data parallel processing 150, and the low-priority processes 52-54 are delayed by the start timings of the parallel individual processes 52-54. The processing 57 to 59 is executed for a long time. As a result, the multi-core processor 20 can be used effectively.

Furthermore, the latency of loading delayed data parallel programs into cache 22 does not occur equally in all of cores 21a-21d. That is, in the delayed data parallel program, the cores 21b to 21d can execute the portion loaded into the cache 22 during the execution of the parallel individual processing 51 of the core 21a that starts processing earlier. 21d can be made smaller than the latency of core 21a. Therefore, even if the processing start timings of the cores 21b to 21d are delayed, the processing time of the entire delayed data parallel processing 150 can be shortened. In the examples of FIGS. 6 and 7, the processing time of the entire delay data parallel processing 150 (in other words, the completion time of the delay data parallel processing 150) and the processing time of the entire data parallel processing 50 (in other words, the completion of the data parallel processing 50) time) are almost the same.

<Detailed description of operation examples of the specifying unit and the generating unit>
When identifying the conversion target partial program in the first text format program 401, the identifying unit 320 focuses on loop processing, for example. For example, consider the case where the first text format program 401 is written in C language. In this case, the identifying unit 320 identifies the for statement in the first text format program 401 . Then, when the loop processing described by the specified for statement handles independent data between loops, the specifying unit 320 sets the specified for statement as the conversion target partial program.

FIG. 8 is a diagram showing an example of a for statement included in the first text format program 401. As shown in FIG. In the loop processing described by the for statement shown in FIG. 8, the same processing of V[i]=X[i]+Y[i] is performed between loops. The loop processing in FIG. 8 handles data sets (V[i], X[i], Y[i]) corresponding to the number of loops i (0≤i≤399), and independent data is processed between loops. are dealing with Therefore, the loop processing described by the for statement shown in FIG. 8 can be converted into data parallel processing. When identifying the for statement shown in FIG. 8 in the first text format program 401, the identification unit 320 converts the identified for statement into a partial program to be converted, that is, a data parallel program in which data parallel processing is described. Let it be the target partial program.

The generation unit 330 converts the conversion target partial program identified by the identification unit 320 into a delayed data parallel program. FIG. 9 is a diagram showing an example of the delayed data parallel program 550. As shown in FIG. A delayed data parallel program 550 in FIG. 9 is obtained by converting the for statement shown in FIG. The delayed data parallel program 550 of FIG. 9 is executed, for example, by four cores 21a, 21b, 21c, and 21d.

In the example of FIG. 9, for example, the core 21a executes V[i]=X[i]+Y[i] for the data set (X[i], Y[i]) (0≤i≤99). do. A process performed by the core 21a to perform V[i]=X[i]+Y[i] in the range of 0≤i≤99 is parallel individual processing (in other words, job) performed by the core 21a in the delayed data parallel processing. Also, for example, the core 21b executes V[i]=X[i]+Y[i] for the data set (X[i], Y[i]) (100≤i≤199). The process of performing V[i]=X[i]+Y[i] in the range of 100≤i≤199 by the core 21b is parallel individual processing performed by the core 21b in the delayed data parallel processing. Also, for example, the core 21c executes V[i]=X[i]+Y[i] for the data set (X[i], Y[i]) (200≦i≦299). The process of performing V[i]=X[i]+Y[i] in the range of 200≤i≤299 by the core 21c is parallel individual processing performed by the core 21c in the delayed data parallel processing. Then, for example, the core 21d executes V[i]=X[i]+Y[i] for the data set (X[i], Y[i]) (300≤i≤399). The process of performing V[i]=X[i]+Y[i] in the range of 300≤i≤399 by the core 21d is parallel individual processing performed by the core 21d in the delayed data parallel processing.

The delayed data parallel program 550 of FIG. 9 includes a program 550a describing delay processing for delaying the start timing of parallel individual processing performed by the core 21 for each of the three cores 21b, 21c, and 21d. . As each of the cores 21b, 21c, and 21d executes the delay processing, the start timing of the parallel individual processing performed by the cores 21b, 21c, and 21d is delayed from the start timing of the parallel individual processing performed by the core 21a. In the example of FIG. 9, the parallel individual processing performed by the core 21a is the preceding job, and the parallel individual processing performed by the cores 21b, 21c, and 21d is the delayed job. In the example of FIG. 9, OpenMP is used to describe the program 550a.

The delay data parallel program 550 of FIG. 9 also includes a program 550b describing monitoring processing for monitoring the execution state of parallel individual processing in the core 21 for each of the four cores 21a to 21d. . The core 21 outputs execution state information (also referred to as core execution state information) indicating the execution state of parallel individual processing in the core 21 during execution of the monitoring process. The core execution state information includes, for example, the execution time of parallel individual processing, the number of executed instructions in parallel individual processing, the number of cache misses during execution of parallel individual processing, and the number of stalls during execution of parallel individual processing. It can also be said that the execution time of parallel individual processing in a certain core 21 is the execution time of delayed data parallel processing in the certain core 21 . The core execution state information is used in updating the delay amount 232 as described later. Information included in the core execution state information is not limited to this.

After generating the delayed data parallel program, the generator 330 generates the second text format program 402 including the delayed data parallel program. This second text format program 402 is obtained by replacing the conversion target partial program in the first text format program 401 with a delayed data parallel program. The second text format program 402 generated by the generation unit 330 is written to the memory 23 after being compiled.

<Example of delay update device>
The processing system 1 of this example includes a delay amount updating device 250 that updates the delay amount 232 . In this example, for example, the multicore processor 20 functions as the delay update device 250 . FIG. 10 is a block diagram showing an example of the delay update device 250. As shown in FIG.

As shown in FIG. 10, the delay update device 250 includes, for example, an acquisition unit 251 that acquires execution state information 600 (also referred to as processor execution state information 600) indicating the execution state of parallel processing of delayed data in the multi-core processor 20. and an update unit 252 that updates the delay amount 232 based on the execution state information 600 acquired by the acquisition unit 251 . The processor execution state information 600 includes core execution state information for each core 21 . The processor execution state information 600 also includes the execution time of the entire delay data parallel processing.

Each of the acquisition unit 251 and the update unit 252 is configured by a functional block realized by executing the update program 231 by a certain core 21 of the multi-core processor 20, for example. The acquisition unit 251 acquires core execution state information from each core 21 of the multi-core processor 20 that is executing the delayed data parallel program. Also, the acquisition unit 251 acquires the execution time of the entire delay data parallel processing during execution of the delay data parallel program.

FIG. 11 is a flowchart showing an example of update processing performed by the delay update device 250. As shown in FIG. The update process shown in FIG. 11 may be executed during the actual operation of the processor system 2 (in other words, during the actual operation of the embedded device in which the processor system 2 is mounted), or before the actual operation of the processor system 2 ( For example, it may be executed before shipment of an embedded device in which the processor system 2 is mounted.

As shown in FIG. 11, in step s11, the acquisition unit 251 causes the multi-core processor 20 to execute the main program 230. As shown in FIG. Next, in step s12, the acquisition unit 251 acquires the processor execution state information 600 while the main program 230 is being executed.

During execution of the main program 230, delayed data parallel processing is repeatedly executed. The initial value of the delay amount 232 used in the delayed data parallel processing is set to a value such that, for example, the completion time of the preceding parallel individual processing (preceding job) becomes the start time of the delayed parallel individual processing (delayed job). be. The initial value of the delay amount 232 is not limited to this.

FIG. 12 is a diagram showing an example of the delay data parallel processing 150 and the processing before and after the delay data parallel processing 150 when the delay amount 232 is set to the initial value. Although FIG. 12 does not show the low priority processes 57 to 59 described above, actually, as shown in FIG. Priority processing 57 to 59 are executed respectively. The same applies to FIG. 13 described later.

The preceding parallel individual processing 51 is started immediately after the sequential processing 55 without any delay in its start timing. In this example, the execution time of the preceding parallel individual processing (preceding job) 51 is represented by t_normal. The delayed parallel individual processes (delayed jobs) 52 to 54 start at the end timing of the preceding parallel individual process 51, and the delay amount 232 is represented by t_delay. Also, the execution time of the delayed parallel individual processes 52 to 54 is represented by t_fast. The overall execution time of the delayed data parallel processing 150, that is, the time from the start of the preceding job to the end of all jobs is represented by t_total.

As described above, the cores 21b-21d can execute portions of the delayed data parallel program that were loaded into the cache 22 during execution of the preceding parallel individual processes 51. FIG. Therefore, the waiting time of the cores 21b to 21d can be made smaller than the waiting time of the core 21a. Therefore, t_normal≧t_fast.

After step s12, in step s13, the update unit 252 determines whether or not an update termination condition, which is a termination condition for updating the delay amount 232, is satisfied. In this example, for example, the following conditional expression (1) is adopted as the update end condition.

In step s13, the updating unit 252 uses the execution time of the preceding job included in the processor execution state information acquired in step s12 and the overall execution time of the delayed data parallel processing 150 included in the processor execution state information to , determines whether or not the conditional expression (1) is satisfied.

When it is determined in step s12 that the update end condition (conditional expression (1)) is satisfied, the update process ends and the execution of the main program 230 ends. This completes the updating of the delay amount 232 . On the other hand, if it is determined in step s13 that the update end condition (conditional expression (1)) is not satisfied, step s14 is executed.

In step s14, the update unit 252 updates the delay amount 232. FIG. In step s14, first, the updating unit 252 obtains a new delay amount 232 (t_delay) using, for example, the following equation (2). Then, the updating unit 252 replaces the delay amount 232 in the memory 23 with the new delay amount 232 . Thereby, the delay amount 232 in the memory 23 is updated.

In step s14, the update unit 252 uses the execution time of the preceding job included in the processor execution state information acquired in step s12 and the execution time of the delayed job included in the processor execution state information to create a new delay. ask for quantity.

After step s14, step s12 is executed again to obtain new processor execution state information. After that, step s13 is executed in a similar manner, and the delay update device 250 operates in a similar manner thereafter.

Here, since the usage state of the cache 22 changes according to the delay amount 232 of the delayed job, the execution time (t_normal) of the preceding job and the execution time (t_fast) of the delayed job also change according to the delay amount 232. do. Therefore, even if the delay amount 232 is updated using the formula (2), the conditional formula (1) does not necessarily hold with one update. Therefore, in this example, the delay amount updating device 250 repeatedly updates the delay amount 232 until the conditional expression (1) is satisfied.

FIG. 13 is a diagram showing an example of the delayed data parallel processing 150 executed using the post-update delay amount 232 and the processing before and after that. As also shown in FIG. 13, in this example, the delay amount 232 (t_delay) is updated so that the execution time (t_total) of the delayed data parallel processing 150 matches the execution time (t_normal) of the preceding parallel individual processing 51. be done. Since the amount of calculation of the plurality of parallel individual processes 51 to 52 is the same, by updating the delay amount 232 as in this example, the delayed parallel individual processes 52 to 52 can be executed at the same timing as the preceding parallel individual process 51. end with .

In this way, by updating the delay amount 232 so that the delayed parallel individual processes 52 to 52 end at the same timing as the preceding parallel individual process 51, even if the start timings of the parallel individual processes 52 to 52 are delayed, , the execution time (t_total) of the delayed data parallel processing 150 can be reduced. For example, as shown in FIGS. 6 and 7 above, the overall execution time of the delayed data parallel processing 150 can be made equivalent to the overall execution time of the data parallel processing 50 that does not include delayed parallel individual processing.

Note that conditions other than conditional expression (1) above may be adopted as the update end condition. Even if the delay amount 232 does not change, the execution time of the parallel individual processing varies, so the following conditional expression (3), for example, may be adopted as the update end condition.

The value of parameter e in conditional expression (3) is a value based on variations in execution time of parallel individual processing. When the value of parameter e is determined, for example, the same delay amount 232 is used to execute delayed data parallel processing multiple times. Then, the value of the parameter e is determined in advance based on the variation in the execution time of the parallel individual processing obtained from the result.

In addition, in the processor system 2 in actual operation, the execution time of parallel individual processing may fluctuate due to interrupt processing or the like in the core 21 during parallel processing of delayed data. Therefore, during the actual operation of the processor system 2, the update process shown in FIG. 11 may be repeatedly executed. As a result, the delay amount 232 can be set to an appropriate value even when the execution time of parallel individual processing fluctuates. The update process may be repeatedly executed periodically or may be repeatedly executed irregularly. Also, the update process may be executed according to a user's instruction.

In the above example, the identification unit 320 selects the specific for statement included in the first text format program 401 as the conversion target partial program, but the other partial program included in the first text format program 401 is the conversion target partial program. may be For example, the identification unit 320 may set a specific while statement included in the first text format program 401 as a partial program to be converted. In this case, if the loop processing described by the while statement handles independent data between loops, the specifying unit 320 may set the while statement as the partial program to be converted. Further, the identifying unit 320 may set each of the specific for statement and the specific while statement included in the first text format program 401 as the partial program to be converted.

When the identifying unit 320 identifies a plurality of conversion target partial programs, the generating unit 330 converts each of the plurality of conversion target partial programs into a delayed data parallel program. The generation unit 330 then generates the second text format program 402 including the obtained multiple delayed data parallel programs. The second text format program 402 including multiple delayed data parallel programs is written to memory 23 as main program 230 after compilation. In this case, the memory 23 stores a plurality of delay amounts 232 respectively used in a plurality of delay data parallel programs. Then, the delay amount update device 250 updates each of the plurality of delay amounts 232 as described above.

Although the delay amount 232 is updated in the above example, the predetermined delay amount 232 may always be used without being updated. In the examples of FIGS. 7, 12, 13, etc., only one parallel individual processing is the preceding job among the plurality of parallel individual processings that constitute the delayed data parallel processing. may be the predecessor job. For example, not only the parallel individual processing executed by the core 21a but also the parallel individual processing executed by the core 21b may be the preceding job. Also, the three parallel individual processes executed by the cores 21a, 21b, and 21c may be the preceding jobs, and the parallel individual processes executed by the core 21d may be the delayed jobs.

As described above, in the present embodiment, the start timing of some cores 21 is delayed from the start timing of other cores 21 in delayed data parallel processing. This allows some of the cores 21 to execute processes other than the parallel individual processes during execution of the delayed data parallel processing. As a result, the multi-core processor 20 can be used effectively.

Furthermore, some cores 21 can execute a portion of the delayed data parallel program that is loaded into the cache 22 during execution of parallel individual processing of other cores that start processing earlier. Therefore, the waiting time of some cores 21 can be made smaller than the waiting time of other cores 21 . Therefore, even if the processing start timings of some of the cores 21 are delayed, the processing time of the entire delayed data parallel processing can be shortened.

Embodiment 2.
In this embodiment, the user designates a partial program to be converted. The configuration of the processing system 1 according to this embodiment is the same as the configuration of the processing system 1 according to the first embodiment described above.

In this embodiment, the user can use the function of the program description unit 310 to specify the partial program to be converted in the first text format program 401 . Specifically, the user uses the function of the program description unit 310 to write a description (also referred to as a designation description) in the first text format program 401 that indicates that the partial program is to be converted into a delayed data parallel program. ) can be included in the first textual program 401 . A specified description is a kind of program. The program description unit 310 includes a specified description in the first text format program 401 based on the input from the user received by the input device 303 . The specified description can be said to be a description indicating that the partial program specified by the user is to be converted into the delayed data parallel program.

FIG. 14 is a diagram showing an example of the designation description 410. As shown in FIG. In the example of FIG. 14, the specification description 410 is expressed using OpenMP. The designation description 410 in FIG. 14 indicates that the for statement immediately below it is to be converted into a delayed data parallel program. The first text format program 401 may include multiple specified descriptions.

In this embodiment, the identifying unit 320 identifies the designated description 410 in the first text format program 401 . Then, the specifying unit 320 specifies the conversion target partial program based on the specified specification description 410 . In the example of FIG. 14, the identifying unit 320 identifies the for statement immediately below the specified description 410 as the conversion target partial program. The generation unit 330 then converts the conversion target partial program identified by the identification unit 320 into the delayed data parallel program, and generates the second text format program 402 including the resulting delayed data parallel program. The second text format program 402 generated by the generation unit 330 is stored in the memory 23 after compilation. Other operations of the processing system 1 according to the present embodiment are the same as those of the processing system 1 according to the first embodiment.

Thus, in this embodiment, the first text format program 401 includes a specification description indicating that a partial program specified by the user is to be converted into a delayed data parallel program. As a result, the specifying unit 320 can set the partial program specified by the user as the conversion target partial program. That is, the user can specify the partial program to be converted.

Here, communication may be performed between multiple cores 21 during execution of data parallel processing. For example, when it is necessary to synchronize the completion of a plurality of parallel individual processes respectively executed by a plurality of cores 21, communication may be performed between the plurality of cores 21. FIG. Depending on the partial program included in the first text format program 401, if it is converted into a delayed data parallel program, the overhead due to communication between the multiple cores 21 during execution of the delayed data parallel program may cause the delay data parallel program to The merit of converting may be small.

In this embodiment, since the user can specify the partial program to be converted, the user can specify, as the partial program to be converted, a partial program that is highly advantageous in converting it into a delayed data parallel program. Therefore, the processing time in the multi-core processor 20 can be shortened more reliably.

Embodiment 3.
In this embodiment, the engineering tool 3 further includes a delay amount estimation model 460 that outputs the delay amount 232 and a model learning unit 360 that learns the delay amount estimation model 460, as shown in FIG. The delay amount estimation model 460 and the model learning unit 360 are provided in the programming device 30 of the engineering tool 3, for example. Each of the delay amount estimation model 460 and the model learning unit 360 is implemented in the processing circuit 300 by the processing circuit 300 executing the program 301a, for example.

The learned delay amount estimation model 460 estimates and outputs the delay amount 232 that makes the delayed parallel individual processing end at the same timing as the preceding parallel individual processing, for example, based on the processor execution state information. In other words, the learned delay amount estimation model 460 estimates the delay amount 232 at which the completion time of the delayed parallel individual processing and the completion time of the preceding parallel individual processing are the same time, for example, based on the processor execution state information. output.

The delay amount estimation model 460 is composed of, for example, a neural network. Processor execution state information 600 is input to the input layer of the neural network (also referred to as the first neural network) that constitutes delay estimation model 460 . A delay amount 232 is output from the output layer of the first neural network. The first neural network may be a convolutional neural network (CNN) or another type of neural network. The first neural network includes parameters learned by model learning section 360 . This parameter includes a weighting factor that indicates the weight of the connections between artificial neurons. The first neural network performs a parameter-based operation on the processor execution state information 600 input to the input layer, and outputs a delay amount 232 from the output layer.

The model learning unit 360 learns the delay amount estimation model 460 by machine learning the parameters of the first neural network, for example. By learning the parameters of the first neural network, the delay amount estimation model 460 outputs the delay amount 232 based on the processor execution state information so that the delayed parallel individual processing ends at the same timing as the preceding parallel individual processing. becomes possible. The model learning unit 360 learns the parameters of the first neural network using, for example, a supervised learning method.

The storage device 301 stores teacher data and learning data (also referred to as learning data) used in learning the parameters of the first neural network. Learning data and teacher data are sometimes collectively referred to as supervised learning data. In this example, for example, the processor system 2 generates learning data and teacher data.

The teacher data includes a delay amount 232 such that the delayed parallel individual processing ends at the same timing as the preceding parallel individual processing. Hereinafter, the delay amount 232 included in the teacher data may be referred to as the reference delay amount 232 .

As the reference delay amount 232, for example, the delay amount 232 that has been updated in the above-described update processing of FIG. 11 is used. Teacher data includes a plurality of reference delay amounts 232 . In the present embodiment, a plurality of reference delay amounts 232 are acquired by repeatedly executing the updating process in FIG. 11 in the processor system 2 before learning the parameters of the first neural network.

Here, as described above, the usage state of the cache 22 changes according to the delay amount 232 . The processor execution state information changes according to the state of use of the cache 22 . Therefore, the processor execution state information changes according to the delay amount 232 . In other words, there is a correlation between the delay amount 232 and the processor execution state information.

Therefore, in this example, processor execution state information is employed as learning data. Specifically, the learning data includes a plurality of pieces of processor execution state information respectively corresponding to the plurality of reference delay amounts 232 included in the teacher data. Here, the processor execution state information corresponding to the reference delay amount 232 is the processor execution state information acquired by the acquisition unit 251 when the delayed data parallel program is executed using the reference delay amount 232. means. The processor execution state information included in the learning data is acquired by the acquisition unit when the delayed data parallel program is executed using the delay amount 232 that causes the delay parallel individual processing to end at the same timing as the preceding parallel individual processing. It can be said that it is the processor execution state information acquired in 251 . Hereinafter, processor execution state information included in learning data may be referred to as learning execution state information.

The learning execution state information includes, for example, core execution state information for each core 21 and the execution time of the entire delayed data parallel processing. The core execution state information included in the learning execution state information includes, for example, the execution time of parallel individual processing, the number of instructions executed in parallel individual processing, the number of cache misses during execution of parallel individual processing, and the number of cache misses during execution of parallel individual processing. stall count.

When learning the first neural network, the model learning unit 360 inputs learning data to the input layer of the first neural network. Model learning section 360 then adjusts the parameters of the first neural network so that the error of the output data output from the output layer of the first neural network with respect to the teacher data is reduced. More specifically, the model learning unit 360 inputs the learning execution state information included in the learning data to the input layer of the first neural network. Then, the model learning unit 360 obtains the learning execution state information for the output data (in other words, the delay amount 232) output from the output layer of the first neural network when the learning execution state information is input to the input layer. The parameters are adjusted so that the error with respect to the reference delay amount 232 corresponding to is small. As a parameter adjustment method, an error backpropagation method may be adopted, or another method may be adopted. When parameter tuning is complete, parameter learning ends. The adjusted parameters and learned parameters are stored in the storage device 301 . The learned parameters in the storage device 301 are written into the memory 23 of the processor system 2 through the writing device 35, for example. In the processor system 2, the learned parameters are used to update the delay amount 232. FIG. Note that the method of learning the parameters of the first neural network is not limited to this.

In this embodiment, the delay update device 250 further includes an updating unit 252a shown in FIG. The updating unit 252a has a trained model 460a. The updating unit 252a updates the delay amount 232 using the trained model 460a. In this example, the update unit 252 described above is used to generate teacher data and learning data, and after the learned parameters are generated, the update unit 252a is used to update the delay amount 232. FIG.

The trained model 460a is composed of, for example, a second neural network including trained parameters generated by the model learning unit 360. FIG. The second neural network has the same configuration as the first neural network. The processor execution state information 600 acquired by the acquisition unit 251 is input to the input layer of the second neural network. The second neural network performs an operation based on learned parameters on the processor execution state information 600 input to the input layer, and outputs the delay amount 232 from the output layer. As a result, the delay amount 232 is output from the output layer of the second neural network such that the delayed parallel individual processing ends at the same timing as the preceding parallel individual processing.

FIG. 17 is a flowchart showing an example of update processing using the update unit 252a. The update process shown in FIG. 17 may be executed during the actual operation of the processor system 2 (in other words, during the actual operation of the embedded device in which the processor system 2 is mounted), or before the actual operation of the processor system 2 ( For example, it may be executed before shipment of an embedded device in which the processor system 2 is mounted. Henceforth, the update process of FIG. 11 may be called the 1st update process, and the update process of FIG. 17 may be called the 2nd update process.

As shown in FIG. 17, steps s11 and s12 described above are performed. After that, in step s24, the updating unit 252a obtains a new delay amount 232 based on the processor execution state information 600 acquired in step s12. Specifically, the updating unit 252a inputs the processor execution state information acquired in step s12 to the input layer of the second neural network. Then, the updating unit 252 a sets the delay amount 232 output from the output layer of the second neural network as the new delay amount 232 . The updating unit 252 replaces the delay amount 232 in the memory 23 with a new delay amount 232 . As a result, the delay amount 232 in the memory 23 is updated, and the second update process ends.

Note that the second update process may be repeatedly executed during the actual operation of the processor system 2 . In this case, the second update process may be repeatedly executed periodically or irregularly. Also, the second update process may be executed according to a user's instruction.

Also, during the actual operation of the processor system 2 , first, the first update process may be repeatedly executed to update the delay amount 232 , and then the second update process may be repeatedly executed to update the delay amount 232 . In this case, learned parameters may be generated based on teacher data and learning data obtained by repeatedly executing the first update process, and the second update process may be repeatedly executed using the learned parameters.

Also, in the above example, the multi-core processor system 2 generates teacher data and learning data, but the multi-core processor system having the same configuration as the multi-core processor system 2 repeats the same process as the first update process. By executing, teacher data and learning data may be generated. In this case, the delay amount updating device 250 does not need the updating unit 252 .

Also, in the above example, the engineering tool 3 includes the model learning section 360 and the delay amount estimation model 460 , but the processor system 2 may include the model learning section 360 and the delay amount estimation model 460 . In this case, the learned delay estimation model 460 may be used as the learned model 460a.

Also, the delay amount estimation model 460 may be re-learned. In this case, new teacher data and learning data are acquired by repeatedly executing the second update process, and the delay amount estimation model 460 is re-learned based on these new teacher data and learning data. good. Then, the learned parameters of the re-learned delay amount estimation model 460 may be used to perform the second update process.

Although the processor system 2 functions as the delay update device 250 in the above example, the delay update device 250 may be provided separately from the processor system 2 . In this case, the processor system 2 may not be included in the processing system 1 including the engineering tool 3 and the delay update device 250 . That is, a system may be constructed that includes the processing system 1 that includes the engineering tool 3 and the delay update device 250, and the processor system 2 that is separate from it.

While the present disclosure has been described in detail, the foregoing description is, in all respects, illustrative and not restrictive. It is understood that a myriad of variations not illustrated may be envisioned.

In addition, it is possible to freely combine each embodiment, and to modify or omit each embodiment as appropriate.

1 processing system, 2 multi-core processor system, 20 multi-core processor, 21, 21a, 21b, 21c, 21d core, 22 shared cache, 30 program creation device, 231 update program, 250 delay amount update device, 251 acquisition unit, 252, 252a Update unit, 320 identification unit, 330 generation unit, 301a program.

Claims (4)

A delay amount for processing a program created by a program creation device that creates a program to be executed by the multi-core processor of a multi-core processor system comprising a multi-core processor including a plurality of cores and a shared cache shared by the plurality of cores an update device,
The programming device is
a specifying unit for specifying a target partial program, which is a target partial program to be converted into a data parallel program in which data parallel processing is described, in the processing target program;
In the plurality of cores, the target partial program is converted into the data parallel program in which the data parallel processing is described such that the processing start timing of some cores is delayed from the processing start timing of the other cores. and a generation unit that generates an execution target program including the data parallel program obtained thereby;
with
The delay update device,
an acquisition unit that acquires execution state information indicating an execution state of the data parallel processing in the multi-core processor;
an updating unit that updates, based on the execution state information, a delay amount of processing start timing in the part of the cores in the data parallel processing described in the data parallel program;
with
The delay update device, wherein the execution state information includes an execution time of the data parallel processing in the part of the cores and an execution time of the data parallel processing in the other cores. The delay amount update device according to claim 1,
The delay amount updating device, wherein the update unit updates the delay amount using a learned model that outputs the delay amount when the execution state information is input. A delay amount update device according to claim 1 or claim 2,
the program creation device for generating the data parallel program to be targeted in the delay update device;
A processing system comprising: In a multi-core processor system comprising a multi-core processor including a plurality of cores and a shared cache shared by the plurality of cores, a program creation device creates a program to be executed by the multi-core processor. A program for executing
The programming device is
a specifying unit for specifying a target partial program, which is a target partial program to be converted into a data parallel program in which data parallel processing is described, in the processing target program;
In the plurality of cores, the target partial program is converted into the data parallel program in which the data parallel processing is described such that the processing start timing of some cores is delayed from the processing start timing of the other cores. and a generation unit that generates an execution target program including the data parallel program obtained thereby;
with
The program, in a computer device,
obtaining execution state information indicating an execution state of the data parallel processing in the multi-core processor;
a step of updating the delay amount of the processing start timing of the some cores in the data parallel processing described in the data parallel program based on the execution state information;
and
The program according to claim 1, wherein the execution state information includes an execution time of the data parallel processing in the part of the cores and an execution time of the data parallel processing in the other cores.

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