JP7306852B2 - discharge circuit - Google Patents

Description

The present invention relates to a discharge circuit.

The following techniques are known as techniques related to the discharge circuit. For example, the discharge circuit described in Patent Document 1 has a function of releasing residual charges.

JP 2015-097443 A

In relation to the functions described above, the discharge circuit is provided, for example, in a microcomputer circuit that receives power (power supply voltage VDD) from a power supply circuit. When the power supply circuit is cut off, the voltage in the microcomputer circuit (the circuit internal voltage VDDL generated from the power supply voltage VDD) theoretically has the same speed as the power supply voltage VDD decreases, as shown in FIG. Decrease in speed. The circuit internal voltage VDDL continues to drop below the reset threshold voltage VRST. After that, when the power supply circuit is turned on again, since the circuit internal voltage VDDL is lower than the reset threshold voltage VRST as described above, the entire system including the microcomputer circuit is normally reinitialized.

However, the circuit internal voltage VDDL actually decreases more gently than the power supply voltage VDD decreases, as shown in FIG. . Therefore, as shown in FIG. 8, if the power supply circuit is turned on again before the circuit internal voltage VDDL falls below the reset threshold voltage VRST, there is a risk that the re-initialization of the system described above will not be performed normally. There is

In order to avoid the situation described above, in the microcomputer circuit described above, the activation unit activates the detection unit by detecting that the power supply voltage VDD has started to decrease. Further, the detection section activates the discharge section by detecting that the circuit internal voltage VDDL has fallen below a predetermined threshold voltage. The discharge circuit discharges charges already accumulated by the circuit internal voltage VDDL in order to lower the circuit internal voltage VDDL at high speed. Thereby, as shown in FIG. 7, it is possible to ensure that the circuit internal voltage VDDL is lower than the reset threshold voltage VRST.

However, since the above-described microcomputer circuit requires the above-described start-up section and detection section in addition to the discharge section, the circuit scale and power consumption become large, and the circuit can be operated with low current consumption. As a result, there is a problem that the required time until the start-up described above becomes longer, that is, the responsiveness deteriorates.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a discharge circuit that does not increase the circuit scale and power consumption, has good responsiveness, and is capable of discharging.

In order to solve the above problems, the discharge circuit according to the present invention includes:
a discharge unit that discharges electric charges accumulated due to a second voltage generated from the first voltage when a control voltage higher than a predetermined voltage is supplied;
A differential amplifier that supplies a voltage obtained by amplifying a voltage difference between the first voltage and the second voltage to the discharge unit as the control voltage when a control current larger than a predetermined current is supplied. and,
a bias unit that supplies the control current larger than the predetermined current to the differential amplifier unit when the first voltage becomes lower than the second voltage;
including.

According to the discharge circuit of the present invention, the bias section supplies the control current larger than the predetermined current to the differential amplifier when the first voltage becomes lower than the second voltage. and the differential amplifying section amplifies a voltage difference between the first voltage and the second voltage as the control voltage when the control current larger than the predetermined current is supplied. to the discharge section, and the discharge section discharges accumulated charge due to a second voltage generated from the first voltage when the control voltage higher than the predetermined voltage is supplied. do. As a result, the discharge circuit according to the present invention can perform the discharge without using the conventional drive section and detection section, and as a result, the circuit scale and power consumption of the discharge circuit can be reduced compared to the conventional one At the same time, it becomes possible to improve the responsiveness as compared with the conventional art.

1 shows the configuration of a differential amplifier unit according to an embodiment of the present invention; 1 shows the configuration of a discharge circuit according to an embodiment of the present invention; 4 shows the operation of the discharge circuit according to the embodiment of the present invention; 1 shows the configuration of a differential amplifier unit according to an embodiment of the present invention; 4 shows the configuration of a differential amplifier unit according to Modification 1 of the present invention. FIG. 11 shows the configuration of a differential amplifier unit according to Modification 2 of the present invention; FIG. Theoretical waveforms of the power supply voltage and the circuit internal voltage when the power supply circuit is cut off and turned on again are shown. The actual waveforms of the power supply voltage and the circuit internal voltage when the power supply circuit is cut off and turned on again are shown.

<Embodiment>
A discharge circuit according to an embodiment of the present invention will be described below with reference to the drawings.

<Configuration of Embodiment>
FIG. 1 shows the configuration of a differential amplification unit according to an embodiment. FIG. 2 shows the configuration of the discharge circuit according to the embodiment. As shown in FIG. 2, the discharge circuit 1 of the embodiment monitors an external voltage VDD applied from the outside, and the external voltage VDD is higher than the internal voltage VDDL (a voltage generated from the external voltage VDD by a regulator 40 described later). The basic idea is that when it goes low, the internal voltage VDDL will start discharging the charge already stored in the capacitor 50 . Under this concept, the discharge circuit 1 includes a differential amplifier section 10, a discharge section 20, a bias section 30, a regulator 40, and a capacitor 50, as shown in FIG. Here, the external voltage VDD corresponds to the "first voltage" and the internal voltage VDDL corresponds to the "second voltage".

The current-driven differential amplifier section 10 and the discharge section 20 are schematically represented as one differential amplifier unit 100 as shown in FIG. The differential amplifier unit 100 has two input terminals in+ and in-, one output terminal Vout, two power supply terminals VDD and GND (ground), and two control terminals pgnb and ibp.

The differential amplifier unit 100 amplifies the voltage difference between the voltage (same as VDD) input to the input terminal in+ and the voltage (same as voltage VDDL) input to the input terminal in−, and converts the voltage after amplification into Depending on the magnitude, the discharge is performed or stopped.

The control terminal pgnb is used to define a monitoring point for monitoring fluctuations in the external voltage VDD. The control terminal ibp is used to control the operation of the differential amplifier unit 100 (activation state, state close to non-activation) by current.

2, in the differential amplifier section 10, the input terminal in+ is connected to the control terminal pgnb, so that the voltage VDD supplied to the control terminal pgnb is applied to the input terminal in+. The voltage of the output terminal Vout (same as the internal voltage VDDL) is applied to the input terminal in-, as described above. The control terminal ibp is connected to the bias section 30, and the current from the bias section 30 has a magnitude that allows the differential amplification section 10 to operate sufficiently, or a magnitude that does not stop the operation. of current. The output terminal of the differential amplifier section 10 is connected to the discharge section 20, and more specifically, to the gate of the MOS transistor in the discharge section 20, for example.

When the discharge unit 20 receives a voltage from the differential amplifier unit 10 that is large enough to activate the discharge unit 20 (more precisely, the MOS transistor), the internal voltage VDDL causes the capacitor 50 to It has the function of discharging the accumulated charge. In order to perform this function, the MOS transistor of the discharge section 20 has its drain connected to the output terminal of the regulator 40 and one electrode of the capacitor 50, and its source and its back gate connected to the ground potential and the capacitor. 50 is connected to the other electrode. Here, the voltage output by the differential amplifier 10 corresponds to the "control voltage".

The bias unit 30 receives voltage Vref1 (same as the external voltage VDD) and voltage Vref2 (same as the internal voltage VDDL) and outputs a current ibp. Normally, ie, when the external voltage VDD is higher than the internal voltage VDDL, the bias unit 30 supplies the differential amplifier unit 10 with a current ibp large enough to prevent the operation of the differential amplifier unit 10 from stopping. On the other hand, the bias unit 30 allows the differential amplifier unit 10 to operate sufficiently when the power supply circuit (not shown) that supplies the external voltage VDD is cut off, that is, when the external voltage VDD is lower than the internal voltage VDDL. A current ibp of a magnitude that can be used is supplied to the differential amplifier 10. Here, the current ibp corresponds to the "control current".

As described above, the regulator 40 generates the internal voltage VDDL from the external voltage VDD and outputs the generated internal voltage VDDL from the terminal Vout.

Capacitor 50 is connected between the output end of regulator 40 and the ground potential to smooth the internal voltage VDDL output from regulator 40 .

<Configuration of Embodiment>
FIG. 3 shows the operation of the discharge circuit according to the embodiment. The operation of the discharge circuit of the embodiment will be described below with reference to FIG. In the following, it is assumed that the external voltage VDD is initially higher than the internal voltage VDDL and then begins to drop at time t1. Also, it is assumed that the discharge unit 20 is initially in a non-activated state (off state).

Since the external voltage VDD is higher than the internal voltage VDDL until time t1, the bias unit 30 does not drive the differential amplifier unit 10 using the current ibp. More specifically, the bias unit 30 supplies the differential amplifier unit 10 with a current ibp that does not stop the operation of the differential amplifier unit 10 .

At time t1, the external voltage VDD begins to drop. After time t1, the internal voltage VDDL also begins to drop under the influence of the external voltage VDD.

At time t2, external voltage VDD becomes lower than internal voltage VDDL. Thereby, the bias unit 30 supplies the differential amplifier unit 10 with a current ibp of a magnitude that allows the differential amplifier unit 10 to operate sufficiently. When the current ibp is supplied, the differential amplifying section 10 starts differential amplifying operation.

After time t2, the external voltage VDD continues to drop. Thereby, the voltage difference between the external voltage VDD and the internal voltage VDDL becomes larger than the predetermined voltage difference. Here, the "predetermined voltage difference" means, for example, if the predetermined voltage difference is amplified, the voltage after the amplification has a magnitude that can activate the MOS transistor in the discharge section 20. is the voltage difference that will have At this point, the differential amplifier 10 outputs a voltage capable of activating the MOS transistor in the discharge section 20 to the gate of the MOS transistor. Upon receiving this voltage, the discharge section 20 starts the discharge operation by being activated (turned on), that is, discharges the charge accumulated in the capacitor 50 up to that point. .

At time t3, the internal voltage VDDL falls below the voltage at which each section in the discharge circuit 1 can operate. As a result, for example, the differential amplifier section 10 cannot output a voltage large enough to drive (turn on) the discharge section 20 . As a result, the discharge section 20 enters a non-activated state (off state), that is, stops discharging.

<Effect of the embodiment>
As described above, in the discharge circuit 1 according to the embodiment, when the external voltage VDD becomes lower than the internal voltage VDDL, the bias section 30 causes the current ibp large enough to allow the differential amplifier section 10 to operate sufficiently. The dynamic amplifier 10 is energized. Further, when the voltage difference between the external voltage VDD and the internal voltage VDDL becomes larger than a predetermined voltage, the differential amplifier 10 outputs a voltage large enough to operate the discharge unit 20 to the discharge unit 20. . As a result, the discharge unit 20 can start discharging the charge accumulated up to that point in the capacitor 50 due to the internal voltage VDDL. In other words, the discharge section 20 does not require the drive section and the detection section that are required in the conventional discharge circuit, that is, it has a smaller circuit scale and power consumption than the conventional discharge circuit, and good responsiveness. Below, the discharge can begin.

<Concrete example>
FIG. 4 is an equivalent circuit diagram showing a specific configuration of the differential amplifier unit. A specific configuration of the differential amplifier unit will be described below with reference to FIG.

<Configuration of specific example>
The differential amplifier unit 100A shown in FIG. 4 is composed of P-channel MOS transistors as shown in FIG. 4 in order to realize the differential amplifier unit 100 shown in FIG. (Metal Oxide Semiconductor) Transistors P1 to P7 (hereinafter abbreviated as “transistor P1”, for example), N-channel MOS transistors N1 to N7 (hereinafter, abbreviated as “transistor N1”, for example), and capacitor C1 , C2.

The transistors P1 and N4 have a source-grounded configuration and are connected in series between the external voltage VDD and the ground potential to perform inversion amplification.

The source and back gate of the transistor P1 are connected to the external voltage VDD, the gate is connected to the drain of the transistor P2 and the drain of the transistor N1, and the drain is connected to the control terminal ibp (bias section 30 (see FIG. 2). ) and the drain of a transistor N4, and a capacitor C1 is connected between the gate and the drain.

For transistor N4, the gate is connected to the gate of transistor N5, the drain and gate are connected together, and the source and backgate are connected to ground potential.

Transistors P2, P4, N1, N3 have a first differential amplification function. Also, the transistors P3, P4, N2, and N3 have a second differential amplification function. For example, regarding the relationship between transistor P2 and transistor N1, the source and back gate of transistor P2 are connected to the external voltage VDD, the gate is connected to the gate of transistor P3 and the gate of transistor P4, and the drain are connected to the drain of the transistor N1, the sources of the transistors N1, N2, and N3 are connected together and to the drain of the transistor N5.

The relationship between the transistor P3 and the transistor N2 and the relationship between the transistor P4 and the transistor N3 are the same as the relationship between the transistor P2 and the transistor N1.

Further, the gates of the transistors N1 and N2 are connected to the terminal in-, the gates of the transistors N3 are connected to the terminal in+, and the back gates of the transistors N2 and N3 are grounded. connected to a potential.

The gates of the transistors P3 and P4, the drains of the transistors P4 and N3, the gate of the transistor P5, and the terminal pgnb are connected to each other. Here, the terminal pgnb and the terminal in+ are interconnected as shown in FIG. 2 (not shown in FIG. 4).

For transistor P5, the source and backgate are connected to the external voltage VDD, and the drain is connected to the drain of transistor N6.

The transistor P6 has a gate connected to the drains of the transistors P3 and N2, a source and a backgate connected to the power supply voltage VDD, and a drain connected to the drain of the transistor N7, the gate of the transistor N8, and the gate of the transistor N8. , is connected to one electrode of the capacitor C2.

Transistor N6 and transistor N7 have a current sink function. For transistor N6, the gate and drain are connected together, the gate is connected to the gate of transistor N7, and the source and backgate are connected to ground potential.

The source and backgate of transistor N7 are connected to the ground potential. Here, regarding the characteristics of the transistor N7, its threshold voltage is smaller than the threshold voltages of the other transistors.

The transistor P7 has a gate connected to the external voltage VDD, a source and a back gate connected to the output terminal Vout, the other electrode of the capacitor C2 and the drain of the transistor N8, and a drain connected to the ground. connected to a potential.

The source and backgate of transistor N8 are connected to the ground potential.

<Operation of specific example>
The operation of the differential amplification unit according to the embodiment will be described.

1. When the external voltage VDD is higher than the internal voltage VDDL (when the voltage at the terminal in+ is higher than the voltage at the terminal in−)
Transistor P5 is in a cut-off state, so transistors N6 and N7 are also in a cut-off state. Thereby, the transistor N8 is cut off, ie the drain of the transistor N8 is open. As a result, the internal voltage VDDL, which is the voltage output by the regulator 40, is applied to the output terminal Vout, as shown in FIG.

2. When the external voltage VDD becomes lower than the internal voltage VDDL (when the voltage of the terminal in+ becomes lower than the voltage of the terminal in−)
When the external voltage VDD becomes lower than the internal voltage VDDL, the transistors P2 and P3 become conductive. The conduction of the former transistor P2 causes the transistor P1 to be in a conducting state. On the other hand, the conduction of the latter transistor P3 causes the transistor P6 to become conductive, and the conduction of the transistor P6 causes the transistor N8 to become conductive.

In addition to the above, when external voltage VDD becomes lower than internal voltage VDDL, transistors N1 and N2 are rendered conductive, and transistor P7 is rendered conductive.

Due to the conduction of transistor N8 and the conduction of transistor P7, as described above, transistors N8 and N7 begin to discharge the charge stored in capacitor 50 (shown in FIG. 2). In addition, since the threshold voltage of transistor P7 is lower than the threshold voltages of the other transistors, the internal voltage VDDL has dropped to such an extent that the other transistors cannot operate after time t3 (shown in FIG. 3). Even later, the discharge operation can be continued.

As for the power source of the current-driven differential amplifier unit 100A, a small amount of current ibp continues to flow. N5 becomes conductive. The conduction of transistors N4, N5 causes a large current flow in the path through transistors P1, N4 and in the path through transistors P2, N1, N5.

<Modification 1>
FIG. 5 shows the configuration of a differential amplifier unit according to Modification 1. As shown in FIG. The differential amplifier unit of Modification 1 will be described below with reference to FIG.

The differential amplifier unit 100B of Modification 1 basically has the same configuration as the differential amplifier unit 100A of the specific example. On the other hand, the differential amplifier unit 100B of Modification 1 further includes three resistors R2, R3, R4, unlike the differential amplifier unit 100A of the specific example. Resistors R2, R3, R4 have resistance values r2Ω, r3Ω, r4Ω. Also, for ease of explanation and understanding of Modification 1, the threshold voltage of the transistor is not considered. Here, the three resistors R2, R3, R4 correspond to the "voltage drop section".

A resistor R4 is provided between the drain of the transistor P4 and the drain of the transistor N3. Since the differential amplification unit 100B also has two differential amplification functions like the differential amplification unit 100A of the specific example, a resistor R2 is provided between the drain of the transistor P2 and the drain of the transistor N1. , and a resistor R3 is provided between the drain of the transistor P3 and the drain of the transistor N2.

Assuming that a current Ids4 flows through the transistor P4 due to the provision of the resistor R4, the voltage at the terminal pgnb is obtained by subtracting the voltage dropped by the resistor R4, that is, r4×Ids4, from the external voltage VDD. It becomes the voltage [VDD-r4×Ids4].

Terminal in+ and terminal pgnb are interconnected as shown in FIG. Therefore, in the differential amplifier unit 100A of the specific example, the voltage of the drain of the transistor P4, which is the voltage applied to the terminal pgnb, ie, the power supply voltage VDD, is applied to the terminal in+ as it is. In contrast, in the differential amplifier unit 100B of Modification 1, a voltage [VDD−R4×Ids4] smaller than the power supply voltage VDD is applied to the terminal in+ instead of the power supply voltage VDD in the specific example. As a result, it is possible to advance the timing of starting the discharge, which is the time when the power supply voltage VDD becomes lower than the internal voltage VDDL. Also, by changing the resistance values of the resistors R4, R2, and R3, it is possible to adjust the timing described above. More specifically, if the resistance value is increased, the above timing can be greatly advanced. Conversely, if the resistance value is decreased, the above timing can be advanced slightly. Note that the resistors R2, R3, and R4 may be configured using variable resistors having variable resistance values.
<Modification 2>
FIG. 6 shows the configuration of a differential amplifier unit according to Modification 2. As shown in FIG. The differential amplifier unit of Modification 2 will be described below with reference to FIG.

The differential amplification unit 100C of Modification 2 basically has a configuration common to the differential amplification unit 100A of the specific example and the differential amplification unit 100B of Modification 1. FIG. On the other hand, the differential amplification unit 100C of Modification 2 differs from the differential amplification unit 100B of Modification 1 in that instead of the three resistors R2, R3, and R4, transistors P2-1 to P2-3, It includes transistors P3-1 to P3-3 and transistors P4-1 to P4-3. Here, the transistors P2-1 to P2-3, the transistors P3-1 to P3-3, and the transistors P4-1 to P4-3 correspond to the "voltage drop section".

The transistors P4-1 to P4-3 are provided between the drain of the transistor P4 and the drain of the transistor N3, and are cascode-connected (cascade-connected) to each other, similar to the resistor R4 in Modification 1. . Further, the back gates of the transistors P4, P4-1 to P4-3 are mutually connected and connected to the external voltage VDD.

Since the differential amplification unit 100C also has two differential amplification functions, the transistors P2-1 to P2-3 are provided between the drain of the transistor P2 and the drain of the transistor N1, and are cascode-connected to each other. there is Further, the back gates of the transistors P2, P2-1 to P2-3 are interconnected and connected to the external voltage VDD. Similarly, transistors P3-1 to P3-3 are provided between the drain of transistor P3 and the drain of transistor N2 and are cascode-connected to each other. Further, the back gates of the transistors P3, P3-1 to P3-3 are connected together and to the external voltage VDD.

Since the cascode-connected transistors P4-1 to P4-3 are provided, the voltage applied to the terminal pgnb, that is, the terminal in+ is applied to the transistors P4-1 to P4 rather than the external voltage VDD, as in the first modification. -3 can be set lower by the sum of the threshold voltages. As a result, as in the first modification, it is possible to advance the timing of starting the discharge. In addition, by changing the number of cascade-connected transistors, it is possible to adjust the timing of starting the above-described discharge. More specifically, if the number of cascade-connected transistors is increased, the above timing can be greatly advanced. Conversely, if the number of cascade-connected transistors is decreased, the above timing can be slightly advanced.

<Other inventions>
Another discharge circuit according to the present invention comprises:
A discharge section that discharges charges accumulated due to an internal voltage that is generated from an external voltage that is applied from the outside, and that enables or disables the discharging of the discharge section. the discharge unit receiving the application of the control voltage of
receiving inputs of the external voltage and the internal voltage, generating the control voltage by amplifying a voltage difference between the external voltage and the internal voltage, and wherein the voltage difference is greater than a predetermined voltage difference; a differential amplifier for applying the control voltage for permitting the discharge by the discharge unit to the discharge unit, the control current for controlling permission or prohibition of the amplification of the differential amplifier unit. the differential amplifier section that receives current;
a bias unit that applies the control current that permits the amplification by the differential amplifier unit to the differential amplifier unit when the external voltage becomes smaller than the internal voltage;
including.

According to another discharge circuit of the present invention, when the external voltage becomes smaller than the internal voltage, the bias section reduces the control current that permits the amplification by the differential amplification section to the differential amplification section. and the differential amplifier allows the discharge by the discharge unit when the voltage difference between the external voltage and the internal voltage becomes greater than a predetermined voltage difference. A voltage is applied to the discharge section. As a result, the discharge section starts discharging the charges accumulated due to the internal voltage. Therefore, unlike the conventional discharge circuit, the discharge circuit according to the present invention can perform the discharge without using the drive section and the detection section. As a result, the circuit scale and power consumption of the discharge circuit can be reduced. In addition, it is possible to improve the responsiveness as compared with the conventional art.

1 Discharge Circuit 10 Differential Amplifier Part 20 Discharge Part 30 Bias Part 40 Regulator 50 Capacitor 100 Differential Amplifier Unit

Claims (4)

a discharge unit that discharges electric charges accumulated due to a second voltage generated from the first voltage when a control voltage higher than a predetermined voltage is supplied;
A differential amplifier that supplies a voltage obtained by amplifying a voltage difference between the first voltage and the second voltage to the discharge unit as the control voltage when a control current larger than a predetermined current is supplied. and,
a bias unit that supplies the control current larger than the predetermined current to the differential amplifier unit when the first voltage becomes lower than the second voltage;
a discharge circuit including The differential amplifier section has a voltage drop section that drops the first voltage, and controls the voltage obtained by amplifying the voltage difference between the first voltage and the second voltage dropped by the voltage drop section. 2. A discharge circuit according to claim 1, which outputs as a voltage. 3. The discharge circuit of claim 2, wherein said voltage drop portion comprises a resistor. 3. The discharge circuit of claim 2, wherein the voltage drop portion comprises a plurality of cascaded transistors.

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