JP7308635B2 - Multi-channel circuit - Google Patents

Description

The present invention relates to multi-channel circuits.

Patent Document 1 below discloses a technique of providing a crosstalk elimination circuit between a sample-and-hold circuit and an A/D converter in an image pickup device using a solid-state image pickup device having left and right horizontal two-channel simultaneous outputs. .

JP-A-2002-044530

By the way, in the background art described above, since a crosstalk elimination circuit is provided between the sample-and-hold circuit and the A/D converter for each channel, the number of crosstalk elimination circuits corresponding to the number of channels is required. However, an increase in the number of crosstalk elimination circuits is not preferable because it causes an increase in cost, an increase in mounting area, and the like.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and provides a multi-channel A/D converter capable of suppressing crosstalk between channels while suppressing an increase in cost and an increase in mounting area. With the goal.

In order to achieve the above object, the present invention provides a multi-channel circuit as a first means for solving a multi-channel circuit, which performs predetermined signal processing on multi-channel input signals, comprising a plurality of input terminals, an input a multiplexer whose ends are respectively connected to the input terminals and which sequentially selects the input terminals and connects them to an output terminal; an amplifier whose input terminals are connected to the output terminals of the multiplexer; and whose input terminals are the amplifiers. and a single signal processing unit that performs predetermined signal processing on the input signal, and a control unit that controls the multiplexer. A means for controlling the multiplexer is employed so that the input signal is input in an order in which the residual charge of the input signal is further reduced.

In the present invention, as a second solution related to a multi-channel circuit, in the first solution, a plurality of the amplifiers are provided in a state of being connected in parallel, and the output terminals of the plurality of amplifiers are selectively connected. An amplifier selection circuit is further provided for selecting and connecting to the signal processing section, and the control section controls the multiplexer and the A means of controlling the amplifier selection circuit is adopted.

In the present invention, as a third solution related to a multi-channel circuit, in the first solution, a plurality of the amplifiers are provided in a state of being connected in parallel, and the output ends of the plurality of amplifiers are selectively connected. An amplifier selection circuit that selects and connects to the signal processing unit is further provided, and the control unit selects the input signal with the highest signal impedance as the first when the number of the input terminals is larger than the number of channels of the input signal. The multiplexer and the amplifier selection circuit are controlled so that the input signal is continuously input to the signal processing unit with no signal placed in the middle.

According to the present invention, as a fourth solving means related to a multi-channel circuit, in any one of the first to third solving means, the signal processing unit performs A/D conversion processing on the input signal. A means of being a conversion circuit is adopted.

In the present invention, as a fifth solution related to a multi-channel circuit, in the above fourth solution, the input signal is a voltage signal indicating a battery voltage, and the signal processing section converts the voltage signal into an A/ A means of detecting the battery voltage through D conversion processing is employed.

ADVANTAGE OF THE INVENTION According to this invention, it is possible to suppress the crosstalk between channels, suppressing the increase in cost and mounting area compared with the past.

1 is a circuit diagram showing the configuration of a battery voltage detection device according to an embodiment of the present invention; FIG. 4 is a first characteristic table showing the order in which input signals (voltage signals) are taken in an embodiment of the present invention; 4 is a second characteristic table showing the order of input signals (voltage signals) taken in according to one embodiment of the present invention.

An embodiment of the present invention will be described below with reference to the drawings.
The battery voltage detection device according to the present embodiment takes in voltages (cell voltages) of a large number of battery cells that make up an assembled battery as multi-channel input signals, and performs A/D conversion processing on the input signals as predetermined signal processing. It is a multi-channel circuit. This battery voltage detection device comprises an input section 1, a self-diagnostic function section 2, a multiplexer 3, an amplifier section 4 and a processor 5, as shown in FIG.

The input section 1 has 1st to 20th input terminals, but FIG. 1 shows the 1st to 9th terminals for the sake of convenience. As shown in FIGS. 1 and 2, the first input terminal has the terminal name "AN000", the second input terminal has the terminal name "AN001", and the third input terminal has the terminal name "AN002". be.

The terminal name of the fourth input terminal is "AN003", the terminal name of the fifth input terminal is "AN010", and the terminal name of the sixth input terminal is "AN011". The terminal name of the seventh input terminal is "AN012", and the terminal name of the eighth input terminal is "AN013". The terminal name of the ninth input terminal is "AN020".

As shown in FIG. 2, the tenth input terminal has a terminal name of "AN021", the eleventh input terminal has a terminal name of "AN022", and the twelfth input terminal has a terminal name of "AN023". . The thirteenth input terminal has a terminal name of "AN030", the fourteenth input terminal has a terminal name of "AN031", and the fifteenth input terminal has a terminal name of "AN032".

The 16th input terminal has a terminal name of "AN033", the 17th input terminal has a terminal name of "AN040", and the 18th input terminal has a terminal name of "AN041". The 19th input terminal has a terminal name of "AN042", and the 20th input terminal has a terminal name of "AN043".

Most of the 1st to 20th input terminals (13) are assigned functions as shown in FIG. It is a terminal (no signal terminal). Multi-channel voltage signals are input from the outside as input signals to the terminals to which the functions are assigned. That is, in the input section 1 of the present embodiment, the number of input terminals (20) is set larger than the number of input signal channels (13).

That is, the first input terminal AN000 is a terminal to which the voltage signal of the first channel (system power supply voltage input 1) is input, the second input terminal AN001 is an empty terminal (no signal terminal), and the third input terminal AN002 is a terminal to which the second channel voltage signal (system power supply voltage input 2) is input. The fourth input terminal AN003 is an empty terminal (no signal terminal), the fifth input terminal AN010 is a terminal to which the voltage signal of the third channel (sensor voltage input 9) is input, and the sixth input terminal AN011 is an empty terminal. (no signal terminal).

The seventh input terminal AN012 is a terminal to which the voltage signal of the fourth channel (sensor voltage input 10) is input, the eighth input terminal AN013 is a blank terminal (no signal terminal), and the ninth input terminal AN020 is a fifth input terminal. This is the terminal to which the channel voltage signal (battery voltage) is input. The tenth input terminal AN021 is a blank terminal (no signal terminal), the eleventh input terminal AN022 is a terminal to which the voltage signal (internal power supply voltage) of the sixth channel is input, and the twelfth input terminal AN023 is a blank terminal ( no signal terminal).

The 13th input terminal AN030 is a terminal to which the voltage signal of the 7th channel (I/F identification input 1) is input, and the 14th input terminal AN031 is the terminal to which the voltage signal of the 8th channel (I/F identification input 2) is input. It is a terminal to be connected. The 15th input terminal AN032 is a terminal to which the 9th channel voltage signal (sensor voltage input 1) is input, and the 16th input terminal AN033 is a terminal to which the 10th channel voltage signal (sensor voltage input 3) is input. be.

The 17th input terminal AN040 is a terminal to which the 11th channel voltage signal (sensor voltage input 5) is input, and the 18th input terminal AN041 is a terminal to which the 12th channel voltage signal (sensor voltage input 7) is input. be. The 19th input terminal AN042 is a terminal to which the voltage signal (sensor voltage input 11) of the 13th channel is input, and the 20th input terminal AN043 is an empty terminal (no signal terminal).

The self-diagnostic function unit 2 is a functional element for checking the soundness of the external connection lines connected to the first to twentieth input terminals. That is, the self-diagnostic function unit 2 is a circuit for checking disconnection of an external connection line that transmits an input signal to some of the first to twentieth input terminals. It is a switching circuit provided for each.

Each opening/closing circuit is composed of a pair of opening/closing switches and a resistor as shown in the figure, and one of the opening/closing switches switches connection/disconnection between the first to twentieth input terminals and each input terminal of the multiplexer 3. At the same time, the input terminals of the multiplexer 3 are short-circuited via the resistors by the other opening/closing switch when they are not connected. Such switching circuits are controlled by the processor 5 .

The multiplexer 3 is a selection circuit having twenty input terminals a1 to a20 and five output terminals b1 to b5, and sequentially selects the input terminals a1 to a20 and connects them to the output terminals b1 to b5. The first output terminal b1 is selectively connected to any one of the input terminals a1-a20 as shown. The second output terminal b2 is selectively connected to any one of input terminal a1, input terminal a5, input terminal a9, input terminal a13, and input terminal a17.

The third output terminal b3 is selectively connected to any one of input terminal a2, input terminal a6, input terminal a10, input terminal a14, and input terminal a18. The fourth output terminal b4 is selectively connected to any one of input terminal a3, input terminal a7, input terminal a11, input terminal a15, and input terminal a19. The fifth output terminal b5 is selectively connected to any one of input terminal a4, input terminal a8, input terminal a12, input terminal a16, and input terminal a20.

Here, the first to twentieth input terminals are divided into four groups (physical channel groups). The multiplexer 3 has four output terminals b2 to b5 corresponding to the physical channel groups.

That is, the second output terminal b2 includes input terminal a1, ie, first input terminal AN000, input terminal a5, ie, fifth input terminal AN010, input terminal a9, ie, ninth input terminal AN020, input terminal a13, ie, thirteenth input terminal AN030, It corresponds to the 0th physical channel group consisting of the input terminal a17, that is, the 17th input terminal AN040.

The third output terminal b3 includes an input terminal a2 that is the second input terminal AN001, an input terminal a6 that is the sixth input terminal AN011, an input terminal a10 that is the tenth input terminal AN021, an input terminal a14 that is the fourteenth input terminal AN031, an input terminal a18 corresponds to the first physical channel group consisting of the eighteenth input terminal AN041.

The fourth output terminal b4 includes an input terminal a3 that is the third input terminal AN002, an input terminal a7 that is the seventh input terminal AN012, an input terminal a11 that is the eleventh input terminal AN022, an input terminal a15 that is the fifteenth input terminal AN032, an input terminal a19 corresponds to the second physical channel group consisting of the 19th input terminal AN042.

The fifth output terminal b5 includes an input terminal a4, i.e., the fourth input terminal AN003, an input terminal a8, i.e., the eighth input terminal AN013, an input terminal a12, i.e., the 12th input terminal AN023, an input terminal a16, i.e., the sixteenth input terminal AN033, an input terminal a20 corresponds to the third physical channel group consisting of the twentieth input terminal AN043.

The amplifier unit 4 includes first to fourth amplifiers 4a to 4d and first to fifth switches 4e to 4i provided for each physical channel group described above. A plurality (four) of the first to fourth amplifiers 4a to 4d are connected in parallel, amplify an input signal input to an input terminal with a predetermined amplification factor, and output the amplified signal to an output terminal.

Among the first to fourth amplifiers 4a to 4d, the first amplifier 4a is provided corresponding to the 0th physical channel group, and the input terminal is connected to the second output terminal b2 of the channel multiplexer 3. and the output end is connected to one contact of the second switch 4f. The second amplifier 4b is provided corresponding to the first physical channel group, the input terminal is connected to the third output terminal b3 of the channel multiplexer 3, and the output terminal is connected to one contact of the third switch 4g. It is

The third amplifier 4c is provided corresponding to the second physical channel group, has an input end connected to the fourth output end b4 of the channel multiplexer 3, and an output end connected to one contact of the fourth switch 4h. It is The fourth amplifier 4d is provided corresponding to the third physical channel group, has an input end connected to the fifth output end b5 of the multiplexer 3, and an output end connected to one contact of the fifth switch 4i. ing.

The first switch 4 e has one contact connected to the first output terminal b 1 of the multiplexer 3 and the other contact connected to the AD input terminal of the processor 5 . The second switch 4f has one contact connected to the output terminal of the first amplifier 4a and the other contact connected to the AD input terminal of the processor 5. FIG.

The third switch 4g has one contact connected to the output terminal of the second amplifier 4b and the other contact connected to the AD input terminal of the processor 5 . The fourth switch 4h has one contact connected to the output terminal of the third amplifier 4c and the other contact connected to the AD input terminal of the processor 5 . The fifth switch 4i has one contact connected to the output terminal of the fourth amplifier 4d and the other contact connected to the AD input terminal of the processor 5 .

The opening/closing operations of the first to fifth switches 4e to 4i of the amplifying section 4 are controlled by the processor 5. FIG. Among the first to fifth switches 4e to 4i, the second to fifth switches 4f to 4i constitute an amplifier selection circuit of the present invention. That is, the second to fifth switches 4f to 4i selectively select the output ends of the plurality of amplifiers, that is, the first to fourth amplifiers 4a to 4d, and connect them to the processor 5 (signal processing section).

The processor 5 is a microprocessor that detects the magnitude (amplitude) of the voltage signal by A/D-converting the voltage signal that is sequentially input through the first to fifth switches 4e to 4i and fetching it as a digital signal. . This processor 5 corresponds to a single signal processing section and control section in the present invention.

That is, the processor 5 has an A/D conversion circuit inside, and an input signal (voltage signal) is sequentially converted into voltage data, and the voltage data is processed by software to detect the magnitude (amplitude) of the voltage signal.

Further, the processor 5 determines the soundness of the external connection line by controlling the self-diagnostic function unit 2 as part of such input signal detection processing. Further, the processor 5 controls the multiplexer 3 and the amplifier 4 as part of such input signal detection processing, thereby changing the order of the input signals to be input to the A/D conversion circuit into voltage data and other voltage data. Adjust so that no crosstalk is mixed in.

Next, the operation of the battery voltage detection device according to the present embodiment, in particular, the operation of setting the order of input signals for reducing or eliminating the crosstalk by the processor 5 will be described in detail.

First, when input signals are sequentially input to the A/D conversion circuit and converted into voltage data, the processor 5 controls the multiplexer 3 and the amplifier unit 4 so that input signals common to the physical channel groups are not continuously input. to control. That is, the processor 5 controls the multiplexer 3 and the amplifier 4 to sequentially input the input signals to the A/D conversion circuit in the order indicated by the arrows in FIG.

The processor 5 causes the voltage signal (system power supply voltage input 1) belonging to the 0th physical channel group to be input to the A/D conversion circuit via the first amplifier 4a and the second switch 4f. to the A/D conversion circuit via the second amplifier 4b and the third switch 4g, and then the voltage signal (system power supply voltage input 2) belonging to the second physical channel group is input to the third amplifier 4c and the third switch 4g. Input to the A/D conversion circuit via the fourth switch 4h.

Then, the processor 5 subsequently causes the non-signal belonging to the third physical channel group to be input to the A/D conversion circuit via the third amplifier 4d and the fourth switch 4i. (sensor voltage input 9) is input to the A/D conversion circuit via the first amplifier 4a and the second switch 4f. Then, each input signal is input to the A/D conversion circuit in the order indicated by the arrows in FIG.

As for the input order (first input order) of such input signals to the A/D conversion circuit, the input signals are not continuously input to the A/D conversion circuit from the same amplifier, but the input signals are continuously input from different amplifiers. and input to the A/D conversion circuit. That is, in such a first input order, the next input signal is input before the residual charge accumulated in the amplifier due to the previous input signal is sufficiently discharged, and there is a delay between the previous input signal and the next input signal. It suppresses or prevents the occurrence of crosstalk in the

Also, the processor 5 sets a second input order as shown in FIG. 3 instead of the first input order described above. In this second input order, the input signals of the same physical channel group are continuously input to the A/D conversion circuit, and the input signal with the highest signal impedance is set first for each physical channel group. , locating a vacant terminal, that is, a no-signal state between each physical channel group.

In such a second input order, the input signal with the highest signal impedance is set in the first order of the input signals of the same physical channel group to be continuously input to the A/D conversion circuit, and the input signal in the middle (that is, each physical inter-channel crosstalk between the previous input signal and the next input signal is suppressed by placing no signal between the channel groups. However, the second input order can be adopted when the number of input terminals in the input section 1 is set to be greater than the number of channels of the input signal.

According to this embodiment, instead of providing a new circuit for suppressing crosstalk between channels, the input order of the input signals is such that the residual charge of the input signal that was previously input to the amplifier is further reduced. Since the multiplexer 3 and the amplifier selection circuits (second to fifth switches 4f to 4i) of the amplifier section 4 are controlled in this way, it is possible to suppress crosstalk between channels while suppressing an increase in cost and an increase in mounting area compared to the conventional technology. is possible.

It should be noted that the present invention is not limited to the above-described embodiments, and for example, the following modifications are conceivable.
(1) In the above embodiment, the case where A/D conversion processing is performed as the signal processing performed on the input signal has been described, but the present invention is not limited to this.

(2) Although the processor 5 controls the multiplexer 3 in the above embodiment, the present invention is not limited to this. The multiplexer 3 may be controlled by a separately provided control unit.

(3) In the above embodiment, the number of physical channel groups is four, but the present invention is not limited to this. Also, the number of input terminals is not limited to 20, of course. That is, the number of input terminals in the multiplexer 3 is not limited to twenty, and the number of output terminals is not limited to five.

1 input unit 2 self-diagnostic function unit 3 multiplexer 4 amplifier unit 4a first amplifier 4b second amplifier 4c third amplifier 4d fourth amplifier 4e first switch 4f second switch (amplifier selection circuit)
4g third switch (amplifier selection circuit)
4h Fourth switch (amplifier selection circuit)
4i Fifth switch (amplifier selection circuit)
5 processor (signal processing unit, control unit)

Claims (4)

A multi-channel circuit that performs predetermined signal processing on multi-channel input signals,
a plurality of input terminals;
a multiplexer having input terminals respectively connected to the input terminals, sequentially selecting the input terminals and connecting the input terminals to an output terminal;
an amplifier whose input is connected to the output of the multiplexer;
a single signal processing unit having its input terminal connected to the output terminal of the amplifier and performing predetermined signal processing on the input signal;
A control unit that controls the multiplexer,
The control unit controls the multiplexer so that the input signal is input in an order in which the residual charge of the input signal that was previously input to the amplifier is further reduced;
a plurality of the amplifiers are provided in a state of being connected in parallel,
further comprising an amplifier selection circuit that alternatively selects the output ends of the plurality of amplifiers and connects them to the signal processing unit;
The multi-channel circuit, wherein the control section controls the multiplexer and the amplifier selection circuit so that the input signals output from the same amplifier are not continuously input to the signal processing section. A multi-channel circuit that performs predetermined signal processing on multi-channel input signals,
a plurality of input terminals;
a multiplexer having input terminals respectively connected to the input terminals, sequentially selecting the input terminals and connecting the input terminals to an output terminal;
an amplifier whose input is connected to the output of the multiplexer;
a single signal processing unit having its input terminal connected to the output terminal of the amplifier and performing predetermined signal processing on the input signal;
A control unit that controls the multiplexer,
The control unit controls the multiplexer so that the input signal is input in an order in which the residual charge of the input signal that was previously input to the amplifier is further reduced;
a plurality of the amplifiers are provided in a state of being connected in parallel,
further comprising an amplifier selection circuit that alternatively selects the output ends of the plurality of amplifiers and connects them to the signal processing unit;
When the number of the input terminals is larger than the number of channels of the input signal, the control unit places the input signal with the highest signal impedance as the first order, and places no signals in the middle. A multi-channel circuit that controls the multiplexer and the amplifier selection circuit so that input signals are continuously input to the signal processing unit. 3. The multi-channel circuit according to claim 1 , wherein the signal processing section is an A/D conversion circuit that performs A/D conversion processing on the input signal . The input signal is a voltage signal indicating a battery voltage,
4. The multi-channel circuit according to claim 3 , wherein the signal processing section performs A/D conversion processing on the voltage signal to detect the battery voltage .

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