JP7312072B2 - Energy limiting circuit and safety barrier - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an energy limiting circuit for limiting excessive current and voltage and a safety barrier with the energy limiting circuit.

For example, Patent Document 1 discloses, as an intrinsically safe explosion-proof barrier, a barrier circuit that limits voltage with a Zener diode and reduces current with a resistor.

JP-A-55-033293

A barrier circuit using Zener diodes and resistors is simple, space-saving, and can realize an inexpensive configuration. However, such barrier circuits have delay characteristics due to Zener diodes and resistors. Therefore, it is difficult to support high-speed communication.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to realize an energy limiting circuit capable of supporting communication at a higher speed than the conventional one.

The energy limiting circuit of the present invention is a limiting circuit that limits energy by a capacitance component and a resistance component, and a separation that separates the capacitance component and the resistance component to reduce delay characteristics caused by the capacitance component and the resistance component. a circuit; More specifically, the resistance component is arranged closer to the input side than the separation circuit, and the capacitance component is arranged closer to the output side than the separation circuit. A capacitance component is connected between the signal line and ground.

In this manner, the energy limiting circuit of the present invention separates the capacitance component and the resistance component by the separation circuit to reduce the delay characteristic, so that it is possible to cope with higher speed communication.

The energy limiting circuit includes a signal processor connected to the limiting circuit, and a limiting element connected to a side of the signal processor opposite to the side to which the limiting circuit is connected to limit the energy. may be provided.

In this case, the resistance value of the resistance component in the limiting circuit can be lowered. Therefore, delay characteristics are further reduced.

Also, the energy limiting circuit may include a power supply circuit that supplies power to the separation circuit, and a second limiting circuit arranged on the input side of the power supply circuit.

That is, when a power supply circuit is connected to the isolation circuit, it is preferable to limit the energy of this power supply circuit as well.

In addition, when a plurality of the isolation circuits and the power supply circuits are provided, a backflow prevention circuit is provided between the second limiting circuit and the plurality of the power supply circuits to limit the flow of current between the power supply circuits. is preferred.

Also, the isolation circuit is specifically a buffer, and the capacitance component is a Zener diode. The Zener diode provides voltage limiting by discharging the overvoltage to ground when an overvoltage occurs.

However, the isolation circuit is not limited to a buffer, and may be, for example, a circuit in which two inverters are connected in series, a drive circuit using a comparator, a drive circuit using an FET, or the like.

The energy limiting circuit may constitute a safety barrier (intrinsically safe equipment).

According to the present invention, it is possible to realize an energy limiting circuit that can handle communications at a higher speed than before.

1 is a block diagram showing the configuration of an intrinsically safe explosion-proof system; FIG. 2 is a block diagram showing the main configuration of the barrier 1; FIG. 2 is a circuit diagram showing a configuration of a limiting circuit 13; FIG. FIG. 4 is a circuit diagram showing a power supply configuration connected to a second limiting circuit 130B; FIG. 3 is a circuit diagram showing a power supply configuration connected to a plurality of second limiting circuits 130B; FIG. 13 is a circuit diagram of a second limiting circuit 130B according to Modification 1; FIG. 13 is a circuit diagram of a second limiting circuit 130B according to Modified Example 2; FIG. 11 is a partial block diagram of a barrier 1 according to Modification 3; FIG. 13 is a circuit diagram of a first limiting circuit 130A according to Modification 4;

FIG. 1 is a block diagram showing the configuration of an intrinsically safe explosion-proof system. The intrinsically safe system comprises barrier 1 , communication equipment 2 and communication equipment 3 . Barrier 1 is an example of a safety barrier. The barrier 1 and the communication device 2 are installed in a non-hazardous place, and the communication device 3 is installed in a dangerous place under an atmosphere of combustible gas or the like. In this embodiment, as an example, the communication device 3 is an intrinsically safe device corresponding to an intrinsically safe explosion-proof structure. The barrier 1 is an intrinsically safe device (safety barrier) for preventing ignition of combustible gas in a hazardous area by limiting electrical energy such as current and voltage to the hazardous area. However, the energy limiting circuit and safety retainer of the present invention can be applied not only to communication equipment with an intrinsically safe explosion-proof structure, but also to other equipment.

FIG. 2 is a block diagram showing the main configuration of the barrier 1. As shown in FIG. Barrier 1 includes connector 11 , conversion circuit 12 , limiting circuit 13 , conversion circuit 14 , connector 15 , CR low pass filter 50 and oscillator 90 .

The connectors 11 and 15 are, for example, Ethernet (registered trademark) standard communication interfaces. The connector 11 and the connector 15 of this embodiment are compatible with the communication standard of 100BASE-TX (100 Mbps).

The conversion circuit 12 converts the serial signal received from the connector 11 into a parallel signal and outputs the parallel signal to the limiter circuit 13 . Thereby, the conversion circuit 12 functions as a serial/parallel conversion circuit. Also, the conversion circuit 12 converts the parallel signal received from the limiting circuit 13 into a serial signal and outputs the serial signal to the connector 11 . Thereby, the conversion circuit 12 also functions as a parallel/serial conversion circuit.

The conversion circuit 14 converts the serial signal received from the connector 15 into a parallel signal and outputs the parallel signal to the limiter circuit 13 . Thereby, the conversion circuit 14 also functions as a serial/parallel conversion circuit. Also, the conversion circuit 14 converts the parallel signal received from the limiting circuit 13 into a serial signal and outputs the serial signal to the connector 15 . Thereby, the conversion circuit 14 also functions as a parallel/serial conversion circuit.

Oscillator 90 outputs a clock signal to conversion circuit 12 and conversion circuit 14 . In this example, oscillator 90 outputs a first clock signal to conversion circuit 12 and a second clock signal to conversion circuit 14 . The first clock signal is output to conversion circuit 12 via CR low-pass filter 50 . The second clock signal is output to the conversion circuit 14 via the limiter circuit 13 .

FIG. 3 is a circuit diagram (a part of which is a block diagram) showing the configuration of the limiting circuit 13. As shown in FIG. Limiting circuit 13 corresponds to the energy limiting circuit of the present invention. The limiting circuit 13 includes a first limiting circuit 130A, a second limiting circuit 130B, and a third limiting circuit 130C.

The first limiting circuit 130A is inserted in each signal line of parallel signals transmitted from the conversion circuit 12 to the conversion circuit 14 . The second limiting circuit 130B is inserted in each signal line of parallel signals transmitted from the conversion circuit 14 to the conversion circuit 12 . The third limiting circuit 130C is inserted in the signal line of the second clock signal transmitted from the oscillator 90 to the converting circuit 14. FIG.

First limiting circuit 130A and second limiting circuit 130B are connected to signal lines of parallel signals transmitted and received between conversion circuit 12 and conversion circuit 14, respectively, to limit energy. The conversion circuit 14 is connected via a connector 15 to a communication device 3 installed in a hazardous area.

The first limiting circuit 130A includes a fuse 131, a constant voltage circuit 132, and a resistor 133. The third limiting circuit 130C also includes a fuse 131, a constant voltage circuit 132, and a resistor 133. The second limiting circuit 130B includes a buffer 70 in addition to the fuse 131, constant voltage circuit 132, and resistor 133. FIG.

The fuse 131 cuts when overcurrent is about to flow to protect the constant voltage circuit 132 . The constant voltage circuit 132 is composed of a plurality of Zener diodes. When an overvoltage occurs, the constant voltage circuit 132 limits the voltage applied to the signal line to a reference value or less by discharging the overvoltage to the ground. In this embodiment, the number of Zener diodes in parallel in the constant voltage circuit 132 is two, which corresponds to category ib in the intrinsically safe explosion-proof structure. The number of Zener diodes connected in parallel may be three or more. If the number of parallels is 3, it corresponds to category ia. Also, the number of Zener diodes in series in the constant voltage circuit 132 is three in this embodiment, and the constant voltage circuit 132 includes a total of six Zener diodes. However, the number of Zener diodes is not limited to this example. The number of Zener diodes is appropriately adjusted according to the desired voltage limit value and delay characteristics.

Resistor 133 is an example of a circuit that limits current. Limiting circuit 13 limits the current to a reference value or less by means of resistor 133 .

Fuse 131 has a predetermined resistance component. Constant voltage circuit 132 has a predetermined capacitance component. Therefore, the first limiting circuit 130A and the third limiting circuit 130C have low-pass filter characteristics due to the fuse 131 and the constant voltage circuit 132, respectively, with respect to the signal to be transmitted to the conversion circuit 14. FIG.

The communication device 2 and the communication device 3 are compliant with, for example, the Ethernet (registered trademark) 100BASE-TX (100 Mbps) communication standard. Therefore, the serial signal transmitted and received by communication device 2 and communication device 3 has a communication speed of 100 Mbps. As the communication speed becomes faster and the frequency becomes higher, the effect of the delay due to the low-pass filter characteristics becomes greater, resulting in data loss and abnormal communication. The barrier 1 of the present embodiment converts a serial signal into a plurality of parallel signals using a conversion circuit 12 and a conversion circuit 14, and limits the energy of each of the plurality of parallel signals to achieve a high communication speed. handle.

As an example, the conversion circuit 12 and the conversion circuit 14 convert a 100 Mbps serial signal into parallel signals driven by a 25 MHz clock, four for each transmission and reception. In this manner, the conversion circuits 12 and 14 reduce the speed of the 100 Mbps serial signal to the parallel signal driven by the 25 MHz clock, thereby reducing the effect of the delay due to the low-pass filter characteristics of the limiting circuit 13 . Therefore, barrier 1 can limit energy without lowering the communication speed between communication device 2 and communication device 3 .

Also, by reducing the capacitance component of the constant voltage circuit 132, the delay characteristic is reduced. Therefore, the barrier 1 reduces the delay characteristic by applying a relatively small capacitance component to each Zener diode that constitutes the constant voltage circuit 132 . Also, by increasing the number of Zener diodes in series, the capacitance component of the constant voltage circuit 132 is reduced, and the delay characteristic is reduced. Therefore, in the present embodiment, the number of Zener diodes in series is plural (three in this example) to reduce the delay characteristic. On the other hand, increasing the number of Zener diodes in series increases the limiting voltage value of the constant voltage circuit 132 . As the limit voltage value increases, the limit circuit 13 needs to increase the resistance value of the resistor 133 to limit the current value in order to meet the standard for intrinsically safe explosion-proof construction. Therefore, the resistance value of resistor 133 is relatively large.

As an example, in the first limiting circuit 130A of this embodiment, the resistance value of the fuse 131 is about 10Ω and the resistance value of the resistor 133 is about 150Ω. As a result, the first limiting circuit 130A limits the energy to below the reference value in the intrinsically safe explosion-proof structure while supporting high-speed communication.

On the other hand, the second limiting circuit 130B is inserted in the signal line for parallel signals transmitted from the conversion circuit 14 to the conversion circuit 12 . The second limiting circuit 130B has a resistor 133 and a constant voltage circuit 132. FIG. If resistor 133 and constant voltage circuit 132 were directly connected, delay characteristics would occur due to the large resistance value of resistor 133 . Since the resistance value of the resistor 133 is much larger than the resistance value of the fuse 131, even a slowed parallel signal driven by a clock of 25 MHz is affected by delay characteristics.

Therefore, second limiting circuit 130B separates the resistance component of resistor 133 and the capacitance component of constant voltage circuit 132 by buffer 70, and reduces the delay characteristic caused by resistor 133 and constant voltage circuit 132. FIG.

Therefore, the second limiting circuit 130B limits the energy of the signal transmitted from the converting circuit 14 to the converting circuit 12 to the reference value or less in the intrinsically safe explosion-proof structure while supporting high-speed communication.

FIG. 4 is a circuit diagram (a part of which is a block diagram) showing the power supply configuration connected to the second limiting circuit 130B. A power supply IC 200 is connected to the buffer 70 of the second limiting circuit 130B.

The power supply IC 200 supplies power to the buffer 70 to drive the buffer 70 . An input side of the power supply IC 200 is connected to a power supply limiting circuit 131B (second limiting circuit in the present invention) composed of a resistor 201, a constant voltage circuit 202, and a fuse 203. FIG. Resistor 201, constant voltage circuit 202, and fuse 203 have the same functions as resistor 133, constant voltage circuit 132, and fuse 131, respectively. Therefore, power supply limiting circuit 131B limits the energy of the power supply line for driving buffer 70 to a reference value or less for the intrinsically safe explosion-proof structure.

Next, FIG. 5 is a circuit diagram (a part of which is a block diagram) showing the power supply configuration connected to the plurality of second limiting circuits 130B. As shown in FIG. 5, the limiting circuit 13 has a plurality of power supply ICs 200 connected to each of the plurality of buffers 70 . The input sides of the plurality of power supply ICs 200 are connected to the power supply limiting circuit 131B.

Diodes 212 are arranged between the power limiting circuit 131B and the plurality of power supply ICs 200, respectively. Diode 212 is an example of a backflow prevention circuit. Diodes 212 limit current flow between the plurality of power supply ICs 200 . In this embodiment, the number of diodes in series is two, which corresponds to category ib in the intrinsically safe explosion-proof structure. Three or more diodes may be connected in series. If the number of series is 3, it corresponds to category ia.

The power lines for the plurality of buffers 70 are spaced apart from each other so as to satisfy the creepage distance required by explosion-proof standards.

Returning to FIG. 3, the third limiting circuit 130C has the same configuration as the first limiting circuit 130A. Oscillator 90 outputs first and second clock signals at 25 MHz. Conversion circuit 12 and conversion circuit 14 process bit data based on a first clock signal and a second clock signal of 25 MHz, respectively. As described above, the third limiting circuit 130</b>C has low-pass filter characteristics due to the resistance component of the fuse 131 and the capacitance component of the constant voltage circuit 132 . The second clock signal is delayed by the low pass filter characteristic. In this state, the phases of the first clock signal and the second clock signal are shifted due to the characteristics of the low-pass filter, and a communication error occurs when the phases are shifted.

Therefore, the CR low-pass filter 50 delays the first clock signal with delay characteristics corresponding to the low-pass filter characteristics. As a result, the barrier 1 eliminates phase shift between the first clock signal and the second clock signal, and synchronizes the operations of the conversion circuit 12 and the conversion circuit 14 . The configuration for delaying the first clock signal may be any configuration such as a buffer as long as it delays the signal.

As described above, the limiting circuit 13 limits the energy of all of the communication signal line, the clock signal line, and the power line connected to the communication device 3 . As a result, the limiting circuit 13 limits the energy to below the reference value in the intrinsically safe explosion-proof structure while supporting high-speed communication.

Note that the description of the present embodiment is an example in all respects, and does not limit the technical scope of the present invention. The technical scope of the present invention is indicated by the claims rather than the above-described embodiments. Furthermore, the technical scope of the present invention is intended to include all modifications within the meaning and technical scope equivalent to the claims.

For example, the separation circuit is not limited to a buffer, and may be a circuit in which two inverters are connected in series, a drive circuit using a comparator, a drive circuit using an FET, or the like.

FIG. 6 is a circuit diagram of a second limiting circuit 130B according to Modification 1. As shown in FIG. A second limiting circuit 130B according to Modification 1 includes a comparator 92 instead of the buffer 70 as a separation circuit. A resistor 133 is connected to the non-inverting input of the comparator 92 and a signal is input from the conversion circuit 14 . Power supply voltage Vcc divided by resistors 95 and 96 is input to the inverting input.

The comparator 92 turns on the signal output when the voltage value of the input signal exceeds a predetermined value (the voltage value of the inverted input), and turns off the signal output when the voltage value of the input signal is less than the predetermined value. do. Therefore, similarly to buffer 70, comparator 92 separates the resistance component of resistor 133 and the capacitance component of constant voltage circuit 132 to reduce the delay characteristic caused when resistor 133 and constant voltage circuit 132 are connected.

Further, in the second limiting circuit 130B according to Modification 1, the voltage value of the comparator 92 output signal can be adjusted by adjusting the resistance values of the resistors 95 and 96 . Therefore, the second limiting circuit 130B according to Modification 1 can adjust the voltage of the input signal to any value. For example, by lowering the voltage value of the input signal, the voltage value becomes closer to the High and Low thresholds, so switching from High to Low is quicker.

Next, FIG. 7 is a circuit diagram of a second limiting circuit 130B according to Modification 2. As shown in FIG. A second limiting circuit 130B according to Modification 2 includes an FET 80 instead of the buffer 70 as an isolation circuit. A resistor 133 is connected to the gate of the FET 80 . The source of FET 80 is connected to ground through resistor 85 . The drain of FET 80 is connected to the power line.

The FET 80 turns on when the voltage value of the input signal exceeds a predetermined value, and outputs a voltage signal corresponding to the resistance value of the resistor 85 . When the voltage value of the input signal is less than the predetermined value, the output of the signal is turned off. Therefore, like buffer 70 and comparator 92, FET 80 separates the resistance component of resistor 133 and the capacitance component of constant voltage circuit 132 to reduce the delay characteristic that occurs when resistor 133 and constant voltage circuit 132 are connected.

Further, in the second limiting circuit 130B according to Modification 2, by adjusting the resistance value of the resistor 85, it is possible to adjust the voltage value of the signal output to the conversion circuit 12 side in the subsequent stage.

Next, FIG. 8 is a partial block diagram of the barrier 1 according to Modification 3. As shown in FIG. The barrier 1 according to Modification 3 includes a limiting element 500 in the front stage of the conversion circuit 14 (that is, on the side opposite to the side to which the second limiting circuit 130B is connected).

Limiting element 500 comprises resistor 501 and coupling capacitor 502 . Limiting element 500 uses these resistors and coupling capacitor 502 to limit the energy of differential signal lines for transmitting and receiving serial signals. The barrier 1 limits the current from the conversion circuit 14 to the connector 15 to a reference value or less by the limiting element 500 . Therefore, the second limiting circuit 130B can lower the resistance value of the resistor 133. FIG. Buffer 70 has a small capacitance component in its internal circuitry. Therefore, resistor 133 and buffer 70 have slight delay characteristics. However, the barrier 1 can reduce the resistance value of the resistor 133 by including the limiting element 500 , thereby reducing the delay characteristic caused by the resistor 133 and the buffer 70 .

In this embodiment, an example is shown in which the communication speed is maintained by converting a 100 Mbps serial signal into a parallel signal driven by a 25 MHz clock using four signal lines each for transmission and reception. The number of lines is not limited to this example. For example, if the signal lines are only for transmission or only for reception, the communication speed can be reduced to 1/10 if there are 10 signal lines. The number of signal lines is appropriately set according to the target communication speed and the delay characteristics of the limiting circuit.

Also, in the present invention, it is not essential to convert serial signals into parallel signals. The present invention can reduce the delay characteristic by separating the resistance component and the capacitance component using the separation circuit. Therefore, in the present invention, if the intended communication speed can be secured by the separation circuit, the serial signal need not be converted into the parallel signal.

Moreover, the energy limiting circuit and the safety retainer of the present invention are not limited to being applied to communication equipment compatible with the Ethernet (registered trademark) standard. The energy limiting circuit and safety barrier of the present invention can also be applied to any other communication standard. Moreover, the energy limiting circuit and the safety retainer of the present invention are not limited to being connected to communication equipment, and may be connected to other general-purpose equipment.

The isolation circuit may be arranged between the fuse 131 and the constant voltage circuit 132 in the first limiting circuit 130A or the third limiting circuit 130C.

FIG. 9 is a circuit diagram of a first limiting circuit 130A according to Modification 4. As shown in FIG. As described above, the first limiting circuit 130A and the third limiting circuit 130C have delay characteristics due to the fuse 131 and the constant voltage circuit 132, respectively, with respect to the signal transmitted to the conversion circuit 14. FIG. However, in the example of FIG. 9, by placing the buffer 75 between the fuse 131 and the constant voltage circuit 132, the resistance component of the fuse 131 and the capacitance component of the constant voltage circuit 132 are separated to reduce the delay characteristics.

Similarly, for the third limiting circuit 130C, by placing the buffer 75 between the fuse 131 and the constant voltage circuit 132, the resistance component of the fuse 131 and the capacitance component of the constant voltage circuit 132 are separated to reduce the delay characteristics. can do. When the buffer 75 is arranged in the third limiting circuit 130C, the time constant of the CR low-pass filter 50 is adjusted. Alternatively, the CR low-pass filter 50 may be omitted if the delay characteristics can be greatly reduced by the buffer 75 .

1... Barrier (safety barrier)
2 Communication device 3 Communication device 11 Connector 12 Conversion circuit (signal processor)
13... Limiting circuit 14... Conversion circuit (signal processor)
15... Connector 50... CR low-pass filter (delay circuit)
70, 75... buffer (separation circuit)
80... FET (isolation circuit)
85... Resistor 90... Oscillator 92... Comparator (separation circuit)
95, 96... Resistor 130A... First limiting circuit 130B... Second limiting circuit 130C... Third limiting circuit 131... Fuse 132... Constant voltage circuit 133... Resistor 200... Power supply IC (power supply circuit)
201... Resistor 202... Constant voltage circuit 203... Fuse 212... Diode (backflow prevention circuit)
500... Limiting element 501... Resistor 502... Coupling capacitor

Claims (8)

a limiting circuit that limits energy by a capacitance component and a resistance component;
a separation circuit that separates the capacitance component and the resistance component to reduce delay characteristics caused by the capacitance component and the resistance component;
Energy limiting circuit with the resistance component is arranged closer to the input side than the separation circuit;
The capacitance component is arranged on the output side of the separation circuit.
2. The energy limiting circuit of claim 1. the capacitance component is connected between a signal line and ground;
3. An energy limiting circuit as claimed in claim 1 or claim 2. a signal processor connected to the limiting circuit;
a limiting element connected to a side of the signal processor opposite to the side to which the limiting circuit is connected and performing energy limitation;
with
4. An energy limiting circuit as claimed in any one of claims 1 to 3. a power supply circuit that supplies power to the separation circuit;
a second limiting circuit arranged on the input side of the power supply circuit;
with
An energy limiting circuit as claimed in any one of claims 1 to 4. comprising a plurality of the separation circuits and the power supply circuits;
A backflow prevention circuit is provided between the second limiting circuit and the plurality of power supply circuits,
6. The energy limiting circuit of Claim 5. the isolation circuit is a buffer;
wherein the capacitance component is a Zener diode;
7. An energy limiting circuit as claimed in any one of claims 1 to 6. comprising the energy limiting circuit according to any one of claims 1 to 7,
safety retainer.

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