JP7316902B2 - Information processing device, its control method, and program - Google Patents

Description

The present invention relates to an information processing apparatus, a control method thereof, and a program for verifying the validity of boot data when a chip such as an ASIC or CPU is started.

In recent years, security against boot-up of a central processing unit (hereinafter referred to as CPU) has been emphasized. Therefore, immediately after the power is turned on, the boot data of the main CPU of the system is checked by the control of the sub CPU to ensure that the boot data has not been altered due to tampering or deterioration over time, and then the main CPU is booted up. there is Verification of changes due to falsification or aged deterioration is collectively referred to as validity verification processing below. Since the verification process is basically a process performed when the power is turned on, it is desirable to complete the verification process as soon as possible to shorten the power-on time, considering the user's convenience.

Japanese Patent Application Laid-Open No. 2002-200002 proposes a method of completing the alteration detection process in a short time by not performing alteration detection on data that does not require verification.

Japanese Patent Application No. 2015-151988

However, the conventional technology described above has the following problems. For example, in the above conventional technology, there is a movement to implement a program that performs validity verification processing (falsification detection processing) not only for upstream software such as BIOS, but also for downstream programs such as applications, and verification processing is implemented. The amount of data to be processed also tends to increase. On the other hand, methods such as increasing the operating clock frequency during the verification process to complete the verification process in a short period of time have also been considered. However, in order to increase the operating clock frequency as much as possible without exceeding the allowable power of the chip, it is necessary to reduce power consumption as much as possible for circuits not used for verification processing.

One possible way to reduce the power consumption of circuits that are not in use is to turn off the power so that power is not supplied. In other words, it is impossible to control the power supply with fine granularity for each functional module (circuit).

The present invention has been made in view of at least one of the above problems, and is a mechanism for reducing the power consumption of verification processing by performing fine-grained clock stop control for circuits that are not used for verification processing. I will provide a.

The present invention is, for example, an information processing apparatus comprising storage means for storing boot data, power supply control means for supplying power to a plurality of blocks each having one or more circuits, and an oscillator for each circuit in each block. clock control means for controlling the supply of a clock to the boot data; first control means for executing verification processing for verifying the validity of the boot data stored in the storage means; a second control means for starting up using the successful boot data and controlling the information processing apparatus, wherein the first control means uses at least one circuit in the verification process by the power supply control means. Power is supplied to a block, power supply to a block in which no circuit is used in the verification process is cut off, a clock is supplied to the circuit used in the verification process by the clock control means, and a clock is supplied to the circuit used in the verification process. The verification process is performed while stopping clock supply to unused circuits.

According to the present invention, it is possible to reduce the power consumption of the verification process by performing fine-grained clock stop control for circuits that are not used for the verification process.

1 is a block diagram showing a data processing system according to one embodiment; FIG. 3 is a block diagram showing the internal configuration of a power control unit 122 and the detailed configuration of power control according to an embodiment; FIG. It is a figure showing the basic operational flow of the data processing system which concerns on one Embodiment. FIG. 4 is a block diagram showing internal operations during verification processing according to an embodiment; 4 is a detailed flowchart of verification processing according to an embodiment; FIG. 4 is a diagram showing power consumption of the ASIC 100 during normal operation according to one embodiment; FIG. 4 is a diagram showing power consumption of the ASIC 100 when power supply cutoff control is performed for unused circuits during verification processing according to one embodiment; FIG. 10 is a diagram showing power consumption of the ASIC 100 when power shutdown control is performed on unused circuits and frequency up is performed on circuits in use during verification processing according to an embodiment; FIG. 10 is a diagram showing power consumption of the ASIC 100 when power supply cutoff control and clock stop control are performed on unused circuits during verification processing according to an embodiment; A diagram showing the power consumption of the ASIC 100 when performing power shutdown control and clock stop control for unused circuits and performing frequency up for circuits to be used during verification processing according to an embodiment. .

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In addition, the following embodiments do not limit the invention according to the scope of claims. Although multiple features are described in the embodiments, not all of these multiple features are essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant description is omitted.

<Configuration of data processing system>
An embodiment of the invention is described below. First, with reference to FIG. 1, a configuration example of a data processing system according to this embodiment will be described. This data processing system is characterized by performing data processing operations after verifying the validity of the boot data of the main CPU when the power is turned on or after returning from sleep. In this embodiment, one information processing apparatus will be described as an example of a data processing system. However, the present invention is not intended to be limited, and may be configured as a system including multiple devices.

100 is an ASIC which is the center of operations in the data processing system. Reference numeral 101 denotes a main CPU (second control means) that performs main control of this data processing system. Reference numeral 102 denotes a sub-CPU (first control means) that performs auxiliary control of the main CPU 101 in this data processing system. A boot data storage unit 107 stores a program for booting up the main CPU 101 . It is assumed that a memory device is used in this embodiment. A boot data storage unit 108 stores a program for booting up the sub CPU 102 . It is assumed that a memory device is used in this embodiment.

In this embodiment, the sub CPU 102 is booted up prior to the main CPU 101 when power is turned on, and operates according to a program stored in the boot data storage unit 108 for the sub CPU. In this operation, a validity verification operation is performed to determine whether or not the boot data stored in the boot data storage unit 107 for the main CPU has been altered due to tampering or deterioration over time. In the following, if there is no problem with the boot-up data of the main CPU 101 through the validity verification operation, the boot-up of the main CPU 101 is performed using the program in the boot data storage unit 107 for the main CPU.

In this system, as memories connected to the ASIC 100, a memory 109 is connected in addition to the boot data storage unit 107 for the main CPU and the boot data storage unit 108 for the sub CPU. Regarding memory 109, the memory device is not used during the verification process.

Reference numeral 103 denotes an IO control unit, which includes, as lower modules, I/F modules for exchanging data with memories and various I/Fs connected to the ASIC 100 . Reference numeral 104 denotes an I/F module in the IO control unit 103, which is a memory I/F.1 serving as an I/F for data transfer with the boot data storage unit 107 for the main CPU. Reference numeral 105 denotes an I/F module in the IO control unit 103, which is a memory I/F 2 serving as an I/F for data exchange with the boot data storage unit 108 for the sub CPU. Reference numeral 106 denotes an I/F module in the IO control unit 103, which is a memory I/F 3 serving as an I/F for data exchange with the memory 109;

Reference numeral 110 denotes a data processing unit 1 which is a first data processing circuit for performing predetermined processing on data to be handled in this system. As for the data processing unit 110, the circuit is not used during verification processing. Reference numeral 111 denotes a data processing unit 2 which is a second data processing circuit for performing predetermined processing on data to be handled in this system. The internal circuit of the data processing unit 111 is divided into modules 112 and 113 as submodule units. As for module 112 , its circuitry is used during the verification process to output control signals to LEDs connected to ASIC 100 . As for module 113, we do not use that circuit during the verification process.

An LED 123 is controlled to be turned on or off by an LED control signal from the module 112 . In the present embodiment, when it is determined that the boot data for the main CPU 101 has not changed as a result of the validity verification process, the LED 123 is kept in the default off state. On the other hand, if it is determined that the boot data has changed, the LED 123 is changed from off to on to notify the user of this.

An oscillator 115 supplies a clock (CLK-OSC) for operating the ASIC 100 . In this embodiment, a clock of 10 MHz is supplied. A clock generator 116 generates a clock to be supplied to each circuit for performing internal operations of the ASIC 100 . The clock generator 116 includes at least a phase-locked loop (PLL), a frequency divider, and a clock gate circuit. The PLL generates a high speed clock from the clock input from oscillator 115 . The frequency dividing circuit generates a clock with a frequency required by each circuit based on the high-speed clock generated by the PLL. A clock gate circuit (hereinafter abbreviated as CG) is a circuit that controls supply and stop of a clock to each circuit. Regarding the clocks output from the clock generation unit 116 , CLK-A is supplied to the data processing unit 110 and CLK-B is supplied to the module 112 within the data processing unit 111 . CLK-C is supplied to the module 113 in the data processing unit 111 and CLK-D is supplied to the memory I/F 104 in the IO control unit 103 . CLK-E to the memory I/F 105 in the IO control unit 103, CLK-F to the memory I/F 106 in the IO control unit 103, CLK-G to the main CPU 101, CLK-H to the sub CPU 102, CLK- I is supplied to the clock control unit 114 which will be described later.

The internal configuration of the clock generator 116 will be described below. A PLL 117 generates a high-speed clock (CLK-PLL) for internal operations of the ASIC 100 from the input clock (CLK-OSC) from the oscillator 115 . In the normal operation of the present embodiment, a clock of 1200 MHz, which is 120 times the input clock of 10 MHz, is generated and output. Reference numeral 118 denotes a frequency dividing unit, which inputs the high-speed clock (CLK-PLL) output from the PLL 117 and divides the clock with a frequency that matches the operating frequency of each circuit in the ASIC 100 from the frequency dividing circuit A. Generated by the circuit ·I. In this embodiment, regarding the frequency of the clock generated by the frequency divider 118 when the ASIC 100 performs normal operation, CLK-A is divided by 12 to 100 MHz, and CLK-B is divided by 12 to 100 MHz. and Also, CLK-C is divided by 24 to 50 MHz, CLK-D is divided by 24 to 50 MHz, CLK-E is divided by 24 to 50 MHz, and CLK-F is divided by 24 to 50 MHz. Further, CLK-G is divided by 8 to obtain 150 MHz, CLK-H is divided by 12 to obtain 100 MHz, and CLK-I is divided by 12 to obtain 100 MHz.

Reference numeral 119 denotes a clock output control unit for inputting the clock output from the frequency dividing unit 118 and divided to the operating frequency of each processing circuit. Further, the clock output control unit 119 controls the supply and stop of the clock by the CG circuits.A to CG circuits.I according to the internal operation state such as the operation mode in the ASIC 100 . In this embodiment, when the ASIC 100 performs normal operation, the CG circuit of the clock output control unit 119 is in a state of supplying all clocks.

A clock control unit 114 has a register inside, and outputs a value set in the register as a control signal for various circuits in the clock generation unit 116 by access from the main CPU 101 or the sub CPU 102. . A PLL control signal is output to the PLL 117 in the clock generator 116 . Although detailed description using a diagram is not provided, as for the PLL control signal, a PLL control signal consisting of a plurality of bits is output in order to set the multiplication factor. Further, to each frequency dividing circuit in the frequency dividing section 118, a frequency dividing circuit control signal for setting a frequency dividing ratio for generating each clock is output. As for the frequency dividing circuit control signal, a multi-bit signal is output for each frequency dividing circuit. Also, to each CG circuit in the clock output control unit 119, a clock output control signal for controlling supply and stop of each clock is output. As for the clock output control signal, a 1-bit signal is output for each CG circuit.

A DATA bus 120 serves as a data bus for transferring data between the various CPUs, data processing units, and various control units described above. A reset control unit 121 supplies reset signals to various CPUs, data processing units, and various control units in the ASIC 100, although detailed connections are omitted in FIG. After the power is turned on, the reset control unit 121 cancels the reset of the sub CPU 102 based on the hardware sequence constructed by the internal circuit. Furthermore, the reset control unit 121 performs reset control of various CPUs, data processing units, and various control units in the ASIC 100 under the control of the sub CPU 102 and the main CPU 101 . The reset control unit 121 needs to control various resets before other CPUs and other circuits operate when the power is turned on. Therefore, the reset control unit 121 is configured to operate by the clock (CLK-OSC) output from the oscillator. .

Although not shown in detail in FIG. 1, the power control unit 122 inputs power for use in circuits within the ASIC 100 from power terminals of the ASIC 100 . Further, the power control unit 122 controls power supply/interruption to each circuit in the ASIC 100 under the control of the main CPU 101 or the sub CPU 102 . However, the power control unit 122 has a limited number of blocks for controlling power supply/interruption, as is the case with general devices, and is not a circuit capable of detailed power control for many processing modules. The power supply control unit 122 according to this embodiment is capable of power supply control of the five blocks of the data processing unit 110, the data processing unit 111, the IO control unit 103, the main CPU 101, and the sub CPU 102. FIG. As for the operating clock of the power control unit 122, the CLK-OSC input from the oscillator 115 is used.

<Power supply controller>
Next, the internal configuration of the power supply control unit 122 according to this embodiment will be described with reference to FIG. A power supply circuit 201 supplies a power supply of 1.0 V to the ASIC 100 as a power supply for operating internal circuits. The supplied power is input to the power control unit 122 .

The internal configuration of the power control unit 122 includes a power control register unit 202 and a plurality of power supply switches (hereinafter abbreviated as SW). The power supply SW is prepared for the number of blocks that control the supply/cutoff of power, and in this embodiment, there are five power supply SWs. The power supply control of the data processing unit 110 is performed by the power supply SW-1 (203), the power supply control of the data processing unit 111 is performed by the power supply SW-2 (204), and the power supply control of the IO control unit 103 is performed by the power supply SW-2 (204). Each is performed in the supply SW-3 (205). The power control of the main CPU 101 is performed by the power supply SW-4 (206), and the power control of the sub CPU 102 is performed by the power supply SW-5 (207). In other words, for the modules 112 and 113, power control is performed by one power supply SW-2 (204) as the data processing unit 111. FIG. Power control is performed by one power supply SW-3 (205) for the memory I/F 104, memory I/F 105, and memory I/F 106 as well.

Although not shown in detail in FIG. 2, the power control register unit 202 performs power ON/OFF operation for each power supply SW for each power supply SW, bit by bit. A SW control signal is connected. The power supply control register unit 202 is connected to the DATA bus (120) and internally has a register for controlling the output of each power supply SW control signal. The register is accessed by the main CPU 101 or the sub CPU 102 to switch the value, thereby controlling power supply and power cutoff.

<Basic operation flow>
Next, with reference to FIG. 3, a basic operational flow of the system in this embodiment will be described.

In S301, the ASIC 100 starts to boot when the system is powered on. When the ASIC 100 is started, first, it enters an operation mode for verifying the validity of boot data (including program codes and the like). In S302, the sub-CPU 102 executes validity verification processing for determining whether or not the boot data of the main CPU 101 stored in the boot data storage unit 107 for the main CPU has changed.

In S303, the sub CPU 102 determines whether or not the boot data of the main CPU 101 has changed based on the result of the validity verification process. If it is determined that there is a change (the verification process fails) (Yes in S303), the LED 123 is turned on to notify that the system cannot be used, and the operation of the system is stopped. Although the details of the verification process are omitted, verification is performed using electronic signature technology to which public key cryptography is applied, and verification is performed by comparison with reliable signature data. The same applies to the processing of FIG. 5, which will be described later.

On the other hand, if it is determined that the boot data of the main CPU 101 has not changed as a result of the verification process (verification process is successful) (No in S303), the process proceeds to S305. In S<b>305 , the sub CPU 102 executes processing for shifting from the validity verification operation mode by the sub CPU 102 to the normal operation mode under the control of the main CPU 101 . After that, in S306, the main CPU 101 controls to shift to the normal operation mode, and this flowchart ends.

<Internal operation during verification processing>
Next, with reference to FIG. 4, a detailed description will be given of the internal operating state during processing for verifying the validity of this system. Circuits not used during verification processing are the data processing unit 110, the module 113 in the data processing unit 111, the memory I/F 106 in the IO control unit 103, and the main CPU 101. FIG. The module 112 in the data processing unit 111 must be operated during the verification process in order to generate an LED control signal for informing the user of the result of the verification process with the LED 123 connected to the ASIC 100 . The memory I/F 104 needs to be operated during the verification process in order to input the boot data for the main CPU from the boot data storage unit 107 for the main CPU connected to the ASIC 100 when performing the verification process. . The memory I/F 105 needs to be operated during the verification process in order to input the boot data for the sub CPU from the boot data storage unit 108 for the sub CPU connected to the ASIC 100 when performing the verification process. . Since the sub CPU 102 controls each processing unit of the ASIC 100 when performing the verification process, it must be operated during the verification process.

Regarding the clock control unit 114, the clock generation unit 116, the reset control unit 121, and the power control unit 122, from the time of startup to the time of verification processing, the power supply, clock, and reset are supplied and controlled to each circuit. Power supply and clock supply will not be stopped. At the time of the verification process here, power saving control is performed with finer granularity by performing both power saving measures such as power cutoff and clock supply stop to circuits not used in the verification process. It should be noted that there is no intention to limit the present invention, and it is desirable to control power saving by at least one of power shutdown and clock supply stop according to the system configuration (especially circuit configuration).

(Power off)
First, a description will be given of how to cut off power to circuits that are not in use. As described above, the general power control unit 122 has a limited number of blocks for controlling power supply/interruption. The power supply control unit 122 according to the present embodiment is capable of power supply control of five blocks: the data processing unit 110, the data processing unit 111, the IO control unit 103, the main CPU 101, and the sub CPU 102. FIG.

In this embodiment, circuits not used for verification processing are the data processing unit 110, the module 113 in the data processing unit 111, the memory I/F 106 in the IO control unit 103, and the main CPU 101. FIG. Of these, only two blocks, the data processing unit 110 and the main CPU 101, can be powered off. The module 113 of the data processing unit 111 is a circuit that is not used for verification processing, but the module 112 is to be used, so the power cannot be cut off. Also, regarding the IO control unit 103, the memory I/F 106 is a circuit that is not used for verification processing, but the memory I/F 104 and the memory I/F 105 are to be used. can't

(Stops clock supply)
Next, the stop of clock supply will be described. Stopping the clock supply is performed for all of the data processing unit 110 that is not used for verification processing, the module 113 in the data processing unit 111, the memory I/F 106 in the IO control unit 103, and the main CPU 101. FIG. Since the data processing unit 110 and the main CPU 101 are powered off, the power consumption in each circuit is zero. However, by stopping the output of the clock from the clock generator 116, the logic circuits such as buffers in the middle of the clock line from the clock generator 116 to the data processor 110 and the main CPU 101 are not driven. becomes. Therefore, power consumption can be reduced, albeit slightly, by stopping the clock.

As described above, power supply is stopped to blocks of circuits that are not used during verification processing, and clocks are stopped for circuits that are not used for verification processing in blocks whose power cannot be stopped. As a result, the power consumption of the ASIC 100 can be made lower than the power consumption during normal operation.

<Effects of this embodiment>
Examples of specific effects according to the present embodiment will be described with reference to FIGS. 6 to 10. FIG. An information processing apparatus (data processing system) according to the present embodiment detects generation of boot code when the apparatus is started. At that time, the information processing apparatus executes at least one of power cutoff control and clock gate control as power saving control for blocks that do not execute processing in the validity verification processing. Further, the information processing apparatus uses power surplus from power saving control to increase the frequency of the operation clock to the processing block that executes the validity verification process, thereby performing the verification process at high speed. Verification results for frequency and power consumption when these controls are applied in stages will be described below.

First, with reference to FIG. 6, the calculated value of the total power consumption during normal operation of the ASIC 100 will be described. FIG. 6 shows each processing module, the type of clock used by the module, its frequency, and the circuit scale of each processing module, and then calculates the power consumption of each module by calculation from the frequency and circuit scale. ing. Furthermore, the sum of them is calculated as the power consumption of the ASIC 100 as a whole. Here, power consumption is calculated assuming that a circuit of 1K gates consumes power of 1 mW when operating at a frequency of 10 MHz. Also, in this embodiment, the allowable power of the package of the ASIC 100 is assumed to be 8100 mW. From FIG. 6, the total power consumption of the entire ASIC 100 during normal operation is 8053 mW, which means that the power consumption during normal operation is below the allowable power.

Next, with reference to FIG. 7, the power consumption of the ASIC 100 when only the power supply is cut off during the verification process in this embodiment will be described. In FIG. 7, regarding the power consumption of each module, the power consumption in the circuit used for the verification process and the power consumption in the circuit not used for the verification process are described separately. In this case, the power consumed by the data processing unit 110 and the main CPU 101 whose power is cut off is zero.

Also, the module 113 in the data processing unit 111 and the memory I/F 106 in the IO control unit 103, which are not processing data but are in a state where power is supplied and a clock is supplied, operate normally. lower power consumption than In this embodiment, in the above case, the power consumption is half of that in the normal data processing state. Therefore, the power consumption of the module 113 in the data processing unit 111 is 1250 mW, and the power consumption of the memory I/F 106 in the IO control unit 103 is 125 mW. As a result, the power consumption of the ASIC 100 as a whole is reduced to 2977 mW.

As described above, by shutting off power to circuits that are not used at the time of legitimacy detection, it is possible to reduce excess power. As a result, it is possible to increase the frequency of the operation clock of the circuit that performs the verification process as long as the allowable power consumption of the ASIC 100 is not exceeded.

FIG. 8 shows, in the operation of the ASIC 100 during verification processing, by cutting off power to circuits that are not used during validity detection, excess power is reduced, and the verification processing is performed accordingly. Power consumption when operating with a high clock frequency is shown.

As described above, in this embodiment, the allowable power of the package of the ASIC 100 is 8100 mW. Therefore, as long as the allowable power of the package does not exceed 8100 mW, the frequency of the circuit used during the validity detection may be increased. Here, CLK-B used in the module 112, CLK-D used in the memory I/F 104 in the IO control unit 103, CLK-E used in the memory I/F 105 in the IO control unit 103, and used in the sub CPU 102 The frequency of CLK-H to be used is increased four times. That is, the frequency of CLK-B is increased from 100 MHz to 400 MHz, CLK-D from 50 MHz to 200 MHz, CLK-E from 50 MHz to 200 MHz, and CLK-H from 100 MHz to 400 MHz. In this case, CLK-I used by the clock control unit 114 is controlled by the clock generation unit 116 by setting the register, so it is assumed that there is no need for high-speed operation, and the frequency of normal operation can be used as it is. and

By increasing the frequency of each clock as described above, the power consumption of the module 112 in the data processing unit 111 is 2000 mW, and the power consumption of the memory I/F 104 in the IO control unit 103 is 100 mW. Furthermore, the power consumption of the memory I/F 105 in the IO control unit 103 is 100 mW, and the power consumption of the sub CPU 102 is 4000 mW, both of which are high. However, the total power consumption of the ASIC 100 is 7627 mW, which is lower than the allowable power of the package of 8100 mW, and can be used without any problem.

On the other hand, regarding the case where the operating frequency of the circuit used for correctness detection is increased by 5 times, the detailed explanation in the table etc. will be omitted, but if the power consumption is calculated in the same manner as above, 9177 mW, exceeding the allowable power of the package. Therefore, it can be seen that the frequency of the operation clock of the circuit used for the validity detection cannot be increased by 5 times only by dealing with power shutdown.

Next, the power consumption of the ASIC 100 when both power supply cutoff control and CG control are performed during the verification process will be described with reference to FIG. In FIG. 9 as well, the power consumption of each module is described in separate columns for power consumption in circuits used for verification processing and power consumption in circuits not used for verification processing.

In this case, the power consumed by the data processing unit 110 and the main CPU 101 whose power is cut off is zero. Also, regarding the module 113 in the data processing unit 111 and the memory I/F 106 in the IO control unit 103, which are not processing data but are in a state where power is supplied and clock supply is stopped, It is even lower than the power consumption during clock supply. Here, in such a case, the power consumption is assumed to be 1/20 of that during normal data processing. Therefore, the power consumption of the module 113 in the data processing unit 111 is 125 mW, and the power consumption of the memory I/F 106 in the IO control unit 103 is 12.5 mW. As a result, the power consumption of the entire ASIC 100 is reduced to 1739.5 mW.

As described above, the supply of power to circuits that are not used at the time of legitimacy detection and to blocks that can be cut off is stopped. In addition, even if the power supply cannot be stopped, if there are circuits that are not used inside the block, the clock can be stopped by CG control. Power consumption can be reduced.

As a result, as long as the power consumption does not exceed the allowable power consumption of the ASIC 100, it is possible to further increase the frequency of the operation clock of the circuit that performs the verification process compared to when only the power supply is cut off.

Referring to FIG. 10, during the verification process, power is cut off and clock supply is stopped to circuits that are not used to reduce excess power, and the operating clock frequency of the circuit to be verified is increased. Power consumption in the case of operating with As described above, in this embodiment, the allowable power of the ASIC 100 package is 8100 mW. Therefore, as long as the allowable power of the package does not exceed 8100 mW, the frequency of the circuit used during the validity detection may be increased.

Therefore, in the present embodiment, the frequencies of CLK-B used in the module 112 in the data processing unit 111 and CLK-D used in the memory I/F 104 in the IO control unit 103 are increased fivefold. Furthermore, the frequencies of CLK-E used in the memory I/F 105 in the IO control unit 103 and CLK-H used in the sub CPU 102 are increased five times to operate. That is, the frequency of CLK-B is increased from 100 MHz to 500 MHz, CLK-D from 50 MHz to 250 MHz, CLK-E from 50 MHz to 250 MHz, and CLK-H from 100 MHz to 500 MHz. In this case, CLK-I used by the clock control unit 114 is controlled by the clock generation unit 116 by setting the register, so it is assumed that there is no need for high-speed operation, and the frequency of normal operation can be used as it is. and

By increasing the frequency of each clock as described above, the power consumption of the module 112 in the data processing unit 111 and the memory I/F 104 in the IO control unit 103 are increased to 2500 mW and 125 mW, respectively. Also, the power consumption of the memory I/F 105 in the IO control unit 103 is 125 mW, and the power consumption of the sub CPU 102 is 5000 mW, both of which are high.

However, the total power consumption of the ASIC 100 is 7939.5 mW, which is lower than the allowable power of the package of 8100 mW, and can be used without any problem. In other words, it is possible to perform the verification process with a higher clock frequency than in the case where only the power supply is cut off to save power.

<Detailed operation flow>
Next, with reference to FIG. 5, a detailed operation flow at startup of the system, including power shutdown control and clock gate control according to the present embodiment, will be described. In addition, in the processing of this flowchart, it is assumed that the time required for verification processing is reduced by increasing the operating clock frequency of the circuit used for verification processing in response to power cutoff control and power reduction by clock gates. ing. Of course, in the present invention, only the power saving control may be applied, and the control for reducing the processing time by increasing the frequency may not be applied.

In S501, the ASIC 100 starts to boot when the system is powered on. Subsequently, in S502, the operation of the reset control unit 121 is started by the operation of the clock from the oscillator 115, and the reset of the clock control unit 114 and the clock generation unit 116 is canceled by the hardware sequence in the reset control unit 121. be. At this time, the PLL control signal and the frequency divider control signal from the clock control unit 114 are set to generate the clock during normal operation according to the initial setting values after the reset is released.

Next, in S503, the clock output control unit 119 sets the clock output control signal so that all the clocks are supplied to each circuit in the same manner as during normal operation, based on the initial setting value after reset release. . After that, in S504, the reset of the sub CPU 102, the memory I/F 104, the memory I/F 105, and the module 112 used in the verification process is canceled by the hardware sequence in the reset control unit 121. FIG. When the reset of each circuit is released, in S505, the sub CPU 102 reads boot data from the boot data storage unit 108 for the sub CPU via the memory I/F 105, and completes booting.

After that, in S506, the sub CPU 102 cuts off the power supply to the circuits not used for the verification process. In this embodiment, the sub CPU 102 shuts off power to the data processing unit 110 and the main CPU 101 . Specifically, the sub CPU 102 rewrites the power control register in the power control unit 122 to cut off power to the data processing unit 110 and the main CPU 101 .

Thereafter, in S507, the sub CPU 102 stops clock supply (clock gating) to circuits not used for verification processing. The sub CPU 102 includes CLK-A used in the data processing unit 110, CLK-C used in the module 113 of the data processing unit 111, CLK-F used in the memory I/F 106 in the IO control unit 103, and used in the main CPU 101. stop the clock to CLK-G that Specifically, the sub CPU 102 rewrites the clock output control signal register of the clock control unit 114 and switches the operation of the CG circuit in the clock generation unit 116 to stop the supply of each clock.

When the clock stop control is completed, in S508, the sub CPU 102 controls to increase the frequency of the clock for the circuit that performs the verification process. In this embodiment, the frequencies of CLK-B used in the module 112 in the data processing unit 111 and CLK-D used in the memory I/F 104 in the IO control unit 103 are raised five times as high as normal. Furthermore, the frequencies of CLK-E used in the memory I/F 105 in the IO control unit 103 and CLK-H used in the sub CPU 102 are raised to five times the normal frequency.

In order to supply a clock with five times the frequency, it is necessary to increase the frequency of the clock (CLK-PLL) output from the PLL 117 from the default setting of 1200 MHz. Therefore, for clocks other than the clock used for verification processing, it is necessary to change the division ratio in order to maintain the frequency of the clock generated with the initial setting value. However, CLK-A used in the data processing unit 110, CLK-F used in the memory I/F 106 in the IO control unit 103, and CLK-G used in the main CPU 101 do not need to change the division ratio. do not have. This is because the clock output has already been stopped by the clock output controller 119 in the clock generator 116 . Therefore, in this embodiment, only the clock control unit 114 changes the division ratio to maintain the frequency of the clock generated with the initial setting value. Specifically, the sub CPU 102 rewrites the register for the PLL control signal and the register for the frequency divider circuit control signal of the clock control unit 114, the frequency of the clock (CLK-PLL) from the PLL 117, and the division ratio of each clock. is changed from the division ratio for normal operation.

First, regarding the setting of the PLL 117, the initial value after the reset is canceled is such that the input CLK-OSC is multiplied by 120 and the CLK-PLL is output at a frequency of 1200 MHz. However, during the verification process in this embodiment, the input CLK-OSC is multiplied by 300 and the CLK-PLL is output at a frequency of 3000 MHz. Further, the frequency of CLK-B used in the module 112 in the data processing unit 111 used for verification processing is increased from 100 MHz to 500 MHz by dividing 1200 MHz by 12 to 3000 MHz by 6. Further, the frequency of CLK-D used in the memory I/F 104 in the IO control unit 103 is increased from 50 MHz to 250 MHz by dividing 1200 MHz by 24 to 3000 MHz by 12. The frequency of CLK-E used in the memory I/F 105 in the IO control unit 103 is also increased from 50 MHz to 250 MHz by dividing 1200 MHz by 24 to 3000 MHz by 6. As for CLK-H used in the sub CPU 102, the frequency is increased from 100 MHz to 500 MHz by dividing 1200 MHz by 12 to 3000 MHz by 6. In this way, each frequency is increased by changing the frequency division ratio. As for the clock control unit 114, the frequency division ratio is changed from 1200 MHz divided by 12 to 3000 MHz divided by 30 in order to maintain the same frequency of 100 MHz as during normal processing.

After completing control over the frequency division of the clock to be used, in S509, the sub CPU 102 executes verification processing. Although a detailed description of the content of the verification process is omitted, under the control of the sub CPU 102, the boot data for the main CPU stored in the boot data storage unit 107 for the main CPU is captured via the memory I/F 104, A determination is made as to whether or not the data has changed. As a result of the verification process, if it is determined that the boot data of the main CPU 101 has changed (verification process fails) (Yes in S510), in S511, the sub CPU 102 cannot use this system. is notified by lighting the LED 123 . After that, the operation of this system is stopped, and this flow chart ends. Specifically, the sub CPU 102 switches the LED control signal output from the module 112 in the data processing unit 111 from the off state to the on state. Here, lighting control of the LED 123 is exemplified as an example, but various forms of notification control may be performed when starting and stopping the vehicle. For example, it may be performed by voice output, information notification to a predetermined device (e-mail, FAX, etc.), recording as history information in a predetermined storage area, print output, display output, or the like.

On the other hand, if it is determined that the boot data of the main CPU 101 has not changed as a result of the verification process (verification process is successful) (No in S510), the process proceeds to S512. Here, processing for shifting from the validity verification operation mode by the sub CPU 102 to the normal operation mode under the control of the main CPU 101 is performed. In S512, the sub CPU 102, as a process for shifting to the normal operation mode, first changes CLK-B used by the module 112 in the data processing unit 111 and CLK-B used by the memory I/F 104 in the IO control unit 103. D and return the frequency to normal operation. Furthermore, the sub CPU 102 restores the frequencies of CLK-E used by the memory I/F 105 in the IO control unit 103 and CLK-H used by the sub CPU 102 to the frequency during normal operation. Specifically, before the verification process, the setting changed by switching the clock frequency is returned to its original state. In other words, the sub CPU 102 rewrites the PLL control signal register of the clock control unit 114, and restores the multiplication factor of the PLL 117 to the value during normal operation. Further, the sub CPU 102 rewrites the register for the frequency dividing circuit control signal of the clock control unit 114 from the sub CPU 102, and changes the frequency dividing ratio for each clock from the frequency dividing ratio for verification processing to the frequency dividing ratio for normal operation. return.

After that, in S513, the sub CPU 102 restores clock supply to circuits not used for the verification process. According to this embodiment, the clock supply to CLK-A used by the data processing unit 110 and CLK-C used by the module 113 in the data processing unit 111, which were stopped during the verification process, is restored. . Furthermore, the clock supply to CLK-F used by the memory I/F 106 in the IO control unit 103 and CLK-G used by the main CPU 101 is restored. Specifically, the sub CPU 102 rewrites the clock output control signal register of the clock control unit 114 and switches the operation of the CG circuit of the clock generation unit 116 to restore the supply of each clock.

After that, in S514, the sub CPU 102 restores the power supply to the circuits not used for the verification process. In this embodiment, the power of the data processing unit 110 and the main CPU 101 is restored. Specifically, the sub CPU 102 rewrites the power control register in the power control unit 122 and restores power to the data processing unit 110 and the main CPU 101 .

When the above processing is completed, in S515, the sub CPU 102 resets the main CPU 101 from the reset control unit 121, the data processing unit 110, the module 113 within the data processing unit 111, the memory I/F 106 within the IO control unit 103, etc. Release the reset. Triggered by the reset release, in S516, the main CPU 101 reads the main CPU boot data from the main CPU boot data storage unit 107 via the memory I/F 104, starts up, and terminates this flowchart. do. With the flow described above, the processing at the time of system startup is completed, and the normal operation is started.

As described above, the present information processing apparatus includes a storage unit for storing boot data, a power control unit for supplying power to a plurality of blocks each having one or more circuits, and an oscillator for supplying power to each circuit in each block. and a clock control unit for controlling the supply of the clock. In addition, the information processing apparatus is started using a sub CPU that executes verification processing for verifying the validity of the boot data stored in the storage unit, and the boot data that has been successfully verified for validity by the sub CPU. and a main CPU for controlling the processing device. The sub-CPU causes the power control unit to supply power to blocks in which at least one circuit is used in the verification process, and cut off power supply to blocks in which no circuits are used in the verification process. Further, the sub CPU causes the clock control unit to supply the clock to the circuit used in the verification process, stops the supply of the clock to the circuit not used in the verification process, and then executes the verification process. As described above, according to the present embodiment, power consumption is reduced during validity detection by shutting off the power supply and stopping the supply of the clock to circuits that are not used during the validity verification process. be able to. As a result, the verification process can be completed at high speed while keeping the upper limit of the allowable power consumption of the chip.

Note that when there is no need to complete the verification process at high speed, there is no need to increase the operating clock during the validity detection, and it is possible to perform the process with reduced power consumption. Further, in the above embodiment, as power saving control, control for both cutting off power and stopping clock supply has been described. It may be used as a control.

<Other embodiments>
The present invention supplies a program that implements one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and one or more processors in the computer of the system or device reads and executes the program. It can also be realized by processing to It can also be implemented by a circuit (for example, ASIC) that implements one or more functions.

The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the claims are appended to make public the scope of the invention.

100: ASIC, 101: main CPU, 102: sub CPU, 103: IO control unit, 104: memory I/F 1, 105: memory I/F 2, 106: memory I/F 3, 107: main Boot data storage unit for CPU 108: Boot data storage unit for sub CPU 109: Memory 3, 110: Data processing unit 1, 111: Data processing unit 2, 112: Module 1, 113: Module 2, 114: clock controller, 115: oscillator, 116: clock generator, 117: PLL, 118: frequency divider, 119: clock output controller, 120: DATA bus, 121: reset controller, 122: power control unit 123: LED

Claims (11)

An information processing device,
a storage means for storing boot data;
power control means for supplying power to a plurality of blocks each having one or more circuits;
clock control means for controlling clock supply from an oscillator to each circuit in each block;
a first control means for executing verification processing for verifying the validity of the boot data stored in the storage means;
a second control means for starting up using the boot data whose validity has been successfully verified by the first control means and controlling the information processing device;
The first control means is
causing the power supply control means to supply power to a block in which at least one circuit is used in the verification process, and cut off power supply to a block in which no circuit is used in the verification process;
causing the clock control means to supply a clock to a circuit used in the verification process and stop supplying a clock to a circuit not used in the verification process;
An information processing apparatus that executes the verification process. The first control means further controls the power supply to each block and the clock supply to each circuit by the power supply control means and the clock control means, and then supplies the clocks to the circuits used in the verification process. by changing the division ratio of the clock to be supplied from that during normal operation, the clock control means controls the frequency of the supplied clock to be higher than that during normal operation, and then the verification processing is executed. 2. The information processing apparatus according to claim 1. the first control means, the second control means, the power supply control means, and the clock control means are included in the plurality of blocks;
3. The information processing apparatus according to claim 2, wherein said first control means causes said clock control means to increase the frequency of said clock within a range not exceeding an allowable power of a package including at least said plurality of blocks. . The first control means is
4. The information processing apparatus according to any one of claims 1 to 3, wherein when the validity verification is successful, at least power supply and clock supply to said second control means are restored. The first control means is
5. The information processing apparatus according to any one of claims 1 to 4, wherein when verification of validity fails, the information processing apparatus is notified to that effect and the information processing apparatus is stopped from starting up. The first control means is
6. The information processing apparatus according to claim 5, wherein said fact is notified by controlling a predetermined LED provided in said information processing apparatus from an off state to an on state. An information processing device,
a storage means for storing boot data;
clock control means for controlling clock supply from an oscillator to each circuit in each block;
a first control means for executing verification processing for verifying the validity of the boot data stored in the storage means;
a second control means for starting up using the boot data whose validity has been successfully verified by the first control means and controlling the information processing device;
The first control means is
causing the clock control means to supply a clock to a circuit used in the verification process and stop supplying a clock to a circuit not used in the verification process;
An information processing apparatus that executes the verification process. a storage means for storing boot data;
power control means for supplying power to a plurality of blocks each having one or more circuits;
clock control means for controlling clock supply from an oscillator to each circuit in each block;
a first control means for executing verification processing for verifying the validity of the boot data stored in the storage means;
A control method for an information processing device comprising: second control means for starting up using boot data whose validity has been successfully verified by the first control means and controlling the information processing device,
The first control means is
causing the power supply control means to supply power to blocks in which at least one circuit is used in the verification process, and cut off power supply to blocks in which no circuits are used in the verification process; and by the clock control means. , supplying a clock to a circuit used in the verification process and stopping the supply of a clock to a circuit not used in the verification process;
and a step of executing the verification process. a storage means for storing boot data;
clock control means for controlling clock supply from an oscillator to each circuit in each block;
a first control means for executing verification processing for verifying the validity of the boot data stored in the storage means;
A control method for an information processing device comprising: second control means for starting up using boot data whose validity has been successfully verified by the first control means and controlling the information processing device,
The first control means is
causing the clock control means to supply a clock to a circuit used in the verification process and stop supplying a clock to a circuit not used in the verification process;
and a step of executing the verification process. a storage means for storing boot data;
power control means for supplying power to a plurality of blocks each having one or more circuits;
clock control means for controlling clock supply from an oscillator to each circuit in each block;
a first control means for executing verification processing for verifying the validity of the boot data stored in the storage means;
and second control means for starting up using the boot data whose validity has been successfully verified by the first control means and controlling the information processing apparatus. A program, wherein the control method includes:
The first control means is
causing the power supply control means to supply power to blocks in which at least one circuit is used in the verification process, and cut off power supply to blocks in which no circuits are used in the verification process; and by the clock control means. , supplying a clock to a circuit used in the verification process and stopping the supply of a clock to a circuit not used in the verification process;
and a step of executing the verification process. a storage means for storing boot data;
clock control means for controlling clock supply from an oscillator to each circuit in each block;
a first control means for executing verification processing for verifying the validity of the boot data stored in the storage means;
and second control means for starting up using the boot data whose validity has been successfully verified by the first control means and controlling the information processing apparatus. A program, wherein the control method includes:
The first control means is
causing the clock control means to supply a clock to a circuit used in the verification process and stop supplying a clock to a circuit not used in the verification process;
and a step of executing the verification process.

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