JP7322941B2 - reflective liquid crystal display - Google Patents

Description

The present invention relates to a reflective liquid crystal display device and, for example, to a reflective liquid crystal display device suitable for accurately measuring the temperature of pixels.

A sub-frame driving method is known as one of halftone display methods in liquid crystal display devices. In the sub-frame driving method, which is a kind of time-axis modulation method, a predetermined period (for example, one frame, which is the display unit of one image in the case of moving images) is divided into a plurality of sub-frames, and the gradation to be displayed is adjusted. Pixels are driven by a combination of corresponding subframes. The gradation to be displayed is determined by the ratio of the pixel driving period to a predetermined period, and this ratio is specified by the combination of subframes.

Among the liquid crystal display devices adopting the sub-frame driving method, each pixel is composed of a master latch and a slave latch, a liquid crystal display element, and a plurality of switching transistors.

In this pixel, 1-bit first data is applied to the input terminal of the master latch through a first switching transistor, and when a row selection signal applied through a row scanning line becomes active, the first switching transistor is It turns on and the first data is written to the master latch.

When data writing to the master latches provided in all pixels is completed, the second switching transistors provided in all pixels are turned on within the subframe period. As a result, the data in the master latches provided for all the pixels are simultaneously read out and written in the slave latches, and the data written in the slave latches are applied to the pixel electrodes of the liquid crystal display element. Similar processing is performed for all pixels in each subframe period. As a result, each pixel can perform a desired gradation display by combining a plurality of sub-frames forming one frame.

Note that the periods of a plurality of subframes forming one frame are assigned in advance to the same or different predetermined periods. For example, when performing maximum gradation display (displaying white) in each pixel, display is performed in all of a plurality of sub-frames constituting one frame, and when performing minimum gradation display (displaying black) In the case where display is not performed in all of a plurality of sub-frames constituting one frame, and other gradation display is performed, a sub-frame to be displayed is selected according to the gradation to be displayed. A liquid crystal display device employing this conventional technique uses digital data indicating gradation as input data, and employs a digital drive system with a two-stage latch structure (see, for example, Patent Document 1).

Japanese Patent No. 5733154

By the way, a liquid crystal display device is generally provided with a temperature sensor for detecting the temperature of a pixel. When a liquid crystal display device is used as a projector element, high-intensity lamp light is incident on the liquid crystal display element, so the liquid crystal display element may become hot and malfunction.
Therefore, the temperature of the liquid crystal display element is kept constant by controlling the number of revolutions of the cooling fan based on the temperature of the pixel detected by the temperature sensor. It is considered that the configuration of Patent Document 1 is also provided with a temperature sensor.

However, in general, the surface of the pixel is covered with glass for displaying an image, and the back surface of the pixel is attached with a heat sink for dissipating heat from the pixel. cannot be installed. Here, there is a temperature error of -5°C to +5°C between the pixel temperature and the heat sink temperature. Therefore, the configuration of Patent Document 1 has a problem that the temperature of the pixel cannot be measured with high accuracy.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a reflective liquid crystal display device capable of accurately measuring the temperature of a pixel.

A reflective liquid crystal display device according to an aspect of the present invention includes a plurality of pixels and a temperature sensor, and the temperature sensor is provided in one or more regions of a plurality of pixel arrangement regions partitioned in a matrix. formed.

According to the present invention, it is possible to provide a reflective liquid crystal display device capable of accurately measuring the temperature of a pixel.

1 is a block diagram showing a liquid crystal display device according to a first embodiment; FIG. 2 is a circuit diagram showing a specific configuration of a pixel provided in the liquid crystal display device shown in FIG. 1; FIG. 3 is a circuit diagram showing a specific configuration of an inverter forming a first data holding unit provided in the pixel shown in FIG. 2; FIG. 3 is a schematic cross-sectional view of the pixel shown in FIG. 2; FIG. 2 is a timing chart showing the operation of the liquid crystal display device shown in FIG. 1; FIG. 4 is a diagram showing the relationship between the voltage applied to the liquid crystal (RMS voltage) and the grayscale value of the liquid crystal; 2 is a circuit diagram showing a specific configuration of a temperature sensor portion of a dummy pixel provided in the liquid crystal display device shown in FIG. 1; FIG. 2 is a schematic cross-sectional view of a dummy pixel provided in the liquid crystal display device shown in FIG. 1; FIG. 2 is a schematic plan view of a temperature sensor portion of a dummy pixel provided in the liquid crystal display device shown in FIG. 1; FIG. 2 is a schematic plan view of a reflective electrode used for each of a plurality of pixels and dummy pixels arranged in a pixel arrangement region of the liquid crystal display device shown in FIG. 1; FIG. 8 is a schematic plan view of reflective electrodes used for each of a plurality of pixels and dummy pixels arranged in a pixel arrangement region of the liquid crystal display device according to the second embodiment; FIG. FIG. 11 is a schematic plan view of a reflective electrode used for each of a plurality of pixels and dummy pixels arranged in a pixel arrangement region of a liquid crystal display device according to a third embodiment;

<Embodiment 1>
Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a reflective liquid crystal display device 10 according to Embodiment 1. As shown in FIG.
As shown in FIG. 1, the reflective liquid crystal display device 10 includes an image display section 11, a timing generator 13, a vertical shift register 14, a data latch circuit 15, and a horizontal driver 16.
And prepare. The horizontal driver 16 includes a horizontal shift register 161, a latch section 162,
and a level shifter/pixel driver 163 .

The image display unit 11 has a plurality of pixels 12 regularly arranged in each of a plurality of pixel arrangement regions partitioned in a matrix. Here, dummy pixels 12d are arranged instead of the pixels 12 in a part of the plurality of pixel arrangement regions (bottom left of the paper surface). dummy pixel 12
d is composed of a dummy liquid crystal display element and a circuit section, in which the pixels 12
A temperature sensor S1 is formed for detecting the temperature of . The temperature of the pixel 12 is kept constant by controlling the rotation speed of the cooling fan based on the temperature of the pixel 12 detected by the temperature sensor S1. Details of the dummy pixel 12d will be described later.

The plurality of pixels 12 includes m (m is a natural number equal to or greater than 2) row scanning lines g1 to gm extending in the row direction (X direction) with one end connected to the vertical shift register 14, and a level shifter/pixel driver 163. are arranged in a two-dimensional matrix at a plurality of intersections where n (n is a natural number of 2 or more) column data lines d1 to dn extending in the column direction (Y direction) with one end connected to the It is All the pixels 12 in the image display section 11 have one end connected to the timing generator 13
are connected in common to trigger lines trig and trigb connected to .

The forward trigger pulse TRI transmitted by the forward trigger pulse trigger line trig and the reverse trigger pulse TRIB transmitted by the reverse trigger pulse trigger line trigb are always in the opposite logical value relationship (complementary relationship). be.

The timing generator 13 receives external signals such as the vertical synchronizing signal Vst, the horizontal synchronizing signal Hst, and the basic clock CLK output from the host device 20 as input signals,
Based on these external signals, alternating signal FR, V start pulse VST, H start pulse HST, clock signals VCK, HCK, latch pulse LT, and trigger pulse TRI
, TRIB and the like are generated.

The alternating signal FR is a signal whose polarity is inverted every subframe, and is supplied to the common electrode of the liquid crystal display elements in the pixels 12 forming the image display section 11 as a common electrode voltage Vcom, which will be described later.

The start pulse VST is a pulse signal output at the start timing of each subframe, which will be described later, and the switching of the subframes is controlled by this start pulse VST.

The start pulse HST is a pulse signal output to the horizontal shift register 161 at the start timing of the horizontal shift register 161 .

The clock signal VCK is a shift clock that defines one horizontal scanning period (1H) in the vertical shift register 14, and the vertical shift register 1 is activated at the timing of the clock signal VCK.
4 performs a shift operation.

A clock signal HCK is a shift clock in the horizontal shift register 161,
This is a signal for shifting data by 2-bit width.

The latch pulse LT is a pulse signal output at the timing when the horizontal shift register 161 has finished shifting data for the number of pixels in one row in the horizontal direction.

The forward trigger pulse TRI and the reverse trigger pulse TRIB are respectively connected to the trigger line trig
, trigb are pulse signals supplied to all the pixels 12 in the image display unit 11 .

Here, the forward trigger pulse TRI and the reverse trigger pulse TRIB are output from the timing generator 13 after data is written in the first data holding units in all the pixels 12 in the image display unit 11 in a certain subframe period. be done. As a result, the data held in the first data holding units in all the pixels 12 in the image display unit 11 are simultaneously transferred to the second data holding units in the corresponding pixels 12 in the subframe period. be.

The vertical shift register 14 transfers the V start pulse VST supplied at the start timing of each subframe according to the clock signal VCK, and sequentially and exclusively supplies row scanning signals to the row scanning lines g1 to gm in units of 1H. . As a result, row scanning lines are sequentially selected one by one in units of 1H from the row scanning line g1 at the top of the image display section 11 to the row scanning line gm at the bottom.

The data latch circuit 15 receives 3 subframe units supplied from an external circuit (not shown).
After 2-bit width data is latched based on the basic clock CLK from the host device 20, it is output to the horizontal shift register 161 in synchronization with the basic clock CLK.

Note that the reflective liquid crystal display device 10 divides one frame of a video signal into a plurality of sub-frames having display periods shorter than one frame period of the video signal, and performs gradation display by combining these sub-frames. ing. Therefore, the external circuit converts the grayscale data indicating the grayscale of each pixel into a plurality of 1-bit subframe data corresponding to a plurality of subframes. Furthermore, the above external circuit collectively supplies the subframe data for 32 pixels belonging to the same subframe to the data latch circuit 15 as 32-bit width data.

When viewed as a 1-bit serial data processing system, the horizontal shift register 161 starts shifting with a start pulse HST supplied from the timing generator 13 at the beginning of 1H, and receives 32-bit width data supplied from the data latch circuit 15. to clock signal H
Shift in synchronization with CK.

After the horizontal shift register 161 has finished shifting the data of n bits, which is the same as the number of pixels n for one row of the image display section 11, the latch section 162 synchronizes with the latch pulse LT supplied from the timing generator 13, The n-bit data (that is, n-pixel subframe data) supplied in parallel from the horizontal shift register 161 is latched and output to the level shifter of the level shifter/pixel driver 163 . When the data transfer of the latch section 162 is completed, the timing generator 13 outputs the start pulse HST again, and the horizontal shift register 161 resumes shifting the 32-bit width data from the data latch circuit 15 according to the clock signal HCK.

The level shifter of the level shifter/pixel driver 163 level-shifts the signal levels of the n subframe data corresponding to the n pixels in one row transferred from the latch unit 162 to the liquid crystal driving voltage amplitude. The pixel driver of the level shifter/pixel driver 163 outputs n subframe data corresponding to n pixels in one row after level shifting to n column data lines d1 to dn in parallel.

In one horizontal scanning period, the horizontal driver 16 outputs subframe data to the pixels in the row selected as the data write target, and outputs subframe data to the pixels in the row selected as the data write target in the next one horizontal scanning period. are performed in parallel with the shift of the subframe data for In a certain horizontal scanning period, n subframe data corresponding to n pixels in one row are transmitted in parallel to n column data lines d1 to dn as data signals, and
output simultaneously.

Among the plurality of pixels 12 forming the image display unit 11, n pixels 12 in one row selected by the row scanning signal from the vertical shift register 14 are output from the level shifter/pixel driver 163 all at once. n sub-frame data are sampled through n column data lines d1 to dn and written into a first data holding section in each pixel 12, which will be described later.

Although the details of the pixel 12 will be described later, in the pixel 12, the inverted data of the input data held in the storage unit SM1 is applied to the reflective electrode PE. That is, pixel 12 is a level shifter/
It has a function of inverting the input data supplied from the pixel driver 163 .

(Specific configuration of pixel 12)
Next, a specific configuration of the pixel 12 will be described.
FIG. 2 is a circuit diagram showing a specific configuration of the pixel 12. As shown in FIG.

As shown in FIG. 2, the pixels 12 are connected to any one of row scanning lines g1 to gm (hereinafter referred to as row scanning line g) and any one of column data lines d1 to dn (hereinafter referred to as column data line d). ) and are provided at the intersections.

The pixel 12 includes an SRAM cell 201, a DRAM cell 202, and a liquid crystal display element LC. The SRAM cell 201 is composed of a switch SW1, which is a first switch, and a storage section SM1, which is a first data holding section. The DRAM cell 202 is composed of a switch SW2, which is a second switch, and a memory section DM2, which is a second data holding section. The liquid crystal display element LC has a known structure in which a liquid crystal LCM is filled in a space between a reflective electrode PE, which is a pixel electrode having a light-reflecting property, and a common electrode CE having a light-transmitting property and which are arranged to face each other with a space therebetween. is.

(Configuration of SRAM cell 201)
The switch SW1 is composed of, for example, an N-channel MOS transistor (hereinafter referred to as an NMOS transistor) MN1. The NMOS transistor MN1 forming the switch SW1 has a source connected to the input terminal (node a) of the storage unit SM1, a drain connected to the column data line d, and a gate connected to the row scanning line g.

The storage unit SM1 includes two inverters IN, one output terminal of which is connected to the other input terminal.
It is a self-holding memory consisting of V11 and INV12. More specifically, the inverter IN
The input terminal of V11 is the output terminal of the inverter INV12 and the N
It is connected to the source of the MOS transistor MN1. The input terminal of the inverter INV12 is connected to the switch SW2 and the output terminal of the inverter INV11.

FIG. 3 is a circuit diagram showing a specific configuration of the inverter INV11.
As shown in FIG. 3, the inverter INV11 includes a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) MP11 and an NMOS transistor MN connected in series.
11, and inverts the input signal supplied to each gate and outputs from each drain. Similarly, the inverter INV12 has a PMOS transistor MP12 and an NMOS transistor MN12 connected in series, and inverts the input signal supplied to each gate to output from each drain.
OS inverter.

Here, the drive capabilities of the inverters INV11 and INV12 are different. Specifically, among the inverters INV11 and INV12 forming the storage unit SM1, the driving capability of the transistors MP11 and MN11 in the inverter INV11 that is on the input side when viewed from the switch SW1 is the same as that of the inverter on the output side when viewed from the switch SW1. Transistor MP12,M in INV12
It is larger than the driving capacity of N12. This makes it easier for data to propagate from the column data line d to the memory unit SM1 via the switch SW1, while the data is transmitted to the memory unit DM via the switch SW2.
2 to the storage unit SM1.

Furthermore, the drive capability of the NMOS transistor MN1 that configures the switch SW1 is greater than the drive capability of the NMOS transistor MN12 that configures the inverter INV12. As a result, for example, when data indicating H level on the column data line d is stored in the storage unit SM1, the current flowing from the column data line d to the input terminal (node a) of the storage unit SM1 through the switch SW1 is Since it is larger than the current flowing from the input terminal of the storage unit SM1 to the ground voltage terminal GND via the NMOS transistor MN12, the data can be accurately stored in the storage unit SM1.

(Structure of DRAM cell 202)
Switch SW2 is a known transmission gate consisting of NMOS transistor MN2 and PMOS transistor MP2 connected in parallel. More specifically, NMOS
The sources of the transistor MN2 and the PMOS transistor MP2 are connected to the storage unit S
They are connected in common to the output terminal of M1, and their respective drains are connected in common to the input terminal of the memory section DM2 and the reflective electrode PE of the liquid crystal display element LC. And NMOS transistor MN
2 is connected to the forward trigger pulse trigger line trig, and the gate of the PMOS transistor MP2 is connected to the reverse trigger pulse trigger line trigb.

For example, the switch SW2 is turned on when the forward trigger pulse supplied through the trigger line trig is at H level (the inverted trigger pulse supplied through the trigger line trigb is at L level). The read data are stored in the storage section DM2 and the reflective electrode P
Transfer to E. Further, the switch SW2 is turned off when the forward trigger pulse supplied through the trigger line trig is at L level (the inverted trigger pulse supplied through the trigger line trigb is at H level). Reading of stored data is not performed.

Since switch SW2 is a known transmission gate, it can transfer a wide range of voltages from ground voltage GND to power supply voltage VDD in the ON state. More specifically, when the voltage applied from the storage unit SM1 to the sources of the transistors MN2 and MP2 is at the ground voltage GND level (L level), the source/drain of the PMOS transistor MP2 does not conduct, but the NMOS transistor MN2 The source/drain can be made conductive with low resistance. On the other hand, when the voltage applied from the storage unit SM1 to the sources of the transistors MN2 and MP2 is at the power supply voltage VDD level (H level), the source/drain of the NMOS transistor MN2 does not become conductive, but the source/drain of the PMOS transistor MP2 becomes It can conduct with low resistance. Thus, in the switch SW2, since the source/drain of the transmission gate can be made conductive with low resistance, a wide range of voltages from the ground voltage GND to the power supply voltage VDD can be transferred in the ON state.

The storage unit DM2 is composed of a capacitor C1. The capacitor C1 is, for example, an MIM (Metal Insulator Metal) capacitor that forms a capacitor between wirings, a diffusion capacitor that forms a capacitor between a substrate and polysilicon, or a PIP (Poly-Si) capacitor that forms a capacitor between two layers of polysilicon. Insulator Poly) capacity or the like can be used.

When the switch SW2 is turned on, the data stored in the memory SM1 is read out and transferred to the capacitor C1 and the reflective electrode PE in the memory DM2 via the switch SW2. Thereby, the data stored in the storage unit DM2 is rewritten.

Here, when the switch SW2 is on, the data held in the capacitor C1 is stored in the storage unit S
It also affects the input gate of the inverter INV12 forming M1. However, since the drive capability of the inverter INV11 is set to be greater than the drive capability of the inverter INV12, the inverter INV1 is set before the inverter INV12 is affected by the data of the capacitor C1.
1 overwrites the data in the capacitor C1. Therefore, the data held in the capacitor C1 does not unintentionally overwrite the data in the storage unit SM1.

As described above, the reflective liquid crystal display device 10 according to the present embodiment includes an SRAM cell and a DRA.
By using the pixel 12 having one M cell, the number of transistors constituting the pixel is reduced compared to the case of using a pixel having two SRAM cells, and the size of the pixel is reduced. .

Although the case where the switch SW2 is composed of the PMOS transistor MP2 and the NMOS transistor MN2 has been described in the present embodiment, the present invention is not limited to this. switch S
W2 can be appropriately changed to a configuration in which either one of the PMOS transistor MP2 and the NMOS transistor MN2 is provided. In that case, only one of the trigger lines trig and trigb is provided.

Note that the reflective liquid crystal display device 10 can not only achieve miniaturization of the pixels by reducing the number of transistors forming the pixels, but also the storage units SM1 and DM2 and the reflective electrodes PE as described below. By effectively arranging the pixels in the height direction, it is also possible to reduce the size of the pixels. A detailed description will be given below with reference to FIG.

(Cross-sectional structure of pixel 12)
FIG. 4 is a schematic cross-sectional view showing the essential parts of the pixel 12. As shown in FIG. In addition, in FIG. 4, a case where the capacitor C1 is configured by an MIM that forms a capacitor between wirings will be described as an example.

As shown in FIG. 4, an N well 101 and a P well 102 are formed on a silicon substrate 100 .

Formed on the N well 101 are a PMOS transistor MP2 of the switch SW2 and a PMOS transistor MP11 of the inverter INV11. More specifically, N
On the well 101, a common diffusion layer serving as sources and two diffusion layers serving as drains of the PMOS transistors MP2 and MP11 are formed. , polysilicon, which serves as the gates of the PMOS transistors MP2 and MP11, is formed through a gate oxide film.

On the P-well 102, an NMOS transistor MN2 of the switch SW2 and an NMOS transistor MN11 of the inverter INV11 are formed. More specifically, P
On the well 102, a common diffusion layer serving as sources and two diffusion layers serving as drains of the NMOS transistors MN2 and MN11 are formed. , polysilicon, which serves as the gates of the NMOS transistors MN2 and MN11, is formed through a gate oxide film.

An element isolation oxide film 103 is formed between the active region (diffusion layer and channel region) on the N-well and the active region on the P-well.

A first metal 106, a second metal 108, a third metal 110, an MIM electrode 112, a fourth metal 114 and a A fifth metal 116 is laminated.

The fifth metal 116 constitutes a reflective electrode PE formed for each pixel.

Diffusion layers forming the drains of the transistors MN2 and MP2 are connected to contacts 118,
First metal 106, through hole 119a, second metal 108, through hole 119b,
Third metal 110, through hole 119c, fourth metal 114, and through hole 11
It is electrically connected to the fifth metal 116 via 9e. Furthermore, the transistor MN
2 and MP2, the diffusion layers forming the drains of the contacts 118, the first metal 106,
Through hole 119a, second metal 108, through hole 119b, third metal 110,
MIM through the through hole 119c, the fourth metal 114, and the through hole 119d
It is electrically connected to electrode 112 . That is, the transistor M
Each source of N2 and MP2 is electrically connected to the reflective electrode PE and MIM electrode 112 .

The reflective electrode PE (fifth metal 116) is spaced and opposed to the common electrode CE, which is a transparent electrode, via a passivation film (PSV) 117, which is a protective film formed on its upper surface. A liquid crystal LCM is filled and sealed between the reflective electrode PE and the common electrode CE. A liquid crystal display element LC is composed of the reflective electrode PE, the common electrode CE, and the liquid crystal LCM therebetween.

Here, the MIM electrode 112 is formed on the third metal 110 with the interlayer insulating film 105 interposed therebetween. The MIM electrode 112, the third metal 110, and the interlayer insulating film 1 therebetween
05 constitutes a capacitor C1. Therefore, the switches SW1 and SW2 and the storage unit SM
1 is formed using a first metal 106 and a second metal 108, which are first and second layer wirings, and a transistor, while the memory part DM2 is formed using a third metal 110, which is an upper layer thereof.
and the MIM electrode 112 are used. That is, the switches SW1, SW2
Also, the memory section SM1 and the memory section DM2 are formed in different layers.

Light from a light source (not shown) passes through the common electrode CE and the liquid crystal LCM, is incident on the reflective electrode PE (fifth metal 116), is reflected, travels backward along the original incident path, and is emitted through the common electrode CE. .

As described above, the reflective liquid crystal display device 10 uses the fifth metal 116, which is the fifth layer wiring, as the reflective electrode PE, uses the third metal 110, which is the third layer wiring, as part of the memory section DM2, By using the first metal 106 and the second metal 108, which are first and second layer wiring, and the transistors as the memory part SM1 and the like, the memory part SM1, the memory part DM2, and the reflective electrode PE can be effectively arranged in the height direction. can be made, the pixel can be further miniaturized. As a result, for example, pixels with a pitch of 3 μm or less can be configured with transistors having a power supply voltage of 3.3V. By using pixels with a pitch of 3 μm or less, a liquid crystal display panel having a diagonal length of 0.55 inches and 4000 pixels in the horizontal direction and 2000 pixels in the vertical direction can be realized.

(Operation of reflective liquid crystal display device 10)
Next, the operation of the reflective liquid crystal display device 10 will be described with reference to FIG.
FIG. 5 is a timing chart showing the operation of the reflective liquid crystal display device 10. FIG.

As described above, in the reflective liquid crystal display device 10, the row scanning lines g1 to gm are sequentially selected one by one in 1H units by the row scanning signal from the vertical shift register 14, so that the image display section 11 is configured. Data is written into the plurality of pixels 12 in units of n pixels in one row commonly connected to the selected row scanning line. After data is written in all of the plurality of pixels 12 forming the image display section 11, the data of all the pixels 12 are read out simultaneously based on the trigger pulses TRI and TRIB (more specifically, The data in the storage section SM1 in all the pixels 12 are transferred to the storage section DM2 and the reflective electrode PE all at once).

FIG. 5A shows changes in subframe data stored in each pixel 12. FIG. The vertical axis represents line numbers, and the horizontal axis represents time. As shown in FIG. 5A, the boundary line of the subframe data slopes downward to the right. This means that subframe data is written later for pixels with larger row numbers. The period from one end to the other end of this boundary line corresponds to the write period of the subframe data. B0b, B1b, and B2b indicate inverted data of the subframe data of bits B0, B1, and B2, respectively.

FIG. 5B shows the output timing (rising timing) of the trigger pulse TRI. Note that the trigger pulse TRIB is omitted because it always indicates a value obtained by logically inverting the trigger pulse TRI. FIG. 5C schematically shows bits of subframe data applied to the reflective electrode PE. (D) of FIG. 5 shows changes in the value of the common electrode voltage Vcom. (E) of FIG. 5 shows changes in the voltage applied to the liquid crystal LCM.

First, in the pixel 12 selected by the row scanning signal, the switch SW1 is turned on, so that the normal subframe data of bit B0 output from the horizontal driver 16 to the column data line d is
The data is sampled by the switch SW1 and written to the storage unit SM1. Similarly, the non-inverted subframe data of bit B0 is written in the memory SM1 of all the pixels 12 forming the image display section 11 . After that, the H-level trigger pulse TRI (and the L-level trigger pulse TRIB) are simultaneously supplied to all the pixels 12 forming the image display section 11 (time T1).

As a result, the switches SW2 of all the pixels 12 are turned on, so that the non-inverted subframe data of bit B0 stored in the storage unit SM1 are transferred all at once to the storage unit DM2 through the switch SW2 and held therein. The normal subframe data of B0 is applied to the reflective electrode PE. Here, as can be seen from FIG. 5C, the period during which the non-inverting subframe data of bit B0 is held by the memory section DM2 (the period in which the non-inverting subframe data of bit B0 is applied to the reflective electrode PE). after the trigger pulse TRI becomes H level (time T1
), and then it is one subframe period until it becomes H level again (time T2).

Here, when the bit value of the subframe data is "1", ie, H level, the power supply voltage VDD (here, 3.3 V) is applied to the reflective electrode PE, and when the bit value is "0", ie, L level, A ground voltage GND (0 V) is applied to the reflective electrode PE. On the other hand, to the common electrode CE, a free voltage can be applied as the common electrode voltage Vcom without being restricted by the ground voltage GND and the power supply voltage VDD. Control is performed so that the common electrode voltage Vcom is synchronously switched to a predetermined voltage. In this example, the common electrode voltage Vcom is higher than 0 V by the liquid crystal threshold voltage Vtt as shown in FIG. Set to low voltage.

The liquid crystal display element LC performs gradation display according to the voltage applied to the liquid crystal LCM, which is the absolute value of the voltage difference between the voltage applied to the reflective electrode PE and the common electrode voltage Vcom. Therefore, the subframe period (time T1 to T2) during which the normal subframe data of bit B0 is applied to the reflective electrode PE
Then, as shown in FIG. 5E, the voltage applied to the liquid crystal LCM is 3.3V+Vtt (=3.3V-(-Vtt)) when the bit value of the subframe data is "1". When the bit value of the data is "0", it becomes +Vtt (=0V-(-Vtt)).

FIG. 6 shows the relationship between the voltage applied to the liquid crystal (RMS voltage) and the grayscale value of the liquid crystal.
Referring to FIG. 6, the grayscale value curve shows that the black grayscale value corresponds to the RMS voltage of the liquid crystal threshold voltage Vtt, and the white grayscale value corresponds to the liquid crystal saturation voltage Vsat (
=3.3V+Vtt). It is possible to match the grayscale values to the useful part of the liquid crystal response curve. Therefore, the liquid crystal display element LC
displays white when the voltage applied to the liquid crystal LCM is (3.3V+Vtt) as described above, and +V
When tt, black is displayed.

Returning to FIG. 5, during the subframe period (time T1 to T2) in which the liquid crystal display element LC displays the normal subframe data of bit B0, all the pixels 1 forming the image display section 11
Writing of the inverted subframe data of the bit B0 to the storage unit SM1 of No. 2 is sequentially started. Then, when the inverted subframe data of bit B0 is written to the memory SM1 of all the pixels 12 forming the image display section 11, all the pixels 12 forming the image display section 11 are set at H level. Trigger pulse TRI (and L level trigger pulse TR
IB) are supplied at the same time (time T2).

As a result, the switches SW2 of all the pixels 12 are turned on, so that the inverted subframe data of the bit B0 stored in the storage unit SM1 are transferred all at once to the storage unit DM2 through the switch SW2 and held therein. is applied to the reflective electrode PE. Here, as can be seen from FIG. 5C, the period during which the memory section DM2 holds the inverted subframe data of the bit B0 (the period during which the inverted subframe data of the bit B0 is applied to the reflective electrode PE) is After the trigger pulse TRI becomes H level (time T2
), and then it is one subframe period until it becomes H level again (time T3). Here, since the inverted subframe data of bit B0 and the normal subframe data of bit B0 always have a relationship of opposite logical values, when the normal subframe data of bit B0 is "1", it is "0". It is "1" when the normal subframe data of B0 is "0".

On the other hand, the common electrode voltage Vcom is such that the inverted subframe data of bit B0 is the reflective electrode PE.
is set to a voltage higher than 3.3 V by the threshold voltage Vtt of the liquid crystal, as shown in FIG. 5(D). Therefore, in the subframe period (time T2 to T3) in which the inverted subframe data of bit B0 is applied to the reflective electrode PE, the voltage applied to the liquid crystal LCM is -Vtt when the bit value of the subframe data is "1". (=3.3V-(
3.3V+Vtt)), and -3.3 when the bit value of the subframe data is "0".
V−Vtt (=0V−(3.3V+Vtt)).

For example, when the bit value of the normal subframe data of bit B0 is "1", the bit value of the inverted subframe data of bit B0 to be applied subsequently becomes "0". At this time, the voltage applied to the liquid crystal LCM becomes −(3.3V+Vtt), and the direction of the potential is reversed compared to when the normal subframe data of bit B0 is applied, but the absolute value is the same. . Therefore, the pixel 12 displays white even when the inverted subframe data of bit B0 is applied, similarly to when the non-inverted frame data of bit B0 is applied. When the bit value of the normal subframe data of bit B0 is "0", the bit value of the inverted subframe data of bit B0 to be applied subsequently becomes "1". At this time, the voltage applied to the liquid crystal LCM becomes -Vtt, and the direction of the potential is reversed, but the absolute value is the same as when the normal subframe data of bit B0 is applied. Therefore, the pixel 12 displays black when the inverted subframe data of bit B0 is applied as well as when the non-inverted frame data of bit B0 is applied.

Therefore, as shown in (E) of FIG. 5, the pixel 12 displays the same gradation for the bit B0 and the complementary bit B0b of the bit B0 during the two subframe periods from time T1 to T3. Since AC driving is performed in which the potential direction is reversed for each subframe, burn-in of the liquid crystal LCM can be prevented.

Subsequently, during the subframe period (time T2 to T3) during which the liquid crystal display element LC displays the inverted subframe data of bit B0, the non-inverted subframe data of bit B1 is written to the storage unit SM1 of all the pixels 12. are started sequentially. And the image display unit 11
When the forward subframe data of bit B1 is written to the storage unit SM1 of all the pixels 12 of the image display unit 11, the H level trigger pulse TRI (and the L level trigger pulse TRIB) is supplied at the same time (time T3).

As a result, the switches SW2 of all the pixels 12 are turned on, so that the non-inverted subframe data of the bit B1 stored in the memory SM1 are simultaneously transferred to the memory DM2 through the switches SW2 and held therein. The normal subframe data of bit B1 is applied to the reflective electrode PE. Here, as can be seen from (C) of FIG. 5, the period during which the non-inverted subframe data of bit B1 is held by the memory section DM2 (the period in which the non-inverted subframe data of bit B1 is applied to the reflective electrode PE). after the trigger pulse TRI becomes H level (time T
3), it is one subframe period until it becomes H level again (time T4).

On the other hand, the common electrode voltage Vcom is such that the non-inverted subframe data of bit B1 is the reflective electrode PE.
is set to a voltage lower than 0 V by the liquid crystal threshold voltage Vtt, as shown in FIG. 5(D). Therefore, in the subframe period (time T3 to T4) in which the normal subframe data of bit B1 is applied to the reflective electrode PE, the voltage applied to the liquid crystal LCM is as shown in FIG. If the bit value is "1",3.
3V+Vtt (=3.3V-(-Vtt)), and the bit value of the subframe data becomes "
0”, +Vtt (=0V-(-Vtt)).

Subsequently, during the subframe period (time T3 to T4) in which the liquid crystal display element LC displays the normal subframe data of bit B1, the bit B1 for the storage unit SM1 of all the pixels 12 constituting the image display unit 11 is displayed. , the writing of the inverted subframe data is started sequentially. Then, the bit B1 is stored in the memory SM1 of all the pixels 12 forming the image display unit 11.
is written, thereafter, an H level trigger pulse TRI (and an L level trigger pulse TRIB
) are supplied at the same time (time T4).

As a result, the switches SW2 of all the pixels 12 are turned on, so that the inverted subframe data of the bit B1 stored in the memory SM1 are transferred all at once to the memory DM2 through the switch SW2 and held therein. is applied to the reflective electrode PE. Here, as can be seen from FIG. 5C, the period during which the memory section DM2 holds the inverted subframe data of the bit B1 (the period during which the inverted subframe data of the bit B1 is applied to the reflective electrode PE) is After the trigger pulse TRI becomes H level (time T4
), and then it is one subframe period until it becomes H level again (time T5). Here, the inverted subframe data of bit B1 always has a relationship of opposite logical values with the normal inverted subframe data of bit B1.

On the other hand, the common electrode voltage Vcom is such that the inverted subframe data of bit B1 is the reflective electrode PE.
is set to a voltage higher than 3.3 V by the threshold voltage Vtt of the liquid crystal, as shown in FIG. 5(D). Therefore, in the subframe period (time T4 to T5) in which the inverted subframe data of bit B1 is applied to the reflective electrode PE, the voltage applied to the liquid crystal LCM is -Vtt when the bit value of the subframe data is "1". (=3.3V-(
3.3V+Vtt)), and -3.3 when the bit value of the subframe data is "0".
V−Vtt (=0V−(3.3V+Vtt)).

As a result, as shown in FIG. 5(E), the pixel 12 displays the same gradation for the bit B1 and the complementary bit B1b of the bit B1 during the two subframe periods from time T3 to T5, and the liquid crystal LCM Since AC driving is performed in which the potential direction of is reversed for each subframe, burn-in of the liquid crystal LCM can be prevented. The same operation is repeated for bit B2 and after.

Thus, the reflective liquid crystal display device 10 performs gradation display by combining a plurality of subframes.

The display periods of the bit B0 and the complementary bit B0b are the same first subframe period, and the display periods of the bit B1 and the complementary bit B1b are also the same second subframe period. The subframe period and the second subframe period are not always the same. Here, as an example, the second subframe period is set to be twice as long as the first subframe period. Further, as shown in FIG. 5(E), the third subframe period, which is the display period of the bit B2 and the complementary bit B2b, is set twice as long as the second subframe period.
The same can be said for other subframe periods. The length of each subframe period and the number of subframes can be arbitrarily set according to system specifications and the like.

(Detailed description of dummy pixel 12d and temperature sensor S1 provided therein)
Next, details of the dummy pixel 12d and the temperature sensor S1 provided therein will be described. As described above, the dummy pixel 12d is composed of a dummy liquid crystal display element and a circuit portion, and the temperature sensor S1 for detecting the temperature of the pixel 12 is formed in the circuit portion.

The dummy pixels 12d (in other words, the temperature sensors S1) are arranged (formed) instead of the pixels 12 in a partial area of a plurality of rectangular pixel arrangement areas in plan view. In the example of FIG. 1, the dummy pixel 12d (in other words, the temperature sensor S1) is located in one of the plurality of pixel arrangement regions provided in a rectangular shape in a plan view (lower left corner of the paper). corner regions) instead of the pixels 12 .

FIG. 7 is a circuit diagram showing a specific configuration of the temperature sensor S1.
As shown in FIG. 7, the temperature sensor S1 is, for example, a PN junction diode configured by shorting the base and collector electrodes of a PNP bipolar transistor. For example, the host device 20 flows a constant current between the anode and cathode of a PN junction diode (emitter-collector of a PNP bipolar transistor), and measures the potential difference between the two electrodes at that time to measure the temperature of the pixel 12. can be calculated. Here, since the temperature sensor S1 is provided adjacent to the pixel 12, the temperature of the pixel 12 can be detected accurately and in real time.

(Cross-sectional structure of dummy pixel 12d)
FIG. 8 is a schematic cross-sectional view showing a main part of the dummy pixel 12d.
A dummy pixel 12d shown in FIG. 8 has a different structure from the pixel 12 shown in FIG.

The temperature sensor S1 is formed in a layer below the first metal 106 .
First, the PNP type bipolar transistor used for the temperature sensor S1 is an N well 10
1, a P-well 102, and diffusion electrodes P1, N1, P2. Specifically, a P-type diffusion electrode P1 and an N-type diffusion electrode N1 formed on the N-well 101 are used as an emitter electrode (P1) and a base electrode (N1), respectively, and formed on the P-well 102. The P-type diffusion electrode P2 is used as a collector electrode (P2). Here, the emitter electrode P1 and the base electrode N1 are PN-junctioned through the N-well 101, and the collector electrode P2 and the base electrode N1 are PN-junctioned through the P-well 102 and the N-well 101. FIG. With such a configuration, a PNP bipolar transistor is formed. Also, the base electrode N1 and the collector electrode P2 are short-circuited via the contact 118 and the first metal 106. FIG. With such a configuration, a PN junction diode, that is, a temperature sensor S1 is formed. P.
The anode and cathode (emitter electrode P1 and collector electrode P2) of the N-junction diode are both connected to an external host device (not shown) 20 via contacts 118, first metal 101, bonding wires (not shown), etc. be done.

(Planar structure of temperature sensor S1)
FIG. 9 is a schematic plan view of each electrode of the PNP-type bipolar transistor used for the temperature sensor S1.

As shown in FIG. 9, each electrode of the PNP bipolar transistor used for the temperature sensor S1 is formed within one pixel arrangement region. Specifically, a P-type diffusion electrode P1 used as an emitter electrode, an N-type diffusion electrode N1 used as a base electrode, and an N-type diffusion electrode P2 used as a collector electrode are formed in one pixel arrangement region. It is
A PN junction diode is formed by short-circuiting the base electrode N1 and the collector electrode of this PNP bipolar transistor via the first metal 106 or the like. PN
The anode and cathode (emitter electrode P1 and collector electrode P2) of the junction diode are
Both are connected to a host device (not shown) 20 via contacts 118, first metal 106, bonding wires (not shown), and the like.

It is preferable that the two wires extending from the temperature sensor S1 to the pad of the chip toward the host device 20 are wired in parallel while being adjacent to each other. As a result, even if noise occurs, noise of the same magnitude occurs in each of the two wirings, so the noise is canceled when the potential difference between the two wirings is measured. As a result, the temperature sensor S
1 can measure the temperature of the pixel 12 with higher accuracy.

In the example of FIG. 9, the case where the temperature sensor S1 is a diode-connected PNP bipolar transistor has been described, but the present invention is not limited to this. The temperature sensor S1 may be a diode-connected NPN bipolar transistor or a general diode.

The pattern shape of the second metal and above of the dummy pixel 12 d is basically the same as the pattern shape of the pixel 12 . Therefore, of the light incident from above the substrate, the reflective electrode PE (
The amount of light that penetrates into the substrate through the gaps of the fifth metal 116) is about the same as that of the pixels 12. FIG. As a result, the temperature sensor S1 provided in the dummy pixel 12d can detect the temperature of the pixel 12 in the same environment as the amount of light incident on the inside of the pixel, so the temperature of the pixel 12 can be detected more accurately. It becomes possible to That is, with this configuration, the temperature of the pixel 12 can be measured with higher accuracy than when the temperature is measured using the temperature sensor attached on the heat sink.

When the display pattern changes due to the difference in picture pattern, the operation contents of each circuit block such as the timing generator 13, the vertical shift register 14, and the horizontal driver 16 shown in FIG. 1 change according to the display pattern. The current consumption also changes according to the display pattern. Here, in a circuit block with increased current consumption, there is a possibility that an IR drop will occur, causing the power supply voltage to drop or the ground voltage to rise. Since the location where the IR drop occurs changes according to the display pattern, the location where the power supply voltage and the ground voltage fluctuate also changes according to the display pattern. Therefore, when a temperature sensor is attached to an empty space in an area surrounding a panel composed of a plurality of pixels, it will be affected by the IR drop, and the temperature of the pixels 12 cannot be measured accurately and in real time.

On the other hand, the reflective liquid crystal display device of this embodiment has the temperature sensor S1 in the pixel arrangement region.
By arranging the
2 temperature can be measured.

(Cross-sectional structure of dummy liquid crystal display element LCd)
Returning to FIG. 8, the description is continued. In the upper layer of the circuit portion of the dummy pixel 12d, similarly to the case of the pixel 12, the reflective electrode PE, the PSV 117, the liquid crystal LCM, and the common electrode CE are formed in this order, and these constitute the dummy liquid crystal display element LCd. there is Here, the reflective electrode PE of the dummy liquid crystal display element LCd is connected to the reflective electrode PE of the liquid crystal display element LC provided in the pixel 12 adjacent to the dummy pixel 12d. A specific description will be given below.

(Planar structure of pixel 12 and dummy pixel 12d)
FIG. 10 is a schematic plan view showing part of the reflective electrode PE used for each of the plurality of pixels 12 and dummy pixels 12d.

In the example of FIG. 10, among a plurality of pixel arrangement regions provided in a rectangular shape in plan view, dummy pixels 12d are arranged in regions located at corners, and a plurality of pixels are arranged in a plurality of regions other than the corner regions. 12
are placed. Further, frame electrodes are arranged in peripheral regions of the plurality of pixel arrangement regions. Note that the common electrode CE of each of the plurality of pixels 12 and the dummy pixels 12d is used as the frame electrode.
At the same time, the alternating signal FR is supplied as the common electrode voltage Vcom. As a result, the potential difference between the frame electrode and the common electrode CE becomes 0 V, so black is displayed on the frame electrode.

Here, the reflective electrode PE of the dummy liquid crystal display element LCd provided in the dummy pixel 12d is
Pixel 12 adjacent to dummy pixel 12d (pixel 12 one above dummy pixel 12d on the paper surface)
is connected to the reflective electrode PE of the liquid crystal display element LC provided in the . Note that dummy pixels 12
The reflective electrode PE of d and the circuit section below it are electrically isolated by adjusting the patterns of contacts and through holes. Therefore, the same voltage is applied to the reflective electrode PE of the dummy pixel 12 d and the reflective electrode PE of the adjacent pixel 12 .

As a result, adjacent pixels 12 connected to the dummy pixel 12d are connected to the dummy pixel 12d.
The same pattern (image) as the pattern (image) of is displayed. However, in the case of, for example, a 4K×2K resolution panel, only one dummy pixel 12d at the corner displays the same pattern as that of the adjacent pixel 12, so that the image disturbance of the entire screen is negligible. to small. Moreover, even if a full-screen black display or a full-screen white display is performed, a bright spot or a black spot where only one pixel shines does not occur. Furthermore, in this case, it is the case of every other horizontal line that is recognized as defective, but the dummy pixel 12d is only one pixel in the corner of the screen, so it is hardly recognized as defective.

Note that the dummy pixel 12d and the adjacent pixel 12 connected thereto are not limited to direct short-circuiting between the reflective electrodes, and may be short-circuited via an underlying metal, through hole, contact, or the like. In this case, the shape of the reflective electrode PE of the dummy pixel 12d can be made the same as the shape of the reflective electrode PE of the pixel 12, so that the dummy pixel 12d and the pixel 12 can have the same aperture ratio.

In addition, since the dummy pixels 12d are arranged at the corners of the screen, it is easy to route two wires extending from the temperature sensor S1 to the pads of the chip toward the host device 20. FIG.

In the present embodiment, the case where the dummy pixels 12d are arranged in the regions located at the corners of the plurality of pixel arrangement regions provided in a rectangular shape in plan view has been described as an example, but the present invention is not limited to this. do not have. The dummy pixels 12d may be arranged in any one of the regions provided along the outer periphery of a plurality of pixel arrangement regions provided in a rectangular shape in plan view. In this case, it is easy to route two wirings extending from the temperature sensor S1 to the pads of the chip toward the host device 20 . Alternatively, the dummy pixels 12d may be arranged in any one of the internal regions among a plurality of pixel arrangement regions provided in a rectangular shape in plan view in order to improve the accuracy of temperature detection by the temperature sensor S1.

Further, in the present embodiment, the dummy pixels 12d are arranged in one of the plurality of pixel arrangement regions.
is arranged, but the present invention is not limited to this. The dummy pixels 12d may be arranged in a plurality of regions among the plurality of pixel arrangement regions. As a result, the area of the temperature sensor S1 can be increased, so that the accuracy of temperature detection by the temperature sensor S1 can be improved. The second embodiment will be described in detail below.

<Embodiment 2>
FIG. 11 is a schematic plan view showing part of the reflective electrode PE used for each of the plurality of pixels 12 and dummy pixels 12d in the liquid crystal display device according to the second embodiment.

In the example of FIG. 11, four dummy pixels 12d are provided in each of 2×2 (a total of four) pixel arrangement regions adjacent to each other among a plurality of pixel arrangement regions provided in a rectangular shape in plan view. A plurality of pixels 12 are arranged in a plurality of other regions.

Note that the temperature sensor S1 includes four PN sensors formed in each of the four dummy pixels 12d.
It may be configured by connecting P-type bipolar transistors in parallel, or may be configured by one PNP-type bipolar transistor enlarged and formed in the circuit portion of the four dummy pixels 12d. When a plurality of dummy pixels 12d are arranged, it is possible to form the PN junction diode for the temperature sensor S1 with a higher degree of freedom than when one dummy pixel 12d is arranged. By arranging a plurality of dummy pixels 12d, connecting a plurality of temperature sensors S1 in parallel, or by arranging one large temperature sensor S1, it is possible to improve the accuracy of the measured temperature.

Further, frame electrodes are arranged in peripheral regions of the plurality of pixel arrangement regions. The frame electrode is supplied with the alternating signal FR as a common electrode voltage Vcom together with the common electrode CE of each of the plurality of pixels 12 and the four dummy pixels 12d. As a result, the potential difference between the frame electrode and the common electrode CE becomes 0 V, so black is displayed on the frame electrode.

Here, the reflective electrodes PE of a total of four dummy pixels 12d arranged in each of the 2×2 pixel arrangement regions are connected to the reflective electrodes PE of four adjacent pixels 12, respectively.
The reflective electrode PE of the dummy pixel 12d and the underlying circuit section are electrically isolated by adjusting the patterns of contacts and through holes. Therefore, the same voltage is applied to the reflective electrode PE of the dummy pixel 12 d and the reflective electrode PE of the adjacent pixel 12 .

As a result, the same pattern (image) as that of the four adjacent pixels 12 connected thereto is displayed on the four dummy pixels 12d. However, in the case of, for example, a 4K×2K resolution panel, only the four dummy pixels 12d display the same pattern as that of the adjacent pixels 12, so that the image disturbance of the entire screen is negligibly small. . Further, even if an all-screen black display or an all-screen white display is performed, there will be no luminescent spots or black spots where only four pixels are illuminated.

Further, in the example of FIG. 11, the reflective electrodes PE of the four dummy pixels 12d are connected to the common adjacent pixel 1
2 reflective electrodes PE of different adjacent pixels 12, respectively.
It is connected to the. As a result, different patterns (images) of the adjacent pixels 12 are displayed on the four dummy pixels 12d, so that it is possible to make the disturbance of the image on the entire screen less noticeable.

Note that the dummy pixel 12d and the adjacent pixel 12 connected thereto are not limited to direct short-circuiting between the reflective electrodes, and may be short-circuited via an underlying metal, through hole, contact, or the like. In this case, the shape of the reflective electrode PE of the dummy pixel 12d can be made the same as the shape of the reflective electrode PE of the pixel 12, so that the dummy pixel 12d and the pixel 12 can have the same aperture ratio.

In the present embodiment, a case where a total of four dummy pixels 12d of 2×2 are arranged adjacent to each other has been described, but the present invention is not limited to this. Any number of dummy pixels 12d may be arranged within a permissible range. Also, the plurality of dummy pixels 12d need not be adjacent to each other.

<Embodiment 3>
FIG. 12 is a schematic plan view showing part of the reflective electrode PE used for each of the plurality of pixels 12 and dummy pixels 12d in the liquid crystal display device according to the third embodiment.

In the example of FIG. 12, among a plurality of pixel arrangement regions provided in a rectangular shape in plan view, a plurality of dummy pixels 12d are arranged in each of a plurality of regions arranged along one side of the outer periphery. A plurality of pixels 12 are arranged in a plurality of regions other than the region.

Note that the temperature sensor S1 includes a plurality of PNs formed in each of the plurality of dummy pixels 12d.
It may be configured by connecting P-type bipolar transistors in parallel, or may be configured by one PNP-type bipolar transistor enlarged and formed in the circuit portion of the plurality of dummy pixels 12d. When a plurality of dummy pixels 12d are arranged, it is possible to form the PN junction diode for the temperature sensor S1 with a higher degree of freedom than when one dummy pixel 12d is arranged. By arranging a plurality of dummy pixels 12d, connecting a plurality of temperature sensors S1 in parallel, or by arranging one large temperature sensor S1, it is possible to improve the accuracy of the measured temperature.

Further, frame electrodes are arranged in peripheral regions of the plurality of pixel arrangement regions. The frame electrode is supplied with the alternating signal FR as a common electrode voltage Vcom together with the common electrode CE of each of the plurality of pixels 12 and the plurality of dummy pixels 12d. As a result, the potential difference between the frame electrode and the common electrode CE becomes 0 V, so black is displayed on the frame electrode.

Here, the reflective electrodes PE of the plurality of dummy pixels 12d arranged along one side of the outer periphery of the entire screen are all connected to the frame electrode. The reflective electrode PE of the dummy pixel 12d and the underlying circuit section are electrically isolated by adjusting the patterns of contacts and through holes. Therefore, the same voltage is applied to the reflective electrode PE and the frame electrode of the dummy pixel 12d.

As a result, a plurality of dummy pixels 12d arranged along one side of the outer periphery of the entire screen display black, which is the same as the frame electrode, instead of displaying a dummy pattern (image). However, since the black displayed by the plurality of dummy pixels 12d is continuous with the black displayed by the frame electrode, only one column of the image of the entire screen is not displayed, and the same pattern is displayed. There is no image disturbance such as is displayed.

Note that the reflective electrode PE of the dummy pixel 12d and the frame electrode connected thereto are not limited to being directly short-circuited, and may be short-circuited via an underlying metal, through hole, contact, or the like. In this case, the shape of the reflective electrode PE of the dummy pixel 12d can be made the same as the shape of the reflective electrode PE of the pixel 12, so that the dummy pixel 12d and the pixel 12 can have the same aperture ratio.

In the present embodiment, a case has been described in which a plurality of dummy pixels 12d for one row are arranged along one side of the outer periphery in a plurality of pixel arrangement regions provided in a rectangular shape in plan view.
It is not limited to this. A plurality of dummy pixels 12d for arbitrary columns may be arranged within a permissible range. Also, the plurality of dummy pixels 12d may be arranged along each of two or more sides, not limited to one side of the outer periphery.

As described above, in the reflective liquid crystal display devices according to the first to third embodiments, by arranging the dummy pixels 12d having the temperature sensors S1 in part of the plurality of pixel arrangement regions,
The temperature of the pixel 12 can be measured accurately and in real time. Further, in the reflective liquid crystal display devices according to the first to third embodiments, the temperature sensor can be formed using the circuit portion of the dummy pixel 12d, and there is no need to separately prepare and install the temperature sensor. , the material cost and installation cost of the temperature sensor can be reduced.

Note that the reflective electrode PE of the dummy pixel 12d, the reflective electrode PE or the frame electrode of the pixel 12,
The connecting means is not limited to the above-described contents, and any connecting means can be used without departing from the scope.

REFERENCE SIGNS LIST 10 liquid crystal display device 11 image display unit 12 pixel 12d dummy pixel 13 timing generator 14 vertical shift register 15 data latch circuit 16 horizontal driver 20 host device 100 silicon substrate 101 N well 102 P well 103 element isolation oxide film 105 interlayer insulating film 106 th 1st metal 108 2nd metal 110 3rd metal 112 MIM electrode 114 4th metal 116 5th metal 117 Passivation film (PSV)
118 contact 119a-119e through-hole 161 horizontal shift register 162 latch unit 163 level shifter/pixel driver 164 latch circuit 1641-1643 latch circuit group 201 SRAM cell 202 DRAM cell d1-dn column data lines dL, dM, dR column data line group g1 ~gm Row scanning line trig, trigb Trigger line BF1 Buffer C1 Capacitor CE Common electrode D1L, D1bL, D2L, D2bL Delay buffer D1R, D1bR, D2R, D2bR Delay buffer DM2 Storage unit INV11, INV12 Inverter IV1 Inverter IV21, IV22 Inverter LC Liquid crystal Display element LCd Dummy liquid crystal display element LCM Liquid crystal MN1, MN2 NMOS transistor MN11, MN12 NMOS transistor MN21, MN22 NMOS transistor MP2 PMOS transistor MP11, MP12 PMOS transistor MP21, MP22 PMOS transistor PE Reflective electrode S1 Temperature sensor SM1 Storage section SW1, SW2 Switch SW21, SW22 switch

Claims (4)

a plurality of pixels;
a temperature sensor;
The temperature sensor is formed in one or more regions of a plurality of pixel arrangement regions partitioned in a matrix,
Each pixel is
a liquid crystal display element composed of a common electrode, a reflective electrode, and a liquid crystal sealed between them;
a circuit unit that applies a voltage corresponding to an image to be displayed to the reflective electrode;
has
A dummy liquid crystal display element is formed so as to cover the temperature sensor,
The temperature sensor is provided so as to be capable of outputting the temperature of the period during which each pixel displays an image in real time at any time through a wiring different from that of the circuit unit.
A reflective liquid crystal display device. The temperature sensor is formed in one of a plurality of regions provided along the outer periphery of the plurality of pixel arrangement regions provided in a rectangular shape in plan view,
2. The reflective liquid crystal display device according to claim 1. The reflective electrode of the dummy liquid crystal display element is formed so as to be short-circuited with the reflective electrode of the liquid crystal display element provided in the pixel adjacent to the dummy liquid crystal display element,
3. The reflective liquid crystal display device according to claim 1. The temperature sensors are formed in a plurality of regions provided along the outer periphery of the plurality of pixel arrangement regions provided in a rectangular shape in plan view,
The reflective electrode of the dummy liquid crystal display element is formed so as to be short-circuited with a frame electrode surrounding the plurality of pixel arrangement regions in plan view,
3. The reflective liquid crystal display device according to claim 1.

Images