JP7323116B2 - Semiconductor package manufacturing method and semiconductor package - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor package having bumps on the lower surface of an outer shell, and to a semiconductor package.

Conventionally, BGA (Ball Grid Array) is known as a semiconductor package having bumps on the lower surface of an outer shell. BGA generally mounts a semiconductor element on the upper surface of the package substrate and electrically connects it to the circuit of the package substrate, then molds the semiconductor element with a thermosetting resin to seal the semiconductor element, and finally attaches to the lower surface of the package substrate. It is manufactured by attaching bumps to the external terminals. A semiconductor package called FOWLP (Fan Out Wafer Level Package) is also known. Since the FOWLP does not have a package substrate like the BGA, it is thin and has a short wiring length. In a typical FOWLP manufacturing method, first, a rewiring layer is formed on a support made of silicon or glass. After the semiconductor element is mounted on the upper surface of the rewiring layer and electrically connected, the semiconductor element is sealed by molding with a thermosetting resin. Finally, the support is removed from the rewiring layer, and bumps are formed on the lower surface side of the rewiring layer (see Patent Document 1 below).

Japanese Patent Application Laid-Open No. 2018-32809

However, in semiconductor packages such as BGA and FOWLP, the material of the outer shell is different between the bump side (lower surface side) and the opposite side (upper surface side), so that the outer shell may be warped and deformed when heated. rice field. As a result, when the semiconductor package mounted on the substrate is subjected to thermal changes, the bumps are peeled off from the substrate, and there is a possibility that the mounting substrate may malfunction.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor package and a semiconductor package that can prevent warping deformation of the outer shell due to heat.

A method of manufacturing a semiconductor package according to the present invention comprises: an external terminal setting step of setting a plurality of external terminals on an upper surface of a support made of a metal material; a first molding step of forming a lower shell holding the plurality of external terminals by molding the upper surface of the lower shell with resin ; a rewiring layer forming step of forming a rewiring layer electrically connected to a plurality of external terminals; and mounting a semiconductor element on the rewiring layer formed by the rewiring layer forming step and rewiring the semiconductor element. A semiconductor element connecting step of electrically connecting to a layer; and after the semiconductor element connecting step, the upper surface of the lower shell is molded with the same resin as the lower shell to form an upper shell, a second molding step of encapsulating the entirety of the semiconductor element and the rewiring layer with an outer shell composed of the lower outer shell and the upper outer shell ; after the second molding step, the outer shell; a support removing step of removing the support from the bottom surface to expose each of the plurality of external terminals on the bottom surface of the shell.

A semiconductor package according to the present invention includes an outer shell formed of resin and having a plurality of external terminals exposed on the lower surface, and a rewiring layer sealed in the outer shell and electrically connected to each of the plurality of external terminals. and a semiconductor element sealed in the outer shell and electrically connected to the rewiring layer, wherein the outer shell includes a lower outer shell sealing the external terminals, and an upper surface of the lower outer shell. and an upper shell body for encapsulating the entirety of the semiconductor element and the rewiring layer , wherein the lower shell body and the upper shell body are made of the same resin.

According to the present invention, it is possible to provide a method for manufacturing a semiconductor package and a semiconductor package that can prevent warping deformation of the outer shell due to heat.

1 is a side cross-sectional view of a semiconductor package according to an embodiment of the present invention; FIG. (a), (b), and (c) are diagrams for explaining the procedure up to the first molding step of the semiconductor package manufacturing method according to the embodiment of the present invention; FIG. 4 is an upper perspective view at the end of an external terminal installation process in a method of manufacturing a semiconductor package according to an embodiment of the present invention; FIG. 11 is an upper perspective view at the end of the first molding step in the semiconductor package manufacturing method according to the embodiment of the present invention; FIG. 4 is an upper perspective view at the end of a via hole forming step in the method of manufacturing a semiconductor package according to an embodiment of the present invention; (a) side cross-sectional view at the end of the copper sputtering process, (b) side cross-sectional view at the end of the copper plating process, and (c) at the end of the resist forming process of the semiconductor package manufacturing method according to the embodiment of the present invention. side view (a) Side sectional view at the end of the etching process (b) Side sectional view at the end of the resist removing process of the semiconductor package manufacturing method according to the embodiment of the present invention FIG. 4 is a side cross-sectional view at the end of a rewiring layer forming step in a method of manufacturing a semiconductor package according to an embodiment of the present invention; FIG. 4 is an upper perspective view at the time when a rewiring layer forming step of the semiconductor package manufacturing method according to the embodiment of the present invention is completed; (a) to (e) diagrams for explaining procedures after a rewiring layer forming step in a semiconductor package manufacturing method according to an embodiment of the present invention; FIG. 4 is an upper perspective view at the end of a semiconductor element mounting process in a method of manufacturing a semiconductor package according to an embodiment of the present invention; FIG. 4 is an upper perspective view at the end of the wire bonding process of the semiconductor package manufacturing method according to the embodiment of the present invention; FIG. 4 is an upper perspective view at the end of the second molding step in the method of manufacturing a semiconductor package according to one embodiment of the present invention; (a) Upper perspective view (b) Lower perspective view at the end of the support removing step in the method for manufacturing a semiconductor package according to an embodiment of the present invention (a) Upper perspective view (b) Lower perspective view at the end of the bump formation step of the method for manufacturing a semiconductor package according to an embodiment of the present invention (a) to (e) diagrams for explaining the steps of a method for manufacturing a semiconductor package according to a modification of the embodiment of the present invention;

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a semiconductor package 1 manufactured by a semiconductor package manufacturing method according to the present embodiment.

The semiconductor package 1 includes an outer shell 11 made of resin and having a plurality of external terminals exposed on the lower surface, and a rewiring layer 13 sealed in the outer shell 11 and electrically connected to each of the plurality of external terminals 12. , a semiconductor element 14 sealed in the outer shell 11 and electrically connected to the rewiring layer 13, and a plurality of bumps 15 formed on the lower surface side of each of the plurality of external terminals 12. ing. In the present embodiment, a plurality of bumps 15 are arranged vertically and horizontally in a matrix, but the number and arrangement of the bumps are not particularly limited. Further, in this embodiment, a thermosetting resin is exemplified as the resin, but a thermoplastic resin may be used.

Next, a method for manufacturing this semiconductor package 1 will be described. In manufacturing the semiconductor package 1, first, a plurality of external terminals 12 are installed on the upper surface of a support 21 made of a metal material (FIG. 2(a), external terminal installation step). In the present embodiment, the external terminals 12 are arranged on the support 21 in a matrix form, each of which is arranged vertically and horizontally in accordance with the arrangement of the bumps 15 of the semiconductor package 1 to be manufactured (Fig. 3). The support 21 is preferably a plate-like member. Also, the support 21 is made of stainless steel (SUS430, for example) here.

In FIG. 2A, gold plating 12M is applied to the lower surface side of each of the plurality of external terminals 12 placed on the upper surface of the support 21 (portion in contact with the upper surface of the support 21). Each of the plurality of external terminals 12 has a collar portion 12T at its upper end. The flange portion 12T has an outer shape larger than the lower surface of the external terminal 12 (the surface in contact with the support 21).

In order to install the plurality of external terminals 12 on the upper surface of the support 21, first, a resist is applied to the upper surface of the support 21, and openings are provided at locations where the external terminals 12 are to be installed. Such openings can be formed by performing processes such as exposure and development. Then, the surface (exposed region) of the support 21 not covered with the resist is plated with gold, and then nickel is grown in the opening. Nickel grown in the opening spreads on the upper surface of the resist to form a collar portion 12T. After removing the resist, the upper surface of the support 21 was plated with gold 12M on the lower surface side, and a plurality of external terminals 12 having a flange portion 12T having an outer shape larger than the surface in contact with the support 21 were installed. state.

After the plurality of external terminals 12 are placed on the upper surface of the support 21, the upper surface of the support 21 is molded with a thermosetting resin using a first compression molding device (not shown), thereby forming the plurality of external terminals 12. is formed (FIGS. 2(b) and 4. First molding step). When the lower outer shell 22 is formed on the upper surface of the support 21, the thermosetting resin heated and in a fluid state flows under the flange portion 12T of each external terminal 12 and is thermally cured in that state. be. Therefore, after the thermosetting resin is thermoset, the flange 12T of each external terminal 12 is sandwiched between the lower shells 22 (FIG. 2(b)).

After the lower shell 22 is formed on the upper surface of the support 21, the lower shell 22 is subjected to laser via processing by a laser via processing device (not shown) to form a via hole 23 (FIGS. 2(c) and 5). via hole formation process). As a result, the upper surface of each external terminal 12 is exposed upward.

After forming the via holes 23 that expose the respective external terminals 12 upward, copper sputtering is applied to the upper surface of the lower shell 22 using a copper sputtering device (not shown) (FIG. 6(a), copper sputtering step). Thereby, a sputtered copper film 24S is formed on the upper surface of the lower shell 22 (including the upper surfaces of the external terminals 12).

After the copper sputter film 24S is formed on the upper surface of the lower shell 22 by the copper sputtering process, a copper plating apparatus (not shown) is used to apply copper plating 24M to the upper surface of the copper sputter film 24S (FIG. 6B. plating process) After the copper plating 24M is applied to the upper surface of the sputtered copper film 24S by the copper plating process, the inside of the via hole 23 is formed by coating the resist 25 with a resist coating device (not shown), exposing it with a resist exposure device, and developing it. And a resist 25 is formed in a region including the periphery of the via hole 23 ((c) of FIG. 6, a resist formation step).

After the resist 25 is formed in the area including the inside of the via hole 23 and the periphery of the via hole 23 by the resist forming step, the copper sputtered film 24S and the copper plating 24M are etched using an etching apparatus (not shown in FIG. 7A. Etching). process). As a result, the sputtered copper film 24S and the copper plating 24M are removed except for the region including the inside of the via hole 23 and the periphery of the via hole 23. Next, as shown in FIG.

After removing the sputtered copper film 24S and the copper plating 24M in the etching step, the resist 25 is removed (washed) by a resist washing device (not shown) (FIG. 7B). resist removal step). As a result, a copper thin film layer in which a film of copper plating 24M is laminated on the upper surface of the sputtered copper film 24S is formed on the upper surface of the external terminal 12, the inner wall of the via hole 23, and the periphery of the via hole 23.

Here, as a method for forming a copper thin film, an etching wiring method is exemplified by the procedure of copper sputtering process→copper plating process→resist formation process→etching process→resist removal process, but other methods may be used. For example, the copper thin film layer may be formed by a conventionally known additive wiring method (a procedure of copper sputtering process→resist application/opening process→additive copper plating process→resist removal process→copper sputter film etching process).

After the copper thin film layer is formed on the upper surface of the external terminal 12, the inner wall of the via hole 23, and the periphery of the via hole 23, the upper surface of the lower shell 22 is electrically connected to the plurality of external terminals 12 by a conventionally known method. A rewiring layer 13 is formed (FIGS. 8 and 9. Rewiring layer forming step). A mount area 26 for mounting the semiconductor element 14 and a plurality of internal terminals 27 electrically connected to the semiconductor element 14 mounted on the mount area 26 are formed on the rewiring layer 13 .

In the rewiring layer forming step, the upper surface of each internal terminal 27 is plated (not shown). This plating consists of nickel plating applied to the surfaces of the internal terminals 27 and gold plating applied to the surfaces of the nickel plating. Such plating may be applied to the mounting area 26 .

A portion of the semiconductor package 1 manufactured by the end of this rewiring layer forming process forms a base portion of the semiconductor package 1, and includes a support 21 made of a metal material and a support 21 mounted on the upper surface of the support 21. a plurality of external terminals 12, a lower shell 22 made of a thermosetting resin and holding the plurality of external terminals 12 installed on the upper surface of a support 21; 12 and a rewiring layer 13 electrically connected thereto. A base portion of the semiconductor package 1 is hereinafter referred to as a "base board 1B". The base substrate 1B corresponds to a substrate in the manufacturing process of a conventional semiconductor package with a substrate.

After the rewiring layer 13 is formed on the upper surface of the lower shell 22 (the base substrate 1B is manufactured) by the rewiring layer forming step, the semiconductor element 14 is mounted on the rewiring layer 13 and the semiconductor element 14 is mounted on the rewiring layer. 13 is electrically connected to a semiconductor element connecting step. The semiconductor element connecting process includes a semiconductor element mounting process (FIGS. 10A and 11) and a wire bonding process (FIGS. 10B and 12) performed after the semiconductor element mounting process. In the semiconductor mounting process, the semiconductor element 14 is mounted on the upper surface of the rewiring layer 13 by a mounter device (not shown). In the wire bonding process, the terminals on the semiconductor element 14 side and the internal terminals 27 are connected with wires 28 by a wire bonding device (not shown).

After the semiconductor element connecting step is completed, the upper surface of the lower shell 22 is molded with a thermosetting resin using a second compression molding device (not shown) to form the upper shell 29 . As a result, the outer shell 11 composed of the lower outer shell 22 and the upper outer shell 29 is formed, and the rewiring layer 13 and the semiconductor element 14 are sealed by the outer shell 11 (FIGS. 10(c) and 13). .second molding step). The thermosetting resin used in the second molding process is the same (same kind) as the thermosetting resin used when forming the lower shell 22 in the first molding process. As a result, the outer shell 11 is entirely made of the same material (thermosetting resin). That is, the outer shell 11 includes a lower shell 22 that seals the external terminals 12 and an upper shell 29 that seals the rewiring layer 13 and the semiconductor element 14. The lower shell 22 and the upper shell 29 are the same. is made of resin. As used herein, the same resin includes resins having equivalent physical properties.

After the outer shell 11 is formed, the support 21 is peeled off from the lower surface of the outer shell 11 and removed (FIG. 10(d). support removing step). As a result, the plurality of external terminals 12 are exposed on the lower surface of the outer shell 11 (the lower surface of the lower outer shell 22) (FIGS. 14A and 14B). When the lower shell 22 is formed on the upper surface of the support 21, the thermosetting resin flows under the flange 12T of each external terminal 12 placed on the upper surface of the support 21 and hardens. The collar portion 12T is sandwiched between the lower outer shell 22. Therefore, when the support 21 is peeled off from the outer shell 11, the collar 12T acts as a retainer, and the external terminal 12 is held by the outer shell. 11 (lower shell 22) is prevented.

After the support removing step is completed, bumps 15 are formed on each of the plurality of external terminals 12 exposed on the lower surface of the outer shell 11 by a bump forming device (not shown) (FIGS. 10E and 15). (a), (b) bump formation process). As a result, the semiconductor package 1 having the bumps 15 on the lower surface of the outer shell 11 encapsulating the rewiring layer 13 and the semiconductor element 14 is completed (FIG. 1).

As can be seen from FIGS. 15A and 15B, the semiconductor package 1 has not only an outer (surrounding) area below the semiconductor element 14 (mounting area 26) but also an inner area below the semiconductor element 14. The external terminals 12 are also provided within the region, and the external terminals 12 are arranged at an extremely high density. This is because the semiconductor package 1 according to the present embodiment has the rewiring layer 13 and the bumps 15 connected thereto, and in addition, the bumps 15 are formed on the upper surface of the support 21 before the rewiring layer 13 is formed. is formed by installing the external terminals 12 (external terminal installation process) and manufacturing the lower shell 22 holding the external terminals 12 (first molding process). ing.

In the above-described embodiment, for the sake of convenience, one semiconductor package 1 is manufactured on one support 21, but in reality, a plurality of semiconductor packages 1 are manufactured on one support 21. Manufactured in a matrix. Then, after the support 21 is removed from the outer shell 11 and the bumps 15 are formed on the respective external terminals 12, the individual semiconductor packages 1 are cut out.

16A to 16E show modifications of the semiconductor package manufacturing method according to the present embodiment. In this modification, the semiconductor element 14 is of the flip-chip type, and a plurality of bonding bumps 14B bonded to internal terminals 27 provided on the upper surface of the base substrate 1B (the upper surface of the rewiring layer 13) are provided on the lower surface. It is configured with. In this modified example, in the semiconductor element connecting step in the above-described embodiment, the mounting of the semiconductor element 14 to the rewiring layer 13 and the electrical connection are performed simultaneously (FIG. 16(a)→FIG. 16(b)). . After the semiconductor element connection step, a second molding step (FIG. 16(c)), a support removing step (FIG. 16(d)), and then a bump forming step (FIG. 16(e)) are performed. A semiconductor package 1 is manufactured.

As described above, according to the manufacturing method of the semiconductor package 1 according to the present embodiment (including the modification), the rewiring layer 13 and the outer shell 11 encapsulating the semiconductor element 14 are entirely the same (the same type). A semiconductor package 1 formed from a resin (a thermosetting resin in this embodiment) is manufactured. In such a semiconductor package 1, there is no difference in the thermal expansion coefficient between the upper and lower surfaces of the outer shell 11, and warping deformation due to heat is less likely to occur. Defects such as peeling off from the substrate are less likely to occur. In addition, since the outer shell 11 is held by the hard support 21 made of a metal material until just before the bumps 15 are formed on its lower surface, it is easy to process, and the final size of the semiconductor package 1 can be made extremely thin. is possible.

Further, in the semiconductor package 1 manufactured by the manufacturing method of the semiconductor package 1 according to the present embodiment, as described above, the flange portion 12T of each external terminal 12 acts as a retainer to prevent the external terminal 12 from coming off. Since the external terminal 12 is prevented from slipping out of the (lower shell 22), even after the bump 15 is formed, the external terminal 12 does not slip downward from the shell 11 (lower shell 22). Therefore, the bumps 15 are unlikely to fall off the outer shell 11, and the semiconductor package 1 with high structural reliability can be obtained.

In addition, in the method of manufacturing the semiconductor package 1 according to the present embodiment, as described above, at least a part of the plurality of external terminals 12 are positioned within the region below the semiconductor element 14 (below the mounting region 26). can do. Therefore, the semiconductor package 1 in which the external terminals 12 are densely arranged can be manufactured.

Also, the base substrate 1B manufactured in the manufacturing process of the semiconductor package 1 can be marketed independently like a substrate used in a semiconductor package with a substrate. That is, a person who purchases the base substrate 1B performs the subsequent steps (the above-described semiconductor element connection step, second molding step, support removal step, and bump formation step) to complete the semiconductor package 1 of the present embodiment. can be manufactured. Since the base substrate 1B in the present embodiment is entirely supported by the support 21 made of a metal material, it can stably maintain its shape even during distribution.

Although the embodiments of the present invention have been described so far, the present invention is not limited to those described above, and various modifications and the like are possible. For example, in the above-described embodiment, the support 21 is made of stainless steel (such as SUS430), but this is an example and may be made of other metal materials (such as copper). In particular, when the support 21 is a plate made of copper, in the support removing process, a method of removing by peeling off from the lower surface of the outer shell 11, or a method of dissolving and removing can be adopted. Also, the number and arrangement of the bumps 15 and the number of the semiconductor elements 14 mounted on the rewiring layer 13 shown in the above embodiment are merely examples, and are not limited to those shown in the drawings.

Provided are a semiconductor package manufacturing method and a semiconductor package capable of preventing warping deformation of an outer shell due to heat.

REFERENCE SIGNS LIST 1 semiconductor package 1B base substrate 11 shell 12 external terminal 13 rewiring layer 14 semiconductor element 15 bump 21 support 22 lower shell 26 mounting area 29 upper shell

Claims (9)

an external terminal installation step of installing a plurality of external terminals on the upper surface of a support made of a metal material;
a first molding step of forming a lower outer shell holding the plurality of external terminals by molding with resin the upper surface of the support on which the plurality of external terminals are arranged in the external terminal installation step;
a rewiring layer forming step of forming a rewiring layer electrically connected to the plurality of external terminals on the upper surface of the lower shell formed in the first molding step ;
a semiconductor element connecting step of mounting a semiconductor element on the rewiring layer formed in the rewiring layer forming step and electrically connecting the semiconductor element to the rewiring layer;
After the semiconductor element connecting step, the upper surface of the lower shell is molded with the same resin as that of the lower shell to form an upper shell. a second molding step of sealing with an outer shell composed of the outer shell and the upper outer shell;
after the second molding step, removing the support from the lower surface of the outer shell to expose each of the plurality of external terminals on the lower surface of the outer shell. Method. 2. The method of manufacturing a semiconductor package according to claim 1, further comprising forming a bump on each of said plurality of external terminals exposed on the lower surface of said outer shell. Each of the plurality of external terminals installed on the support has a collar portion having an inner diameter larger than the surface in contact with the support at the upper end, and the lower outer shell is formed by the first molding process. 3. The method of manufacturing a semiconductor package according to claim 1, wherein the resin flows between the support and the flange portion when the resin is cured. 4. The method of manufacturing a semiconductor package according to claim 1, wherein at least part of said plurality of external terminals are located in a region below said semiconductor element. 5. The method of manufacturing a semiconductor package according to claim 1, wherein in said support removing step, said support is removed from the lower surface of said outer shell by peeling or dissolving. an outer shell formed of resin and provided with a plurality of external terminals exposed on the lower surface;
a rewiring layer sealed by the outer shell and electrically connected to each of the plurality of external terminals;
a semiconductor element sealed by the outer shell and electrically connected to the rewiring layer;
The outer shell includes a lower shell that seals the external terminals, and an upper shell that is formed on an upper surface of the lower shell and seals the entire semiconductor element and the rewiring layer ,
The semiconductor package, wherein the lower shell and the upper shell are made of the same resin. 7. The semiconductor package according to claim 6, further comprising a plurality of bumps formed on the lower surface side of each of said plurality of external terminals. 8. The outer shell according to claim 6 or 7, wherein each of the plurality of external terminals has a flange formed at an upper end thereof and having an inner diameter larger than a surface exposed on the lower surface of the outer shell and embedded inside the outer shell. semiconductor package. 9. The semiconductor package according to claim 6, wherein at least some of said plurality of external terminals are located in a region below said semiconductor element.

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