JP7330396B2 - Semiconductor device and power conversion device - Google Patents

Description

The present disclosure relates to a semiconductor device and a power conversion device to which the semiconductor device is applied.

Insulated gate semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are widely used as power switching elements. As an insulated gate semiconductor device, a trench gate semiconductor device is being developed.

As such a trench gate type semiconductor device, there is a MOSFET which includes a gate trench in which a gate electrode is formed and a Schottky trench in which a Schottky electrode is formed, and which incorporates an SBD (Schottky barrier diode) (for example, See Patent Document 1).

2019-216224 publication

However, such a conventional semiconductor device has a problem that a high electric field tends to occur near the bottom of the Schottky trench, and the reverse leakage current tends to increase.

The present disclosure has been made to solve the above-described problems, and an object thereof is to obtain a semiconductor device with reduced reverse leakage current.

A semiconductor device according to the present disclosure includes a first-conductivity-type drift layer, a second-conductivity-type body region provided on the drift layer, a first-conductivity-type source region provided on the body region, and a body region. a gate insulating film provided in a gate trench penetrating through the drift layer and the source region in the thickness direction of the drift layer; a Schottky electrode provided in a Schottky trench that penetrates the body region in the thickness direction of the drift layer; and a first bottom protection region of a second conductivity type provided in contact with the portion, wherein the Schottky trench is formed shallower than the gate trench in the thickness direction of the drift layer. do.

The semiconductor device according to the present disclosure has the effect of reducing the reverse leakage current because the Schottky trench is formed shallower than the gate trench in the MOSFET containing the SBD.

1 is a schematic plan view showing the overall configuration of a semiconductor device according to a first embodiment; FIG. 2 is a schematic plan view showing the layout of the cell region of the semiconductor device of Embodiment 1; FIG. 2 is a schematic cross-sectional view showing a cell region of the semiconductor device of Embodiment 1; FIG. FIG. 2 is a first diagram showing each step of the method for manufacturing the semiconductor device of Embodiment 1; FIG. 2B is a second diagram showing each step of the method for manufacturing the semiconductor device of the first embodiment; FIG. 3 is a third diagram showing each step of the method for manufacturing the semiconductor device of Embodiment 1; FIG. 4 is a fourth diagram showing each step of the manufacturing method of the semiconductor device of Embodiment 1; 4A to 4C are diagrams showing steps of another example of the method for manufacturing the semiconductor device of the first embodiment; FIG. FIG. 5 is a fifth diagram showing each step of the method of manufacturing the semiconductor device of the first embodiment; FIG. 6 is a sixth diagram showing each step of the method of manufacturing the semiconductor device of the first embodiment; 7 is a seventh diagram showing each step of the manufacturing method of the semiconductor device of Embodiment 1; FIG. 8 is an eighth diagram showing each step of the method of manufacturing the semiconductor device of the first embodiment; FIG. FIG. 10 is a schematic cross-sectional view showing a cell region of a semiconductor device according to a second embodiment; FIG. 10 is a first diagram showing each step of the method of manufacturing the semiconductor device of the second embodiment; 8A to 8C are diagrams showing steps of another example of the method for manufacturing the semiconductor device of the second embodiment; FIG. FIG. 10 is a second diagram showing each step of the method of manufacturing the semiconductor device of the second embodiment; FIG. 10 is a third diagram showing each step of the method for manufacturing the semiconductor device of the second embodiment; FIG. 10 is a fourth diagram showing each step of the method for manufacturing the semiconductor device of the second embodiment; FIG. 10 is a fifth diagram showing each step of the method for manufacturing the semiconductor device of the second embodiment; FIG. 13 is a schematic plan view showing the layout of the cell region of the semiconductor device of the third embodiment; FIG. 10 is a schematic cross-sectional view showing a cell region of a semiconductor device according to a third embodiment; 10A to 10C are diagrams showing steps of a method for manufacturing a semiconductor device according to a third embodiment; FIG. FIG. 10 is a diagram showing each step of a modification of the method for manufacturing the semiconductor device of the third embodiment; FIG. 10 is a diagram showing each step of a modification of the method for manufacturing the semiconductor device of the third embodiment; FIG. 10 is a diagram showing each step of another example of the manufacturing method of the semiconductor device of Embodiment 3; It is a figure which shows each process of the manufacturing method of the modification of the semiconductor device of Embodiment 3. FIG. It is a figure which shows each process of the manufacturing method of the modification of the semiconductor device of Embodiment 3. FIG. FIG. 11 is a schematic cross-sectional view showing a cell region of a semiconductor device according to a fourth embodiment; 10A to 10C are diagrams showing steps of a method for manufacturing a semiconductor device according to a fourth embodiment; FIG. FIG. 12 is a block diagram showing the configuration of a power conversion system to which the power conversion device of Embodiment 5 is applied;

Embodiments of the present disclosure will be described below based on the drawings. It should be noted that the drawings are shown schematically, and the mutual relationship between the sizes and positions of the images shown in different drawings is not necessarily described accurately and may be changed as appropriate. In the drawings below, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

Also, in each drawing, dashed lines may be shown to indicate specific regions or boundaries between regions, but these are described for convenience of explanation or to facilitate understanding of the drawings. However, it does not limit the contents of each embodiment.

Also, in the following description, terms such as “upper”, “lower”, “side”, “bottom”, “front” and “back” may be used that mean specific positions and directions. are used for convenience in order to facilitate understanding of the contents of the embodiments, and are not related to the direction of actual implementation.

In the present disclosure, when the interrelationship between constituent elements is expressed using terms such as “upper” and “lower”, it does not preclude the presence of an intervening element between the constituent elements. For example, when "B provided on A" is described, it includes the case where another component C is provided between A and B, and the case where it is not provided. In addition, in the present disclosure, expressions using terms such as “upper” and “lower” include the concept of upper and lower with a laminated structure in mind. For example, when describing "B provided on A covering the groove", B includes the meaning of existing in the opposite direction to the groove surface viewed from A, and within the scope of that meaning, Including oblique directions.

In the following description, with respect to the conductivity type of the impurity, a case where the first conductivity type is n-type and the second conductivity type is p-type will be described. I don't mind. Also, "impurity concentration" indicates the maximum value of impurities in each region. In addition, the description “n ⁻ type” indicates that the impurity concentration is lower than that described as “n type”, and the description “n ⁺ type” indicates “n type”. This indicates that the impurity concentration is higher than that of the Similarly, the description “p ⁻ type” indicates that the impurity concentration is lower than that described as “p type”, and the description “p ⁺ type” is described as “p type”. This indicates that the impurity concentration is higher than that of the

In the following description, the current flowing from the drain to the source of the MOSFET is called the forward current, the current flowing from the source to the drain is called the forward current, and the current flowing from the source to the drain is called the reverse current. . The term "MOS" has long been used for a junction structure of metal/oxide/semiconductor, and is an acronym for Metal-Oxide-Semiconductor. However, especially in field effect transistors having a MOS structure (hereinafter simply referred to as "MOS transistors"), materials for gate insulating films and gate electrodes have been improved from the viewpoint of recent integration and improvements in manufacturing processes.

For example, in MOS transistors, polycrystalline silicon has been adopted as the material of the gate electrode instead of metal, mainly from the viewpoint of forming the source/drain in a self-aligned manner. Also, from the viewpoint of improving electrical characteristics, a material with a high dielectric constant is employed as the material of the gate insulating film, but this material is not necessarily limited to oxide.

Therefore, the term "MOS" is not necessarily employed to be limited to metal/oxide/semiconductor stacked structures only, and this specification does not presuppose such a limitation. In other words, in view of common technical knowledge, the term "MOS" here is not only an abbreviation derived from its etymology, but also broadly includes the layered structure of conductor/insulator/semiconductor.

Embodiment 1.
The semiconductor device of Embodiment 1 will be described with reference to FIGS. 1 to 12. FIG.

First, the configuration of the semiconductor device of Embodiment 1 will be described with reference to FIGS. 1 to 3. FIG. FIG. 1 is a schematic plan view schematically showing the top surface configuration of the entire semiconductor device 101 of this embodiment. FIG. 2 is an enlarged view of the region X shown in FIG. 1, and is a schematic plan view schematically showing the layout of the MOSFET cells in the semiconductor device 101. As shown in FIG. FIG. 3 is a cross-sectional view taken along the line A-A' in FIG. 2, and is a schematic cross-sectional view showing a cross section of a part of the active region 40 in the semiconductor device 101 of this embodiment. 2 corresponds to a top view of a lateral cross section at a certain depth between the bottom surface of the Schottky trench 11 and the body region 3 shown in FIG.

As shown in FIG. 1, a semiconductor device 101 has a rectangular outer shape, and an active region 40 in which a plurality of minimum unit structures (MOSFET cells) of MOSFETs called "unit cells" are arranged in the center. is provided, and the outside of the active region 40 is surrounded by a termination region 41 . A plurality of gate trenches 6 and a plurality of Schottky trenches 11 are provided in parallel in the active region 40 with a space therebetween. The plurality of gate trenches 6 are connected to gate wiring provided in the active region 40, and the gate wiring is connected to a gate pad, but illustration and description of these are omitted.

As shown in FIG. 2, the gate trenches 6 and the Schottky trenches 11 are formed in stripes in plan view. Further, in plan view, the extending direction of the gate trench 6 and the extending direction of the Schottky trench 11 are formed to be the same direction. In the SBD region 20 , a Schottky interface 22 is formed on the side surface of the Schottky trench 11 exposed to the drift layer 2 .

1 and 2 show a structure in which two MOS regions 19 sandwich one SBD region 20, but the arrangement of each region is not limited to this. For example, a structure in which two MOS regions 19 sandwich two SBD regions 20 may be used. , and one Schottky trench 11 in the SBD region 20 may be repeated, and the structure is not limited to these examples.

In the semiconductor device 101, a plurality of MOSFET cell structures as shown in FIG. In addition, below, the characteristic structure shown in the area|region X shown in FIG. 1 is demonstrated as each embodiment and its modification, and FIG. 1 is common to each embodiment and its modification.

As shown in FIG. 3, a semiconductor device 101 includes a substrate 1, a drift layer 2, a body region 3, a source region 4, a body contact region 5, a gate trench 6, a gate insulating film 7, a gate electrode 8, an interlayer insulating film 9, It comprises a Schottky trench 11 , a Schottky electrode 12 , a source electrode 13 , a drain electrode 14 , a first bottom protection region 15 and a contact region 17 .

MOS region 19 has gate trench 6 , gate insulating film 7 , gate electrode 8 , and interlayer insulating film 9 . The SBD region 20 has a Schottky trench 11 and a Schottky electrode 12 . The semiconductor layer 21 also includes the drift layer 2 and the body region 3 , the source region 4 , the body contact region 5 , and the first bottom protection region 15 , which are impurity regions formed on or inside the drift layer 2 .

The substrate 1 is an n ⁺ -type SiC (silicon carbide) semiconductor substrate and has, for example, a 4H polytype. The substrate 1 may be a (0001) plane having an off angle θ inclined in the <11-20> axis direction. In this case, the off angle θ may be, for example, 10° or less.

An n ⁻ -type drift layer 2 having a lower n-type impurity concentration than the substrate 1 is provided on the substrate 1 . Drift layer 2 uses SiC (silicon carbide) as a semiconductor material. The drift layer 2 occupies most of the semiconductor layer 21 and constitutes the main portion of the semiconductor layer 21 . When the main surface of the substrate 1 is a (0001) plane having an off angle θ inclined in the <11-20> axis direction, the main surface of the drift layer 2 is also a (0001) plane having a similar off angle θ. That is, the drift layer 2 has a main surface provided with an off angle larger than 0° in the <11-20> axial direction.

A p-type body region 3 is provided above the drift layer 2 . An n ⁺ -type source region 4 is selectively provided above the drift layer 2 (body region 3). The source region 4 is a semiconductor region having an n-type impurity concentration higher than that of the drift layer 2 . A p ⁺ -type body contact region 5 is selectively provided above the drift layer 2 (body region 3 ) adjacent to the source region 4 . The body contact region 5 is a semiconductor region having a p-type impurity concentration higher than that of the body region 3 .

The MOS region 19 is provided with a gate trench 6 penetrating the body region 3 in the thickness direction of the drift layer 2 . Gate trench 6 is formed to extend from the surface of semiconductor layer 21 through source region 4 and body region 3 to reach drift layer 2 . The bottom of the gate trench 6 is typically planar, but may be tapered with a thin, sharp tip. Also, the side surfaces of the gate trench 6 are typically substantially parallel, but may have a tapered shape that is inclined with respect to each other.

A gate insulating film 7 is provided on the bottom and side surfaces of the gate trench 6 . A gate electrode 8 is provided in the gate trench 6 so as to fill the gate trench 6 with the gate insulating film 7 interposed therebetween. Gate electrode 8 is provided to face drift layer 2 , body region 3 , and source region 4 with gate insulating film 7 interposed therebetween. An interlayer insulating film 9 is provided on the gate trench 6 so as to cover the gate electrode 8 .

A Schottky trench 11 that penetrates the body region 3 in the thickness direction of the drift layer 2 is provided in the SBD region 20 . Schottky trench 11 is formed to reach drift layer 2 from the surface of semiconductor layer 21 through source region 4 and body region 3 . Schottky trench 11 is formed shallower than gate trench 6 in the thickness direction of drift layer 2 . More specifically, the bottom surface of Schottky trench 11 is formed above the top surface of first bottom protection region 15 . Schottky trench 11 is formed such that the trench width in the direction perpendicular to the thickness direction of drift layer 2 is the same as that of gate trench 6 . The bottom of the Schottky trench 11 is typically planar, but may be tapered with a thin, sharp tip. Also, the side surfaces of the Schottky trench 11 are typically substantially parallel, but may have a tapered shape that is inclined with respect to each other.

Schottky trench 11 is not limited to being formed so that the trench width in the direction perpendicular to the thickness direction of drift layer 2 is the same as that of gate trench 6 . Gate trench 6 and Schottky trench 11 may have different trench widths in the direction orthogonal to the thickness direction of drift layer 2 . Either of these trenches may have a wider width or a narrower width, depending on the specifications of each semiconductor device.

A Schottky electrode 12 is provided in the Schottky trench 11 . The Schottky electrode 12 is made of metal such as Ti (titanium) or Mo (molybdenum). The Schottky electrode 12 is in contact with the drift layer 2, the body region 3, and the source region 4 at the bottom or side of the Schottky trench 11, and is electrically connected thereto.

Schottky electrode 12 forms a Schottky junction with drift layer 2 on the side surface of Schottky trench 11 . That is, the Schottky electrode 12 forms Schottky interfaces 22 (not shown in FIG. 3) with the drift layer 2 on the side and bottom surfaces of the Schottky trench 11, as shown in FIGS. As a result, a parasitic Schottky barrier diode (hereinafter simply referred to as SBD) between the Schottky electrode 12 and the drift layer 2 is formed on the side and bottom surfaces of the Schottky trench 11 .

A contact region 17 is formed on the source region 4 and the body contact region 5 . The contact region 17 is a silicide of a metal such as Ni (nickel) or Ti (titanium) and the semiconductor layer 21, and is in contact with the source region 4 and the body contact region 5 to form an ohmic contact therewith.

A source electrode 13 is provided on the interlayer insulating film 9, the contact region 17, and the Schottky electrode 12 so as to cover them. The source electrode 13 is an electrode made of metal whose main component is Al (aluminum). In the MOS region 19, the source electrode 13 functions together with the contact region 17 as a main electrode on the front surface side. Source electrode 13 is electrically connected to source region 4 and body contact region 5 via contact region 17 . In the SBD region 20 , the source electrode 13 is connected to the Schottky electrode 12 and forms the anode electrode of the SBD together with the Schottky electrode 12 .

A drain electrode 14 containing a metal such as Ni (nickel) is provided on the surface of the substrate 1 opposite to the surface on which the source electrode 13 is provided. The source electrode 13 is provided on the front surface (first main surface) side of the substrate 1 (semiconductor layer 21), and the drain electrode 14 faces the front surface of the substrate 1 (semiconductor layer 21). It is provided on the back surface (second main surface) side.

A p ⁺ -type first bottom protection region 15 is provided below the gate trench 6 (gate insulating film 7 ) along the extending direction of the gate trench 6 so as to cover the bottom of the gate trench 6 . The first bottom protection region 15 is in contact with the bottom surface of the gate trench 6, part of the side surfaces, and the corners between the bottom surface and the side surfaces, and is provided to cover the entire bottom of the gate trench 6 including the corners. It is Thereby, the gate trench 6 is provided so as to be embedded in the first bottom protection region 15 . In addition, the “bottom surface” and the “side surface” do not necessarily have to be planar. Also, the "corners" may be rounded.

Next, the impurity concentration of each semiconductor region in semiconductor device 101 of the first embodiment will be described. The n-type impurity concentration of the drift layer 2 is 1.0×10 ¹⁴ to 1.0×10 ¹⁷ cm ⁻³ and is set based on the withstand voltage of the semiconductor device. The p-type impurity concentration of the body region 3 is set to 1.0×10 ¹⁴ to 1.0×10 ¹⁸ cm ⁻³ . The n-type impurity concentration of the source region 4 is set to 1.0×10 ¹⁸ to 1.0×10 ²¹ cm ⁻³ . The p-type impurity concentration of the body contact region 5 is 1.0×10 ¹⁸ to 1.0×10 ²¹ cm ⁻³ . The impurity concentration is set to be high. The p-type impurity concentration of the first bottom protection region 15 is preferably 1.0×10 ¹⁴ or more and 1.0×10 ²⁰ cm ⁻³ or less, and the concentration profile may not be uniform.

Next, operation of the semiconductor device 101 according to the first embodiment will be briefly described. In the MOS region 19 , when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 8 , the conductivity type is inverted in the body region 3 , that is, an n-type channel is formed along the sides of the gate trench 6 . Then, a current path of the same conductivity type (n-type in the first embodiment) is formed between the source electrode 13 and the drain electrode 14, so that current flows. The semiconductor device 101 is turned on when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 8 .

On the other hand, when a voltage lower than the threshold voltage is applied to the gate electrode 8, a channel is not formed in the body region 3, so a current path is not formed as in the ON state. Therefore, even if a voltage is applied between the drain electrode 14 and the source electrode 13 , almost no current flows from the drain electrode 14 to the source electrode 13 . The state in which the voltage of the gate electrode 8 is less than the threshold voltage in this way is the off state of the semiconductor device 101 .

By controlling the voltage applied to the gate electrode 8, the semiconductor device 101 operates by switching between an ON state and an OFF state. Thus, the semiconductor device 101 has a MOSFET structure composed of the gate electrode 8, the gate insulating film 7, the drift layer 2, the body region 3, the source region 4, the source electrode 13, the drain electrode 14, etc. in the MOS region 19. have

On the other hand, when a forward voltage is applied to the SBD in the SBD region 20 while the semiconductor device 101 is off, a unipolar current flows between the Schottky electrode 12 and the drain electrode 14 . When the bias is further applied, a bipolar current begins to flow through the parasitic pn diodes formed in the body region 3, the first bottom protection region 15, and the like. The current value obtained before this parasitic pn diode starts bipolar operation is the maximum unipolar current of the element.

In FIGS. 1 and 2, the gate trench 6 and Schottky trench 11 are preferably formed so that their extending directions are parallel to the <11-20> axis direction. This is because the side surfaces of the gate trench 6 and the Schottky trench 11 serve as current paths, so that when the semiconductor layer 21 has an off angle θ inclined in the <11-20> axial direction, the opposite side surfaces of each trench are turned off. This is to avoid the difference in characteristics between the two side surfaces due to the influence of the angle which results in different crystal planes.

When the semiconductor device 101 is turned off, the first bottom protection region 15 promotes depletion of the n-type region of the drift layer 2 by a depletion layer extending from the first bottom protection region 15 , and also promotes depletion of the n-type region of the drift layer 2 to the bottom of the gate trench 6 . By alleviating the electric field concentration, the electric field applied to the gate insulating film 7 is reduced and the gate insulating film 7 is prevented from being destroyed.

By electrically connecting the first bottom protection region 15 to the body region 3 of the MOS region 19 and fixing the potential of the first bottom protection region 15, electric field concentration at the bottom of the gate trench 6 can be further alleviated. can be planned. For example, a p-type connection region (not shown) in contact with the first bottom protection region 15 and the body region 3 may be formed on the side surface of the gate trench 6 . The potential of the first bottom protection region 15 is grounded by being electrically connected to the source electrode 13 via the connection region, the body region 3 and the source region 4 . This electrical connection is provided, for example, through adjacent cells. The connection region may have, for example, a p-type impurity concentration of 1.0×10 ¹⁴ or more and 1.0×10 ²⁰ cm ⁻³ or less.

Further, when the gate trench 6 is formed in a line shape, by extending a low-concentration p-type connection region (p ⁻⁻ region) on the side surface of the end portion in the longitudinal direction of the gate trench 6, this The first bottom protection region 15 at ^the bottom of the gate trench 6 and the body region 3 above can be electrically connected through the p-- region.

The gate trenches 6 may be formed in a grid pattern. In this case, a first bottom protective region 15 at the bottom of the gate trenches 6 and the gate electrodes 8 are formed at the intersections of the gate electrodes 8 through the gate electrodes 8 . By providing a contact connecting the source electrode 13 in the upper layer of the , the first bottom protection region 15 can be electrically connected to the body region 3 through the contact and the source electrode 13 .

By connecting the first bottom protection region 15 to the source potential, extension of the depletion layer from the first bottom protection region 15 toward the drift layer 2 is promoted when the semiconductor device 101 is turned off, and the electric field intensity at the bottom of the gate trench 6 is reduced. can be reduced. Further, when the semiconductor device 101 is turned on and off, a current path for charging and discharging the pn junction formed by the first bottom protection region 15 and the drift layer 2 is ensured, and electric charges are extracted to the source electrode 13, resulting in depletion. Layer response is faster and switching losses can be reduced.

Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. 4 to 12. FIG. 4 to 12 are diagrams showing each step of the method for manufacturing the semiconductor device 101 of this embodiment.

As shown in FIG. 4, first, a substrate 1 having an n ⁻ -type semiconductor layer 21 made of silicon carbide is prepared. More specifically, the n ⁻ -type semiconductor layer 21 may be formed by epitaxial growth on the substrate 1, which is an n ⁺ -type silicon carbide substrate. Also, the n-type impurity concentration of the semiconductor layer 21 is formed so as to correspond to the n-type impurity concentration of the drift layer 2 described above.

Then, as shown in FIG. 5, a p-type body region 3 is formed in the upper layer portion of the semiconductor layer 21 (drift layer 2) by ion implantation, and the upper layer of the body region 3 (semiconductor layer 21 or drift layer 2) is formed. An n ⁺ -type source region 4 and a p ⁺ -type body contact region 5 are selectively formed by ion implantation. In the ion implantation, when forming an n-type region, ions such as N (nitrogen) or P (phosphorus) are implanted as donors, and when forming a p-type region, ions such as Al (aluminum) or B are implanted as acceptors. Ions such as (boron) are implanted. The impurity concentration in each region is formed to have the values described above.

The order of forming the body region 3, the source region 4, and the body contact region 5 may be reversed, and all or part of the regions may be formed by epitaxial growth instead of ion implantation. When forming the body region 3 , the source region 4 and the body contact region 5 by epitaxial growth, each region is stacked on the drift layer 2 .

Based on the above, "forming the body region 3 on the upper part of the drift layer 2" includes those formed by any of the above-described manufacturing methods of ion implantation and epitaxial growth, and "the body region 3 is the drift layer. 2” means that in the finally completed semiconductor device 101, the region occupied by the body region 3 is the drift layer 2, regardless of whether the manufacturing method is ion implantation or epitaxial growth. shall mean located on the area occupied by Similarly, "the source region 4 is formed above the body region 3" includes those formed by any of the above-described manufacturing methods of ion implantation and epitaxial growth. “provided on the region 3 ” means that the region occupied by the source region 4 is positioned on the region occupied by the body region 3 in the semiconductor device 101 . The same applies to other areas.

Next, as shown in FIG. 6, using a first mask 51, reactive ion etching (RIE) is performed from the surface of the semiconductor layer 21 through the source region 4 and the body region 3 to reach the drift layer 2. A gate trench 6 and a Schottky trench 11 are formed. At this time, the width of the gate trench 6 and the width of the Schottky trench 11 may be different. Alternatively, multiple masks may be used to form the gate trench 6 in the MOS region 19 and the Schottky trench 11 in the SBD region 20 using separate etching steps.

Then, as shown in FIG. 7, using a first mask 51 and a second mask 52, only the gate trench 6 is additionally etched. Thus, after the gate trench 6 is formed deeper than the Schottky trench 11, ions are implanted in an oblique direction slightly inclined (for example, an inclination angle of 10 to 50°) from the vertical direction with respect to the surface of the semiconductor layer 21. conduct. The second mask 52 is a mask provided so as to cover the Schottky trench 11 and open only the gate trench 6 . By implanting p-type ions into the bottom of the gate trench 6 in this manner, the first bottom protection region 15 having a width larger than that of the gate trench 6 is formed. By doing so, the bottom surface of the Schottky trench 11 can be formed to be positioned above the top surface of the first bottom protection region 15 .

Alternatively, as shown in FIG. 8, the first bottom protection region 15 is formed by epitaxially growing the n ⁻ -type first drift layer 25 on the substrate 1 and then implanting ions into the upper layer of the first drift layer 25 in advance. It may be formed selectively or embedded by epitaxial growth. In this case, after forming the first bottom protection region 15, the n ⁻ -type second drift layer 26 is formed on the first drift layer 25 and the first bottom protection region 15 by epitaxial growth, and then each semiconductor region and the trench are formed. will be formed. For example, the body region 3 is formed in the upper layer portion of the second drift layer 26 . A combination of the first drift layer 25 and the second drift layer 26 corresponds to the drift layer 2 described above.

As shown in FIG. 7, the first bottom protection region 15 formed in this way protrudes from the side surface of the gate trench 6 toward the drift layer 2 (direction perpendicular to the thickness direction of the drift layer 2). .

Next, as shown in FIG. 9, using a first mask 51 and a second mask 52, the gate trench 6 is additionally etched. By doing so, the bottom surface of the gate trench 6 can be embedded in the first bottom protection region 15 . That is, the corners of the gate trench 6 are covered with the first bottom protection region 15 .

Next, as shown in FIG. 10, the first mask 51 and the second mask 52 are removed by selective etching or the like using a resist mask or the like, and the gate insulating film 7 is entirely formed on the semiconductor layer 21 . , the gate insulating film 7 is formed on the bottom and side surfaces of the gate trenches 6 and on the bottom and side surfaces of the Schottky trenches 11 . After that, a conductive polycrystalline silicon film, for example, is formed on the gate insulating film 7 by the low pressure CVD method, and is etched back to form a polycrystalline silicon film only inside the gate trench 6 and the Schottky trench 11 . The membrane is left to obtain the cross-sectional structure shown in FIG. Since the polycrystalline silicon film in the gate trench 6 becomes the gate electrode 8, it is illustrated as the gate electrode 8 in FIG.

After that, as shown in FIG. 11, the polycrystalline silicon film in the Schottky trench 11 is removed by a wet etching method using an alkaline etchant such as an alkaline developer. Also, an interlayer insulating film 9 is formed to cover the gate electrode 8 . A third mask 53 is formed on the interlayer insulating film 9 covering the gate trench 6 . The third mask 53 is used to pattern the gate insulating film 7 as well as the interlayer insulating film 9 to expose the surface of the semiconductor layer 21 . Thereby, a contact hole can be opened.

Next, as shown in FIG. 12, a contact region 17 is formed using a metal such as Ni (nickel) on the surface of the semiconductor layer 21 (the surfaces of the source region 4 and the body contact region 5) exposed through the opening of the contact hole. Form. Contact region 17 is a silicide between metal and semiconductor layer 21 .

After that, the insulating film formed on the bottom and side surfaces of the Schottky trench 11 is removed to expose the surface of the semiconductor layer 21 . Then, a metal such as Ti (titanium) or Mo (molybdenum) is deposited on the exposed semiconductor layer 21 to form the Schottky electrode 12 in the Schottky trench 11 in the SBD region 20 . In the SBD region 20 and the MOS region 19, the source electrode 13 is formed by depositing a metal such as Al (aluminum) on the Schottky electrode 12, the contact region 17, and the interlayer insulating film 9 so as to cover them. do. Then, a drain electrode 14 is formed so as to cover the back surface of the substrate 1 . Through the above steps, the semiconductor device 101 shown in FIGS. 1 to 3 can be manufactured.

Both gate insulating film 7 and interlayer insulating film 9 are typically formed as oxide films. Therefore, in FIG. 10 and the like, the portion of the gate insulating film 7 that protrudes outside the gate trench 6 (protrudes over the surface of the semiconductor layer 21) is described as if it were the same layer as the interlayer insulating film 9. ing.

Features and effects of the semiconductor device 101 according to the first embodiment configured as described above will be described.

The semiconductor device 101 is a power switching element in which an SBD as a unipolar freewheeling diode is built in anti-parallel in a MOSFET, which is a unipolar semiconductor device. Therefore, the cost can be reduced compared to the case of using an externally attached individual diode.

Moreover, since the semiconductor device 101 is a MOSFET using silicon carbide (SiC) as the base material of the substrate 1 and the semiconductor layer 21, by incorporating the SBD, it is possible to suppress the bipolar operation due to the parasitic pn diode. This is because, in a semiconductor device using silicon carbide, the reliability of the device may be impaired by extension of crystal defects caused by recombination energy of carriers due to parasitic pn diode operation.

The semiconductor device 101 is a so-called trench gate type MOSFET having a gate electrode 8 in a gate trench 6 formed in the element. Therefore, compared with a planar MOSFET having a gate electrode 8 on the element surface, the channel can be formed on the side wall of the gate trench 6, so that the channel width density can be improved and the on-resistance can be reduced.

Furthermore, the semiconductor device 101 is a trench gate type MOSFET, and has a structure in which a Schottky electrode 12 is embedded in the Schottky trench 11 in the SBD region 20 and a Schottky interface 22 is formed on the side surface of the Schottky trench 11. be. Therefore, since both the gate electrode 8 and the Schottky electrode 12 are formed inside the gate trench 6 and the Schottky trench 11, respectively, the inter-trench distance, that is, the cell pitch of each cell can be kept small, and a high current density can be obtained. can.

The semiconductor device 101 is a trench gate type MOSFET incorporating an SBD having the features described above. In the trench type device structure, there is a problem that electric field concentration occurs at the bottom of the trench when a high voltage is applied in the OFF state of the semiconductor device. In particular, in trench-type silicon carbide semiconductor devices, since SiC has a high dielectric breakdown strength, gate insulating film breakdown due to electric field concentration at the bottom of the trench occurs prior to avalanche breakdown in the drift layer in the MOS region. As for the SBD region, there is a problem that the reverse leakage current tends to increase due to the high electric field at the Schottky interface on the side and bottom of the trench.

In contrast, semiconductor device 101 according to the first embodiment forms first bottom protection region 15 below gate trench 6 in MOS region 19 . Since a depletion layer is formed around the first bottom protection region 15, the electric field strength in that portion is reduced. Therefore, in the MOS region 19, the occurrence of dielectric breakdown of the gate insulating film 7 due to electric field concentration at the bottom of the gate trench 6 can be suppressed. In particular, in the semiconductor device 101 , in the MOS region 19 , the bottom of the gate trench 6 is embedded in the first bottom protection region 15 , and the corner between the bottom and side surfaces of the gate trench 6 is the first bottom protection region 15 . It is configured to be covered with Therefore, the semiconductor device 101 can suppress the corner of the gate trench 6 from becoming a high electric field, and can suppress dielectric breakdown of the gate insulating film 7 .

On the other hand, as described above, in the SBD region 20, the deeper the Schottky trench 11, the higher the electric field in the vicinity of the bottom, and the formation of the Schottky interface in the vicinity of the bottom tends to increase the reverse leakage current. . Therefore, it is conceivable to provide the gate trench 6 and the Schottky trench 11 shallowly, but the first bottom protection region 15 is formed below the gate trench 6, and the gate trench 6 and the Schottky trench 11 are both shallowly formed. As a result, the JFET resistance between the body region 3 and the first bottom protection region 15 increases.

Therefore, since semiconductor device 101 of the present embodiment does not form a bottom protection region under Schottky trench 11 formed in SBD region 20, the bottom surface of Schottky trench 11 also serves as a Schottky interface. Therefore, the Schottky trench 11 can be shallowly formed within the limit of the position where the Schottky interface area for obtaining the required Schottky current density is secured. That is, by forming the Schottky trench 11 so that the depth in the thickness direction of the drift layer 2 is shallower than that of the gate trench 6, it is possible to suppress a high electric field in the vicinity of the bottom of the Schottky trench 11. By forming the bottom surface of the key trench 11 above the top surface of the first bottom protection region 15, the electric field near the bottom can be further reduced. Therefore, the semiconductor device 101 has the effect of suppressing an increase in reverse leakage current in the SBD region 20 and suppressing an increase in JFET resistance in the MOS region 19 .

As described above, in the semiconductor device 101, since the bottom of the gate trench 6 is buried in the first bottom protection region 15 in the MOS region 19, the high electric field can be further suppressed. can be formed. On the other hand, in the SBD region 20, by forming the Schottky trench 11 shallow, it is possible to suppress a high electric field at the bottom. With such a configuration, in the semiconductor device 101, dielectric breakdown of the gate insulating film 7 in the MOS region 19 can be suppressed, and an increase in reverse leakage current in the SBD region 20 can be suppressed, thereby improving reliability. effect that can be achieved.

Further, in the semiconductor device 101 of Embodiment 1, the drift layer 2 has a main surface provided with an off angle larger than 0° in the <11-20> axial direction, and the gate trench 6 and the Schottky trench 11 , and <11-20> axial directions, variation in characteristics due to the side surfaces of the trench can be reduced, and the operation of the semiconductor device 101 can be stabilized.

Although the gate trenches 6 and the Schottky trenches 11 are formed in stripes in plan view in the first embodiment described above, the present invention is not limited to this. For example, either the gate trench 6 or the Schottky trench 11 may be lattice-shaped.

Further, in this embodiment, the case where the bottom surface of the Schottky trench 11 is formed above the top surface of the first bottom protection region 15 is described, but the present invention is not limited to this. The top surface of protection region 15 and the bottom surface of Schottky trench 11 may be provided at the same position. In the case of such a configuration, there is no need to additionally etch the gate trench 6 in the step shown in FIG.

Embodiment 2.
A semiconductor device and a method for manufacturing the semiconductor device according to the second embodiment will be described with reference to FIGS. 13 to 19. FIG. FIG. 13 is a schematic cross-sectional view showing a cross-section of part of the active region 40 in the semiconductor device 201 of the present embodiment, corresponding to the cross-sectional view taken along line AA' in FIG. 14 to 19 are diagrams showing each step of the method for manufacturing the semiconductor device 201 of this embodiment.

Semiconductor device 201 of the present embodiment differs from semiconductor device 101 of the first embodiment in that second bottom protection region 16 is formed on the bottom surface of Schottky trench 11, as shown in FIG. Other configurations of the semiconductor device 201 of the present embodiment are the same as those of the semiconductor device 101 of the first embodiment, and therefore the points different from the semiconductor device 101 will be mainly described below.

In the semiconductor device 201 , a p ⁺ -type second bottom protection region 16 is provided below the Schottky trench 11 (Schottky electrode 12 ) along the extending direction of the Schottky trench 11 . The second bottom protection region 16 is in contact with the bottom of the Schottky trench 11 and is provided so as to cover the entire bottom of the Schottky trench 11 . The second bottom protection region 16 covers the entire bottom of the Schottky trench 11 so as to protrude in the width direction, so that the width of the second bottom protection region 16 is larger than the width of the Schottky trench 11 . there is

Second bottom protection region 16 is not limited to being provided in contact with the bottom of Schottky trench 11 , and may be provided below and apart from the bottom of Schottky trench 11 in drift layer 2 .

Second bottom protection region 16 is not limited to covering the entire bottom of Schottky trench 11 , and may be provided to cover at least a portion of the bottom of Schottky trench 11 . For example, the second bottom protection regions 16 are spaced along the extending direction of the Schottky trenches 11 (the longitudinal direction in plan view in the case of stripe shape, and the direction is defined for each Schottky trench 11 in the case of lattice shape). , or may be provided so as to cover about half of the bottom of Schottky trench 11 in a cross section orthogonal to the extending direction.

Next, a method for manufacturing the semiconductor device 201 will be described with reference to FIGS. 14 to 19, focusing on points different from the method for manufacturing the semiconductor device 101 of the first embodiment.

First, gate trenches 6 and Schottky trenches 11 are formed as shown in FIG. After that, as shown in FIG. 14, using a first mask 51, ion implantation is performed in an oblique direction that is slightly inclined from the vertical direction with respect to the surface of the semiconductor layer 21. Next, as shown in FIG. In this manner, p-type ions are implanted into the bottom of the gate trench 6 to form the p ⁺ -type first bottom protection region 15, and p-type ions are implanted into the bottom of the Schottky trench 11. A p ⁺ -type second bottom protection region 16 is formed.

Alternatively, as shown in FIG. 15, the first bottom protection region 15 and the second bottom protection region 16 are formed by epitaxially growing the n ⁻ -type first drift layer 25 on the substrate 1, and then forming the first drift layer 25 in advance. may be selectively formed in the upper layer by ion implantation, or buried by epitaxial growth. In this case, after forming the first bottom protection region 15 and the second bottom protection region 16, an n ⁻ -type second silicon layer is formed on the first drift layer 25, the first bottom protection region 15, and the second bottom protection region 16. 2 After forming the drift layer 26 by epitaxial growth, each semiconductor region and trench are formed. For example, the body region 3 is formed in the upper layer portion of the second drift layer 26 . A combination of the first drift layer 25 and the second drift layer 26 corresponds to the drift layer 2 described above.

As shown in FIG. 14, the first bottom protection region 15 and the second bottom protection region 16 formed in this manner are closer to the drift layer 2 than the side surfaces of the gate trench 6 and the Schottky trench 11 (drift layer 2). direction orthogonal to the thickness direction).

Next, as shown in FIG. 16, using a first mask 51 and a second mask 52, the gate trench 6 is additionally etched. By doing so, the bottom surface of the gate trench 6 can be embedded in the first bottom protection region 15 . That is, the corners of the gate trench 6 are covered with the first bottom protection region 15 .

Next, as shown in FIG. 17, a gate insulating film 7 is formed on the entire surface of the semiconductor layer 21 to provide gate insulation on the bottom and side surfaces of the gate trenches 6 and on the bottom and side surfaces of the Schottky trenches 11 . A membrane 7 is formed. After that, in the same manner as the method of manufacturing the semiconductor device 101 described in the first embodiment, the gate trench 6 is filled with, for example, polysilicon (Poly-Si) through the gate insulating film 7, and the gate electrode is formed. 8 is formed.

After that, as shown in FIG. 18, the polycrystalline silicon film in Schottky trench 11 is removed in the same manner as in the method of manufacturing semiconductor device 101 described in the first embodiment. Also, an interlayer insulating film 9 is formed to cover the gate electrode 8 . A third mask 53 is formed on the interlayer insulating film 9 covering the gate trench 6 . Using the third mask 53, the interlayer insulating film 9 and the gate insulating film 7 are also patterned to expose the surface of the semiconductor layer 21 and open contact holes.

Next, as shown in FIG. 19, contact regions 17 are formed on the surfaces of the semiconductor layer 21 (the surfaces of the source region 4 and the body contact region 5) exposed through the opening of the contact holes using a metal such as Ni (nickel). Form.

After that, the Schottky electrode 12 is formed in the Schottky trench 11 in the same manner as the manufacturing method of the semiconductor device 101 described in the first embodiment, and the Schottky electrode 12, the contact region 17, and the interlayer insulating film 9 are covered with the Schottky electrode 12. , a source electrode 13 is formed. Then, a drain electrode 14 is formed so as to cover the back surface of the substrate 1 . Through the above steps, the semiconductor device 201 shown in FIG. 13 can be manufactured.

Even the semiconductor device 201 configured in this manner has the same effect as the semiconductor device 101 of the first embodiment. Furthermore, in the semiconductor device 201 of the present embodiment, the second bottom protection region 16 is formed below the Schottky trench 11 in the SBD region 20 , so that the depletion layer spreading around the second bottom protection region 16 provides a shot barrier. This has the effect of reducing the electric field on the key interface 22 and further suppressing an increase in reverse leakage current.

Embodiment 3.
A semiconductor device and a method for manufacturing the semiconductor device according to the third embodiment will be described with reference to FIGS. 20 to 28. FIG. FIG. 20 is an enlarged view of the region X shown in FIG. 1, and is a schematic plan view schematically showing the layout of the MOSFET cells in the semiconductor device 301. As shown in FIG. FIG. 21 is a cross-sectional view taken along the line BB' of FIG. 20, and is a schematic cross-sectional view showing a cross section of a part of the active region 40 in the semiconductor device 301 of the present embodiment. 20 corresponds to a top view of a lateral cross section at a certain depth between the body region 3 and the first bottom protection region 15 shown in FIG. 22 to 28 are diagrams showing the steps of the method for manufacturing the semiconductor device 301 of this embodiment.

As shown in FIGS. 20 and 21, the semiconductor device 301 of the present embodiment has a first low-resistance region 31 and a second low-resistance region 32 formed in the MOS region 19 and the SBD region 20, respectively. It differs from the semiconductor device 201 of the second embodiment. Other configurations of the semiconductor device 301 of the present embodiment are the same as those of the semiconductor device 201 of the second embodiment, so that the points different from the semiconductor device 201 will be mainly described below.

The first low-resistance region 31 is an n ⁺ -type semiconductor region provided along the gate trench 6 in the extending direction of the gate trench 6 and having a higher n-type impurity concentration than the drift layer 2 . The first low resistance region 31 is provided on the side of the gate trench 6, as shown in FIGS. More specifically, as shown in FIG. 20, the first low-resistance region 31 is formed in contact with the entire side surface of the gate trench 6 to cover the side surface of the gate trench 6 in the extending direction of the gate trench 6 . . 21, the first low resistance region 31 is formed in contact with the body region 3 and the first bottom protection region 15. As shown in FIG.

The second low-resistance region 32 is an n ⁺ -type semiconductor region provided along the Schottky trench 11 in the extending direction of the Schottky trench 11 and having an n-type impurity concentration higher than that of the drift layer 2 . The second low resistance region 32 is provided on the side of the Schottky trench 11 as shown in FIGS. 20 and 21 . More specifically, the second low-resistance region 32 is formed so as to be in contact with the entire side surface of the Schottky trench 11 and cover the side surface of the Schottky trench 11 in the extending direction of the Schottky trench 11 . The second low resistance region 32 is formed in contact with the body region 3 and the second bottom protection region 16, as shown in FIG.

20 and 21 show the case where the first low-resistance region 31 in the MOS region 19 and the second low-resistance region 32 in the SBD region 20 are separated from each other. may be in contact with each other.

Moreover, the first low-resistance regions 31 are not limited to being provided on both opposing side surfaces of the gate trench 6, and may be formed on only one of the side surfaces. Further, the first low-resistance region 31 may not be formed so as to be in contact with the entire side surface of the gate trench 6 in the extending direction of the gate trench 6, and may be partially formed such as only a part of the region. .

Similarly, the second low-resistance regions 32 are not limited to being provided on both opposing side surfaces of the Schottky trench 11, and may be formed on only one of the side surfaces. In addition, the second low-resistance region 32 may not be formed so as to contact the entire side surface of the Schottky trench 11 in the extending direction of the Schottky trench 11, and may be partially formed such as only a part of the region. good too.

The first low-resistance region 31 is not limited to being provided in contact with the side surface of the gate trench 6 , and may be provided at a position apart from the side surface of the gate trench 6 within the drift layer 2 . Similarly, the second low resistance region 32 is not limited to being provided in contact with the side surface of the Schottky trench 11 , and may be provided at a position away from the side surface of the Schottky trench 11 within the drift layer 2 .

The first low-resistance region 31 is not limited to being provided in contact with the body region 3 and the first bottom protection region 15 , and may be provided in the drift layer 2 at a position away from these regions. Similarly, the second low resistance region 32 is not limited to being provided in contact with the body region 3 and the second bottom protection region 16, and may be provided in the drift layer 2 at a position away from these regions. .

In this embodiment, the semiconductor device 301 has the first bottom protection region 15 and the first low resistance region 31 on the gate trench 6 side, and the second bottom protection region 16 and the second low resistance region 31 on the Schottky trench 11 side. A case where the resistance region 32 is provided will be described, but the present invention is not limited to this. And a configuration without the second low-resistance region 32 may be used.

Next, a method for manufacturing the semiconductor device 301 will be described with reference to FIGS. 22 to 28, focusing on points different from the method for manufacturing the semiconductor device 201 of the second embodiment.

First, gate trenches 6, Schottky trenches 11, first bottom protection regions 15, and second bottom protection regions 16 are formed as shown in FIG. After formation, the gate trenches 6 are additionally etched as shown in FIG. Then, with the first mask 51 formed, or after removing the first mask 51 as shown in FIG. An n ⁺ -type first low-resistance region 31 and second low-resistance region 32 are formed by tilted ion implantation such as the above.

Here, the first low-resistance region 31 and the second low-resistance region 32 are formed so that the n-type impurity concentration in these regions is lower than the p-type impurity concentration in the body region 3 . By doing so, the conductivity type of body region 3 can be prevented from being inverted to the n type. Also, by forming in this way, the n-type impurity concentration in the first low-resistance region 31 is lower than the p-type impurity concentration in the first bottom protection region 15 . Similarly, the n-type impurity concentration in the second low resistance region 32 is lower than the p-type impurity concentration in the second bottom protection region 16 . Therefore, the conductivity types of the first bottom protection region 15 and the second bottom protection region 16 are not inverted to n-type, and the corners of the gate trench 6 remain buried in the first bottom protection region 15 .

When forming a p-type connection region (not shown) on the side surface of the gate trench 6 , the p-type impurity concentration in the connection region is formed to be higher than the n-type impurity concentration in the first low resistance region 31 . By doing so, the connection region can be formed by inverting the conductivity type of the region originally serving as the first low-resistance region 31 to the p-type. Since the connection region is usually set to have a p-type impurity concentration higher than that of the body region 3, the connection region is also formed in the region that was originally the body region 3. FIG.

By doing so, the first low-resistance region 31 and the second low-resistance region 32 can be formed to cover the side surfaces of the gate trench 6 and the Schottky trench 11, respectively. Other parts can be manufactured in the same manner as the semiconductor device 201 of the second embodiment.

Note that the first low-resistance region 31 and the second low-resistance region 32 may be formed as follows. 23 and 24 are diagrams showing a part of steps of another manufacturing method of the semiconductor device 301 according to the third embodiment. First, the body region 3, the source region 4, and the body contact region 5 are formed as shown in FIG. , a fourth mask 54 having an opening wider than the gate trench 6 and the Schottky trench 11 to be formed in a later step is formed on the semiconductor layer 21 . Then, ion implantation is performed perpendicularly to the surface of the semiconductor layer 21 to form the first low resistance region 31 and the second low resistance region 32 .

After removing the fourth mask 54, as shown in FIG. 24, the first mask 51 having openings narrower than those of the fourth mask 54 (the first low-resistance region 31 and the second low-resistance region 32) is applied to the semiconductor layer. 21. The openings of the first mask 51 are formed so as to be positioned above the first low resistance region 31 and the second low resistance region 32 . Then, using a first mask 51, reactive ion etching (RIE) is performed to form a gate trench 6 and a Schottky trench 11 extending from the surface of the semiconductor layer 21 through the source region 4 and the body region 3 to reach the drift layer 2. to form At this time, the gate trenches 6 and the Schottky trenches 11 are formed so that the trench bottoms are shallower than the lower portions of the first low-resistance regions 31 and the second low-resistance regions 32, as shown in FIG.

Further, using a first mask 51, ions are implanted in an oblique direction that is slightly inclined from the vertical direction with respect to the surface of the semiconductor layer 21 to form a first bottom protection region 15 at the bottom of the gate trench 6. A second bottom protection region 16 is formed at the bottom of the key trench 11 . After that, a mask similar to the second mask 52 explained in FIG. 16 is formed, and the gate trench 6 is additionally etched. Other parts can be manufactured in the same manner as the semiconductor device 201 of the second embodiment.

Even the semiconductor device 301 configured in this manner has the same effect as the semiconductor device 201 of the second embodiment. Furthermore, in the semiconductor device 301 of the present embodiment, the first low-resistance region 31 having a higher n-type impurity concentration than the drift layer 2 is formed adjacent to the first bottom protection region 15 . The resistance around the bottom protection region 15 is reduced, and the ON resistance of the MOSFET can be reduced. Similarly, since the second low-resistance region 32 having a higher n-type impurity concentration than the drift layer 2 is formed adjacent to the second bottom protection region 16, the surroundings of the second bottom protection region 16 during SBD operation. is reduced, and a high Schottky current can be obtained.

Furthermore, the first low-resistance region 31 and the second low-resistance region 32 are formed around the first bottom protection region 15 and the second bottom protection region 16, so that the first bottom protection region 15 and the second bottom protection region 16 are formed. The n-type impurity concentration around the region 16 is high. That is, the pn junction composed of the first bottom protection region 15 and the first low resistance region 31 and the pn junction composed of the second bottom protection region 16 and the second low resistance region 32 are the drift layers. 2, the potential of the n-type region of the pn junction increases. As the potential of the n-type region of the pn junction increases, the built-in voltage of the body diode formed by the pn junction also increases, making it difficult for current to flow through the body diode.

Here, when the body diode composed of the pn junction is made of SiC (silicon carbide), a current of about 3.5 V normally flows through the body diode from the bandgap of silicon carbide. However, if the potential of the n-type region of the pn junction is high, the body diode will not turn on unless a correspondingly high bias is applied. Therefore, when a forward bias is applied to the body diode, the pn junctions of the first bottom protection region 15 and the second bottom protection region 16 adjacent to the first low resistance region 31 and the second low resistance region 32 are more Bipolar operation is suppressed up to a high voltage.

On the other hand, the SBD can be turned on by applying a bias by a Schottky barrier, and is usually turned on at a voltage of about 1 to 2 V, which is lower than the body diode composed of a pn junction. Therefore, when a forward bias is applied, first a Schottky current, which is a unipolar current, starts to flow due to the SBD, and when the bias becomes higher, a bipolar current starts to flow due to the body diode.

Therefore, by forming the first low-resistance region 31 and the second low-resistance region 32 having a higher n-type impurity concentration than the drift layer 2 around the first bottom protection region 15 and the second bottom protection region 16, A higher maximum unipolar current can be obtained in the SBD because the potential of the n-type region of the pn junction can be increased and the operating voltage of the body diode consisting of the pn junction can be increased.

In the case of a configuration without the second bottom protection region 16 and the second low-resistance region 32, as shown in FIG. A gate trench 6, a Schottky trench 11 and a first bottom protection region 15 are formed and the gate trench 6 is additionally etched. Thereafter, as shown in FIG. 25, while the second mask 52 is still formed, an n ⁺ -type first ion implantation of N (nitrogen), P (phosphorus), or the like is performed at an angle from the inner walls of the gate trench 6 and the Schottky trench 11 . A low resistance region 31 is formed. Other parts can be manufactured in the same manner as the semiconductor device 101 of the first embodiment.

Next, a modified example of the semiconductor device 301 according to the second embodiment will be described. A semiconductor device 302 according to Modification 1 differs from the semiconductor device 301 in that a low resistance region 33 is formed. The low-resistance region 33 is an n-type semiconductor region formed on the first drift layer 27 and having a higher n-type impurity concentration than the first drift layer 27 .

A portion of the low-resistance region 33 formed in the MOS region 19 (a portion formed along the side surface of the gate trench 6) corresponds to the first low-resistance region 31, and is formed in the SBD region 20. A portion (a portion formed along the side surface of the Schottky trench 11 ) corresponds to the second low resistance region 32 . Other configurations are the same as those of the semiconductor device 301 shown in FIGS.

Next, a method for manufacturing the semiconductor device 302 according to Modification 1 will be described. 26 and 27 are diagrams showing some steps of the method for manufacturing the semiconductor device 302 according to Modification 1. FIG. In the semiconductor device 302, the low resistance region 33 can be formed by epitaxial growth. That is, as shown in FIG. 26, after the n ⁻ -type first drift layer 27 is formed on the substrate 1 by epitaxial growth, the n ⁺ -type low resistance region 33 is formed on the first drift layer 27 by epitaxial growth. . A combination of the first drift layer 27 and the low-resistance region 33 corresponds to the drift layer 2 described above.

Subsequently, in the same manner as the manufacturing method shown in FIG. 5 of the first embodiment, the body region 3, the source region 4, and the body contact region 5 are formed in the low resistance region 33 corresponding to the upper portion of the drift layer 2 described above. It is formed in the upper layer by ion implantation. The body region 3, the source region 4, and the body contact region 5 can also be formed on the low resistance region 33 by epitaxial growth.

Then, as shown in FIG. 27, using a first mask 51, reactive ion etching (RIE) is performed from the surface of the semiconductor layer 21 through the source region 4 and the body region 3 to reach the low resistance region 33. Gate trenches 6 and Schottky trenches 11 are formed. At this time, the gate trench 6 and the Schottky trench 11 are formed so that the bottom surface of the trench is shallower than the bottom surface of the low resistance region 33 . Further, using a first mask 51, ions are implanted in an oblique direction that is slightly inclined from the vertical direction with respect to the surface of the semiconductor layer 21 to form a p ⁺ -type first bottom protection region 15 at the bottom of the gate trench 6. As shown in FIG. A p ⁺ -type second bottom protection region 16 is formed at the bottom of the Schottky trench 11 . At this time, the first bottom protection region 15 and the second bottom protection region 16 are formed so that their lower portions are at the same depth as or deeper than the lower portion of the low resistance region 33 .

By doing so, the low resistance region 33 can be formed in the portion of the drift layer 2 located above the lower portions of the first bottom protection region 15 and the second bottom protection region 16 . Other parts can be manufactured in the same manner as the semiconductor device 301 of the third embodiment.

In the semiconductor device 302 according to Modification 1 as well, effects similar to those described in Embodiments 2 and 3 can be obtained.

Embodiment 4.
A semiconductor device and a method for manufacturing the semiconductor device according to the fourth embodiment will be described with reference to FIGS. 28 and 29. FIG. FIG. 28 is a schematic cross-sectional view showing a cross-section of part of the active region 40 in the semiconductor device 401 of the present embodiment, corresponding to the cross-sectional view taken along line AA' in FIG. 29A and 29B are diagrams showing a part of the steps of the method for manufacturing the semiconductor device 401 of this embodiment.

A semiconductor device 401 of the present embodiment differs from the semiconductor device 201 of the second embodiment in that a current diffusion region 34 is formed under the body region 3 as shown in FIG. Other configurations of the semiconductor device of the present embodiment are the same as those of the semiconductor device 201 of the second embodiment, so that the points different from the semiconductor device 201 will be mainly described below.

Current diffusion region 34 is an n ⁺ -type semiconductor region formed under body region 3 so that its upper surface is in contact with the lower surface of body region 3 . The n-type impurity concentration of current diffusion region 34 is higher than the n-type impurity concentration of drift layer 2 . That is, the current diffusion region 34 has a lower resistance than the drift layer 2 .

Next, a method of manufacturing the semiconductor device 401 will be described with reference to FIG. 29, focusing on the differences from the method of manufacturing the semiconductor device 101 of the first embodiment or the method of manufacturing the semiconductor device 201 of the second embodiment.

First, after forming the drift layer 2 as shown in FIG. 4 in the same manner as the method of manufacturing the semiconductor device 101 described in the first embodiment, as shown in FIG. A contact region 5 and a current diffusion region 34 are each formed by ion implantation. Note that any of these may be formed by epitaxial growth.

By doing so, a current diffusion region 34 can be formed below the body region 3 . Other parts can be manufactured in the same manner as the semiconductor device 201 of the second embodiment.

Even the semiconductor device 401 configured in this way has the same effect as the semiconductor device 201 of the second embodiment. Furthermore, in semiconductor device 401 of the present embodiment, since current diffusion region 34 is formed at the bottom of body region 3, the JFET resistance between body region 3 and first bottom protection region 15 can be reduced. , there is an effect that the loss can be reduced by lowering the on-resistance.

Further, in the semiconductor device 401 of the present embodiment, a Schottky current also flows in the vicinity of the body region 3 during freewheeling operation. effect that can be achieved.

Embodiment 5.
The present embodiment applies the semiconductor device according to any one of the first to fourth embodiments described above to a power converter. Although the present disclosure is not limited to a specific power converter, a case where the present disclosure is applied to a three-phase inverter will be described below as a fifth embodiment.

FIG. 30 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

The power conversion system shown in FIG. 30 includes a power supply 500, a power conversion device 600, and a load 700. The power supply 500 is a DC power supply and supplies DC power to the power conversion device 600 . The power supply 500 can be composed of various things, for example, it can be composed of a DC system, a solar battery, a storage battery, or it can be composed of a rectifier circuit or an AC/DC converter connected to an AC system. good too. Also, power supply 500 may be configured by a DC/DC converter that converts DC power output from a DC system into predetermined power.

Power converter 600 is a three-phase inverter connected between power supply 500 and load 700 , converts DC power supplied from power supply 500 into AC power, and supplies AC power to load 700 . As shown in FIG. 30, the power conversion device 600 includes a main conversion circuit 601 that converts input DC power into AC power and outputs it, and a driving circuit that outputs a drive signal for driving each switching element of the main conversion circuit 601. A circuit 602 and a control circuit 603 for outputting a control signal for controlling the driving circuit 602 to the driving circuit 602 are provided.

Load 700 is a three-phase electric motor driven by AC power supplied from power conversion device 600 . Note that the load 700 is not limited to a specific application, but is an electric motor mounted on various electrical equipment, such as a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an electric motor for an air conditioner.

Details of the power conversion device 600 will be described below. The main conversion circuit 601 includes a switching element and a freewheeling diode (not shown). By switching the switching element, the DC power supplied from the power supply 500 is converted into AC power and supplied to the load 700 . Although there are various specific circuit configurations of the main conversion circuit 601, the main conversion circuit 601 according to the present embodiment is a two-level three-phase full bridge circuit, and has six switching elements and It can consist of six freewheeling diodes connected in anti-parallel. The semiconductor device according to any one of the first to fourth embodiments described above is applied to at least one of each switching element and each freewheeling diode of the main conversion circuit 601 . Among them, the MOSFET structure arranged in the MOS region 19 can be used as a switching element, and the SBD arranged in the SBD region 20 can be used as a free wheel diode. Six switching elements are connected in series every two switching elements to form upper and lower arms, and each upper and lower arm forms each phase (U phase, V phase, W phase) of the full bridge circuit. Output terminals of the upper and lower arms, that is, three output terminals of the main conversion circuit 601 are connected to the load 700 .

It should be noted that the semiconductor devices according to the first to fourth embodiments have an integrated structure in which the switching element and the freewheeling diode are built in one chip. Therefore, by using the MOSFET structure arranged in the MOS region 19 as the switching element of the main conversion circuit 601 and using the SBD arranged in the SBD region 20 as the freewheeling diode, the switching element and the freewheeling diode are formed separately. The mounting area can be reduced compared to when two or more chips are used.

The drive circuit 602 generates a drive signal for driving the switching element of the main conversion circuit 601 and supplies it to the gate electrode of the switching element of the main conversion circuit 601 . Specifically, in accordance with a control signal from a control circuit 603, which will be described later, a drive signal for turning on a switching element and a drive signal for turning off a switching element are output to the gate electrode of each switching element. When maintaining the switching element in the ON state, the driving signal is a voltage signal (ON signal) equal to or higher than the threshold voltage of the switching element, and when maintaining the switching element in the OFF state, the driving signal is a voltage equal to or less than the threshold voltage of the switching element. signal (off signal).

The control circuit 603 controls the switching elements of the main conversion circuit 601 so that the desired power is supplied to the load 700 . Specifically, based on the power to be supplied to the load 700, the time (on time) during which each switching element of the main conversion circuit 601 should be in the ON state is calculated. For example, the main conversion circuit 601 can be controlled by PWM control that modulates the ON time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit 602 so that an ON signal is output to the switching element that should be in the ON state at each time point, and an OFF signal is output to the switching element that should be in the OFF state. The drive circuit 602 outputs an ON signal or an OFF signal as a drive signal to the gate electrode of each switching element according to this control signal.

In the power converter according to the present embodiment, since the semiconductor device according to any one of the first to fourth embodiments is applied as the switching element of the main converter circuit 601, the bipolar deterioration is suppressed and the highly reliable semiconductor device is obtained. By using it, it is possible to improve the reliability of the power converter. Further, by applying the semiconductor device according to any one of the first to fourth embodiments as the switching element of the main conversion circuit 601, the mounting area can be reduced, so that the size of the entire device can be reduced. can.

Furthermore, in any of the semiconductor devices of the first to fourth embodiments, dielectric breakdown of gate insulating film 7 can be suppressed in MOS region 19 and an increase in reverse leakage current can be suppressed in SBD region 20 . Therefore, by applying the semiconductor device according to any one of Embodiments 1 to 4, the power conversion device according to the present embodiment can improve the withstand voltage and improve the reliability. play.

In the present embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this, and can be applied to various power converters. In this embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may be used. You can apply it. In addition, the present disclosure can be applied to a DC/DC converter or an AC/DC converter when power is supplied to a DC load or the like.

In addition, the power conversion device to which the present disclosure is applied is not limited to the case where the above-described load is an electric motor. It can also be used as a power conditioner for a photovoltaic power generation system, an electric storage system, or the like.

In the first to fifth embodiments according to the present disclosure described above, the case where the semiconductor material is silicon carbide has been described, but other semiconductor materials may be used. That is, the substrate 1 and the semiconductor layer 21 including the drift layer 2, the body region 3, the source region 4, the body contact region 5, etc. can be composed of other semiconductor materials. Other semiconductor materials include, for example, so-called wide bandgap semiconductors that have a wider bandgap than silicon. Wide bandgap semiconductors other than silicon carbide include gallium nitride, aluminum nitride, aluminum gallium nitride, gallium oxide, and diamond. Similar effects can be obtained even when these wide bandgap semiconductors are used.

In addition, in each of the above-described embodiments described in this specification, the material, material, size, shape, relative arrangement relationship, implementation conditions, etc. of each component may be described, but these are all , and is not limited to the description of each embodiment. Therefore, a myriad of variations not illustrated are envisioned within the scope of each embodiment. For example, when any component is modified, added or omitted, and at least one component of at least one embodiment is extracted and combined with a component of another embodiment. .

In addition, as long as there is no contradiction, "one" or more of the components described as "one" may be provided in each of the above embodiments. Furthermore, each component is a conceptual unit, including cases where one component is composed of a plurality of structures and cases where one component corresponds to a part of a certain structure.

Also, nothing discussed herein is an admission that it is prior art.

Note that appropriate combinations, modifications, and omissions of the embodiments are also included within the scope of the present disclosure.

Reference Signs List 1 substrate 2 drift layer 3 body region 4 source region 5 body contact region 6 gate trench 7 gate insulating film 8 gate electrode 9 interlayer insulating film 11 schottky trench 12 schottky electrode 13 source electrode 14 drain electrode 15 first bottom protection region 16 second bottom protection region 17 contact region 19 MOS region 20 SBD region 21 semiconductor layer 22 Schottky interface 25, 27 first drift layer 26 second drift layer, 31 first low resistance region, 32 second low resistance region, 33 low resistance region, 34 current diffusion region, 40 active region, 41 termination region,
101, 201, 301, 302, 401 semiconductor devices,
500 power supply, 600 power converter, 601 main conversion circuit, 602 drive circuit, 603 control circuit, 700 load

Claims (7)

a first conductivity type drift layer;
a body region of a second conductivity type provided on the drift layer;
a first conductivity type source region provided on the body region;
a gate insulating film provided in a gate trench passing through the body region and the source region in the thickness direction of the drift layer;
a gate electrode provided in the gate trench and provided so as to face the source region via the gate insulating film;
a Schottky electrode provided in a Schottky trench penetrating the body region in the thickness direction of the drift layer;
a first bottom protection region of a second conductivity type provided in contact with a bottom surface of the gate trench, a portion of the side surface, and a corner between the bottom surface and the side surface;
a second bottom protection region of a second conductivity type provided below the Schottky electrode;
a first conductivity type second low resistance region provided on a side of the Schottky trench and having a first conductivity type impurity concentration higher than that of the drift layer;
with
The semiconductor device, wherein the Schottky trench is shallower than the gate trench in the thickness direction of the drift layer. 2. The semiconductor device according to claim 1, wherein the bottom surface of said Schottky trench is located above the top surface of said first bottom protection region. 3. The semiconductor device according to claim 1, further comprising a first conductive type first low resistance region provided on a side of the gate trench and having a first conductive type impurity concentration higher than that of the drift layer. semiconductor device. 4. The semiconductor device according to any one of claims 1 to 3, further comprising a first conductivity type current diffusion region provided below the body region and having a first conductivity type impurity concentration higher than that of the drift layer. The semiconductor device described. The drift layer has a main surface provided with an off angle larger than 0° in the <11-20> axial direction,
5. The semiconductor device according to claim 1, wherein the gate trench and the Schottky trench are formed so that their extending directions are parallel to the <11-20> axis direction. The semiconductor device according to any one of claims 1 to 5 , wherein the drift layer uses a wide bandgap semiconductor as a semiconductor material. A main conversion circuit having the semiconductor device according to any one of claims 1 to 6 and converting input power and outputting the converted power;
a drive circuit that outputs a drive signal to the semiconductor device;
a control circuit that outputs a control signal to the drive circuit;
A power converter with

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