JP7334580B2 - Automatic placement and routing device, automatic placement and routing method, automatic placement and routing program, storage medium storing automatic placement and routing program, and semiconductor integrated circuit - Google Patents

Description

The present invention relates to an automatic placement and routing apparatus for placing and routing circuit elements in a semiconductor integrated circuit, an automatic placement and routing program, a storage medium storing the automatic placement and routing program, and a semiconductor integrated circuit.

2. Description of the Related Art In recent years, as semiconductor integrated circuits have become larger in scale, there has been a demand for ensuring a high fault coverage. Therefore, in the design of semiconductor integrated circuits, design for testability is widely used to improve the fault detection rate.

As a design for testability, there is a method of improving the fault coverage by inserting a fault detection circuit. For example, Patent Document 1 describes an example using BIST (Built-In Self Test) as a failure detection circuit. Further, Patent Document 2 describes an example using a scan circuit (scan path) as a failure detection circuit.

However, even if a fault detection circuit is inserted in the design for testability, a part that cannot be controlled or observed may occur, and a circuit element whose fault cannot be detected (hereinafter referred to as an undetected fault element) may occur.

Such undetected faulty elements may be arranged and routed far from undetected faulty elements on the same wiring. At that time, the automatic placement and routing equipment may satisfy the requirements by inserting circuit elements into the undetected failure part without satisfying the design constraints such as the required timing and the design rules determined by each manufacturing technology. . In this case, the inserted circuit element becomes an undetected faulty element, and the number of undetected faulty elements increases.

Therefore, in Japanese Patent Laid-Open No. 2002-100001, the placement unit determines the length of the wiring between a plurality of circuit elements whose faults cannot be detected to satisfy the design constraints, based on the acquired information necessary for placement and routing and the undetected fault information. By arranging them as close to each other as possible, when an undetected faulty element is detected, the undetected faulty element is taken into consideration so as not to lower the fault coverage.

However, since circuit elements whose faults cannot be detected are placed and routed nearby, other design restrictions may not be satisfied, and the number of gates may increase due to excessive insertion of buffer circuits.

Timing design is becoming more and more important in recent high-speed designs. If the timing design cannot be satisfied, the design specifications cannot be satisfied, and the value of the product is lost. In the past, there was no problem if only the improvement of the fault detection rate was focused, but it is desired to improve the fault detection rate while solving the problem of unsatisfactory timing due to speeding up.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the problem of unsatisfactory timing and improve the fault detection rate.

In order to solve the above-described problems, the present invention includes circuit information acquisition means for acquiring circuit element information and wiring information in a semiconductor integrated circuit, and placement and routing means for placing and wiring circuit elements. In the automatic placement and routing apparatus, undetected fault element information obtaining means for obtaining undetected fault element information, which is information of circuit elements whose faults cannot be detected among the circuit elements, and whether or not to give priority to design constraints relating to timing are set. and priority information obtaining means for obtaining priority information, wherein the circuit obtained by the circuit information obtaining means, when the placement and routing means is set in the priority information so as not to give priority to the design constraints related to the timing. Wiring that satisfies a design constraint on wiring in which wiring between a plurality of said fault-undetectable circuit elements connected by the same wiring is predetermined based on element information and wiring information and said undetected faulty element information. If the priority information is set to give priority to the design constraints on timing, the circuit elements that cannot be detected as faults are placed and routed with priority given to the design constraints on timing. , characterized in that

According to the present invention, since the priority setting means is provided for setting the design constraints related to timing so as to give priority, it is possible to improve the fault detection rate while solving the problem of unsatisfactory timing.

1 is a configuration diagram of an automatic placement and routing apparatus according to a first embodiment of the present invention; FIG. 2 is a configuration diagram showing a functional configuration of the automatic placement and routing apparatus shown in FIG. 1; FIG. FIG. 4 is a circuit diagram showing an example of a logic circuit including undetected faulty elements; FIG. 4 is an explanatory diagram showing an example of an arrangement wiring pattern of the logic circuit shown in FIG. 3; FIG. 4 is an explanatory diagram showing an example of an arrangement wiring pattern in which circuit elements are inserted in order to satisfy design rules in the logic circuit shown in FIG. 3; 6 is a logic circuit diagram of the layout and wiring pattern shown in FIG. 5; FIG. 7 is an explanatory diagram showing the delay time of each element in the logic circuit shown in FIG. 6; FIG. FIG. 4 is an explanatory diagram showing an example of an arrangement and wiring pattern in which the logic circuit shown in FIG. 3 is arranged and routed with priority given to timing; 3 is a configuration diagram of a modification of the automatic placement and routing apparatus shown in FIG. 2; FIG. FIG. 9 is a circuit diagram showing an example of a logic circuit targeted by the automatic placement and routing apparatus according to the second embodiment of the present invention; FIG. 11 is an explanatory diagram showing an example of an arrangement wiring pattern of the logic circuit shown in FIG. 10; 12 is an explanatory diagram showing an example in which a buffer circuit is inserted in the layout and wiring pattern shown in FIG. 11; FIG. FIG. 11 is an explanatory diagram showing an example of an arrangement and wiring pattern when the timing constraint is set rather severely for the logic circuit shown in FIG. 10; FIG. 11 is a configuration diagram showing a functional configuration of an automatic placement and routing device according to a third embodiment of the present invention;

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIGS. 1 to 9. FIG. FIG. 1 is a configuration diagram of an automatic placement and routing apparatus according to the first embodiment of the present invention.

The automatic layout and wiring apparatus 10 shown in FIG. 3, a storage device 4 for storing data and programs, and a display device 5 for displaying an input screen (for example, GUI: Graphical User Interface) and processing results. As is clear from FIG. 1, the automatic placement and routing apparatus 10 is composed of a normal computer and its peripheral devices. A pointing device such as a tablet or trackball may be used instead of the mouse 3 . A semiconductor memory, a hard disk, or the like may be arbitrarily used as the storage device 4, and a CRT, a liquid crystal display, or the like may be arbitrarily used as the display device 5, for example.

FIG. 2 shows the functional configuration of the automatic placement and routing apparatus 10. As shown in FIG. The automatic placement and routing apparatus 10 includes a placement unit 20, a post-placement optimization unit 21, a clock tree synthesis unit 22, a post-clock tree optimization unit 23, a wiring unit 24, and a post-routing optimization unit 25. , and a priority determination unit 26 . The placement unit 20, the post-placement optimization unit 21, the clock tree synthesis unit 22, the post-clock tree optimization unit 23, the wiring unit 24, the post-routing optimization unit 25, and the priority determination unit 26 are the same as those shown in FIG. The processing device 1 functions.

The placement unit 20 includes information 30 necessary for placement and routing, such as cell libraries, netlists, design rules, and timing constraints, that is, circuit element information and wiring information, and undetected fault information 31, which is information on circuit elements whose faults cannot be detected. , a floor plan is performed, the chip size, I/O placement positions, hard macro placement positions, etc. are determined, and cells are placed. The information 30 required for placement and wiring and the undetected failure information 31 are pre-stored in the storage device 4, for example. That is, the storage device 4 functions as a first storage device and a second storage device, and the placement unit 20 functions as circuit information acquisition means, undetected fault element information acquisition means, and placement and wiring means. The information 30 required for placement and wiring and the undetected failure information 31 may be stored in separate storage devices.

The design rule includes restrictions on layout and wiring design of circuit elements, such as the minimum dimension of elements, distance between elements, wiring width and distance between wirings, and includes design restrictions related to wiring. A timing constraint is a constraint on a permissible delay time such as a delay time (operating frequency) of data transfer between flip-flops of the circuit, and corresponds to a design constraint on timing.

The undetected fault information 31 includes the type (cell name) of the circuit element that is the undetected fault element, the instance name, connection information, and the like (undetected fault element information). A result obtained by performing a fault simulation with another device may be used. Of course, the automatic placement and wiring apparatus 10 may be provided with a fault simulation function to read a netlist or the like, perform fault simulation, and generate the undetected fault information 31 from the result.

The post-placement optimization unit 21 optimizes the cell placement performed by the placement unit 20 . In addition, the post-arrangement optimization unit 21 switches between optimizing the arrangement with priority given to timing and optimizing the arrangement so that undetected faulty elements are placed close to each other under the control of the priority order determination unit 26, which will be described later. be done.

The clock tree synthesizer 22 recognizes the clock signal and flip-flops in the netlist, and synthesizes a clock tree for connecting the clock signal and each flip-flop.

The post-clock tree optimizing unit 23 optimizes the placement of clock drivers and the like based on the clock tree synthesized by the clock tree synthesizing unit 22 .

The wiring unit 24 connects the circuit elements optimized by the post-placement optimization unit 21 and the post-clock tree optimization unit 23 by wiring. That is, the wiring section 24 functions as an arrangement and wiring means.

The post-routing optimization unit optimizes the wiring performed by the wiring unit 24 based on design rules and design constraints such as timing constraints so as to satisfy them.

Based on the priority setting information 33, the priority determination unit 26 informs the post-placement optimization unit 21 of whether to optimize placement with priority given to timing, or to optimize by arranging undetected faulty elements closer to each other. instruct. The priority setting information 33 indicates information for setting whether the placement is optimized with timing priority or the optimization is performed by arranging undetected faulty elements close to each other (undetected node allowance). In other words, the priority setting information 33 is priority information for setting whether or not to give priority to design constraints related to timing. The priority determination unit 26 functions as priority information acquisition means for acquiring priority information.

As an example of this priority setting information 33,
set_dft_placemethod_timing_priority = on: Timing priority
set_dft_placemethod_timing_priority=off: It can be a file in which commands such as undetected node allowance priority are described. Then, the priority determination unit 26 reads the file. Alternatively, the command may be input directly from the keyboard 2.

Layout data 32 is finally output by sequentially executing from the placement unit 20 to the post-wiring optimization unit 25 . The layout data 32 is output to the storage device 4, for example. Therefore, FIG. 2 shows the flow of processing (flowchart) as well as the functional configuration. Therefore, each block also functions as a circuit information acquisition step, an undetected fault element information acquisition step, a priority information acquisition step, and a placement and routing step of the automatic placement and routing method executed by the automatic placement and routing apparatus.

Next, the placement and routing of undetected faulty elements in the automatic placement and routing apparatus 10 having the above configuration will be described with reference to FIGS. 3 to 7. FIG.

FIG. 3 is a circuit diagram showing an example of a logic circuit serving as an undetected failure element. The circuit diagram of FIG. 3 shows the path from hard macro H1 to hard macro H2. A NOT circuit IV1, a flip-flop FF1, an AND circuit AD1, a flip-flop FF2, and a NOT circuit IV2 are connected in order between the hard macros H1 and H2.

In such a circuit, the wiring between the hard macro H1 and the NOT circuit IV1 and the wiring between the NOT circuit IV1 and the flip-flop FF1 are undetected failure nodes UN1 and UN1', respectively. Also, the wiring between the flip-flop FF2 and the NOT circuit IV2 and the wiring between the NOT circuit IV2 and the hard macro H2 are undetected failure nodes UN2 and UN2', respectively. That is, the NOT circuits IV1 and IV2 and the flip-flops FF1 and FF2 connected to the undetected failure nodes UN1, UN1', UN2 and UN2' are undetected failure elements.

FIG. 4 shows an example of layout and wiring of the logic circuit of FIG. In FIG. 4, undetected faulty elements are arranged and wired close to each other by the method disclosed in Patent Document 3. FIG. In FIG. 4, when the drive capability of the flip-flop FF1 and the AND circuit AD1 is limited and the design rule cannot be satisfied, buffers are provided between the flip-flop FF1 and the AND circuit AD1 and between the AND circuit AD1 and the flip-flop FF2 to satisfy the design rule. A circuit is inserted.

FIG. 5 shows the state in which the buffer circuit is inserted. In FIG. 5, a circuit denoted by BF1 is a buffer circuit inserted between the flip-flop FF1 and the AND circuit AD, and a circuit denoted by BF2 is inserted between the AND circuit AD and the flip-flop FF2. buffer circuit. FIG. 6 shows the layout and wiring shown in FIG. 5 as a logic circuit.

A case where a timing violation occurs in the circuit of FIG. 6 will be described. It is assumed that the circuit in FIG. 6 operates at 2.0 GHz, and the delay time of each circuit element is the value shown in FIG. In this case, in order to operate at 2.0 GHz, the signal must reach between the flip-flops FF1 and FF2 at 500 ps (picoseconds). The signal arrival time between the flip-flops FF1 and FF2 is the delay time of the flip-flop FF1+the delay time of the buffer circuit BF1+the delay time of the AND circuit AD1+the delay time of the buffer circuit BF2+the setup time of the flip-flop FF2. That is, as shown in FIG. 7, 200 ps+50 ps+50 ps+50 ps+200 ps=550 ps, a timing violation of 50 ps occurs, and the product specification cannot be satisfied.

Therefore, in the present embodiment, when the priority determination unit 26 refers to the setting value of the priority setting information 33 and the timing is prioritized, the design constraints related to the timing are given priority and the post-placement optimization is performed. do. FIG. 8 shows an example of optimizing placement and routing with priority given to timing. As shown in FIG. 8, the circuit elements are arranged evenly by performing optimization that emphasizes timing rather than the constraint of forced placement close to the undetected nodes UN1, UN1′, UN2, and UN2′. , the buffer circuit required to satisfy the design rule is not inserted. Therefore, it becomes possible to meet the timing constraints. Here, even when priority is given to timing constraints, non-failure detection elements may be brought closer as long as the timing constraints are satisfied. The present embodiment prioritizes timing constraints and does not satisfy only timing constraints.

In addition, when the priority determination unit 26 refers to the setting value of the priority setting information 33 and the timing is not prioritized, the same The wiring between a plurality of undetected faulty elements (between circuit elements) connected by wiring is optimized so as to be close to each other so that the wiring length satisfies a predetermined wiring design constraint.

According to the present embodiment, when the priority setting information 33 is not set to give priority to timing, the priority determining unit 26 determines that the information 30 required for placement and routing acquired by the post-placement optimizing unit 21 and the Based on the undetected fault information 31, the wiring between a plurality of undetected fault elements is brought closer to a wiring length that satisfies the design constraints on wiring, and the layout is optimized. On the other hand, if the priority setting information 33 is set to give priority to timing, the post-placement optimization unit 21 places undetected faulty elements with priority given to design constraints related to timing. are optimizing. By doing so, it becomes possible to place and route undetected faulty elements with priority given to timing, and to prevent the risk of not being able to satisfy the timing constraint and the excessive increase in the number of gates. . Therefore, it is possible to improve the fault detection rate while solving the problem of unsatisfactory timing.

In the above description, the optimization unit 21 after placement performs optimization so as to give priority to timing. This is because forced placement is performed on undetected failure nodes at the stage of initial placement in the placement unit 20, so the setting of timing priority may not work effectively. In general, post-placement optimization is performed by optimizing portions that are critical in terms of timing based on the initial placement. In short, fine adjustments are repeated based on the initial arrangement. Initial placement is therefore important. If the forced placement near the undetected failure node is enabled at the stage of initial placement, there is a possibility that the subsequent optimization may not be able to improve the timing even though the timing should originally be satisfied. In order to improve on this point, it is desirable to consider timing information and set priorities before initial placement. In other words, when the priority setting information 33 indicates that priority is given to timing, it is desirable to determine the feasibility of design constraints regarding timing and perform initial placement.

Therefore, as a modification of FIG. 2, the priority determination unit 26 can acquire the timing information 34 as shown in FIG. Then, the priority judging section 26 judges the timing convergence difficulty level of the path passing through the undetected fault element from the undetected fault information 31 and the timing information 34, To enable a placement unit 20 to execute automatic placement with priority given to timing without executing forced placement around detected faulty elements. That is, the priority determination unit 26 functions as feasibility determination means for determining the feasibility of the design constraints related to timing. When the priority information is set to give priority to the design constraint on timing and the feasibility determination means determines that there is no feasibility, the placement unit 20 gives priority to the design constraint on timing and detects a circuit in which a fault cannot be detected. Initial placement of elements.

The timing information 34 may be the result of timing analysis performed by another tool, or may be the timing analysis performed within the automatic placement and routing apparatus 10 . Alternatively, based on the information of the node that becomes a bottleneck in the timing analysis, timing information may be acquired only for that part.

By configuring as shown in FIG. 9, it is possible to perform automatic placement prioritizing timing from the stage of initial placement, prevent timing failure due to initial placement, and solve the problem that timing cannot be fully improved by optimization. can be done.

(Second embodiment)
Next, an automatic placement and routing apparatus according to a second embodiment of the present invention will be described with reference to FIGS. 10 to 13. FIG. In addition, the same reference numerals are given to the same parts as in the first embodiment described above, and the description thereof is omitted.

This embodiment is a layout method around undetected fault nodes that is effective, for example, in a case where there are many logic circuits and undetected fault nodes occur. FIG. 10 shows an example of a multistage circuit with many logic circuits. FIG. 10 shows a logic circuit between flip-flops FF3 and FF4. A combinational circuit C1, a buffer circuit BF3, an AND circuit AD2, a multiplexer MX1, a buffer circuit BF4, and a combinational circuit C2 are connected in order between the flip-flops FF3 and FF4. In such a logic circuit, it is assumed that the wire between the AND circuit AD2 and the multiplexer MX1 is the undetected failure node UN3.

FIG. 11 shows an example of layout and wiring of the logic circuit shown in FIG. In FIG. 11, undetected faulty elements are arranged and wired close to each other by the method disclosed in Patent Document 3. FIG. In FIG. 11, when the distance between the flip-flop FF3 and the flip-flop FF4 is long and the elements around the undetected failure node UN3 are forcibly arranged closer, the drive capability of the buffer circuits BF3 and BF4 is insufficient. may occur. In such a case, as shown in FIG. 12, buffer circuits BF3' and BF4' are inserted between the buffer circuit BF3 and the AND circuit AD2 and between the buffer circuit BF4 and the combinational circuit C2, respectively. When such buffer circuits BF3' and BF4' are inserted, timing violations may occur as described in the first embodiment.

Therefore, in the present embodiment, the priority setting information 33 described in the first embodiment is set so as to tighten the timing constraint. That is, setting is made so as to tighten the design constraints regarding timing. Specifically, set the command as follows.
set_dft_placemethod_timing_priority = pssimism

FIG. 13 shows an example of placement and wiring performed with this setting. As shown in FIG. 13, since the distances between the flip-flops FF3 and FF4 are shortened, there is no place where the design rule cannot be satisfied, and no useless buffer circuit is inserted.

According to this embodiment, by setting the timing constraint stricter than the default state, layout is performed so that the distance between the flip-flops is shortened. Therefore, even in the case where there are many logic circuits and undetected fault nodes occur, it is possible to prevent a drop in the fault coverage while satisfying the timing.

Incidentally, in the present embodiment, the amount of strictness may be set in advance on the automatic placement and wiring apparatus 10 side, or may be given by the user with another command. Alternatively, it may be generated within the automatic placement and routing apparatus 10 based on the undetected fault information 31 and frequency-based timing constraints.

(Third Embodiment)
Next, an automatic placement and routing apparatus according to a third embodiment of the present invention will be described with reference to FIG. In addition, the same reference numerals are given to the same parts as in the first embodiment described above, and the description thereof is omitted.

In this embodiment, the numerical ranges of the parameters defined in the cell library created by the semiconductor vendor are relaxed. The delay values of cells (circuit elements) such as general buffer circuits and AND circuits in semiconductor integrated circuit design are defined in tables such as those shown in Table 1 prepared by semiconductor vendors. Each value is guaranteed by the semiconductor vendor. Table 1 defines cell delay values (ps) by capacitance and transition values.

On the other hand, the transition of the signal input to the cell is generally specified for each pin (terminal) of each cell.
time_unit : "1ps";
max_transition : 1200;
capacitive_load_unit(1, "pf");
max_capacitance : 0.31088;
And so on, and improvements are being made in the implementation based on this information.

Here, for example, in the transition, although the range of 3.149 ps to 1321 ps is guaranteed as shown in Table 1, the actual implementation is limited to 1200 ps as described above, which is a rather strict implementation. are being implemented. For example, if the transition constraint is 1321 ps, the buffer is not inserted into the undetected fault node, but if the transition constraint is 1200 ps, the buffer is inserted into the undetected fault node. Sometimes.

Therefore, in the present embodiment, a relief portion 27 is provided as shown in FIG. The relaxation unit 27 relaxes parameter restrictions such as transition restrictions and capacitance restrictions in accordance with the setting of a predetermined command, for example. That is, in this embodiment, parameters such as transition constraints and capacitance constraints are included in design constraints related to timing.

Specifically, the following command is used as a predetermined command to set whether or not to relax the restrictions on transitions and capacitance.
set_dft_placemethod_active_transition = on: Relaxed transition restrictions
set_dft_placemethod_active_transition = off: no relaxation of transition constraints
set_dft_placemethod_active_capacitance = on: Relaxed capacitance constraint
set_dft_placemethod_active_capacitance = off: no relaxation of capacitance constraint

The above settings allow relaxation of transition and capacitance constraints for all cells. Therefore, transition restrictions and capacitance can be relaxed from the initial placement stage within the range of delay calculation guarantees, and the insertion of buffer circuits around undetected fault nodes can be suppressed, thereby suppressing a drop in fault coverage.

In the example described above, transition restrictions and capacitance restrictions were relaxed for all cells, but in that case, all layout designs would be designed with zero margins, and some factors such as fluctuations in the power supply would occur. There is a risk that it will not be able to operate as specified. Therefore, it is preferable to relax the transition constraint and the capacitance constraint only where necessary. Therefore, the relaxation of the transition constraint and the capacitance constraint may be limited to the vicinity of the undetected failure node.

Specifically, in the mitigation unit 27, based on the undetected fault information 31, the circuit information is back-traced from the undetected fault element to identify the instance name and cell name ahead of the undetected fault element, and Forward tracing is performed to identify the instance name and cell name behind the non-faulty detected element. Then, it is possible to relax the transition constraint and the capacitance constraint only for the specified cell.

According to this embodiment, the relaxing unit 27 can be set to relax the restrictions on the transitions and capacitances (parameters) set in the cell library. By doing so, it is possible to relax the restrictions within the range guaranteed by the semiconductor vendor. It is possible to suppress the insertion of buffer circuits in the vicinity of the node, thereby suppressing the deterioration of the fault detection rate.

In addition, the alleviation unit 27 may apply settings for alleviating restrictions on transitions and capacitances (parameters) set in the cell library only to undetected fault elements and elements before and after such elements. In this case, it is no longer necessary to design the entire layout design with a zero margin, and it is possible to reliably suppress the insertion of buffer circuits only in the peripheral portions of undetected faulty elements, thereby suppressing a drop in fault detection rate.

Note that the priority determination unit 26 and the alleviation unit 27 described in the above embodiment are not provided as functional blocks, but the placement unit 20 and the post-placement optimization unit 21 have the functions of these blocks. good too.

Further, for example, due to the arrangement of other circuit elements, it may not be possible to arrange the undetected failure elements close to each other as described above. In this case, there is a possibility that the insertion of the above-described undetected faulty elements will occur and the fault coverage will decrease. Therefore, placement and wiring may be implemented by adding or changing (changing the circuit) appropriate elements so that failures of undetected faulty elements can be detected. In other words, the automatic placement and routing apparatus 10 has circuit changing means. This circuit changing means may be provided as a single functional block, or may also serve as the placement section 20 or the like. When the circuit is changed, a changed netlist is generated.

Further, when performing automatic placement and routing, the processing from the placement unit 20 shown in FIG. 2 to the post-wiring optimization unit 25 is often repeated. At that time, if automatic placement and routing is performed in consideration of design constraints, logic elements may be inserted so as to satisfy the requirements for placement and routing. Due to the insertion of this element, the undetected failure information 31 may differ from that initially obtained. Therefore, for example, after the optimization unit 25 after wiring, redetection of the undetected fault elements may be performed, and if updating is necessary, the undetected fault information 31 may be updated.

By doing so, it is possible to perform processing corresponding to a circuit change or the like during placement and wiring in consideration of undetected faulty element information. That is, the configuration may include undetected fault element detection means and undetected fault element information update means.

Further, the automatic placement and routing apparatus 10 may be configured as an automatic placement and routing program that can be read and operated by a computer. In this case, the placement unit 20, the post-placement optimization unit 21, the clock tree synthesis unit 22, the post-clock tree optimization unit 23, the wiring unit 24, the post-routing optimization unit 25, and the priority determination shown in FIG. A part in which the processing device 1 functions, such as the part 26, is configured as a program. Also, this automatic placement and routing program may be stored in a computer-readable storage medium such as a memory card.

It should be noted that the present invention is not limited to the above embodiments. That is, various modifications can be made without departing from the gist of the present invention.

REFERENCE SIGNS LIST 1 processing device 4 storage device 10 automatic placement and routing device 20 placement unit (circuit information acquiring means, undetected faulty element information acquiring means, placement and routing means, circuit changing means)
21 Optimization unit after placement 24 Wiring unit (placement and routing means)
25 post-wiring optimization unit 26 priority determination unit (priority information acquisition means, feasibility determination means)
27 Alleviation section 30 Information necessary for placement and wiring (circuit element information and wiring information)
31 undetected failure information (information on circuit elements for which failure detection is not possible)
32 layout data 33 priority setting information (priority information)

JP 2007-328852 A JP-A-2001-83213 Japanese Patent No. 6051548

Claims (10)

An automatic placement and routing apparatus comprising: circuit information acquiring means for acquiring circuit element information and routing information in a semiconductor integrated circuit; and placement and routing means for placing and routing circuit elements,
undetected fault element information obtaining means for obtaining undetected fault element information, which is information of a circuit element whose fault cannot be detected among the circuit elements;
priority information acquisition means for acquiring priority information indicating whether or not to give priority to design constraints related to timing;
The placement and routing means is
When the priority information is set not to give priority to the design constraint related to the timing, the same arranging the wiring between the plurality of circuit elements connected by wiring where the failure cannot be detected so as to be close to each other so that the wiring length satisfies predetermined design constraints on the wiring;
if the priority information is set to give priority to the design constraint regarding timing, placing and wiring the circuit element in which the fault cannot be detected with priority given to the design constraint regarding timing;
An automatic placement and routing device characterized by: feasibility determination means for determining the feasibility of the design constraints related to the timing;
When the priority information is set to give priority to the design constraint on the timing and the feasibility determination means determines that the feasibility is not feasible, the placement and routing means gives priority to the design constraint on the timing. initial placement of circuit elements for which failure detection is not possible;
2. The automatic placement and routing apparatus according to claim 1, wherein: 3. The automatic placement and routing apparatus according to claim 1, wherein said priority information can be set so as to tighten the design constraints relating to said timing. 4. The automatic placement and routing apparatus according to claim 1, wherein the priority information can be set so as to relax constraints of parameters set in the cell library. 5. The automatic device according to claim 4, wherein said placement and routing means applies the setting that relaxes the constraint of said parameter set in said cell library only to said circuit element that cannot be detected as a failure and peripheral elements. Place-and-route device. When the placement and wiring means cannot place the circuit element whose failure cannot be detected so close to the wiring length that satisfies the design constraint on the wiring, the circuit including the circuit element whose failure cannot be detected is changed to change the circuit element information. 6. The automatic placement and routing apparatus according to claim 1, further comprising circuit changing means for changing said wiring information. In an automatic placement and routing method for placing and routing circuit elements in a semiconductor integrated circuit by an automatic placement and routing device,
a circuit information acquisition step of acquiring circuit element information and wiring information in a semiconductor integrated circuit;
an undetected fault element information obtaining step of obtaining undetected fault element information, which is information of a circuit element whose fault cannot be detected among the circuit elements;
a priority information obtaining step of obtaining priority information for setting whether or not to give priority to design constraints related to timing; A design constraint on wiring in which wiring between a plurality of circuit elements whose faults cannot be detected and which are connected by the same wiring is determined in advance based on the circuit element information and wiring information and the undetected fault element information. If the priority information is set to give priority to the design constraint on the timing, the design constraint on the timing is given priority and the circuit element whose failure cannot be detected is arranged. and a place and route step that routes
are sequentially executed by the automatic placement and routing apparatus. 8. A semiconductor integrated circuit manufactured using the automatic placement and routing apparatus according to claim 1 or the automatic placement and routing method according to claim 7. In an automatic placement and routing program that causes a computer to function as circuit information acquiring means for acquiring circuit element information and routing information in a semiconductor integrated circuit and placement and routing means for placing and routing circuit elements,
undetected fault element information obtaining means for obtaining undetected fault element information, which is information of a circuit element whose fault cannot be detected among the circuit elements;
causing the computer to function as priority information acquisition means for acquiring priority information for setting whether or not to give priority to design constraints related to timing;
The placement and routing means is
When the priority information is set not to give priority to the design constraint related to the timing, the same arranging the wiring between the plurality of circuit elements connected by wiring where the failure cannot be detected so as to be close to each other so that the wiring length satisfies predetermined design constraints on the wiring;
if the priority information is set to give priority to the design constraint regarding timing, placing and wiring the circuit element in which the fault cannot be detected with priority given to the design constraint regarding timing;
An automatic placement and routing program characterized by: 10. A computer-readable storage medium storing the automatic placement and routing program according to claim 9.

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