JP7341885B2 - switching circuit - Google Patents

Description

TECHNICAL FIELD This disclosure relates to switching circuits.

In power conversion circuits and the like, high-frequency driving of switching elements is effective for reducing the size and weight of power conversion circuits and the like. However, in high-frequency driving of the switching element, a problem arises due to the high voltage (surge voltage) that is transiently generated when the switching element is turned off.

As a configuration for suppressing such surge voltage, it has been known to provide a surge suppression clamp circuit between the control terminal of the switching element and the high potential side main terminal. However, in such a configuration, since the voltage of the high potential side main terminal is applied to the control terminal, the loss that occurs when the switching element is driven at high voltage and high speed (high frequency) increases.

On the other hand, Patent Document 1 below discloses a configuration in which a circuit element in which a diode and a Zener diode are connected in series as a surge suppression clamp circuit is provided between a control terminal and a low-potential side main terminal. .

Japanese Patent Application Publication No. 2018-88772

In the configuration as in Patent Document 1, surge voltage is suppressed using the voltage of the parasitic inductance on the low potential side of the switching element. Therefore, the loss can be reduced compared to the conventional configuration in which a surge suppression clamp circuit is provided between the control terminal and the high potential side main terminal.

However, in the configuration as disclosed in Patent Document 1, there is room for improvement from the viewpoint of appropriate protection of the switching elements.

The present disclosure aims to solve the above-mentioned problems, and to provide a switching circuit that can suppress surge voltage with low loss and protect switching elements more appropriately. .

A switching circuit according to one aspect of the present disclosure includes: a switching element having a pair of main terminals and a control terminal; a drive circuit that drives the switching element by applying a drive voltage to the control terminal; a surge suppression circuit that suppresses generation of surge voltage between main terminals, the drive circuit has a drive signal output terminal and a drive reference potential terminal, and the drive signal output terminal is connected to the main terminal of the switching element. connected to a control terminal, the drive reference potential terminal is connected via a first wiring to a control reference potential terminal provided on the low potential side of the switching element separately from the low potential side main terminal of the switching element, The surge suppression circuit includes: a resistor element provided on the first wiring; a diode and a capacitor provided in series on a second wiring connecting the drive reference potential terminal and the low potential side main terminal; a capacitor voltage setting circuit that sets the voltage applied to the capacitor, the diode has a cathode connected to the driving reference potential terminal side, an anode connected to the low potential side main terminal side, and the diode has a cathode connected to the drive reference potential terminal side, an anode connected to the low potential side main terminal side, The setting circuit sets a surge suppression operating voltage for causing current to flow through the surge suppression circuit by actively or passively changing the voltage applied to the capacitor.

According to the above configuration, during off-operation, the drive voltage applied to the control terminal of the switching element decreases, the current flowing between the main terminals of the switching element decreases, and an excessive voltage (surge voltage) occurs between the main terminals. When this occurs, the current flowing through the parasitic inductance of the low-potential side main terminal suddenly decreases, and an induced voltage is generated by the parasitic inductance.In the surge suppression circuit, a current (clamp current) flows from the low-potential side main terminal toward the drive reference potential terminal. ) flows. As a result, a voltage is generated in the resistance element provided on the first wiring, and the current flowing from the drive reference potential terminal to the control reference potential terminal of the switching element becomes small. Therefore, the switching speed (turn-off speed) of the switching element becomes slow, and surge voltage is suppressed. At this time, the induced voltage generated by the parasitic inductance is a low voltage, and the surge suppression circuit can be operated at a low operating voltage, so that losses due to suppression of the surge voltage can be reduced. Furthermore, by actively or passively changing the voltage applied to the capacitor, the capacitor voltage setting circuit changes the surge suppression operating voltage at which current flows through the surge suppression circuit. For example, during ON operation, the capacitor voltage setting circuit increases the voltage applied to the capacitor. As the voltage applied to the capacitor increases, the voltage generated across the resistive element decreases due to the voltage generated across the parasitic inductance. Therefore, during the ON operation of the switching element, in which the voltage applied to the capacitor is high, the voltage generated in the resistance element is reduced, making it difficult for a clamp current to flow through the surge suppression circuit. Therefore, by suppressing the clamp current from flowing during the ON operation of the switching element, it is possible to prevent excessive voltage from being applied between the control terminal and the control reference potential terminal. Thereby, the switching element can be appropriately protected.

The surge suppression circuit includes a bypass circuit connected in parallel to surge suppression wiring including the first wiring and the second wiring between the low potential side main terminal and the control reference potential terminal, and the bypass circuit is connected in parallel to the surge suppression wiring including the first wiring and the second wiring. The circuit may be configured such that a bypass circuit operating voltage for allowing current to flow through the bypass circuit is within a range of a surge suppression operating voltage set by the capacitor voltage setting circuit.

According to the above configuration, when the clamp current flowing through the surge suppression circuit increases and the voltage applied between the low potential side main terminal and the control reference potential terminal becomes larger than the bypass circuit operating voltage due to the clamp current, the bypass circuit increases. Current flows through the circuit and the clamp current is suppressed. Therefore, it is possible to prevent excessive voltage from being applied between the control terminal and the control reference potential terminal, and the switching element can be appropriately protected.

A switching circuit according to another aspect of the present disclosure includes: a switching element having a pair of main terminals and a control terminal; a drive circuit that drives the switching element by applying a drive voltage to the control terminal; a surge suppression circuit that suppresses surge voltage from occurring between the main terminals of the drive circuit, a drive signal output terminal of the drive circuit is connected to the control terminal of the switching element, and the surge suppression circuit is connected to the control terminal of the switching element. A diode and a capacitor provided in series on a surge suppression wiring connecting a terminal and the low potential side main terminal, and a capacitor voltage setting circuit that sets a voltage applied to the capacitor, the diode comprising: A cathode is connected to the control terminal side, an anode is connected to the low potential side main terminal side, and the capacitor voltage setting circuit actively or passively changes the voltage applied to the capacitor, A surge suppression operating voltage is set so that a current flows through the surge suppression circuit.

According to the above configuration, when the drive voltage applied to the control terminal of the switching element decreases, the current flowing between the main terminals of the switching element decreases, and an excessive voltage (surge voltage) occurs between the main terminals, the voltage decreases. As the current flowing through the parasitic inductance of the main terminal on the potential side suddenly decreases, an induced voltage is generated due to the parasitic inductance, and a current (clamp current) flows from the main terminal on the low potential side toward the control terminal in the surge suppression wiring of the surge suppression circuit. . The clamp current flowing through the control terminal of the switching element slows down the switching speed of the switching element, suppressing surge voltage. At this time, since the voltage generated by the current flowing through the parasitic inductance due to the surge voltage is a low voltage, it is possible to reduce the loss that occurs when suppressing the surge voltage. Furthermore, by actively or passively changing the voltage applied to the capacitor, the capacitor voltage setting circuit changes the surge suppression operating voltage at which current flows through the surge suppression circuit. For example, during ON operation, the capacitor voltage setting circuit increases the voltage applied to the capacitor. When the voltage applied to the capacitor increases, it becomes difficult for the clamp current generated by the voltage generated in the parasitic inductance to flow. Therefore, by suppressing the clamp current from flowing during the ON operation of the switching element, it is possible to prevent excessive voltage from being applied between the control terminal and the low potential side main terminal. Thereby, the switching element can be appropriately protected.

The drive reference potential terminal of the drive circuit is connected via a first wiring to a control reference potential terminal provided on the low potential side of the switching element separately from the low potential side main terminal of the switching element, and includes a bypass circuit connected in parallel to a low potential side wiring connecting between the low potential side main terminal and the control reference potential terminal, and the bypass circuit is a bypass circuit for current to flow through the bypass circuit. The circuit operating voltage may be configured to be within a range of a surge suppression operating voltage set by the capacitor voltage setting circuit.

According to the above configuration, when the clamp current flowing in the surge suppression circuit increases and the voltage applied between the low potential side main terminal and the control terminal becomes larger than the bypass circuit operating voltage due to the clamp current, the bypass circuit Current flows and clamp current is suppressed. Therefore, it is possible to prevent excessive voltage from being applied between the control terminal and the low potential side main terminal, and the switching element can be appropriately protected.

The capacitor voltage setting circuit sets the voltage applied to the capacitor so that the voltage applied to the capacitor becomes a predetermined voltage higher when the switching element is turned on than when the switching element is turned off. Good too.

The capacitor voltage setting circuit may be configured such that the drive circuit applies the predetermined voltage to the capacitor based on the drive signal for turning on the switching element.

According to the above configuration, since the voltage applied to the capacitor is switched based on the drive signal, there is no need to generate a new signal, and a reliable voltage switching operation can be realized.

The capacitor voltage setting circuit includes a Zener diode connected in parallel to the capacitor, the Zener diode has a cathode connected to the low potential main terminal side of the capacitor, and an anode connected to the control reference potential terminal of the capacitor. May be connected to the side.

According to the above configuration, the surge suppression operating voltage is set as the breakdown voltage of the Zener diode. When the voltage generated by the parasitic inductance exceeds the surge suppression operating voltage, a clamping current flows through the surge suppression circuit. When a clamp current flows through the surge suppression circuit, the capacitor is charged, and the operating voltage (surge suppression operating voltage) of the surge suppression circuit increases. By increasing the surge suppression operating voltage, it becomes difficult for the clamp current to flow, and it is possible to suppress excessive clamp current from flowing through the surge suppression circuit. When the clamp current stops flowing, the charge stored in the capacitor is discharged through the path of the Zener diode, and the surge suppression operating voltage returns to its original state (breakdown voltage of the Zener diode). Therefore, it is possible to realize a capacitor voltage setting circuit that passively generates and resets the voltage of the capacitor without separately generating a control signal to determine the voltage to be applied to the capacitor.

The capacitor voltage setting circuit adjusts the surge suppression operating voltage by a current flowing from the low potential side main terminal to the drive reference potential terminal while the drive circuit outputs the drive signal that turns on the switching element. The capacitor may be charged until the predetermined voltage reaches the predetermined voltage, which is higher than the bypass circuit operating voltage.

According to the above configuration, since the capacitor is charged using the clamp current flowing through the surge suppression circuit, the operating voltage of the surge suppression circuit increases. When the surge suppression operating voltage increases and becomes higher than the bypass circuit operating voltage, current flows through the bypass circuit and the clamp current is suppressed. This prevents excessive current from flowing through the surge suppression circuit. Therefore, it is possible to prevent excessive voltage from being applied between the terminals of the switching element, and the switching element can be appropriately protected.

A switching circuit according to another aspect of the present disclosure includes: a switching element having a pair of main terminals and a control terminal; a drive circuit that drives the switching element by applying a drive voltage to the control terminal; a surge suppression circuit that suppresses a surge voltage from occurring between the main terminals of the switching element, the drive circuit having a drive signal output terminal and a drive reference potential terminal, and the drive signal output terminal being the main terminal of the switching element. connected to the control terminal, the drive reference potential terminal is connected via a first wiring to a control reference potential terminal provided on the low potential side of the switching element separately from the low potential side main terminal of the switching element; The surge suppression circuit includes a resistance element provided on the first wiring, a first diode and a first diode provided in series on a second wiring connecting the drive reference potential terminal and the low potential side main terminal. 1 Zener diode, and a bypass circuit connected in parallel to surge suppression wiring including the first wiring and the second wiring between the low potential side main terminal and the control reference potential terminal, The first diode has a cathode connected to the driving reference potential terminal side and an anode connected to the low potential main terminal side, and the first Zener diode has a cathode connected to the low potential main terminal side, An anode is connected to the control reference potential terminal side, and the bypass circuit is configured such that a bypass circuit operating voltage for allowing a current to flow through the bypass circuit is connected to the resistance element on the surge suppression wiring, the first diode, and the first diode. The voltage is configured to be higher than the surge suppression operating voltage for current to flow through the Zener diode.

According to the above configuration, during off-operation, the drive voltage applied to the control terminal of the switching element decreases, the current flowing between the main terminals of the switching element decreases, and an excessive voltage (surge voltage) occurs between the main terminals. When this occurs, the current flowing through the parasitic inductance of the low-potential side main terminal suddenly decreases, and an induced voltage is generated by the parasitic inductance.In the surge suppression circuit, a current (clamp current) flows from the low-potential side main terminal toward the drive reference potential terminal. ) flows. As a result, a voltage is generated in the resistance element provided on the first wiring, and the current flowing from the drive reference potential terminal to the control reference potential terminal of the switching element becomes small. Therefore, the switching speed (turn-off speed) of the switching element becomes slow, and surge voltage is suppressed. At this time, the induced voltage generated by the parasitic inductance is a low voltage, and the surge suppression circuit can be operated at a low operating voltage, so that losses due to suppression of the surge voltage can be reduced. Additionally, when the clamp current flowing through the surge suppression circuit increases and the voltage applied between the low potential side main terminal and the control reference potential terminal becomes larger than the bypass circuit operating voltage, the current flows through the bypass circuit. current, and the clamp current is suppressed. Therefore, it is possible to prevent excessive voltage from being applied between the control terminal and the control reference potential terminal, and the switching element can be appropriately protected.

A switching circuit according to another aspect of the present disclosure includes: a switching element having a pair of main terminals and a control terminal; a drive circuit that drives the switching element by applying a drive voltage to the control terminal; a surge suppression circuit that suppresses a surge voltage from occurring between the main terminals of the switching element, the drive circuit having a drive signal output terminal and a drive reference potential terminal, and the drive signal output terminal being the main terminal of the switching element. connected to the control terminal, the drive reference potential terminal is connected via a first wiring to a control reference potential terminal provided on the low potential side of the switching element separately from the low potential side main terminal of the switching element; The surge suppression circuit includes a first diode and a first Zener diode provided in series on a second wiring connecting the control terminal and the low potential side main terminal, and the low potential side main terminal and the control reference. a bypass circuit connected in parallel to a low potential side wiring connecting between the potential terminal and the first diode, the first diode has a cathode connected to the control terminal side, and an anode connected to the low potential main terminal side. The first Zener diode has a cathode connected to the low potential main terminal side, an anode connected to the control terminal side, and the bypass circuit is a bypass circuit for allowing current to flow through the bypass circuit. The operating voltage is configured to be higher than a surge suppression operating voltage for allowing current to flow through the first diode and the first Zener diode on the second wiring.

According to the above configuration, when the drive voltage applied to the control terminal of the switching element decreases, the current flowing between the main terminals of the switching element decreases, and an excessive voltage (surge voltage) occurs between the main terminals, the voltage decreases. As the current flowing through the parasitic inductance of the main terminal on the potential side suddenly decreases, an induced voltage is generated due to the parasitic inductance, and a current (clamp current) flows from the main terminal on the low potential side toward the control terminal in the surge suppression wiring of the surge suppression circuit. . The clamp current flowing through the control terminal of the switching element slows down the switching speed of the switching element, suppressing surge voltage. At this time, since the voltage generated by the current flowing through the parasitic inductance due to the surge voltage is a low voltage, it is possible to reduce the loss that occurs when suppressing the surge voltage. Additionally, when the clamp current flowing through the surge suppression circuit increases and the voltage applied between the low-potential side main terminal and the control terminal becomes larger than the bypass circuit operating voltage, current flows through the bypass circuit. Clamp current is suppressed. Therefore, it is possible to prevent excessive voltage from being applied between the control terminal and the low potential side main terminal, and the switching element can be appropriately protected.

The bypass circuit is configured such that a second diode and a second Zener diode are connected in series, and the second diode has a cathode connected to the control reference potential terminal side and an anode connected to the low potential side main terminal. The second Zener diode may have a cathode connected to the low potential main terminal side and an anode connected to the control reference potential terminal side.

According to the configuration of the present disclosure, surge voltage can be suppressed with low loss, and switching elements can be more appropriately protected.

FIG. 1 is a diagram showing a schematic configuration of a switching circuit according to Embodiment 1 of the present disclosure. FIG. 2 is a diagram showing a case where an example of a capacitor voltage setting circuit is applied to the switching circuit shown in FIG. 1. FIG. 3 is a diagram showing a case where another example of the capacitor voltage setting circuit is applied to the switching circuit shown in FIG. 1. FIG. 4 is a diagram showing a schematic configuration of a switching circuit according to Embodiment 2 of the present disclosure. FIG. 5 is a circuit diagram showing a specific example of the bypass circuit shown in FIG. 4. FIG. 6 is a diagram showing a schematic configuration of a switching circuit according to Embodiment 3 of the present disclosure. FIG. 7 is a diagram showing a schematic configuration of a switching circuit according to Embodiment 4 of the present disclosure. FIG. 8 is a diagram showing a schematic configuration of a switching circuit according to Embodiment 5 of the present disclosure. FIG. 9 is a diagram showing a schematic configuration of a switching circuit according to Embodiment 6 of the present disclosure. FIG. 10 is a graph showing the simulation results of the surge suppression operation in the switching circuit of the first embodiment. FIG. 11 is a graph showing a simulation result in which the bypass circuit functions during the off-operation in the switching circuit of the second embodiment and false call calls are suppressed. FIG. 12 is a graph showing simulation results during on-operation in the switching circuit of the second embodiment.

Embodiments of the present invention will be described below with reference to the drawings. Note that, hereinafter, elements that are the same or have the same functions are designated by the same reference numerals throughout all the figures, and redundant explanation thereof will be omitted.

(Embodiment 1)
FIG. 1 is a diagram showing a schematic configuration of a switching circuit 1A according to Embodiment 1 of the present disclosure. The switching circuit 1A in this embodiment includes at least one switching element 2. The switching element 2 includes a pair of main terminals (a high potential side main terminal T1 and a low potential side main terminal T2) and a control terminal T3.

Further, the switching element 2 includes a control reference potential terminal T4 provided on the low potential side of the switching element 2, separately from the low potential side main terminal T2. The control reference potential terminal T4 is provided to set a reference potential of the drive circuit 3, which will be described later. For example, the switching element 2 is constituted by an n-type MOSFET having a four-terminal structure. The control reference potential terminal T4 is located closer to the FET chip on the low potential side of the switching element 2 than the low potential side main terminal T2. By providing the control reference potential terminal T4 separately from the low potential side main terminal T2 to which the load is connected, the influence on the drive signal (drive voltage) in the drive circuit 3 can be reduced. In addition, in FIG. 1, a virtual coil 2a is illustrated in order to represent the parasitic inductance Lp that occurs in the wiring between the control reference potential terminal T4 and the low potential side main terminal T2.

Furthermore, the switching circuit 1A includes a drive circuit 3 that drives the switching element 2 by applying a drive voltage Vd to the control terminal T3. The drive circuit 3 has a drive signal output terminal T5 and a drive reference potential terminal T6. The drive signal output terminal T5 is connected to the control terminal T3 of the switching element 2. The drive reference potential terminal T6 is connected to the control reference potential terminal T4 of the switching element 2 via a first wiring W1, which will be described later.

The drive circuit 3 outputs a drive signal having a potential higher than the potential of the drive reference potential terminal T6 by the drive voltage Vd of the switching element 2 to the drive signal output terminal T5. When the drive signal causes the control voltage Vg applied between the control terminal T3 and the control reference potential terminal T4 of the switching element 2 to reach a predetermined on-voltage, the switching element 2 is turned on. Further, when the drive voltage Vd applied between the drive signal output terminal T5 and the drive reference potential terminal T6 becomes low and the control voltage Vg becomes a predetermined off voltage lower than the on voltage, the switching element 2 turns off. do.

During off-operation, when the current between the main terminals T1 and T2 (switch current Ia) decreases due to a decrease in the control voltage Vg due to a decrease in the drive voltage Vd, a transient current occurs between the main terminals T1 and T2 of the switching element 2. An excessive voltage (surge voltage Vs) may occur. If the voltage Va across the switch including the surge voltage Vs exceeds the withstand voltage of the switching element 2, the switching element 2 will be damaged. On the other hand, high frequency switching in the switching circuit 1A is effective in reducing the size and weight of a power conversion circuit in which such a switching circuit 1A is used. Therefore, the switching circuit 1A is required to perform high-speed switching operation in order to perform high-frequency switching. As a result, a situation arises in which a high surge voltage Vs is likely to occur.

In order to suppress generation of such a surge voltage Vs between the pair of main terminals T1 and T2, the switching circuit 1A includes a surge suppression circuit 4A as a protection circuit for the switching element 2. The surge suppression circuit 4A includes a resistance element 5, a diode (first diode) 6, a capacitor 7, and a capacitor voltage setting circuit 8.

The resistance element 5 is provided on the first wiring W1. That is, the first end of the resistance element 5 is connected to the control reference potential terminal T4 of the switching element 2, and the second end of the resistance element 5 is connected to the drive reference potential terminal T6 of the drive circuit 3.

The diode 6 and the capacitor 7 are provided in series on the second wiring W2 that connects the drive reference potential terminal T6 of the drive circuit 3 and the low potential side main terminal T2 of the switching element 2. The diode 6 has a cathode connected to the drive reference potential terminal T6 side, and an anode connected to the low potential side main terminal T2 side. The capacitor 7 is configured to be chargeable by a current flowing from the low potential side main terminal T2 to the drive reference potential terminal T6.

In the example of FIG. 1, a capacitor 7 is connected to the cathode side of the diode 6. That is, the low potential side main terminal T2 is connected to the anode of the diode 6, one end (high potential side) of the capacitor 7 is connected to the cathode of the diode 6, and the other end (low potential side) of the capacitor 7 is the drive reference. It is connected to potential terminal T6.

The off-operation of the switching circuit 1A in this embodiment will be explained below. In order to lower the control voltage Vg applied to the control terminal T3 of the switching element 2 to below the threshold voltage at which the switching element 2 is turned off, the drive circuit 3 lowers the drive voltage Vd, and the control voltage Vg is applied from the drive reference potential terminal T6. A current (discharge current) Id flows toward the reference potential terminal T4. When the control voltage Vg applied to the control terminal T3 of the switching element 2 decreases, the switch current Ia flowing between the main terminals T1 and T2 of the switching element 2 decreases, causing excessive voltage (surge voltage) between the main terminals T1 and T2. Vs) may occur. At this time, the current flowing through the virtual coil 2a (parasitic inductance Lp) of the low-potential side main terminal T2 suddenly decreases, so that an induced voltage V _L is generated due to the parasitic inductance Lp, and the induced voltage V _L is caused by the surge suppression circuit 4A. When the surge suppression operating voltage Vo is higher than the surge suppression operating voltage Vo, a current (clamp current) Icp flows from the low potential side main terminal T2 to the drive reference potential terminal T6 in the surge suppression circuit 4A. As a result, a voltage (resistance voltage V _R ) is generated in the resistance element 5 provided on the first wiring W1, and the discharge current Id flowing from the drive reference potential terminal T6 to the control reference potential terminal T4 of the switching element 2 becomes smaller. .

Therefore, the speed of discharge in the drive circuit 3 becomes slow. That is, the switching speed (turn-off speed) of the switching element 2 becomes slow, and the surge voltage Vs is suppressed. At this time, the induced voltage _VL generated by the parasitic inductance Lp is a low voltage, and the surge suppression circuit 4A can be operated at a low operating voltage, so that losses due to suppression of the surge voltage Vs can be reduced.

Here, the capacitor voltage setting circuit 8 is configured to set the voltage applied to the capacitor 7. The capacitor voltage setting circuit 8 actively or passively changes the voltage applied to the capacitor 7 to set a surge suppression operating voltage Vo for current to flow through the surge suppression circuit 4A. More specifically, the capacitor voltage setting circuit 8 sets the voltage applied to the capacitor 7 to a predetermined voltage V _C2 when the switching element 2 is in the ON operation, which is higher than the voltage V _C1 when the switching element 2 is in the OFF operation. , sets the voltage applied to the capacitor 7.

When the switching element 2 is turned on, an oscillatory current flows through the parasitic inductance Lp, and an induced voltage _VL is generated, and when the induced voltage _VL becomes equal to or higher than the surge suppression operating voltage Vo of the surge suppression circuit 4A, A clamp current Icp may flow through the surge suppression circuit 4A. When the clamp current Icp flows through the surge suppression circuit 4A during the ON operation, the control voltage Vg may become excessive.

Therefore, during the ON operation, the capacitor voltage setting circuit 8 increases the voltage applied to the capacitor 7. As the voltage applied to the capacitor 7 increases, the surge suppression operating voltage Vo, which is the sum of the voltage applied to the capacitor 7 and the voltage applied to the diode 6, increases. When the surge suppression operating voltage during OFF operation is Vo1 and the surge suppression operating voltage during ON operation is Vo2, Vo2>Vo1. As a result, the resistance voltage V _R generated in the resistance element 5 due to the induced voltage V _L becomes smaller.

Therefore, when the switching element 2 is turned on, where the voltage applied to the capacitor 7 is high, the resistance voltage _VR generated in the resistance element 5 becomes small, and the clamp current Icp becomes difficult to flow through the surge suppression circuit 4A. Therefore, by suppressing the clamp current Icp from flowing during the ON operation of the switching element 2, it is possible to prevent excessive voltage from being applied between the control terminal T3 and the control reference potential terminal T4. Thereby, the switching element 2 can be appropriately protected.

Note that the capacitor voltage setting circuit 8 sets the voltage applied to the capacitor 7 so that the voltage applied to the capacitor 7 becomes a predetermined voltage V _C2 which is higher than the voltage V _C1 when the switching element 2 is turned off when the switching element 2 is turned on. There is no particular limitation as long as the applied voltage can be set.

FIG. 2 is a diagram showing an example of a capacitor voltage setting circuit applied to the switching circuit 1A shown in FIG. In the example of FIG. 2, the capacitor voltage setting circuit is designated by 8a. In the example of FIG. 2, the capacitor voltage setting circuit 8a has the same configuration as the drive circuit 3. Capacitor voltage setting circuit 8a has a drive signal output terminal T7 and a drive reference potential terminal T8. The drive signal output terminal T7 is connected to the high potential side terminal of the capacitor 7, and the drive reference potential terminal T8 is connected to the low potential side terminal of the capacitor 7.

A drive signal is output from the drive signal output terminal T7 of the capacitor voltage setting circuit 8a at the same timing as the drive signal output from the drive signal output terminal T5 of the drive circuit 3. That is, while the on-voltage is applied as the control voltage Vg to the switching element 2 based on the drive voltage Vd output from the drive circuit 3, the drive signal output terminal T7 has a potential higher by a predetermined voltage than the potential of the drive reference potential terminal T8. outputs a drive signal having the following values. The voltage of the drive signal output by the capacitor voltage setting circuit 8a may be the same as or different from the drive voltage Vd output by the drive circuit 3.

In this way, the capacitor voltage setting circuit 8a is configured to apply a predetermined voltage to the capacitor 7 based on the drive signal for the drive circuit 3 to turn on the switching element 2. That is, since the voltage applied to the capacitor 7 is switched based on the drive signal of the switching element 2, there is no need to generate a new signal, and a reliable voltage switching operation can be realized.

FIG. 3 is a diagram showing a case where another example of the capacitor voltage setting circuit is applied to the switching circuit 1A shown in FIG. 1. In the example of FIG. 3, the capacitor voltage setting circuit is designated by 8b. In the example of FIG. 3, capacitor voltage setting circuit 8b includes a Zener diode 13 connected in parallel to capacitor 7.

The Zener diode 13 has a cathode connected to the low potential main terminal T2 side of the capacitor 7 (in the example of FIG. 3, between the capacitor 7 and the diode 6), and an anode connected to the control reference potential terminal T4 side of the capacitor 7. Ru. Furthermore, in the example of FIG. 3, a resistance element 14 is connected in series to the Zener diode 13.

According to the above configuration, the surge suppression operating voltage Vo is set as the breakdown voltage Vz3 of the Zener diode 13. When the induced voltage _VL generated by the parasitic inductance Lp exceeds the surge suppression operating voltage Vo during ON or OFF operation, a clamp current Icp flows through the surge suppression circuit 4A.

When the clamp current Icp flows through the surge suppression circuit 4A, the capacitor 7 is charged, and the operating voltage (surge suppression operating voltage) Vo of the surge suppression circuit 4A increases. By increasing the surge suppression operating voltage Vo, it becomes difficult for the clamp current Icp to flow, and it is possible to suppress excessive clamp current Icp from flowing through the surge suppression circuit 4A.

When the ON or OFF operation is completed and the clamp current Icp stops flowing, the charge charged in the capacitor 7 is discharged through the path of the Zener diode 13, and the surge suppression operating voltage Vo returns to its original state (breakdown voltage of the Zener diode 13). Vz3). Therefore, the capacitor voltage setting circuit 8b that passively generates and resets the voltage of the capacitor 7 can be realized without separately generating a control signal to determine the voltage applied to the capacitor 7.

When the switching element 2 is turned off, when the clamp current Icp flowing through the surge suppression wiring of the surge suppression circuit 4A increases, the resistance voltage _VR generated in the resistance element 5 increases, and the voltage between the control terminal T3 and the control reference potential terminal T4 increases. The control voltage Vg applied during this period increases. If the control voltage Vg becomes excessively large, there is a risk that the switching element 2 will turn on (erroneous roll call).

Regarding this problem, if the capacitor voltage setting circuit 8b shown in FIG. It is possible to suppress the voltage between them from becoming excessive, and it is possible to prevent erroneous roll calls.

(Embodiment 2)
Next, a second embodiment of the present disclosure will be described. FIG. 4 is a diagram showing a schematic configuration of a switching circuit 1B according to Embodiment 2 of the present disclosure. In this embodiment, the same components as in Embodiment 1 are designated by the same reference numerals, and the description thereof will be omitted.

The difference between the switching circuit 1B in the present embodiment and the switching circuit 1A in the first embodiment is that the surge suppression circuit 4B, which is a protection circuit, is connected between the low potential side main terminal T2 and the control reference potential terminal T4. It is equipped with a bypass circuit 9. The bypass circuit 9 is connected in parallel to surge suppression wiring including the first wiring W1 and the second wiring W2. The surge suppression wiring is provided with a diode 6, a capacitor 7, and a resistance element 5 between the low potential side main terminal T2 and the control reference potential terminal T4.

The bypass circuit 9 is configured such that the bypass circuit operating voltage Vp for current to flow through the bypass circuit 9 is within the range (variation range) of the surge suppression operating voltage Vo set by the capacitor voltage setting circuit 8. . In the present embodiment, the relationship between the surge suppression operating voltage Vo1 during OFF operation, the surge suppression operating voltage Vo2 during ON operation, and the bypass circuit operating voltage Vp is Vo1<Vp<Vo2.

As described above, when the clamp current Icp flowing through the surge suppression wiring of the surge suppression circuit 4B increases, the control voltage Vg applied between the control terminal T3 and the control reference potential terminal T4 increases. If the control voltage Vg becomes excessively large, there is a risk that the switching element 2 will turn on (erroneous roll call).

Therefore, in this embodiment, the switching circuit 1B is configured to allow current to flow through the bypass circuit 9 when the clamp current Icp increases. That is, according to the above configuration, the clamp current Icp flowing through the surge suppression circuit 4B increases, and the control voltage Vg applied between the low potential side main terminal T2 and the control reference potential terminal T4 increases with the clamp current Icp. When it becomes higher than the bypass circuit operating voltage Vp, a current (bypass current Ib) flows through the bypass circuit 9, and the clamp current Icp flowing through the surge suppression wiring is suppressed. Therefore, it is possible to prevent an excessive voltage from being applied between the control terminal T3 and the control reference potential terminal T4, thereby preventing the switching element 2 from performing an erroneous roll call.

Furthermore, by providing the bypass circuit 9, even if an excessive voltage is applied between the low potential side main terminal T2 and the control reference potential terminal T4 during ON operation, the bypass current Ib flows through the bypass circuit 9. Therefore, it is possible to suppress the clamp current Icp from flowing during the ON operation of the switching element 2, and it is possible to prevent excessive voltage from being applied between the control terminal T3 and the control reference potential terminal T4. .

The bypass circuit 9 is not particularly limited as long as it has a configuration that causes the bypass current Ib to flow between the low potential side main terminal T2 and the control reference potential terminal T4 when a voltage equal to or higher than the predetermined bypass circuit operating voltage Vp is applied. FIG. 5 is a circuit diagram showing a specific example of the bypass circuit 9 shown in FIG. 4. For example, the bypass circuit 9 is configured such that a diode (second diode) 11 and a Zener diode 12 are connected in series.

The diode 11 has a cathode connected to the control reference potential terminal T4 side, and an anode connected to the low potential side main terminal T2 side. The Zener diode 12 has a cathode connected to the low potential side main terminal T2 side, and an anode connected to the control reference potential terminal T4 side. In the bypass circuit 9 shown in the example of FIG. 5, the voltage obtained by adding the breakdown voltage Vz2 of the Zener diode 12 and the forward voltage drop of the diode 11 becomes the bypass circuit operating voltage Vp. In the example of FIG. 5, the cathode of the diode 11 is connected to the cathode of the Zener diode 12, but the anodes of both elements 11 and 12 may be connected to each other.

Furthermore, in this embodiment, when the capacitor voltage setting circuit 8b shown in FIG. A current flowing from the low potential side main terminal T2 of the element 2 to the drive reference potential terminal T6 of the drive circuit 3 charges the capacitor 7 until the surge suppression operating voltage Vo reaches a predetermined voltage higher than the bypass circuit operating voltage Vp. may be configured.

As a result, the capacitor 7 is charged using the clamp current Icp flowing through the surge suppression circuit 4B, so that the surge suppression operating voltage Vo of the surge suppression circuit 4B increases. When the surge suppression operating voltage Vo rises and becomes larger than the bypass circuit operating voltage Vp, the bypass current Ib flows through the bypass circuit 9, and the clamp current Icp is suppressed. This prevents excessive current from flowing through the surge suppression circuit 4B. Therefore, it is possible to prevent excessive voltage from being applied between the main terminals T1 and T2 of the switching element 2, and the switching element 2 can be appropriately protected.

(Embodiment 3)
Next, a third embodiment of the present disclosure will be described. FIG. 6 is a diagram showing a schematic configuration of a switching circuit 1C according to Embodiment 3 of the present disclosure. In this embodiment, the same components as in Embodiment 2 are denoted by the same reference numerals, and the description thereof will be omitted.

The difference between the switching circuit 1C in this embodiment and the switching circuit 1B in the second embodiment is that a Zener diode (the first The surge suppression circuit 4C is provided with a Zener diode (zener diode) 10.

That is, the surge suppression circuit 4C includes a resistance element 5 provided on the first wiring W1, a first diode 6 and a first Zener diode 10 provided in series on the second wiring W2, and a low potential side main terminal. A bypass circuit 9 is provided between T2 and the control reference potential terminal T4, which is connected in parallel to the surge suppression wiring including the first wiring W1 and the second wiring W2. The first diode 6 has a cathode connected to the drive reference potential terminal T6 side, and an anode connected to the low potential side main terminal T2 side. The first Zener diode 10 has a cathode connected to the low potential side main terminal T2, and an anode connected to the control reference potential terminal T4.

In the present embodiment, the bypass circuit 9 has a bypass circuit operating voltage Vp that allows current to flow through the bypass circuit 9, and a current that flows through the resistive element 5, the first diode 6, and the first Zener diode 10 on the surge suppression wiring. It is configured to be larger than the surge suppression operating voltage Vo for flowing.

In this embodiment, as in the first embodiment, when the induced voltage _VL generated by the parasitic inductance Lp becomes equal to or higher than the surge suppression operating voltage Vo of the surge suppression circuit 4C, the clamp current Icp is applied to the surge suppression circuit 4C. flows. As a result, a resistance voltage V _R is generated in the resistance element 5 provided on the first wiring W1, and the discharge current Id flowing from the drive reference potential terminal T6 to the control reference potential terminal T4 of the switching element 2 becomes small. Therefore, the switching speed in the switching element 2 is slowed down, and the surge voltage Vs is suppressed.

Furthermore, as in the second embodiment, the clamp current Icp flowing through the surge suppression circuit 4C increases, and the voltage applied between the low potential side main terminal T2 and the control reference potential terminal T4 increases with the clamp current Icp. When it becomes higher than the bypass circuit operating voltage Vp, the bypass current Ib flows through the bypass circuit 9, and the clamp current Icp is suppressed. Therefore, it is possible to prevent excessive voltage from being applied between the control terminal T3 and the control reference potential terminal T4, and the switching element 2 can be appropriately protected.

(Embodiment 4)
Next, a fourth embodiment of the present disclosure will be described. FIG. 7 is a diagram showing a schematic configuration of switching circuit 1D according to Embodiment 4 of the present disclosure. In this embodiment, the same components as in Embodiment 1 are designated by the same reference numerals, and the description thereof will be omitted.

The difference between the switching circuit 1D in this embodiment and the switching circuit 1A in the first embodiment is that, as a protection circuit, a diode 6 and a capacitor 7 in the surge suppression circuit 4A connect the control terminal T3 and the low potential side main terminal T2. A surge suppression circuit 4D is provided in series on the surge suppression wiring W3.

That is, the diode 6 has a cathode connected to the control terminal T3 side, and an anode connected to the low potential side main terminal T2 side. Further, the capacitor 7 is configured to be chargeable by a current flowing from the low potential side main terminal T2 to the control terminal T3.

In this embodiment, when the control voltage Vg applied to the control terminal T3 of the switching element 2 decreases as the switch drive voltage Vd decreases, the switch current Ia flowing between the main terminals T1 and T2 of the switching element 2 decreases. However, an excessive voltage (surge voltage Vs) may occur between the main terminals T1 and T2. At this time, the current flowing through the parasitic inductance Lp of the low-potential side main terminal T2 suddenly decreases, so an induced voltage V _L is generated by the parasitic inductance Lp, and the induced voltage V _L exceeds the surge suppression operating voltage Vo of the surge suppression circuit 4D. In this case, a current (clamp current Icp) flows from the low potential side main terminal T2 to the control terminal T3 in the surge suppression wiring W3 of the surge suppression circuit 4D. As a result, the current flowing through the control terminal T3 of the switching element 2 slows down the switching speed of the switching element 2, and suppresses the surge voltage Vs. At this time, since the induced voltage _VL generated by the current flowing through the parasitic inductance Lp due to the surge voltage Vs is a low voltage, it is possible to reduce the loss that occurs when suppressing the surge voltage Vs.

Furthermore, as in the first embodiment, capacitor voltage setting circuit 8 increases the voltage applied to capacitor 7 during on-operation. When the voltage applied to the capacitor 7 becomes higher, the clamp current Icp generated by the voltage generated in the parasitic inductance Lp becomes difficult to flow. Therefore, by suppressing the clamp current Icp from flowing during the ON operation of the switching element 2, it is possible to prevent excessive voltage from being applied between the control terminal T3 and the low potential side main terminal T2. . Thereby, the switching element 2 can be appropriately protected.

Note that as the capacitor voltage setting circuit 8 in this embodiment, either of the capacitor voltage setting circuits 8a and 8b described in Embodiment 1 (FIGS. 2 and 3) can be adopted.

(Embodiment 5)
Next, Embodiment 5 of the present disclosure will be described. FIG. 8 is a diagram showing a schematic configuration of a switching circuit 1E according to Embodiment 5 of the present disclosure. In this embodiment, the same components as in Embodiment 4 are designated by the same reference numerals, and the description thereof will be omitted.

The difference between the switching circuit 1E in this embodiment and the switching circuit 1D in the fourth embodiment is that a surge suppression circuit 4E, which is a protection circuit, is connected between the low potential side main terminal T2 and the control reference potential terminal T4. It is equipped with a bypass circuit 9. The bypass circuit 9 is connected in parallel to a low potential side wiring W4 that connects between the low potential side main terminal T2 and the control reference potential terminal T4. The configuration of bypass circuit 9 is similar to that of the second embodiment.

In this embodiment, the clamp current Icp flowing through the surge suppression circuit 4E increases, and the voltage applied between the low potential side main terminal T2 and the control terminal T3 becomes lower than the bypass circuit operating voltage Vp due to the clamp current Icp. When it becomes large, a current (bypass current Ib) flows through the bypass circuit 9, and the clamp current Icp is suppressed. Therefore, it is possible to prevent excessive voltage from being applied between the control terminal T3 and the low potential side main terminal T2, and the switching element 2 can be appropriately protected.

(Embodiment 6)
Next, a sixth embodiment of the present disclosure will be described. FIG. 9 is a diagram showing a schematic configuration of a switching circuit 1F according to Embodiment 6 of the present disclosure. In this embodiment, the same components as in Embodiment 5 are denoted by the same reference numerals, and the description thereof will be omitted.

The difference between the switching circuit 1F in this embodiment and the switching circuit 1E in the fifth embodiment is that, as a protection circuit, a Zener diode (first The surge suppression circuit 4F is provided with a Zener diode (zener diode) 10.

That is, the surge suppression circuit 4F maintains a low potential between the first diode 6 and the first Zener diode 10 provided in series on the surge suppression wiring W3, the low potential side main terminal T2, and the control reference potential terminal T4. A bypass circuit 9 is connected in parallel to the side wiring W4. The first diode 6 has a cathode connected to the drive reference potential terminal T6 side, and an anode connected to the low potential side main terminal T2 side. The first Zener diode 10 has a cathode connected to the low potential side main terminal T2, and an anode connected to the control reference potential terminal T4.

In the present embodiment, the bypass circuit 9 has a bypass circuit operating voltage Vp that allows current to flow through the bypass circuit 9, and a current that flows through the resistive element 5, the first diode 6, and the first Zener diode 10 on the surge suppression wiring. It is configured to be larger than the surge suppression operating voltage Vo for flowing.

In this embodiment, as in the fourth embodiment, when the induced voltage _VL generated by the parasitic inductance Lp becomes equal to or higher than the surge suppression operating voltage Vo of the surge suppression circuit 4F, the clamp current Icp is applied to the surge suppression circuit 4F. flows. As a result, the current flowing through the control terminal T3 of the switching element 2 slows down the switching speed of the switching element 2, and suppresses the surge voltage Vs.

Further, as in the fifth embodiment, the clamp current Icp flowing through the surge suppression circuit 4F increases, and the voltage applied between the low potential side main terminal T2 and the control terminal T3 increases with the clamp current Icp to the bypass circuit. When it becomes higher than the operating voltage Vp, a bypass current Ib flows through the bypass circuit 9, and the clamp current Icp is suppressed. Therefore, it is possible to prevent excessive voltage from being applied between the control terminal T3 and the low potential side main terminal T2, and the switching element 2 can be appropriately protected.

[simulation result]
FIG. 10 is a graph showing the simulation results of the surge suppression operation in the protection circuit of the first embodiment. The graph shown in FIG. 10 is a graph showing, from top to bottom, temporal changes in induced voltage V _L caused by parasitic inductance Lp, clamp current Icp, resistance voltage V _R , discharge current Id, and voltage Va across the switch during off-operation. be.

As shown in the graph of the discharge current Id in FIG. 10, when the off-operation is started, the discharge current Id accompanying the discharge of the drive voltage in the drive circuit 3 is controlled from the drive reference potential terminal T6 on the first wiring W1. It flows toward the reference potential terminal T4. This discharge current Id gradually decreases over time because the drive voltage drops with discharge.

When this discharge current Id flows through the resistance element 5, a resistance voltage _VR is generated in the resistance element 5. As shown in the graph of the resistance voltage _VR in FIG. 10, the resistance voltage _VR also gradually decreases over time as the discharge current Id decreases.

On the other hand, as shown in the graph of the voltage Va across the switch in FIG. 10, as the switching element 2 turns off, a surge voltage Vs is generated between the main terminals T1 and T2. In particular, in the graph of FIG. 10, relatively large voltages are generated at time t1 and time t2. As the switch current Ia changes during turn-off, an induced voltage V _L is generated due to the parasitic inductance Lp, as shown in the graph of the induced voltage V _L in FIG. 10 .

As shown in the graph of the clamp current Icp in FIG. 10, the induced voltage _VL generated with the generation of the surge voltage Vs at times t1 and t2 becomes equal to or higher than the surge suppression operating voltage Vo of the surge suppression circuit 4A, so that the clamp current Icp is occurring. This clamp current Icp temporarily raises the resistance voltage _VR at times t1 and t2. As a result, the discharge of the drive circuit 3 is suppressed, and the discharge current Id becomes small.

By suppressing the discharge of the drive circuit 3, the switching speed (turn-off speed) in the switching element 2 is slowed down, and subsequent generation of the surge voltage Vs is suppressed. The example in the graph of the voltage Va across the switch in FIG. 10 shows the switching circuit 1A of the first embodiment equipped with the surge suppression circuit 4A, and the comparative example shows the voltage across the switch in a switching circuit not equipped with the surge suppression circuit 4A. It shows Va. A comparison between the example and the comparative example in this graph shows that the provision of the surge suppression circuit 4A in the switching element 2 suppresses the generation of the surge voltage Vs.

FIG. 11 is a graph showing simulation results in which the bypass circuit 9 functions during the off-operation in the switching circuit 1B of the second embodiment, and erroneous call calls are suppressed. The graph shown in FIG. 11 is a graph showing, from top to bottom, temporal changes in switch drive voltage Vd, switch current Ia, induced voltage V _L , clamp current Icp, bypass current Ib, and switch voltage Va during off-operation. .

As shown in the graph of the switch drive voltage Vd in FIG. 11, the drive voltage Vd decreases over time due to the start of the off-operation. As drive voltage Vd decreases, switch current Ia also decreases. Corresponding to these, the voltage Va across the switch rapidly increases. At this time, a surge voltage Vs may occur between the main terminals T1 and T2. For example, in a conventional surge suppression circuit configured with a capacitor and a Zener diode as in Patent Document 1, there is no bypass circuit 9 as in Embodiment 2, so an erroneous call occurs during off-operation. As shown in the broken line waveform (waveform of the comparative example) in the graph of the voltage Va across the switch in No. 11, the waveform of the voltage Va across the switch may be oscillatory.

In contrast, in the present embodiment, when the induced voltage VL generated by the parasitic inductance Lp due to the generation of the surge voltage _Vs becomes equal to or higher than the surge suppression operating voltage Vo (the surge suppression operating voltage Vo1 during off-operation), As shown in the graph of clamp current Icp in FIG. 11, clamp current Icp flows through the surge suppression circuit 4B. As a result, the turn-off speed of the switching element 2 is slowed down, and the surge voltage Vs is suppressed, as shown by the solid line waveform (waveform of the example) in the graph of the voltage Va across the switch in FIG.

Furthermore, as shown in the graph of the bypass current Ib in FIG. 11, when the induced voltage _VL exceeds the bypass circuit operating voltage Vp at, for example, time t3, the bypass current Ib flows through the bypass circuit 9. This prevents the clamp current Icp from becoming excessive, as shown in the graph of the clamp current Icp in FIG. As a result, erroneous roll calls are suppressed and the switching element 2 is appropriately protected.

FIG. 12 is a graph showing simulation results during on-operation in the switching circuit 1B of the second embodiment. The graph shown in FIG. 12 is a graph showing, from top to bottom, temporal changes in switch drive voltage Vd, switch current Ia, induced voltage V _L , clamp current Icp, bypass current Ib, and switch voltage Va during off-operation. .

As shown in the graph of the switch drive voltage Vd in FIG. 12, the drive voltage Vd increases over time due to the start of the on operation at time t4. When the drive voltage Vd increases, as shown in the graph of the induced voltage _VL in FIG. 12, the surge suppression operating voltage is switched from the voltage Vo1 during the OFF operation to a higher voltage Vo2.

As shown in the graph of the switch current Ia in FIG. 12, the switch current Ia also increases as the drive voltage Vd increases. Correspondingly, as shown in the graph of the voltage Va across the switch in FIG. 12, the voltage Va across the switch rapidly decreases. As shown in the graph of the induced voltage V _L in FIG. 12, an induced voltage V _L is generated by the parasitic inductance Lp of the switching element 2 with such a sudden change in the voltage Va across the switch.

However, if a clamp current Icp similar to that during off-operation flows through the surge suppression circuit 4B due to such an induced voltage _VL , the switch drive voltage Vd becomes excessive, and the control applied to the switching element 2 accordingly becomes excessive. If the voltage Vg exceeds the withstand voltage of the switching element 2, the switching element 2 may be damaged.

On the other hand, in the present embodiment, the capacitor voltage setting circuit 8 switches the surge suppression operating voltage Vo during the ON operation to a voltage Vo2 higher than the voltage Vo1 during the OFF operation. Therefore, as shown in the graph of the clamp current Icp in FIG. 12, even if the induced voltage V _L is generated, the induced voltage V _L is less than the surge suppression operating voltage Vo2, and the clamp current Icp is not generated.

Further, in this example, the bypass circuit operating voltage Vp is set to a voltage lower than the surge suppression operating voltage Vo2 during the ON operation. Therefore, as shown in the graph of the induced voltage V _L in FIG. 12, the induced voltage V _L exceeds the bypass circuit operating voltage Vp at time t5. As a result, bypass current Ib is generated, as shown in the graph of bypass current Ib in FIG.

In this way, even if a relatively large induced voltage _VL occurs, bypass current Ib flows through bypass circuit 9 before clamp current Icp flows. Thereby, during the ON operation, it is possible to prevent the clamp current Icp from flowing as much as possible, and it is possible to prevent the switch drive voltage Vd from becoming excessive.

As described above, according to the graphs of FIGS. 10 to 12, in each embodiment of the present disclosure, it is possible to suppress the surge voltage Vs with low loss, and moreover, protect the switching element 2 more appropriately. It has been shown that it can be done. Note that although FIGS. 10 to 12 show simulation results for the protection circuit in the first embodiment or the protection circuit in the second embodiment, other embodiments also have configurations that exhibit similar effects. It is presumed that similar simulation results can be obtained.

(Other embodiments)
Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various improvements, changes, and modifications can be made without departing from the spirit thereof.

For example, in each of the above embodiments, an example is shown in which an n-type MOSFET having a four-terminal structure is used as the switching element 2, but the configuration of the present disclosure can be applied to other FET elements such as a p-type MOSFET, IGBT, etc. It is also applicable to other types of switching elements 2, such as bipolar transistor elements.

INDUSTRIAL APPLICABILITY The present disclosure can suppress surge voltage with low loss in a switching circuit, and is useful for more appropriately protecting switching elements.

1A to 1F Switching circuit 2 Switching element 3 Drive circuit 4A to 4F Surge suppression circuit (protection circuit)
5 Resistance element 6 Diode (first diode)
7 Capacitor 8, 8a, 8b Capacitor voltage setting circuit 9 Bypass circuit 10 Zener diode (first Zener diode)
11 Diode (second diode)
12 Zener diode (second Zener diode)
13 Zener diode (third Zener diode)
T1 High potential side main terminal (pair of main terminals)
T2 Low potential side main terminal (pair of main terminals)
T3 Control terminal T4 Control reference potential terminal T5 Drive signal output terminal T6 Drive reference potential terminal W1 First wiring W2 Second wiring W3 Surge suppression wiring

Claims (10)

a switching element having a pair of main terminals and a control terminal;
a drive circuit that drives the switching element by applying a drive voltage to the control terminal;
a surge suppression circuit that suppresses generation of surge voltage between the pair of main terminals;
The drive circuit has a drive signal output terminal and a drive reference potential terminal,
The drive signal output terminal is connected to the control terminal of the switching element,
The drive reference potential terminal is connected to a control reference potential terminal provided on the low potential side of the switching element separately from the low potential side main terminal of the switching element via a first wiring,
The surge suppression circuit includes:
a resistance element provided on the first wiring;
a diode and a capacitor provided in series on a second wiring connecting the drive reference potential terminal and the low potential side main terminal;
a capacitor voltage setting circuit that sets the voltage applied to the capacitor;
The diode has a cathode connected to the drive reference potential terminal side, an anode connected to the low potential side main terminal side,
The capacitor voltage setting circuit is a switching circuit that actively or passively changes the voltage applied to the capacitor to set a surge suppression operating voltage for current to flow through the surge suppression circuit. The surge suppression circuit includes a bypass circuit connected in parallel to surge suppression wiring including the first wiring and the second wiring between the low potential side main terminal and the control reference potential terminal,
The bypass circuit according to claim 1, wherein the bypass circuit is configured such that a bypass circuit operating voltage for allowing a current to flow through the bypass circuit is within a range of a surge suppression operating voltage set by the capacitor voltage setting circuit. switching circuit. a switching element having a pair of main terminals and a control terminal;
a drive circuit that drives the switching element by applying a drive voltage to the control terminal;
a surge suppression circuit that suppresses generation of surge voltage between the pair of main terminals;
A drive signal output terminal of the drive circuit is connected to the control terminal of the switching element,
The surge suppression circuit includes:
a diode and a capacitor provided in series on a surge suppression wiring connecting the control terminal and the low potential side main terminal of the switching element ;
a capacitor voltage setting circuit that sets the voltage applied to the capacitor;
The diode has a cathode connected to the control terminal side, an anode connected to the low potential main terminal side,
The capacitor voltage setting circuit is a switching circuit that actively or passively changes the voltage applied to the capacitor to set a surge suppression operating voltage for current to flow through the surge suppression circuit. The drive reference potential terminal of the drive circuit is connected to a control reference potential terminal provided on the low potential side of the switching element separately from the low potential side main terminal of the switching element via a first wiring,
The surge suppression circuit includes a bypass circuit connected in parallel to a low potential side wiring connecting between the low potential side main terminal and the control reference potential terminal,
4. The bypass circuit according to claim 3, wherein the bypass circuit is configured such that a bypass circuit operating voltage for allowing a current to flow through the bypass circuit is within a range of a surge suppression operating voltage set by the capacitor voltage setting circuit. switching circuit. The capacitor voltage setting circuit sets the voltage applied to the capacitor so that the voltage applied to the capacitor becomes a predetermined voltage higher when the switching element is turned on than when the switching element is turned off. A switching circuit according to any one of claims 1 to 4. 6. The capacitor voltage setting circuit according to claim 1, wherein the drive circuit applies a predetermined voltage to the capacitor based on a drive signal for turning on the switching element. Switching circuit described in . The drive reference potential terminal of the drive circuit is connected to a control reference potential terminal provided on the low potential side of the switching element separately from the low potential side main terminal of the switching element via a first wiring,
The capacitor voltage setting circuit includes a Zener diode connected in parallel to the capacitor,
6. The switching circuit according to claim 1, wherein the Zener diode has a cathode connected to the low potential main terminal side of the capacitor, and an anode connected to the control reference potential terminal side of the capacitor. The capacitor voltage setting circuit adjusts the surge suppression operating voltage by a current flowing from the low potential side main terminal to the drive reference potential terminal while the drive circuit outputs a drive signal that turns on the switching element. 5. The switching circuit according to claim 2, wherein the switching circuit is configured to charge the capacitor until it reaches a predetermined voltage greater than the bypass circuit operating voltage. a switching element having a pair of main terminals and a control terminal;
a drive circuit that drives the switching element by applying a drive voltage to the control terminal;
a surge suppression circuit that suppresses generation of surge voltage between the pair of main terminals;
The drive circuit has a drive signal output terminal and a drive reference potential terminal,
The drive signal output terminal is connected to the control terminal of the switching element,
The drive reference potential terminal is connected to a control reference potential terminal provided on the low potential side of the switching element separately from the low potential side main terminal of the switching element via a first wiring,
The surge suppression circuit includes:
a resistance element provided on the first wiring;
a first diode and a first Zener diode provided in series on a second wiring connecting the drive reference potential terminal and the low potential side main terminal;
a bypass circuit connected in parallel to surge suppression wiring including the first wiring and the second wiring between the low potential side main terminal and the control reference potential terminal;
The first diode has a cathode connected to the drive reference potential terminal side, an anode connected to the low potential side main terminal side,
The first Zener diode has a cathode connected to the low potential side main terminal side, an anode connected to the control reference potential terminal side,
In the bypass circuit, a bypass circuit operating voltage for allowing a current to flow through the bypass circuit is a surge suppressing operating voltage for allowing a current to flow through the resistive element on the surge suppression wiring, the first diode, and the first Zener diode. A switching circuit configured to be larger. a switching element having a pair of main terminals and a control terminal;
a drive circuit that drives the switching element by applying a drive voltage to the control terminal;
a surge suppression circuit that suppresses generation of surge voltage between the pair of main terminals;
The drive circuit has a drive signal output terminal and a drive reference potential terminal,
The drive signal output terminal is connected to the control terminal of the switching element,
The drive reference potential terminal is connected to a control reference potential terminal provided on the low potential side of the switching element separately from the low potential side main terminal of the switching element via a first wiring,
The surge suppression circuit includes:
a first diode and a first Zener diode provided in series on a second wiring connecting the control terminal and the low potential side main terminal;
a bypass circuit connected in parallel to a low potential side wiring connecting between the low potential side main terminal and the control reference potential terminal,
The first diode has a cathode connected to the control terminal side, an anode connected to the low potential main terminal side,
The first Zener diode has a cathode connected to the low potential main terminal side, an anode connected to the control terminal side,
The bypass circuit is configured such that a bypass circuit operating voltage for allowing current to flow through the bypass circuit is higher than a surge suppression operating voltage for allowing current to flow through the first diode and the first Zener diode on the second wiring. configured ,
The bypass circuit is configured such that a second diode and a second Zener diode are connected in series,
The second diode has a cathode connected to the control reference potential terminal side, an anode connected to the low potential side main terminal side,
A switching circuit in which the second Zener diode has a cathode connected to the low potential side main terminal side and an anode connected to the control reference potential terminal side.

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