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JP7355709B2 - Bonding jig and semiconductor device manufacturing method - Google Patents
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JP7355709B2 - Bonding jig and semiconductor device manufacturing method - Google Patents

Bonding jig and semiconductor device manufacturing method Download PDF

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JP7355709B2
JP7355709B2 JP2020093801A JP2020093801A JP7355709B2 JP 7355709 B2 JP7355709 B2 JP 7355709B2 JP 2020093801 A JP2020093801 A JP 2020093801A JP 2020093801 A JP2020093801 A JP 2020093801A JP 7355709 B2 JP7355709 B2 JP 7355709B2
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thin plate
support member
semiconductor chip
close contact
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JP2021190540A (en
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真尚 山崎
高彰 宮崎
靖 池田
宇幸 串間
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Minebea Power Semiconductor Device Inc
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Hitachi Power Semiconductor Device Ltd
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Priority to PCT/JP2021/014688 priority patent/WO2021241017A1/en
Priority to CN202180032770.2A priority patent/CN115516610B/en
Priority to TW110118187A priority patent/TWI750094B/en
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting

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  • Die Bonding (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Description

本発明は、接合治具および半導体装置の製造方法に関し、例えば、焼結接合に利用される接合治具、および、その接合治具を用いた半導体装置の製造方法に関する。 The present invention relates to a bonding jig and a method for manufacturing a semiconductor device, and for example, to a bonding jig used for sinter bonding and a method for manufacturing a semiconductor device using the bonding jig.

炭化珪素(SiC)基板を用いたMOSFET(Metal Oxide Semiconductor Field Effect Transistor)またはIGBT(Insulated Gate Bipolar Transistor)などの半導体素子が開発されている。SiC-MOSFETは、従来のSi-MOSFETよりも素子抵抗が小さく、高速スイッチングが可能であり、電鉄および電気自動車などにおける低損失化に大きく貢献できる。また、SiC-MOSFETは、Si-MOSFETよりも高温環境において動作可能である。 Semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) using silicon carbide (SiC) substrates have been developed. SiC-MOSFETs have lower element resistance than conventional Si-MOSFETs, are capable of high-speed switching, and can greatly contribute to lower losses in electric railways, electric vehicles, and the like. Furthermore, SiC-MOSFETs can operate in higher temperature environments than Si-MOSFETs.

一方で、半導体チップを配線基板などに搭載する際、半導体チップと配線基板との接合には、従来、はんだ接合が用いられていた。しかし、はんだ接合は、SiC-MOSFETに要求される高温環境での動作に対応できない場合がある。そこで、高温環境への対応が可能になるように、焼結接合の適用が推進されている。 On the other hand, when mounting a semiconductor chip on a wiring board or the like, solder bonding has conventionally been used to join the semiconductor chip and the wiring board. However, solder joints may not be able to support operation in high-temperature environments required of SiC-MOSFETs. Therefore, the application of sintered bonding is being promoted so that it can cope with high-temperature environments.

焼結接合では、接合時に加圧が必要な場合があり、この加圧によって焼結材が接合面で押し広げられる。しかし、焼結材が接合面に対して十分に広がらず、放熱性が低下するという問題がある。一方で、焼結材が広がりすぎて、焼結材が半導体チップの外側へはみ出し、半導体チップと配線基板とが短絡するという問題がある。 In sintered bonding, pressure may be required during bonding, and this pressure causes the sintered material to be spread out at the bonding surface. However, there is a problem in that the sintered material does not spread sufficiently over the joint surface, resulting in reduced heat dissipation. On the other hand, there is a problem in that the sintered material spreads too much and protrudes to the outside of the semiconductor chip, causing a short circuit between the semiconductor chip and the wiring board.

例えば、特許文献1には、半導体チップが緩挿可能な開口部と、開口部よりも大きい断面積を有する接合材逃がし部と、を有する接合治具が開示されている。 For example, Patent Document 1 discloses a bonding jig that has an opening into which a semiconductor chip can be loosely inserted, and a bonding material escape portion having a larger cross-sectional area than the opening.

特開2011-216772号公報Japanese Patent Application Publication No. 2011-216772

焼結接合における加圧工程において、焼結材の押し広げに関連した不良としては、焼結材の広がり不足による放熱性の低下と、焼結材のはみ出しによる短絡とが挙げられる。 In the pressurizing step of sinter joining, defects related to the spreading of the sintered material include a decrease in heat dissipation due to insufficient spreading of the sintered material, and short circuits due to the protrusion of the sintered material.

焼結材のはみ出しによる短絡については、主に二つの形態が考えられる。一つ目の形態は、はみ出した焼結材が半導体チップの上面にまで這い上がることによる短絡である。二つ目の形態は、はみ出した焼結材に十分な加圧が為されず、焼結密度が低下し、焼結材が脱落することによる短絡である。 There are two main types of short circuits caused by the protrusion of the sintered material. The first type is a short circuit caused by the protruding sintered material creeping up to the top surface of the semiconductor chip. The second form is a short circuit due to insufficient pressure being applied to the protruding sintered material, resulting in a decrease in sintered density and the sintered material falling off.

上述の特許文献1における接合治具では、はみ出した焼結材の脱落に起因する短絡は防止できるが、半導体チップの周辺部に隙間が生じる。それ故、焼結材が、上記隙間を介して半導体チップの上面へ這い上がる恐れがある。 Although the bonding jig in Patent Document 1 described above can prevent short circuits caused by the protruding sintered material falling off, a gap is created around the semiconductor chip. Therefore, there is a risk that the sintered material may creep up onto the upper surface of the semiconductor chip through the gap.

従って、配線基板および半導体チップを備えた半導体装置では、焼結接合によって配線基板上に半導体チップを搭載させる際に、上述のような短絡を抑制することが求められる。すなわち、半導体装置の信頼性を向上させる技術が求められ、それを実現可能な接合治具の開発が求められる。 Therefore, in a semiconductor device including a wiring board and a semiconductor chip, it is required to suppress the above-mentioned short circuit when mounting the semiconductor chip on the wiring board by sinter bonding. In other words, there is a need for a technology that improves the reliability of semiconductor devices, and there is a need to develop a bonding jig that can achieve this.

その他の課題および新規な特徴は、本明細書の記述および添付図面から明らかになる。 Other objects and novel features will become apparent from the description herein and the accompanying drawings.

本願において開示される実施の形態のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。 A brief overview of typical embodiments disclosed in this application will be as follows.

一実施の形態における接合治具は、天板と、その上端部が前記天板に取り付けられた加圧部材と、平面視において前記加圧部材を囲むように、その上端部が前記天板に取り付けられた第1薄板、第2薄板、第3薄板および第4薄板と、その側面が前記第1薄板の下端部に取り付けられた円柱状の第1支持部材と、その側面が前記第2薄板の下端部に取り付けられた円柱状の第2支持部材と、その側面が前記第3薄板の下端部に取り付けられた円柱状の第3支持部材と、その側面が前記第4薄板の下端部に取り付けられた円柱状の第4支持部材と、を備える。 A joining jig in one embodiment includes a top plate, a pressure member whose upper end is attached to the top plate, and a pressure member whose upper end is attached to the top plate so as to surround the pressure member in a plan view. A first thin plate, a second thin plate, a third thin plate, and a fourth thin plate attached, a cylindrical first support member whose side surface is attached to the lower end of the first thin plate, and a side surface of which is attached to the second thin plate. a cylindrical second support member attached to the lower end of the third thin plate; a cylindrical third support member whose side surface is attached to the lower end of the third thin plate; and a third cylindrical support member whose side surface is attached to the lower end of the fourth thin plate. and a cylindrical fourth support member attached thereto.

また、一実施の形態における接合治具は、天板と、その上端部が前記天板に取り付けられた加圧部材と、平面視において前記加圧部材を囲む支持部材と、を備える。ここで、半導体チップの焼結接合時において、前記半導体チップの4つの側面を前記支持部材に密着させた状態で、前記加圧部材によって前記半導体チップの上面を加圧可能である。 Moreover, the joining jig in one embodiment includes a top plate, a pressure member whose upper end portion is attached to the top plate, and a support member surrounding the pressure member in plan view. Here, when the semiconductor chips are sintered and bonded, the upper surface of the semiconductor chip can be pressed by the pressure member while the four side surfaces of the semiconductor chip are in close contact with the support member.

また、一実施の形態における半導体装置の製造方法は、天板と、その上端部が前記天板に取り付けられた加圧部材と、平面視において前記加圧部材を囲むように、その上端部が前記天板に取り付けられた第1薄板、第2薄板、第3薄板および第4薄板と、その側面が前記第1薄板の下端部に取り付けられた円柱状の第1支持部材と、その側面が前記第2薄板の下端部に取り付けられた円柱状の第2支持部材と、その側面が前記第3薄板の下端部に取り付けられた円柱状の第3支持部材と、その側面が前記第4薄板の下端部に取り付けられた円柱状の第4支持部材と、を備えた接合治具を用いて行われる。また、半導体装置の製造方法は、(a)上面と、前記上面と反対側の下面と、平面視における第1方向において互いに向き合う第1側面および第2側面と、平面視で前記第1方向と交差する第2方向において互いに向き合う第3側面および第4側面と、を有する半導体チップを用意する工程、(b)配線基板上に焼結材を設ける工程、(c)前記半導体チップの前記下面が前記焼結材に接触するように、前記焼結材上に前記半導体チップを搭載する工程、(d)前記(c)工程後、平面視において前記加圧部材が前記半導体チップに重なるように、前記半導体チップの上方に前記接合治具を配置する工程、(e)前記(d)工程後、前記接合治具を前記半導体チップに近づけることで、前記第1支持部材を前記第1側面および前記配線基板に密着させ、前記第2支持部材を前記第2側面および前記配線基板に密着させ、前記第3支持部材を前記第3側面および前記配線基板に密着させ、前記第4支持部材を前記第4側面および前記配線基板に密着させる工程、(f)前記(e)工程後、前記接合治具を前記半導体チップに更に近づけ、前記半導体チップの前記上面を前記加圧部材によって加圧しながら、前記焼結材を加熱することで、少なくとも前記半導体チップの前記下面と前記配線基板との間に焼結層を形成する工程、を有する。 Further, a method for manufacturing a semiconductor device according to an embodiment includes a top plate, a pressure member whose upper end portion is attached to the top plate, and a pressure member whose upper end portion is attached to the top plate so as to surround the pressure member in a plan view. a first thin plate, a second thin plate, a third thin plate and a fourth thin plate attached to the top plate; a cylindrical first support member whose side surface is attached to the lower end of the first thin plate; and a columnar first support member whose side surface is attached to the lower end of the first thin plate; a cylindrical second support member attached to the lower end of the second thin plate; a cylindrical third support member whose side surface is attached to the lower end of the third thin plate; and a cylindrical third support member whose side surface is attached to the fourth thin plate. This is performed using a joining jig including a cylindrical fourth support member attached to the lower end of the joining jig. The method for manufacturing a semiconductor device further includes: (a) an upper surface, a lower surface opposite to the upper surface, a first side surface and a second side surface facing each other in a first direction in a plan view, and a first side surface and a second side surface facing each other in a first direction in a plan view; (b) providing a sintered material on a wiring board; (c) the bottom surface of the semiconductor chip is (d) mounting the semiconductor chip on the sintered material so as to make contact with the sintered material; (d) after the step (c), the pressing member overlaps the semiconductor chip in plan view; arranging the bonding jig above the semiconductor chip; (e) after the step (d), moving the bonding jig close to the semiconductor chip, thereby positioning the first support member on the first side surface and the the second support member is brought into close contact with the second side surface and the wiring board; the third support member is brought into close contact with the third side surface and the wiring board; and the fourth support member is brought into close contact with the third side surface and the wiring board. (f) After the step (e), the bonding jig is brought closer to the semiconductor chip, and while pressing the upper surface of the semiconductor chip with the pressure member, The method includes a step of heating a sintered material to form a sintered layer between at least the lower surface of the semiconductor chip and the wiring board.

一実施の形態によれば、半導体装置の信頼性を向上させることができる。また、それを実現可能な接合治具を提供できる。 According to one embodiment, reliability of a semiconductor device can be improved. Furthermore, it is possible to provide a joining jig that can achieve this.

実施の形態1における接合治具および半導体装置の製造方法を示す断面図である。1 is a cross-sectional view showing a bonding jig and a method for manufacturing a semiconductor device in Embodiment 1. FIG. 実施の形態1における接合治具を示す平面図である。1 is a plan view showing a joining jig in Embodiment 1. FIG. 図1に続く半導体装置の製造方法を示す断面図である。FIG. 2 is a cross-sectional view showing a method for manufacturing a semiconductor device following FIG. 1; 実施の形態1における半導体装置の製造方法を示す平面図である。1 is a plan view showing a method for manufacturing a semiconductor device in Embodiment 1. FIG. 図4に続く半導体装置の製造方法を示す平面図である。FIG. 5 is a plan view showing a method for manufacturing a semiconductor device following FIG. 4; 実施の形態2における接合治具を示す要部平面図である。FIG. 7 is a plan view of main parts showing a joining jig in Embodiment 2. FIG. 実施の形態3における接合治具および半導体装置の製造方法を示す断面図である。7 is a cross-sectional view showing a bonding jig and a method for manufacturing a semiconductor device in Embodiment 3. FIG. 図7に続く半導体装置の製造方法を示す断面図である。8 is a cross-sectional view showing a method for manufacturing a semiconductor device following FIG. 7. FIG. 実施の形態3の変形例における接合治具および半導体装置の製造方法を示す断面図である。FIG. 7 is a cross-sectional view showing a bonding jig and a method for manufacturing a semiconductor device in a modification of the third embodiment. 実施の形態4における接合治具および半導体装置の製造方法を示す断面図である。7 is a cross-sectional view showing a bonding jig and a method for manufacturing a semiconductor device in Embodiment 4. FIG. 図10に続く半導体装置の製造方法を示す断面図である。11 is a cross-sectional view showing a method for manufacturing a semiconductor device following FIG. 10. FIG.

以下、実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。また、以下の実施の形態では、特に必要なとき以外は同一または同様な部分の説明を原則として繰り返さない。 Hereinafter, embodiments will be described in detail based on the drawings. In addition, in all the drawings for explaining the embodiment, members having the same function are given the same reference numerals, and repeated explanation thereof will be omitted. Furthermore, in the following embodiments, descriptions of the same or similar parts will not be repeated in principle unless particularly necessary.

また、実施の形態を説明する図面では、構成を分かり易くするために、平面図であってもハッチングが付されている場合もあるし、断面図であってもハッチングが省略されている場合もある。 In addition, in the drawings explaining the embodiments, hatching may be added even in plan views, and hatching may be omitted even in cross-sectional views, in order to make the configuration easier to understand. be.

また、実施の形態において説明されるX方向、Y方向およびZ方向は互いに交差(直交)ている。本願では、Z方向は、ある構造体の上下方向、高さ方向または厚さ方向として説明されている。また、X方向およびY方向によって構成される面は平面を成し、Z方向に対して垂直な平面である。例えば、本願において「平面視」と表現した場合、それは、X方向およびY方向によって構成される面をZ方向から見ることを意味する。 Furthermore, the X direction, Y direction, and Z direction described in the embodiments intersect (orthogonal to) each other. In this application, the Z direction is described as the vertical direction, height direction, or thickness direction of a certain structure. Further, the plane formed by the X direction and the Y direction forms a plane, and is a plane perpendicular to the Z direction. For example, in the present application, when the expression "planar view" is used, it means that a plane constituted by the X direction and the Y direction is viewed from the Z direction.

(実施の形態1)
<接合治具100の構成>
図1および図2を用いて、実施の形態1における接合治具100について説明する。接合治具100は、主に、上述のような、はみ出した焼結材(焼結層)の脱落または這い上がりによる短絡を抑制するために使用される。
(Embodiment 1)
<Configuration of joining jig 100>
The joining jig 100 in Embodiment 1 will be described using FIGS. 1 and 2. The joining jig 100 is mainly used to suppress short circuits caused by the protruding sintered material (sintered layer) falling off or creeping up, as described above.

図1および図2に示されるように、接合治具100は、天板1、加圧部材2、薄板31~34および支持部材41~44を備える。 As shown in FIGS. 1 and 2, the joining jig 100 includes a top plate 1, a pressure member 2, thin plates 31-34, and support members 41-44.

加圧部材2の上端部、および、薄板31~34の各々の上端部は、天板1に取り付けられている。平面視において、薄板31~34は、天板1を囲み、それぞれ天板1の四方に設けられている。 The upper end of the pressure member 2 and the upper end of each of the thin plates 31 to 34 are attached to the top plate 1. In plan view, the thin plates 31 to 34 surround the top plate 1 and are provided on each side of the top plate 1.

支持部材41~44の各々は、円柱状を成し、支持部材41~44の各々の側面は、薄板31~34の各々の下端部に取り付けられている。なお、本願における円柱状は、真円柱状である場合も含むし、楕円柱状である場合も含む。すなわち、支持部材41~44延在方向に対して垂直な断面視において、支持部材41~44の各々の形状は、真円でもよいし、楕円でもよい。 Each of the support members 41 to 44 has a cylindrical shape, and the side surface of each of the support members 41 to 44 is attached to the lower end of each of the thin plates 31 to 34. Note that the cylindrical shape in this application includes the case of a perfect cylindrical shape and also the case of an elliptical cylindrical shape. That is, in a cross-sectional view perpendicular to the direction in which the support members 41 to 44 extend, the shape of each of the support members 41 to 44 may be a perfect circle or an ellipse.

また、図1に示されるように、実施の形態1では、断面視において、薄板31~34は、天板1に対して垂直な方向(Z方向)に取り付けられている。また、支持部材41~44は、それぞれ加圧部材2よりも低い位置に設けられている。言い換えれば、図1の破線で示されるように、天板1から支持部材41~44の各々の中心4aまでの距離は、天板1から加圧部材2の下端部までの距離よりも大きい。そのため、焼結接合時において、支持部材41~44は、加圧部材2よりも先に半導体チップ5に接触できる。 Further, as shown in FIG. 1, in the first embodiment, the thin plates 31 to 34 are attached in a direction perpendicular to the top plate 1 (Z direction) when viewed in cross section. Furthermore, the support members 41 to 44 are each provided at a lower position than the pressure member 2. In other words, as shown by the broken line in FIG. 1, the distance from the top plate 1 to the center 4a of each of the support members 41 to 44 is greater than the distance from the top plate 1 to the lower end of the pressure member 2. Therefore, during sintering and bonding, the supporting members 41 to 44 can contact the semiconductor chip 5 before the pressing member 2 can.

図2に示されるように、薄板31および薄板32はX方向において互いに向き合い、薄板33および薄板34はY方向において互いに向き合っている。支持部材41および支持部材42はY方向に延在し、支持部材43および支持部材44はX方向に延在している。 As shown in FIG. 2, the thin plates 31 and 32 face each other in the X direction, and the thin plates 33 and 34 face each other in the Y direction. Support member 41 and support member 42 extend in the Y direction, and support member 43 and support member 44 extend in the X direction.

後述するように、焼結接合時では、薄板31~34の撓みを利用して、支持部材41~44によって半導体チップが加圧される。そのため、X方向において、薄板31および薄板32の各々の幅は、支持部材41および支持部材42の各々の幅よりも小さく設計され、Y方向において、薄板33および薄板34の各々の幅は、支持部材43および支持部材44の各々の幅よりも小さく設計されている。 As will be described later, during sintering and bonding, the semiconductor chips are pressurized by the support members 41 to 44 by utilizing the deflection of the thin plates 31 to 34. Therefore, in the X direction, the width of each of the thin plates 31 and 32 is designed to be smaller than the width of each of the supporting members 41 and 42, and in the Y direction, the width of each of the thin plates 33 and 34 is designed to be smaller than the width of each of the thin plates 33 and 34. It is designed to be smaller than the width of each of the member 43 and the support member 44.

また、天板1および加圧部材2は、例えば金属材料またはカーボンからなる。薄板31~34は、弾性を有し、且つ、耐熱性の高い金属材料からなる。支持部材41~44は、耐熱性の高い金属材料またはカーボンからなる。支持部材41~44が金属材料からなる場合、その金属材料は、後述の焼結材6aに含まれる金属材料と反応し難い材料によって構成され、焼結接合時における加熱で融解しない材料によって構成され、例えばプラチナ(Pt)のような貴金属材料である。これにより、焼結接合時において、焼結材6aと支持部材41~44とが反応し、互いに接合されることが防止される。 Further, the top plate 1 and the pressure member 2 are made of, for example, a metal material or carbon. The thin plates 31 to 34 are made of a metal material that is elastic and has high heat resistance. The support members 41 to 44 are made of a highly heat-resistant metal material or carbon. When the supporting members 41 to 44 are made of a metal material, the metal material is made of a material that does not easily react with the metal material contained in the sintered material 6a, which will be described later, and is made of a material that does not melt when heated during sintering and joining. , for example, a noble metal material such as platinum (Pt). This prevents the sintered material 6a and the supporting members 41 to 44 from reacting and being joined to each other during sintering and joining.

<半導体装置200の製造方法>
以下に図1、図3~図5を用いて、実施の形態1における半導体装置200の製造方法を説明する。半導体装置200の製造方法には、上述の接合治具100が用いられる。半導体装置200は、例えば、鉄道の車両または自動車の車体などに搭載される半導体モジュール(パワーモジュール)である。
<Method for manufacturing semiconductor device 200>
A method for manufacturing the semiconductor device 200 according to the first embodiment will be described below with reference to FIGS. 1 and 3 to 5. The above-described bonding jig 100 is used in the method of manufacturing the semiconductor device 200. The semiconductor device 200 is, for example, a semiconductor module (power module) mounted on a railway vehicle or an automobile body.

図1に示されるように、半導体装置200は、配線基板7上に搭載された半導体チップ5を備え、配線基板7および半導体チップ5は、焼結材6aを焼結することで形成された焼結層6bによって接合されている。また、半導体チップ5は、例えばSiC基板を用いたMOSFETまたはIGBTなどの半導体素子を備えている。なお、半導体装置200は、配線基板7上に搭載された他の半導体チップおよび電子デバイスなどを更に備えていてもよい。 As shown in FIG. 1, the semiconductor device 200 includes a semiconductor chip 5 mounted on a wiring board 7, and the wiring board 7 and the semiconductor chip 5 are formed by sintering a sintered material 6a. They are joined by a conjunctiva 6b. Further, the semiconductor chip 5 includes a semiconductor element such as a MOSFET or an IGBT using a SiC substrate, for example. Note that the semiconductor device 200 may further include other semiconductor chips, electronic devices, etc. mounted on the wiring board 7.

図1、図4および図5に示されるように、半導体チップ5は、上面TSと、上面TSと反対側の下面BSと、X方向において互いに向き合う側面SS1および側面SS2と、Y方向において互いに向き合う側面SS3および側面SS4とを有する。 As shown in FIGS. 1, 4 and 5, the semiconductor chip 5 has a top surface TS, a bottom surface BS opposite to the top surface TS, a side surface SS1 and a side surface SS2 facing each other in the X direction, and facing each other in the Y direction. It has a side surface SS3 and a side surface SS4.

焼結材6aは、金属材料および溶剤を含むペースト状の接合材である。この金属材料は、ナノメートルレベルからマイクロメートルレベルの金属粒子(金属粉末)であり、例えば銅(Cu)または銀(Ag)である。なお、焼結接合時において、焼結材6aに含まれる上記溶剤は加熱によって無くなるので、焼結接合後、配線基板7と半導体チップ5との間には、上記金属材料からなる焼結層6bが形成される。 The sintered material 6a is a paste-like bonding material containing a metal material and a solvent. This metal material is a metal particle (metal powder) from a nanometer level to a micrometer level, and is, for example, copper (Cu) or silver (Ag). Note that during sintering and bonding, the solvent contained in the sintered material 6a is eliminated by heating, so after sintering and bonding, a sintered layer 6b made of the metal material is provided between the wiring board 7 and the semiconductor chip 5. is formed.

以下に、半導体装置200の製造方法に含まれる各工程について説明する。 Each step included in the method for manufacturing the semiconductor device 200 will be described below.

まず、図1に示されるように、半導体チップ5を用意し、配線基板7上に焼結材6aを設ける。次に、半導体チップ5の下面BSが焼結材6aに接触するように、焼結材6a上に半導体チップ5を搭載する。 First, as shown in FIG. 1, a semiconductor chip 5 is prepared, and a sintered material 6a is provided on a wiring board 7. Next, the semiconductor chip 5 is mounted on the sintered material 6a so that the lower surface BS of the semiconductor chip 5 contacts the sintered material 6a.

次に、平面視において加圧部材2が半導体チップ5に重なるように、半導体チップ5の上方に接合治具100を配置する。 Next, the bonding jig 100 is placed above the semiconductor chip 5 so that the pressure member 2 overlaps the semiconductor chip 5 in plan view.

実施の形態1では、支持部材41~44は、それぞれ平面視において半導体チップ5の側面SS1~SS4に重なるように位置している。言い換えれば、加圧部材2側となる支持部材41~44の半分(半円柱体)が、それぞれ平面視において半導体チップ5の側面SS1~SS4に重なるように位置している。更に言い換えれば、断面視において、支持部材41~44各々の側面のうち、最下端部となる第1の四半円点4bと、加圧部材2側に位置する第2の四半円点4cとを含む曲面が、それぞれ、側面SS1~SS4の直上に位置している。 In the first embodiment, the support members 41 to 44 are positioned so as to overlap the side surfaces SS1 to SS4 of the semiconductor chip 5, respectively, in a plan view. In other words, half of the support members 41 to 44 (semi-cylindrical bodies) on the pressure member 2 side are located so as to overlap the side surfaces SS1 to SS4 of the semiconductor chip 5, respectively, in a plan view. In other words, in a cross-sectional view, among the side surfaces of each of the support members 41 to 44, the first quarter circle point 4b, which is the lowest end, and the second quarter circle point 4c, which is located on the pressure member 2 side. The curved surfaces included are located directly above the side surfaces SS1 to SS4, respectively.

次に、図3に示されるように、接合治具100を押し下げ、接合治具100を半導体チップ5に近づけることで、支持部材41~44を、それぞれ半導体チップ5の側面SS1~SS4および配線基板7に密着させる。 Next, as shown in FIG. 3, by pressing down the bonding jig 100 and bringing the bonding jig 100 closer to the semiconductor chip 5, the supporting members 41 to 44 are attached to the side surfaces SS1 to SS4 of the semiconductor chip 5 and the wiring board, respectively. Place it in close contact with 7.

実施の形態1では、まず、接合治具100を半導体チップ5に近づけることで、加圧部材2側となる支持部材41~44の半分(半円柱体)を、半導体チップ5に接触させる。すなわち、支持部材41~44の各々の曲面(第1の四半円点4bと第2の四半円点4cとを含む曲面)を、半導体チップ5に接触させる。ここで、支持部材41~44は、それぞれ加圧部材2よりも低い位置に設けられているので、支持部材41~44は、加圧部材2よりも先に半導体チップ5に接触する。 In the first embodiment, first, by bringing the bonding jig 100 close to the semiconductor chip 5, half of the support members 41 to 44 (semi-cylindrical bodies) on the pressure member 2 side are brought into contact with the semiconductor chip 5. That is, each curved surface of the supporting members 41 to 44 (the curved surface including the first quadrant point 4b and the second quadrant point 4c) is brought into contact with the semiconductor chip 5. Here, since the support members 41 to 44 are each provided at a lower position than the pressure member 2, the support members 41 to 44 contact the semiconductor chip 5 before the pressure member 2 does.

次に、接合治具100を半導体チップ5に更に近づけることで、薄板31~34を撓ませながら、支持部材41~44をそれぞれ側面SS1~SS4に密着させる。すなわち、接合治具100を半導体チップ5に近づけると、支持部材41~44の各々の曲面に沿うように、支持部材41~44には、半導体チップ5の外側へ押し出す力が加えられる。そうすると、薄板31~34が、撓み、板バネのように作用するので、支持部材41~44から半導体チップ5へ向かう方向に対して、圧力が加えられる。 Next, by bringing the bonding jig 100 closer to the semiconductor chip 5, the supporting members 41 to 44 are brought into close contact with the side surfaces SS1 to SS4, respectively, while bending the thin plates 31 to 34. That is, when the bonding jig 100 is brought close to the semiconductor chip 5, a force is applied to the supporting members 41-44 to push the semiconductor chip 5 outward along the curved surfaces of the supporting members 41-44. Then, the thin plates 31 to 34 are bent and act like leaf springs, so that pressure is applied in the direction from the supporting members 41 to 44 toward the semiconductor chip 5.

次に、接合治具100を半導体チップ5に更に近づけることで、薄板31~34を撓ませながら、支持部材41~44をそれぞれ配線基板7に密着させる。ここで、薄板31~34の撓みによる支持部材41~44からの圧力が半導体チップ5に加えられた状態のまま、支持部材41~44が配線基板7に密着する。 Next, by bringing the bonding jig 100 closer to the semiconductor chip 5, the supporting members 41-44 are brought into close contact with the wiring board 7, respectively, while bending the thin plates 31-34. Here, the support members 41 to 44 are brought into close contact with the wiring board 7 while the pressure from the support members 41 to 44 due to the bending of the thin plates 31 to 34 is applied to the semiconductor chip 5.

次に、焼結接合を実施する。接合治具100を半導体チップ5に更に近づけ、加圧部材2によって半導体チップ5の上面TSを加圧しながら、焼結材6aを加熱する。この加熱処理は、例えば300℃以上、400℃以下で行われる。これにより、少なくとも半導体チップ5の下面BSと配線基板7との間に焼結層6bが形成される。焼結層6bは、焼結材6aに含まれていた金属材料からなる。 Next, sinter bonding is performed. The bonding jig 100 is brought closer to the semiconductor chip 5, and the sintered material 6a is heated while pressing the upper surface TS of the semiconductor chip 5 with the pressure member 2. This heat treatment is performed, for example, at a temperature of 300°C or higher and 400°C or lower. As a result, a sintered layer 6b is formed at least between the lower surface BS of the semiconductor chip 5 and the wiring board 7. The sintered layer 6b is made of the metal material contained in the sintered material 6a.

このように、実施の形態1によれば、半導体チップ5の焼結接合時において、半導体チップ5の4つの側面SS1~SS4を支持部材41~44に密着させた状態で、加圧部材2によって半導体チップ5の上面TSを加圧可能である。これにより、半導体チップ5の下面BSの全体に焼結層6bが形成されるので、焼結材6aの広がり不足による放熱性の低下を抑制することができる。 As described above, according to the first embodiment, when the semiconductor chip 5 is sintered and bonded, the four side surfaces SS1 to SS4 of the semiconductor chip 5 are in close contact with the supporting members 41 to 44, and the pressure member 2 The upper surface TS of the semiconductor chip 5 can be pressurized. Thereby, the sintered layer 6b is formed over the entire lower surface BS of the semiconductor chip 5, so that it is possible to suppress a decrease in heat dissipation due to insufficient spread of the sintered material 6a.

また、支持部材41~44の各々の断面視における半径は、焼結層6bの厚さT1よりも大きく、焼結層6bの厚さT1および半導体チップ5の厚さT2の合計よりも小さい。そのため、焼結接合時において、支持部材41~44が側面SS1~SS4に密着している状態が保たれている。 Furthermore, the radius of each of the supporting members 41 to 44 in a cross-sectional view is larger than the thickness T1 of the sintered layer 6b and smaller than the sum of the thickness T1 of the sintered layer 6b and the thickness T2 of the semiconductor chip 5. Therefore, during sintering and bonding, the support members 41 to 44 are maintained in close contact with the side surfaces SS1 to SS4.

焼結層6bは、半導体チップ5の下面BSからはみ出し、側面SS1、側面SS2、側面SS3または側面SS4の一部または全部にも形成される。すなわち、焼結層6bは半導体チップ5の上面TS側へ這い上がるように形成されるが、支持部材41~44が側面SS1~SS4に密着しているので、焼結層6bは、支持部材41~44によって差し止められ、上面TSに到達しない。 The sintered layer 6b protrudes from the lower surface BS of the semiconductor chip 5 and is also formed on part or all of the side surface SS1, side surface SS2, side surface SS3, or side surface SS4. That is, the sintered layer 6b is formed so as to creep up toward the upper surface TS side of the semiconductor chip 5, but since the supporting members 41 to 44 are in close contact with the side surfaces SS1 to SS4, the sintered layer 6b ~44 and does not reach the top surface TS.

従って、実施の形態1における接合治具100を用いることで、配線基板7と半導体チップの上面TSとが短絡するという不具合を抑制でき、半導体装置200の信頼性を向上させることができる。 Therefore, by using the bonding jig 100 in Embodiment 1, it is possible to suppress the short circuit between the wiring board 7 and the top surface TS of the semiconductor chip, and it is possible to improve the reliability of the semiconductor device 200.

また、焼結層6bの端部の断面は、支持部材41~44の側面に沿った形状を成し、フィレット形状を成している。言い換えれば、下面BSからはみ出した焼結層6bの断面は、側面SS1~SS4から離れるに連れて焼結層6bの厚さが小さくなるように、裾広がりのテーパ形状を成している。 Further, the cross section of the end portion of the sintered layer 6b has a shape along the side surfaces of the supporting members 41 to 44, and has a fillet shape. In other words, the cross section of the sintered layer 6b protruding from the lower surface BS has a tapered shape that widens at the bottom so that the thickness of the sintered layer 6b decreases as it moves away from the side surfaces SS1 to SS4.

例えば、焼結層6bの形成時に配線基板7が反る場合があるが、その場合、仮に、焼結層6bの端部が角状を成していると、角状の端部において焼結層6bからの応力が集中し、焼結層6bの接合強度が低下する恐れがある。上述のように、焼結層6bの端部が裾広がりのテーパ形状を成していることで、応力の集中が緩和され、そのような恐れを抑制できる。 For example, the wiring board 7 may warp during the formation of the sintered layer 6b. In that case, if the end of the sintered layer 6b is angular, sintering will occur at the angular end. There is a possibility that the stress from the layer 6b will be concentrated and the bonding strength of the sintered layer 6b will be reduced. As described above, since the end portion of the sintered layer 6b has a widening tapered shape, concentration of stress is alleviated, and such a fear can be suppressed.

以下に、図4および図5を用いて、半導体チップ5を焼結材6a上に搭載させた時における微小な位置誤差について説明する。 The minute positional error when the semiconductor chip 5 is mounted on the sintered material 6a will be described below with reference to FIGS. 4 and 5.

半導体チップ5は、位置誤差無く焼結材6a上に搭載されることが理想的であるが、半導体チップ5の位置が若干ずれる場合があり、例えば、半導体チップ5の位置が設計値よりも±1mm程度ずれる場合がある。 Ideally, the semiconductor chip 5 would be mounted on the sintered material 6a without any positional error, but the position of the semiconductor chip 5 may shift slightly. For example, the position of the semiconductor chip 5 may be ± from the design value. There may be a deviation of about 1 mm.

しかしながら、そのような位置誤差が、支持部材41~44の各々の曲面(第1の四半円点4bと第2の四半円点4cとを含む曲面)と重なる範囲内であれば、薄板31~34の撓みを利用して、半導体チップ5の位置を正常な位置へと修正できる。すなわち、図4のように、半導体チップ5の位置がずれていた場合、最初は支持部材41~44の一部のみが半導体チップ5の側面SS1~SS4に接触するが、最終的には図5の黒矢印のように、側面SS1~SS4には、支持部材41~44から圧力が加えられ、半導体チップ5の位置は、それぞれ正常な位置へと修正される。 However, if such positional error is within the range overlapping the curved surface of each of the supporting members 41 to 44 (the curved surface including the first quadrant point 4b and the second quadrant point 4c), the thin plates 31 to 44 overlap. The position of the semiconductor chip 5 can be corrected to the normal position by using the deflection of the semiconductor chip 34. That is, as shown in FIG. 4, when the position of the semiconductor chip 5 is shifted, only some of the supporting members 41 to 44 initially come into contact with the side surfaces SS1 to SS4 of the semiconductor chip 5, but eventually As shown by the black arrows in , pressure is applied from the supporting members 41 to 44 to the side surfaces SS1 to SS4, and the positions of the semiconductor chips 5 are corrected to their respective normal positions.

このように、実施の形態1における接合治具100を用いれば、半導体チップ5の位置誤差の有無に因らず、半導体チップ5の焼結接合を行うことができる。 In this way, by using the bonding jig 100 in the first embodiment, the semiconductor chips 5 can be sintered and bonded regardless of the presence or absence of positional errors of the semiconductor chips 5.

また、支持部材41~44は、焼結材6aに含まれる金属材料と反応し難い材料によって構成され、耐熱性の高い金属材料またはカーボンからなるが、支持部材41~44が、金属材料またはカーボン以外の材料で構成されていてもよい。例えば、支持部材41~44が、耐熱性の高い弾性体によって構成されていてもよい。このような弾性体は、焼結材6aに含まれる金属材料よりも高い融点を有し、例えばゴムである。 Further, the supporting members 41 to 44 are made of a material that does not easily react with the metallic material contained in the sintered material 6a, and are made of a highly heat-resistant metallic material or carbon. It may be made of other materials. For example, the support members 41 to 44 may be made of an elastic body with high heat resistance. Such an elastic body has a higher melting point than the metal material contained in the sintered material 6a, and is, for example, rubber.

(実施の形態2)
以下に図6を用いて、実施の形態2における接合治具100を説明する。なお、以下では、主に実施の形態1との相違点について説明する。
(Embodiment 2)
The joining jig 100 according to the second embodiment will be described below using FIG. 6. Note that, below, differences from Embodiment 1 will be mainly explained.

実施の形態2では、半導体チップ5の4つの角部に対応する領域に、4つの支持部材(第5~第8支持部材)が設けられ、4つの支持部材には、それぞれ薄板(第5~第8薄板)が取り付けられている。図6では、半導体チップ5の1つの角部に対応する領域に、第5薄板35および第5支持部材45が設けられている様子が示されている。 In the second embodiment, four supporting members (fifth to eighth supporting members) are provided in areas corresponding to the four corners of the semiconductor chip 5, and each of the four supporting members has a thin plate (fifth to eighth supporting members). 8th thin plate) is attached. FIG. 6 shows that the fifth thin plate 35 and the fifth support member 45 are provided in a region corresponding to one corner of the semiconductor chip 5.

すなわち、接合治具100は、薄板31と薄板33とが近接する箇所において、その上端部が天板1に取り付けられた第5薄板35と、その側面が第5薄板35の下端部に取り付けられた円柱状の第5支持部材45とを更に備えている。なお、ここでは図示されていないが、薄板32と薄板33とが近接する箇所、薄板33と薄板34とが近接する箇所および薄板31と薄板34とが近接する箇所においても、第5薄板35のような第6~第8薄板と、第5支持部材45のような第6~第8支持部材とが設けられている。 That is, the joining jig 100 has a fifth thin plate 35 whose upper end is attached to the top plate 1 and a side surface attached to the lower end of the fifth thin plate 35 at a location where the thin plates 31 and 33 are close to each other. It further includes a fifth support member 45 having a cylindrical shape. Although not shown here, the fifth thin plate 35 is also located at locations where the thin plates 32 and 33 are close to each other, where the thin plates 33 and 34 are close to each other, and where the thin plates 31 and 34 are close to each other. Sixth to eighth thin plates such as the above and sixth to eighth support members such as the fifth support member 45 are provided.

第5支持部材45および第6~第8支持部材は、それぞれL字型の円柱体であり、Y方向に延在する第1円柱体と、X方向に延在する第2円柱体とが結合された結合円柱体である。第1円柱体および第2円柱体は、それぞれ斜切円柱体であり、2つの斜切円柱体が結合されることで、第5支持部材45および第6~第8支持部材が構成されている。 The fifth support member 45 and the sixth to eighth support members are each L-shaped cylindrical bodies, and a first cylindrical body extending in the Y direction and a second cylindrical body extending in the X direction are combined. It is a connected cylindrical body. The first cylindrical body and the second cylindrical body are each diagonally cut cylindrical bodies, and the two diagonally cut cylindrical bodies are combined to form the fifth support member 45 and the sixth to eighth support members. .

第5薄板35の向きは、薄板31の向きおよび薄板33の向きと異なり、薄板31の向きおよび薄板33の向きに対して45度傾いている。同様に、第6薄板の向きは、薄板32の向きおよび薄板33の向きと異なり、薄板32の向きおよび薄板33の向きに対して45度傾いている。第7薄板の向きは、薄板33の向きおよび薄板34の向きと異なり、薄板33の向きおよび薄板34の向きに対して45度傾いている。第8薄板の向きは、薄板31の向きおよび薄板34の向きと異なり、薄板31の向きおよび薄板34の向きに対して45度傾いている。 The orientation of the fifth thin plate 35 is different from the orientation of the thin plate 31 and the thin plate 33, and is inclined at 45 degrees with respect to the orientation of the thin plate 31 and the thin plate 33. Similarly, the orientation of the sixth thin plate is different from the orientation of the thin plates 32 and 33, and is inclined at 45 degrees with respect to the directions of the thin plates 32 and 33. The orientation of the seventh thin plate is different from the orientations of the thin plates 33 and 34, and is inclined at 45 degrees with respect to the directions of the thin plates 33 and 34. The orientation of the eighth thin plate is different from the orientation of the thin plate 31 and the thin plate 34, and is inclined at 45 degrees with respect to the orientation of the thin plate 31 and the thin plate 34.

焼結接合時では、接合治具100を半導体チップ5に近づけることで、第5薄板35および第6~第8薄板を撓ませながら、第5支持部材45および第6~第8支持部材をそれぞれ側面SS1~SS4に密着させる。そして、接合治具100を半導体チップ5に更に近づけることで、第5薄板35および第6~第8薄板を撓ませながら、第5支持部材45および第6~第8支持部材をそれぞれ配線基板7に密着させる。図6の黒矢印のように、第5支持部材45および第6~第8支持部材から半導体チップ5へ向かって圧力が加えられる。 During sinter bonding, by bringing the bonding jig 100 close to the semiconductor chip 5, the fifth thin plate 35 and the sixth to eighth thin plates are bent, while the fifth supporting member 45 and the sixth to eighth supporting members are bent, respectively. Bring it into close contact with the sides SS1 to SS4. Then, by bringing the bonding jig 100 closer to the semiconductor chip 5, the fifth thin plate 35 and the sixth to eighth thin plates are bent, and the fifth supporting member 45 and the sixth to eighth supporting members are respectively attached to the wiring board 7. Closely contact. As indicated by the black arrows in FIG. 6, pressure is applied toward the semiconductor chip 5 from the fifth support member 45 and the sixth to eighth support members.

実施の形態1のように支持部材41~44のみが設けられている場合、半導体チップ5の角部において、焼結材6aがはみ出す可能性がある。実施の形態2では、半導体チップ5の角部に対応する領域に、第5支持部材45および第6~第8支持部材と、第5薄板35および第6~第8薄板とが設けられている。これにより、半導体チップ5の角部において焼結材6aが這い上がり、配線基板7と半導体チップ5の上面TSとが短絡する恐れを、更に抑制することができる。 When only the supporting members 41 to 44 are provided as in the first embodiment, there is a possibility that the sintered material 6a protrudes from the corners of the semiconductor chip 5. In the second embodiment, the fifth support member 45 and the sixth to eighth support members, and the fifth thin plate 35 and the sixth to eighth thin plates are provided in the area corresponding to the corner of the semiconductor chip 5. . Thereby, it is possible to further suppress the possibility that the sintered material 6a creeps up at the corner of the semiconductor chip 5, causing a short circuit between the wiring board 7 and the upper surface TS of the semiconductor chip 5.

(実施の形態3)
以下に図7および図8を用いて、実施の形態3における接合治具100および半導体装置200の製造方法を説明する。なお、以下では、主に実施の形態1との相違点について説明する。
(Embodiment 3)
A method for manufacturing the bonding jig 100 and the semiconductor device 200 according to the third embodiment will be described below with reference to FIGS. 7 and 8. Note that, below, differences from Embodiment 1 will be mainly explained.

実施の形態1では、断面視において、薄板31~34は、天板1に対して垂直な方向(Z方向)に取り付けられていた。実施の形態3では、図7に示されるように、断面視において、薄板31~34は、天板1に対して垂直な方向から傾斜している。すなわち、薄板31~34の各々の下端部は、薄板31~34の各々の上端部よりも、加圧部材2の近くに位置している。 In the first embodiment, the thin plates 31 to 34 are attached in a direction perpendicular to the top plate 1 (Z direction) when viewed in cross section. In the third embodiment, as shown in FIG. 7, the thin plates 31 to 34 are inclined from a direction perpendicular to the top plate 1 in a cross-sectional view. That is, the lower ends of each of the thin plates 31 to 34 are located closer to the pressure member 2 than the upper ends of each of the thin plates 31 to 34.

焼結接合時では、接合治具100は、平面視において加圧部材2が半導体チップ5に重なるように、半導体チップ5の上方に配置される。ここで、実施の形態3では、支持部材41~44は、平面視において半導体チップ5に重ならない。言い換えれば、支持部材41~44は、側面SS1~SS4の直上から離れた場所に位置している。 During sinter bonding, the bonding jig 100 is placed above the semiconductor chip 5 so that the pressure member 2 overlaps the semiconductor chip 5 in plan view. Here, in the third embodiment, the supporting members 41 to 44 do not overlap the semiconductor chip 5 in plan view. In other words, the support members 41 to 44 are located away from directly above the side surfaces SS1 to SS4.

図8に示されるように、接合治具100を半導体チップ5に近づけることで、まず、支持部材41~44が配線基板7に密着し、薄板31~34が撓んだ状態になる。次に、接合治具100を半導体チップ5に更に近づけることで、薄板31~34を撓ませながら支持部材41~44が、それぞれ側面SS1~SS4に密着する。そして、薄板31~34の撓みによる支持部材41~44からの圧力が、半導体チップ5に加えられる。 As shown in FIG. 8, by bringing the bonding jig 100 close to the semiconductor chip 5, the supporting members 41 to 44 first come into close contact with the wiring board 7, and the thin plates 31 to 34 are bent. Next, by bringing the bonding jig 100 closer to the semiconductor chip 5, the supporting members 41-44 are brought into close contact with the side surfaces SS1-SS4, respectively, while bending the thin plates 31-34. Then, pressure from the supporting members 41 to 44 is applied to the semiconductor chip 5 due to the bending of the thin plates 31 to .

このように、実施の形態3では、支持部材41~44を半導体チップ5の外側から接近させる。それ故、複数の半導体チップ5が密集したような領域では、実施の形態3の接合治具100は、実施の形態1と比較して、不向きである。しかしながら、実施の形態3の接合治具100は、実施の形態1と比較して、半導体チップ5へより強い圧力を加え易いという利点を有する。従って、複数の半導体チップ5の間隔が十分に広い場合には、実施の形態3の接合治具100を適用することで、半導体装置200の信頼性を更に向上させることができる。 In this manner, in the third embodiment, the supporting members 41 to 44 are approached from the outside of the semiconductor chip 5. Therefore, compared to the first embodiment, the bonding jig 100 of the third embodiment is not suitable for areas where a plurality of semiconductor chips 5 are crowded together. However, the bonding jig 100 of the third embodiment has the advantage that stronger pressure can be easily applied to the semiconductor chip 5 compared to the first embodiment. Therefore, when the distance between the plurality of semiconductor chips 5 is sufficiently wide, the reliability of the semiconductor device 200 can be further improved by applying the bonding jig 100 of the third embodiment.

また、実施の形態3で開示した技術に、実施の形態2で開示した技術を組み合わせることも可能である。 Further, it is also possible to combine the technology disclosed in Embodiment 3 with the technology disclosed in Embodiment 2.

(変形例)
図9は、実施の形態3の変形例における接合治具100を示している。
(Modified example)
FIG. 9 shows a joining jig 100 in a modification of the third embodiment.

実施の形態3では、薄板31~34が平板であったが、図9に示される変形例のように、薄板31~34は予め撓んだ状態の曲板であってもよい。言い換えれば、薄板31~34は、断面視において曲線を成していてもよい。 In the third embodiment, the thin plates 31 to 34 are flat plates, but as in a modification shown in FIG. 9, the thin plates 31 to 34 may be curved plates that are bent in advance. In other words, the thin plates 31 to 34 may have a curved line when viewed in cross section.

このような変形例における薄板31~34も、実施の形態3における薄板31~34と同様に使用することができる。 The thin plates 31 to 34 in such a modified example can also be used in the same way as the thin plates 31 to 34 in the third embodiment.

(実施の形態4)
以下に図10および図11を用いて、実施の形態4における接合治具100および半導体装置200の製造方法を説明する。なお、以下では、主に実施の形態3との相違点について説明する。
(Embodiment 4)
The method for manufacturing the bonding jig 100 and the semiconductor device 200 according to the fourth embodiment will be described below with reference to FIGS. 10 and 11. Note that, below, differences from Embodiment 3 will be mainly explained.

実施の形態4では、図10に示されるように、4組の薄板31~34および支持部材41~44の代わりに、4つの弾性体が用いられている。図10に示される弾性体81は、薄板31および支持部材41に相当し、弾性体82は、薄板32および支持部材42に相当する。図示はしないが、実施の形態4における接合治具100は、薄板33および支持部材43に相当する弾性体と、薄板34および支持部材44に相当する弾性体とを更に備えている。このような弾性体は、焼結材6aに含まれる金属材料よりも高い融点を有し、例えばゴムである。 In the fourth embodiment, as shown in FIG. 10, four elastic bodies are used instead of the four sets of thin plates 31-34 and support members 41-44. The elastic body 81 shown in FIG. 10 corresponds to the thin plate 31 and the support member 41, and the elastic body 82 corresponds to the thin plate 32 and the support member 42. Although not shown, the joining jig 100 in the fourth embodiment further includes an elastic body corresponding to the thin plate 33 and the support member 43, and an elastic body corresponding to the thin plate 34 and the support member 44. Such an elastic body has a higher melting point than the metal material contained in the sintered material 6a, and is, for example, rubber.

なお、4つの弾性体の各々の上端部は、天板1に取り付けられている。4つの弾性体の各々の下端部は、支持部材41~44の形状に対応しており、半円柱状となっている。 Note that the upper end portions of each of the four elastic bodies are attached to the top plate 1. The lower end portion of each of the four elastic bodies corresponds to the shape of the support members 41 to 44, and has a semi-cylindrical shape.

焼結接合時では、接合治具100は、平面視において加圧部材2が半導体チップ5に重なるように、半導体チップ5の上方に配置される。ここで、実施の形態4では、4つの弾性体は、平面視において半導体チップ5に重ならない。言い換えれば、4つの弾性体は、側面SS1~SS4の直上から離れた場所に位置している。 During sinter bonding, the bonding jig 100 is placed above the semiconductor chip 5 so that the pressure member 2 overlaps the semiconductor chip 5 in plan view. Here, in the fourth embodiment, the four elastic bodies do not overlap the semiconductor chip 5 in plan view. In other words, the four elastic bodies are located away from directly above the side surfaces SS1 to SS4.

図11に示されるように、接合治具100を半導体チップ5に近づけることで、まず、4つの弾性体が配線基板7に密着し、4つの弾性体が撓んだ状態になる。次に、接合治具100を半導体チップ5に更に近づけることで、4つの弾性体を撓ませながら4つの弾性体が、それぞれ側面SS1~SS4に密着する。そして、4つの弾性体からの圧力が、半導体チップ5に加えられる。 As shown in FIG. 11, by bringing the bonding jig 100 close to the semiconductor chip 5, first, the four elastic bodies come into close contact with the wiring board 7, and the four elastic bodies become bent. Next, by bringing the bonding jig 100 closer to the semiconductor chip 5, the four elastic bodies are brought into close contact with the side surfaces SS1 to SS4, respectively, while being bent. Then, pressure from the four elastic bodies is applied to the semiconductor chip 5.

実施の形態4では、このような弾性体を使用することで、接合治具100の構成を簡略化できる。しかしながら、弾性体を使用することで、支持部材41~44を構成する金属材料と比較して、長期間に及ぶ高温環境下における信頼性が小さくなる恐れがあるので、そのような場合には、上述の実施の形態3の技術を適用することが好ましい。 In the fourth embodiment, by using such an elastic body, the configuration of the joining jig 100 can be simplified. However, by using an elastic body, there is a risk that the reliability under a high temperature environment for a long period of time will be lower than that of the metal material that constitutes the support members 41 to 44, so in such a case, It is preferable to apply the technique of the third embodiment described above.

以上、本発明をその実施の形態に基づき具体的に説明したが、本発明は、上記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々の変更が可能である。 Although the present invention has been specifically described above based on the embodiments thereof, the present invention is not limited to the above embodiments, and various changes can be made without departing from the gist thereof.

その他、上記実施の形態に記載された内容の一部を以下に記載する。 In addition, some of the contents described in the above embodiments will be described below.

[付記1]
天板と、
その上端部が前記天板に取り付けられた加圧部材と、
平面視において前記加圧部材を囲むように、その上端部が前記天板に取り付けられた第1弾性体、第2弾性体、第3弾性体および第4弾性体と、
を備えた接合治具を用いた半導体装置の製造方法であって、
前記第1弾性体、前記第2弾性体、前記第3弾性体および前記第4弾性体の各々の下端部は、前記第1弾性体、前記第2弾性体、前記第3弾性体および前記第4弾性体の各々の前記上端部よりも、前記加圧部材の近くに位置し、
(a)上面と、前記上面と反対側の下面と、平面視における第1方向において互いに向き合う第1側面および第2側面と、平面視で前記第1方向と交差する第2方向において互いに向き合う第3側面および第4側面と、を有する半導体チップを用意する工程、
(b)配線基板上に焼結材を設ける工程、
(c)前記半導体チップの前記下面が前記焼結材に接触するように、前記焼結材上に前記半導体チップを搭載する工程、
(d)前記(c)工程後、平面視において前記加圧部材が前記半導体チップに重なるように、前記半導体チップの上方に前記接合治具を配置する工程、
(e)前記(d)工程後、前記接合治具を前記半導体チップに近づけることで、前記第1弾性体を前記第1側面および前記配線基板に密着させ、前記第2弾性体を前記第2側面および前記配線基板に密着させ、前記第3弾性体を前記第3側面および前記配線基板に密着させ、前記第4弾性体を前記第4側面および前記配線基板に密着させる工程、
(f)前記(e)工程後、前記接合治具を前記半導体チップに更に近づけ、前記半導体チップの前記上面を前記加圧部材によって加圧しながら、前記焼結材を加熱することで、少なくとも前記半導体チップの前記下面と前記配線基板との間に焼結層を形成する工程、
を有する、半導体装置の製造方法。
[Additional note 1]
The top plate and
a pressure member whose upper end is attached to the top plate;
a first elastic body, a second elastic body, a third elastic body, and a fourth elastic body whose upper end portions are attached to the top plate so as to surround the pressure member in a plan view;
A method for manufacturing a semiconductor device using a bonding jig comprising:
The lower end portions of each of the first elastic body, the second elastic body, the third elastic body, and the fourth elastic body are connected to the first elastic body, the second elastic body, the third elastic body, and the fourth elastic body. located closer to the pressure member than the upper end of each of the four elastic bodies,
(a) an upper surface, a lower surface opposite to the upper surface, a first side surface and a second side surface facing each other in a first direction in a plan view, and a first side surface and a second side surface facing each other in a second direction intersecting the first direction in a plan view; preparing a semiconductor chip having three side surfaces and a fourth side surface;
(b) a step of providing a sintered material on the wiring board;
(c) mounting the semiconductor chip on the sintered material so that the lower surface of the semiconductor chip contacts the sintered material;
(d) after the step (c), arranging the bonding jig above the semiconductor chip so that the pressure member overlaps the semiconductor chip in plan view;
(e) After the step (d), the first elastic body is brought into close contact with the first side surface and the wiring board by bringing the bonding jig close to the semiconductor chip, and the second elastic body is brought into close contact with the second elastic body. bringing the third elastic body into close contact with the third side surface and the wiring board; bringing the fourth elastic body into close contact with the fourth side surface and the wiring board;
(f) After the step (e), the bonding jig is brought closer to the semiconductor chip, and while the upper surface of the semiconductor chip is pressed by the pressure member, the sintered material is heated, thereby at least the forming a sintered layer between the lower surface of the semiconductor chip and the wiring board;
A method for manufacturing a semiconductor device, comprising:

[付記2]
付記1に記載の半導体装置の製造方法において、
前記(f)工程において、前記焼結層は、前記下面からはみ出し、前記第1側面、前記第2側面、前記第3側面または前記第4側面の一部または全部にも形成され、
前記下面からはみ出した前記焼結層の断面は、前記第1側面、前記第2側面、前記第3側面または前記第4側面から離れるに連れて前記焼結層の厚さが小さくなるように、裾広がりのテーパ形状を成す、半導体装置の製造方法。
[Additional note 2]
In the method for manufacturing a semiconductor device according to Supplementary Note 1,
In the step (f), the sintered layer protrudes from the lower surface and is also formed on part or all of the first side, the second side, the third side, or the fourth side,
The cross section of the sintered layer protruding from the lower surface is such that the thickness of the sintered layer decreases as it moves away from the first side, the second side, the third side, or the fourth side. A method for manufacturing semiconductor devices that form a tapered shape with a widening base.

[付記3]
付記1に記載の半導体装置の製造方法において、
前記(e)工程は、
(e6)前記接合治具を前記半導体チップに近づけることで、前記第1弾性体を前記配線基板に密着させ、前記第2弾性体を前記配線基板に密着させ、前記第3弾性体を前記配線基板に密着させ、前記第4弾性体を前記配線基板に密着させる工程、
(e7)前記(e6)工程後、前記接合治具を前記半導体チップに更に近づけることで、前記第1弾性体を撓ませながら前記第1弾性体を前記第1側面に密着させ、前記第2弾性体を撓ませながら前記第2弾性体を前記第2側面に密着させ、前記第3弾性体を撓ませながら前記第3弾性体を前記第3側面に密着させ、前記第4弾性体を撓ませながら前記第4弾性体を前記第4側面に密着させる工程、
を含む、半導体装置の製造方法。
[Additional note 3]
In the method for manufacturing a semiconductor device according to Supplementary Note 1,
The step (e) is
(e6) By bringing the bonding jig close to the semiconductor chip, the first elastic body is brought into close contact with the wiring board, the second elastic body is brought into close contact with the wiring board, and the third elastic body is brought into close contact with the wiring board. bringing the fourth elastic body into close contact with the wiring board;
(e7) After the step (e6), by bringing the bonding jig closer to the semiconductor chip, the first elastic body is brought into close contact with the first side surface while bending the first elastic body, and the second The second elastic body is brought into close contact with the second side surface while the elastic body is bent, the third elastic body is brought into close contact with the third side surface while the third elastic body is bent, and the fourth elastic body is bent. bringing the fourth elastic body into close contact with the fourth side surface while
A method for manufacturing a semiconductor device, including:

[付記4]
付記1に記載の半導体装置の製造方法において、
前記第1弾性体、前記第2弾性体、前記第3弾性体および前記第4弾性体は、それぞれ、前記焼結材に含まれる金属材料よりも高い融点を有する材料によって構成されている、半導体装置の製造方法。
[Additional note 4]
In the method for manufacturing a semiconductor device according to Supplementary Note 1,
The first elastic body, the second elastic body, the third elastic body, and the fourth elastic body are each made of a material having a higher melting point than the metal material contained in the sintered material, a semiconductor. Method of manufacturing the device.

[付記5]
天板と、
その上端部が前記天板に取り付けられた加圧部材と、
平面視において前記加圧部材を囲むように、その上端部が前記天板に取り付けられた第1弾性体、第2弾性体、第3弾性体および第4弾性体と、
を備え、
前記第1弾性体、前記第2弾性体、前記第3弾性体および前記第4弾性体の各々の下端部は、前記第1弾性体、前記第2弾性体、前記第3弾性体および前記第4弾性体の各々の前記上端部よりも、前記加圧部材の近くに位置している、接合治具。
[Additional note 5]
The top plate and
a pressure member whose upper end is attached to the top plate;
a first elastic body, a second elastic body, a third elastic body, and a fourth elastic body whose upper end portions are attached to the top plate so as to surround the pressure member in a plan view;
Equipped with
The lower end portions of each of the first elastic body, the second elastic body, the third elastic body, and the fourth elastic body are connected to the first elastic body, the second elastic body, the third elastic body, and the fourth elastic body. The joining jig is located closer to the pressure member than the upper end of each of the four elastic bodies.

1 天板
2 加圧部材
4a 中心
4b、4c 四半円点
5 半導体チップ
6a 焼結材
6b 焼結層
7 配線基板
31~35 薄板
41~45 支持部材
81、82 弾性体
100 接合治具
200 半導体装置
BS 半導体チップの下面
SS1~SS4 半導体チップの側面
TS 半導体チップの上面
1 Top plate 2 Pressure member 4a Center 4b, 4c Quadrant point 5 Semiconductor chip 6a Sintered material 6b Sintered layer 7 Wiring board 31 to 35 Thin plate 41 to 45 Support members 81, 82 Elastic body 100 Bonding jig 200 Semiconductor device BS Bottom surface of semiconductor chip SS1 to SS4 Side surface of semiconductor chip TS Top surface of semiconductor chip

Claims (15)

天板と、
その上端部が前記天板に取り付けられた加圧部材と、
平面視において前記加圧部材を囲むように、その上端部が前記天板に取り付けられた第1薄板、第2薄板、第3薄板および第4薄板と、
その側面が前記第1薄板の下端部に取り付けられた円柱状の第1支持部材と、
その側面が前記第2薄板の下端部に取り付けられた円柱状の第2支持部材と、
その側面が前記第3薄板の下端部に取り付けられた円柱状の第3支持部材と、
その側面が前記第4薄板の下端部に取り付けられた円柱状の第4支持部材と、
を備えた、接合治具。
The top plate and
a pressure member whose upper end is attached to the top plate;
a first thin plate, a second thin plate, a third thin plate, and a fourth thin plate whose upper end portions are attached to the top plate so as to surround the pressure member in a plan view;
a cylindrical first support member whose side surface is attached to the lower end of the first thin plate;
a cylindrical second support member whose side surface is attached to the lower end of the second thin plate;
a cylindrical third support member whose side surface is attached to the lower end of the third thin plate;
a cylindrical fourth support member whose side surface is attached to the lower end of the fourth thin plate;
A joining jig equipped with
請求項1に記載の接合治具において、
前記第1薄板および前記第2薄板は、平面視における第1方向において互いに向き合い、
前記第3薄板および前記第4薄板は、平面視で前記第1方向と交差する第2方向において互いに向き合い、
前記第1支持部材および前記第2支持部材は、前記第2方向に延在し、
前記第3支持部材および前記第4支持部材は、前記第1方向に延在している、接合治具。
The joining jig according to claim 1,
the first thin plate and the second thin plate face each other in a first direction in plan view;
The third thin plate and the fourth thin plate face each other in a second direction intersecting the first direction in plan view,
the first support member and the second support member extend in the second direction;
The third support member and the fourth support member are a joining jig, wherein the third support member and the fourth support member extend in the first direction.
請求項2に記載の接合治具において、
前記第1薄板と前記第3薄板とが近接する箇所において、その上端部が前記天板に取り付けられた第5薄板と、
前記第2薄板と前記第3薄板とが近接する箇所において、その上端部が前記天板に取り付けられた第6薄板と、
前記第3薄板と前記第4薄板とが近接する箇所において、その上端部が前記天板に取り付けられた第7薄板と、
前記第1薄板と前記第4薄板とが近接する箇所において、その上端部が前記天板に取り付けられた第8薄板と、
その側面が前記第5薄板の下端部に取り付けられた円柱状の第5支持部材と、
その側面が前記第6薄板の下端部に取り付けられた円柱状の第6支持部材と、
その側面が前記第7薄板の下端部に取り付けられた円柱状の第7支持部材と、
その側面が前記第8薄板の下端部に取り付けられた円柱状の第8支持部材と、
を更に備え、
前記第5薄板の向きは、前記第1薄板の向きおよび前記第3薄板の向きと異なり、
前記第6薄板の向きは、前記第2薄板の向きおよび前記第3薄板の向きと異なり、
前記第7薄板の向きは、前記第3薄板の向きおよび前記第4薄板の向きと異なり、
前記第8薄板の向きは、前記第1薄板の向きおよび前記第4薄板の向きと異なる、接合治具。
The joining jig according to claim 2,
a fifth thin plate whose upper end is attached to the top plate at a location where the first thin plate and the third thin plate are close to each other;
a sixth thin plate whose upper end is attached to the top plate at a location where the second thin plate and the third thin plate are close to each other;
a seventh thin plate whose upper end portion is attached to the top plate at a location where the third thin plate and the fourth thin plate are close to each other;
an eighth thin plate whose upper end is attached to the top plate at a location where the first thin plate and the fourth thin plate are close to each other;
a cylindrical fifth support member whose side surface is attached to the lower end of the fifth thin plate;
a cylindrical sixth support member whose side surface is attached to the lower end of the sixth thin plate;
a cylindrical seventh support member whose side surface is attached to the lower end of the seventh thin plate;
a cylindrical eighth support member whose side surface is attached to the lower end of the eighth thin plate;
further comprising;
The orientation of the fifth thin plate is different from the orientation of the first thin plate and the third thin plate,
The orientation of the sixth thin plate is different from the orientation of the second thin plate and the third thin plate,
The orientation of the seventh thin plate is different from the orientation of the third thin plate and the fourth thin plate,
The joining jig, wherein the direction of the eighth thin plate is different from the direction of the first thin plate and the direction of the fourth thin plate.
請求項3に記載の接合治具において、
前記第5支持部材、前記第6支持部材、前記第7支持部材および前記第8支持部材は、それぞれ、前記第1方向に延在する第1円柱体と、前記第2方向に延在する第2円柱体とが結合された結合円柱体である、接合治具。
The joining jig according to claim 3,
The fifth support member, the sixth support member, the seventh support member, and the eighth support member each include a first cylindrical body extending in the first direction and a cylindrical body extending in the second direction. A joining jig, which is a joining cylindrical body in which two cylindrical bodies are joined.
請求項1に記載の接合治具において、
前記第1薄板、前記第2薄板、前記第3薄板および前記第4薄板の各々の前記下端部は、前記第1薄板、前記第2薄板、前記第3薄板および前記第4薄板の各々の前記上端部よりも、前記加圧部材の近くに位置している、接合治具。
The joining jig according to claim 1,
The lower end portions of each of the first thin plate, the second thin plate, the third thin plate, and the fourth thin plate are connected to the lower end portions of each of the first thin plate, the second thin plate, the third thin plate, and the fourth thin plate. A joining jig located closer to the pressure member than the upper end.
請求項1に記載の接合治具において、
断面視において、前記天板から前記第1支持部材の中心、前記第2支持部材の中心、前記第3支持部材の中心または前記第4支持部材の中心までの距離は、前記天板から前記加圧部材の下端部までの距離よりも大きい、接合治具。
The joining jig according to claim 1,
In a cross-sectional view, the distance from the top plate to the center of the first support member, the center of the second support member, the center of the third support member, or the center of the fourth support member is the distance from the top plate to the center of the fourth support member. A joining jig that is larger than the distance to the bottom end of the pressure member.
天板と、
その上端部が前記天板に取り付けられた加圧部材と、
平面視において前記加圧部材を囲む支持部材と、
を備え、
半導体チップの焼結接合時において、前記半導体チップの4つの側面を前記支持部材に密着させた状態で、前記加圧部材によって前記半導体チップの上面を加圧可能である、接合治具。
The top plate and
a pressure member whose upper end is attached to the top plate;
a support member surrounding the pressure member in plan view;
Equipped with
A bonding jig capable of pressurizing an upper surface of the semiconductor chip with the pressure member while keeping four side surfaces of the semiconductor chip in close contact with the support member during sinter bonding of the semiconductor chip.
天板と、
その上端部が前記天板に取り付けられた加圧部材と、
平面視において前記加圧部材を囲むように、その上端部が前記天板に取り付けられた第1薄板、第2薄板、第3薄板および第4薄板と、
その側面が前記第1薄板の下端部に取り付けられた円柱状の第1支持部材と、
その側面が前記第2薄板の下端部に取り付けられた円柱状の第2支持部材と、
その側面が前記第3薄板の下端部に取り付けられた円柱状の第3支持部材と、
その側面が前記第4薄板の下端部に取り付けられた円柱状の第4支持部材と、
を備えた接合治具を用いた半導体装置の製造方法であって、
(a)上面と、前記上面と反対側の下面と、平面視における第1方向において互いに向き合う第1側面および第2側面と、平面視で前記第1方向と交差する第2方向において互いに向き合う第3側面および第4側面と、を有する半導体チップを用意する工程、
(b)配線基板上に焼結材を設ける工程、
(c)前記半導体チップの前記下面が前記焼結材に接触するように、前記焼結材上に前記半導体チップを搭載する工程、
(d)前記(c)工程後、平面視において前記加圧部材が前記半導体チップに重なるように、前記半導体チップの上方に前記接合治具を配置する工程、
(e)前記(d)工程後、前記接合治具を前記半導体チップに近づけることで、前記第1支持部材を前記第1側面および前記配線基板に密着させ、前記第2支持部材を前記第2側面および前記配線基板に密着させ、前記第3支持部材を前記第3側面および前記配線基板に密着させ、前記第4支持部材を前記第4側面および前記配線基板に密着させる工程、
(f)前記(e)工程後、前記接合治具を前記半導体チップに更に近づけ、前記半導体チップの前記上面を前記加圧部材によって加圧しながら、前記焼結材を加熱することで、少なくとも前記半導体チップの前記下面と前記配線基板との間に焼結層を形成する工程、
を有する、半導体装置の製造方法。
The top plate and
a pressure member whose upper end is attached to the top plate;
a first thin plate, a second thin plate, a third thin plate, and a fourth thin plate whose upper end portions are attached to the top plate so as to surround the pressure member in a plan view;
a cylindrical first support member whose side surface is attached to the lower end of the first thin plate;
a cylindrical second support member whose side surface is attached to the lower end of the second thin plate;
a cylindrical third support member whose side surface is attached to the lower end of the third thin plate;
a cylindrical fourth support member whose side surface is attached to the lower end of the fourth thin plate;
A method for manufacturing a semiconductor device using a bonding jig comprising:
(a) an upper surface, a lower surface opposite to the upper surface, a first side surface and a second side surface facing each other in a first direction in a plan view, and a first side surface and a second side surface facing each other in a second direction intersecting the first direction in a plan view; preparing a semiconductor chip having three side surfaces and a fourth side surface;
(b) a step of providing a sintered material on the wiring board;
(c) mounting the semiconductor chip on the sintered material so that the lower surface of the semiconductor chip contacts the sintered material;
(d) after the step (c), arranging the bonding jig above the semiconductor chip so that the pressure member overlaps the semiconductor chip in plan view;
(e) After the step (d), the first support member is brought into close contact with the first side surface and the wiring board by bringing the bonding jig closer to the semiconductor chip, and the second support member is brought into close contact with the second support member. bringing the third support member into close contact with the third side surface and the wiring board; bringing the fourth support member into close contact with the fourth side surface and the wiring board;
(f) After the step (e), the bonding jig is brought closer to the semiconductor chip, and while the upper surface of the semiconductor chip is pressed by the pressure member, the sintered material is heated, so that at least the forming a sintered layer between the lower surface of the semiconductor chip and the wiring board;
A method for manufacturing a semiconductor device, comprising:
請求項8に記載の半導体装置の製造方法において、
前記(f)工程において、前記焼結層は、前記下面からはみ出し、前記第1側面、前記第2側面、前記第3側面または前記第4側面の一部または全部にも形成され、
前記下面からはみ出した前記焼結層の断面は、前記第1側面、前記第2側面、前記第3側面または前記第4側面から離れるに連れて前記焼結層の厚さが小さくなるように、裾広がりのテーパ形状を成す、半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 8,
In the step (f), the sintered layer protrudes from the lower surface and is also formed on part or all of the first side, the second side, the third side, or the fourth side,
The cross section of the sintered layer protruding from the lower surface is such that the thickness of the sintered layer decreases as it moves away from the first side, the second side, the third side, or the fourth side. A method for manufacturing semiconductor devices that form a tapered shape with a widening base.
請求項8に記載の半導体装置の製造方法において、
前記(d)工程において、前記第1支持部材、前記第2支持部材、前記第3支持部材および前記第4支持部材の各々の側面のうち、最下端部となる第1の四半円点と、前記加圧部材側に位置する第2の四半円点とを含む曲面が、それぞれ、前記第1側面、前記第2側面、前記第3側面および前記第4側面の直上に位置する、半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 8,
In the step (d), a first quadrant point that is the lowest end of each side surface of the first support member, the second support member, the third support member, and the fourth support member; A semiconductor device, wherein curved surfaces including a second quarter circle point located on the pressure member side are located directly above the first side surface, the second side surface, the third side surface, and the fourth side surface, respectively. Production method.
請求項10に記載の半導体装置の製造方法において、
前記(e)工程は、
(e1)前記接合治具を前記半導体チップに近づけることで、前記第1支持部材、前記第2支持部材、前記第3支持部材および前記第4支持部材の各々の前記曲面を、前記半導体チップに接触させる工程、
(e2)前記(e1)工程後、前記接合治具を前記半導体チップに更に近づけることで、前記第1薄板を撓ませながら前記第1支持部材を前記第1側面に密着させ、前記第2薄板を撓ませながら前記第2支持部材を前記第2側面に密着させ、前記第3薄板を撓ませながら前記第3支持部材を前記第3側面に密着させ、前記第4薄板を撓ませながら前記第4支持部材を前記第4側面に密着させる工程、
(e3)前記(e2)工程後、前記接合治具を前記半導体チップに更に近づけることで、前記第1薄板を撓ませながら前記第1支持部材を前記配線基板に密着させ、前記第2薄板を撓ませながら前記第2支持部材を前記配線基板に密着させ、前記第3薄板を撓ませながら前記第3支持部材を前記配線基板に密着させ、前記第4薄板を撓ませながら前記第4支持部材を前記配線基板に密着させる工程、
を含む、半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 10,
The step (e) is
(e1) By bringing the bonding jig close to the semiconductor chip, the curved surfaces of each of the first support member, the second support member, the third support member, and the fourth support member are attached to the semiconductor chip. a step of bringing it into contact;
(e2) After the step (e1), the first support member is brought into close contact with the first side surface while the first thin plate is bent by bringing the bonding jig closer to the semiconductor chip, and the second thin plate is brought into close contact with the first side surface. The second support member is brought into close contact with the second side surface while bending the third thin plate, the third support member is brought into close contact with the third side surface while bending the third thin plate, and the second support member is brought into close contact with the third side face while bending the fourth thin plate. 4. Bringing the support member into close contact with the fourth side surface;
(e3) After the step (e2), by bringing the bonding jig closer to the semiconductor chip, the first support member is brought into close contact with the wiring board while bending the first thin plate, and the second thin plate is brought into close contact with the wiring board. The second support member is brought into close contact with the wiring board while being bent, the third support member is brought into close contact with the wiring board while the third thin plate is bent, and the fourth support member is brought into close contact with the wiring board while being bent. a step of closely contacting the wiring board with the wiring board;
A method for manufacturing a semiconductor device, including:
請求項8に記載の半導体装置の製造方法において、
前記第1薄板、前記第2薄板、前記第3薄板および前記第4薄板の各々の前記下端部は、前記第1薄板、前記第2薄板、前記第3薄板および前記第4薄板の各々の前記上端部よりも、前記加圧部材の近くに位置し、
前記(d)工程において、記第1支持部材、前記第2支持部材、前記第3支持部材および前記第4支持部材は、前記第1側面、前記第2側面、前記第3側面および前記第4側面の直上から離れた場所に位置している、半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 8,
The lower end portions of each of the first thin plate, the second thin plate, the third thin plate, and the fourth thin plate are connected to the lower end portions of each of the first thin plate, the second thin plate, the third thin plate, and the fourth thin plate. located closer to the pressure member than the upper end;
In the step (d), the first support member, the second support member, the third support member, and the fourth support member include the first side surface, the second side surface, the third side surface, and the fourth side surface. A method for manufacturing semiconductor devices that are located away from directly above the sides.
請求項12に記載の半導体装置の製造方法において、
前記(e)工程は、
(e4)前記接合治具を前記半導体チップに近づけることで、前記第1支持部材を前記配線基板に密着させ、前記第2支持部材を前記配線基板に密着させ、前記第3支持部材を前記配線基板に密着させ、前記第4支持部材を前記配線基板に密着させる工程、
(e5)前記(e4)工程後、前記接合治具を前記半導体チップに更に近づけることで、前記第1薄板を撓ませながら前記第1支持部材を前記第1側面に密着させ、前記第2薄板を撓ませながら前記第2支持部材を前記第2側面に密着させ、前記第3薄板を撓ませながら前記第3支持部材を前記第3側面に密着させ、前記第4薄板を撓ませながら前記第4支持部材を前記第4側面に密着させる工程、
を含む、半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 12,
The step (e) is
(e4) By bringing the bonding jig close to the semiconductor chip, the first support member is brought into close contact with the wiring board, the second support member is brought into close contact with the wiring board, and the third support member is brought into close contact with the wiring board. bringing the fourth support member into close contact with the wiring board;
(e5) After the step (e4), by bringing the bonding jig closer to the semiconductor chip, the first support member is brought into close contact with the first side surface while bending the first thin plate, and the second thin plate is brought into close contact with the first side surface. The second support member is brought into close contact with the second side surface while bending the third thin plate, the third support member is brought into close contact with the third side surface while bending the third thin plate, and the second support member is brought into close contact with the third side face while bending the fourth thin plate. 4. Bringing the support member into close contact with the fourth side surface;
A method for manufacturing a semiconductor device, including:
請求項8に記載の半導体装置の製造方法において、
前記第1支持部材、前記第2支持部材、前記第3支持部材および前記第4支持部材の各々の断面視における半径は、前記焼結層の厚さよりも大きく、前記焼結層の厚さおよび前記半導体チップの厚さの合計よりも小さい、半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 8,
The radius in a cross-sectional view of each of the first support member, the second support member, the third support member, and the fourth support member is larger than the thickness of the sintered layer, and A method for manufacturing a semiconductor device, wherein the thickness is smaller than the total thickness of the semiconductor chips.
請求項8に記載の半導体装置の製造方法において、
前記第1支持部材、前記第2支持部材、前記第3支持部材および前記第4支持部材は、それぞれ、前記(f)工程における前記焼結材の加熱によって融解しない材料によって構成されている、半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 8,
The first support member, the second support member, the third support member, and the fourth support member are each made of a material that does not melt due to heating of the sintered material in the step (f), a semiconductor. Method of manufacturing the device.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003243891A (en) 2002-02-13 2003-08-29 Nec Corp Chip joining device
JP2007266086A (en) 2006-03-27 2007-10-11 Toyota Motor Corp Semiconductor device and manufacturing method thereof
JP2011216772A (en) 2010-04-01 2011-10-27 Mitsubishi Electric Corp Method of manufacturing semiconductor device, and bonding jig

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0786487A (en) * 1993-09-20 1995-03-31 Toshiba Corp Semiconductor device and manufacturing method thereof
JPH07297209A (en) * 1994-04-22 1995-11-10 Mitsubishi Electric Corp Die bonding method
TW451372B (en) * 1999-06-17 2001-08-21 Shinkawa Kk Die-holding mechanism, die-packing device and die-bonding device
JP3894077B2 (en) * 2002-09-05 2007-03-14 株式会社デンソー Semiconductor device
CN101689516B (en) * 2007-06-28 2011-09-14 松下电器产业株式会社 Method for manufacturing the semiconductor element mounting structure and pressurizing tool
JP5977592B2 (en) * 2012-06-20 2016-08-24 東京応化工業株式会社 Pasting device
JP6917127B2 (en) * 2016-08-23 2021-08-11 ローム株式会社 Semiconductor devices and power modules

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003243891A (en) 2002-02-13 2003-08-29 Nec Corp Chip joining device
JP2007266086A (en) 2006-03-27 2007-10-11 Toyota Motor Corp Semiconductor device and manufacturing method thereof
JP2011216772A (en) 2010-04-01 2011-10-27 Mitsubishi Electric Corp Method of manufacturing semiconductor device, and bonding jig

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