JP7357243B2 - Semiconductor device, mounting structure of semiconductor device, and manufacturing method of semiconductor device - Google Patents

Description

The present disclosure relates to a semiconductor device, a mounting structure for a semiconductor device, and a method for manufacturing a semiconductor device.

In recent years, in order to achieve both higher density of semiconductor devices and increased number of pins of electrode terminals, attempts have been made to narrow the pitch between the electrode terminals of semiconductor devices and to reduce the area of the electrode terminals. 2. Description of the Related Art Flip-chip mounting is known as one of the techniques for mounting a semiconductor device on a mounting board, in which the pitch between electrode terminals is narrowed and the area of the electrode terminals is reduced.

In flip-chip mounting, protruding electrodes are formed on electrode terminals of semiconductor devices such as system LSIs, memories, CPUs, etc., and are pressed against electrode pads of a mounting board and heated. Then, the electrode terminals are bump-connected to the electrode pads of the mounting board, and the semiconductor device is flip-chip mounted on the mounting board.

Solder bumps are often used as protruding electrodes formed on electrode terminals. As a method of forming protruding solder bumps on electrode terminals, there is a known method in which solder is formed on the electrode terminals by, for example, screen printing, dispensing, or electrolytic plating, and then heated in a reflow oven to a temperature above the solder melting point. ing. However, as the pitch between electrode terminals becomes narrower, bridging defects are likely to occur, where melted and deformed solder bumps connect to other solder bumps due to their surface tension during the pressure bonding and heating processes during flip-chip mounting. Therefore, the stricter the requirement for narrowing the pitch between electrode terminals, the more difficult it becomes to employ solder bumps in the protruding electrodes.

Therefore, a method is known in which, instead of the solder bump, a columnar fine metal bump made of copper or the like is used for the protruding electrode formed on the electrode terminal. In this method, the tip of the protruding electrode is plastically deformed during the pressure bonding and heating process during flip-chip mounting, and the protruding electrode is bonded to the electrode pad by solid-phase diffusion. According to this method, the fine metal bumps are not melted during the pressure bonding and heating steps during flip-chip mounting, so it is possible to prevent bridge defects caused by melting and deformation of the fine metal bumps. Therefore, it becomes easy to cope with narrowing the pitch between the electrode terminals.

Furthermore, it is known that as the diameter of fine metal bumps becomes smaller and the pitch becomes narrower, a problem arises in which connection reliability decreases. For example, thermal stress caused when a semiconductor device is repeatedly used at high or low temperatures may cause problems such as cracks or disconnections at the root portions of fine metal bumps. Therefore, a structure in which an inclined pedestal portion is provided at the root portion of a fine metal bump and a method for manufacturing the same have been proposed (for example, Patent Document 1).

7A and 7B are cross-sectional views showing the structure of a semiconductor device Ua in the prior art. The semiconductor device Ua includes a plurality of electrode pads 20 on a semiconductor substrate 110, and a pedestal portion 31 is provided on the electrode pads 20. Further, the bump 32 is provided on the pedestal portion 31. The bump 32 includes a columnar portion 33 that is narrower than the pedestal portion 31 and a tapered portion 34 that gradually widens from the end of the columnar portion 33 on the pedestal portion 31 side toward the pedestal portion 31. Here, the bumps 32 are made of copper, for example, and the columnar portions 33 are, for example, cylindrical.

According to the prior art, by providing the taper portion 34 at the base of the bump 32, thermal stress caused by repeated high and low temperatures can be alleviated, thereby providing a semiconductor device and a wiring board that can improve connection reliability. It is said that it can be done.

Japanese Patent Application Publication No. 2014-3201

By the way, in semiconductor components that are becoming smaller and faster in transmission, the dielectric constant of insulating layers used in semiconductor devices Ua and circuit boards Ba is becoming lower, and the weakening of such insulating layers is noticeable.

FIG. 7B is a cross-sectional view showing the mounting structure of the semiconductor device Ua in the prior art.

The electrode pad 122 of the circuit board Ba and the electrode pad 20 of the semiconductor device Ua are bonded via bumps 32. Here, the circuit board Ba has a fragile insulating layer 121 on the board body 120 and has electrode pads 122 on the insulating layer 121.

This mounting structure is constructed by bringing the semiconductor device Ua closer to the circuit board Ba and connecting the bumps 32 of the semiconductor device Ua to the electrode pads 122 of the circuit board Ba.

Here, since the top of the columnar portion 33 of the bump 32 is flat and the thickness of the tapered portion 34 is extremely thin compared to the columnar portion 33, the amount of deformation of the bump 32 is extremely small. As a result, in the mounting process, compressive stress acts on the electrode pad 122, and further compressive stress acts on the fragile insulating layer 121 below the electrode pad 122. At this time, if the compressive stress exceeds the destructive stress of the insulating layer 121, there is a problem in that the insulating layer 121 suffers from mounting defects such as breaks and cracks. Furthermore, there is also a problem in that the electrical characteristics of the transistor layer under the insulating layer 121 vary due to the compressive stress.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a semiconductor device, a mounting structure for a semiconductor device, and a method for manufacturing a semiconductor device that can alleviate stress applied to a circuit board during a mounting process.

The main disclosure that solves the above-mentioned problems is:
A semiconductor device including a plurality of electrode pads,
having a bump on each of the plurality of electrode pads;
The bump has a tapered part, a stress relaxation part, and a columnar part in order from the electrode pad side,
The tapered portion has a straight slope;
The stress relaxation part has a truncated cone shape in which the bottom area is larger than the top area and the slope is curved inward,
The stress relaxation part has a shape in which a side surface of the stress relaxation part bulges laterally from a bottom surface of the stress relaxation part,
The bump has a constricted shape on the ground plane of the tapered part and the stress relaxation part ,
It is a semiconductor device.

Also, in other situations,
The above semiconductor device,
a circuit board disposed to face the semiconductor device and having a plurality of board-side electrode pads;
the plurality of electrode pads of the semiconductor device and the plurality of substrate-side electrode pads of the circuit board are respectively connected via the bumps;
Mounting structure of semiconductor devices.

Also, in other situations,
A method of manufacturing a semiconductor device including a plurality of electrode pads, the method comprising:
a seed layer forming step of forming a seed layer so as to cover the plurality of electrode pads;
a resist forming step of forming a resist covering the seed layer;
A resist in which a nanoimprint mold is pressed from an upper surface side of the resist against a region of the resist where the plurality of electrode pads are formed, and a plurality of openings that do not reach the electrode pads are formed in the resist. opening process,
a resist curing step of applying light energy to the resist from the upper surface side of the resist, and then performing heat treatment to harden the resist;
a developing step of causing the resist to react with a developer and causing the opening to reach the electrode pad so that the opening width of the opening increases toward the electrode pad;
a metal filling step of filling the opening with metal to form a bump;
a peeling step of peeling off the resist;
A method of manufacturing a semiconductor device comprising:
The development step includes:
In the vicinity of the seed layer of the resist, the opening width expands radially due to the wettability of the seed layer;
In the resist other than in the vicinity of the seed layer, the opening width is expanded in the vertical and planar directions depending on the degree of crosslinking of the resist,
The bump has a tapered part, a stress relaxation part, and a columnar part in order from the electrode pad side,
The stress relaxation part has a truncated cone shape with a bottom area larger than the top area and an inwardly curved slope.
This is a method for manufacturing a semiconductor device.

According to the semiconductor device according to the present disclosure, it is possible to alleviate stress applied to the circuit board side in the mounting process.

Cross-sectional diagram illustrating the structure of a semiconductor device according to Embodiment 1 Cross-sectional diagram illustrating the structure of a semiconductor device according to Embodiment 1 Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to Embodiment 1 Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to Embodiment 1 Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to Embodiment 1 Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to Embodiment 1 Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to Embodiment 1 Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to Embodiment 1 Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to Embodiment 1 Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to Embodiment 1 Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to Embodiment 1 Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to Embodiment 1 A conceptual diagram of a cross-sectional view of a semiconductor device detailing the development process shown in FIG. 2E A conceptual diagram of a cross-sectional view of a semiconductor device detailing the development process shown in FIG. 2E A conceptual diagram of a cross-sectional view of a semiconductor device detailing the development process shown in FIG. 2E A conceptual diagram of a cross-sectional view of a semiconductor device detailing the development process shown in FIG. 2E Enlarged view of bumps of the semiconductor device according to Embodiment 1 Enlarged view of bumps of the semiconductor device according to Embodiment 1 Cross-sectional diagram illustrating the structure of a semiconductor device according to a second embodiment Cross-sectional diagram illustrating the structure of a semiconductor device according to a second embodiment Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment Cross-sectional diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment Cross-sectional view showing the structure of a semiconductor device in conventional technology Cross-sectional view showing the structure of a semiconductor device in conventional technology

In view of the above-mentioned problems, the present disclosure provides a structure and a manufacturing method of a semiconductor device that is provided with a protruding electrode that relieves stress during mounting in a semiconductor device that is increasingly becoming more pin-multiplexed and more fragile. Embodiments of the present disclosure will be described below with reference to the drawings.

Further advantages and effects of one aspect of the disclosure will become apparent from the specification and drawings. Such advantages and/or effects may be provided by each of the embodiments and features described in the specification and drawings, but not necessarily all to obtain one or more of the same features. There's no need.

[Embodiment 1]
<Structure of semiconductor device>
1A and 1B are cross-sectional views illustrating the structure of a semiconductor device U according to the first embodiment.

FIG. 1A is a cross-sectional view showing the structure of a semiconductor device U before mounting. Note that in the following description, in order to explain the positional relationship of the members, the normal direction of the surface of the semiconductor device U on which the electrode pads 2 are formed will be referred to as an upward direction. However, this direction does not indicate the posture of the semiconductor device U when it is used.

The semiconductor device U has a structure in which an electrode pad 2, an insulating film 3, a seed layer 4, and a bump 5 are formed in this order on a device body 1.

The device main body 1 is, for example, a semiconductor element such as a transistor, a rectifying element, a sensor element, a light emitting element, or a light receiving element. The device main body 1 has a structure in which a semiconductor element is formed in a semiconductor substrate of silicon, gallium arsenide, gallium nitride, silicon carbide, indium gallium arsenide, gallium nitride, or indium phosphide, for example. Note that the device main body 1 may be a discrete device or a monolithic IC.

The electrode pad 2 is made of metal, such as gold, copper, aluminum, aluminum silicon, aluminum copper, or tungsten. Note that a plurality of electrode pads 2 are provided on the device main body 1.

An insulating film 3 having an opening is provided on the electrode pad 2, a seed layer 4 is formed on the insulating film 3, a bump 5 is formed on the seed layer 4, and the bump 5 and the electrode pad 2 are connected to each other. It is electrically conductive. Note that the bumps 5 are formed on each of the plurality of electrode pads 2.

Here, the bump 5 has a structure in which a tapered part 5a, a stress relaxation part 5b, and a columnar part 5c are formed in order from the electrode pad 2 side, and the bottom side of the bump 5 (representing the base end side of the bump 5). The diameter gradually decreases from the top side of the bump 5 (representing the tip side of the bump 5; the same applies below). There is no gap at the interface between the tapered part 5a and the stress relaxation part 5b, and between the stress relaxation part 5b and the columnar part 5c, and they are integrally formed. Therefore, the bumps 5 have high bonding strength to the electrode pads 2, and do not peel off from the electrode pads 2 even if high stress is applied to the bumps 5 during the mounting process or in the usage environment. The bumps 5 are made of a conductive material, such as copper, cobalt, gold, silver, etc.

The seed layer 4 is a thin conductive layer that is formed over the entire upper surface of the device body 1 and is used as an electrode in the metal filling process. If the metal filling process is an electroplating process, the seed layer 4 is also used as a base layer for forming the electroplating. Seed layer 4 is made of copper, cobalt, gold, titanium, and chromium, for example. The electrode pads 2 have a pitch of, for example, 10 μm and a diameter of 8 μm.

FIG. 1B is a cross-sectional view showing a mounting structure in which the semiconductor device U shown in FIG. 1A is mounted on a circuit board B.

The circuit board B has, for example, a structure in which an insulating layer 10 and an electrode pad 7 are formed in this order on a board body 6.

The substrate body 6 is made of, for example, silicon, gallium arsenide, indium phosphide, indium gallium arsenide, silicon carbide, gallium nitride, or the like. Further, the electrode pad 7 is made of, for example, gold, gold-nickel, copper, aluminum, aluminum copper, aluminum silicon, or the like. Electric circuits such as transistors are formed on the substrate body 6.

The insulating layer 10 is an insulating film provided to electrically insulate the transistor layer (or wiring layer) formed on the substrate body 6 from the outside of the substrate body 6. The insulating layer 10 is made of, for example, an inorganic film, such as SiN, SiO ₂ , tetraethyl orthosilicate, F-doped SiO ₂ , SiOC, or the like. The thickness of the insulating layer 10 is, for example, 10 nm to 3 μm.

The electrode pad 7 (hereinafter also referred to as "substrate-side electrode pad 7") is provided to electrically connect the electric circuit within the substrate body 6 and an external device (here, semiconductor device U). A plurality of electrode pads 7 are formed on the insulating layer 10.

In the mounting structure of the semiconductor device U, the electrode pads 2 of the semiconductor device U and the electrode pads 7 of the circuit board B are arranged so that their positions match and face each other, and the electrode pads 2 and 7 are arranged as follows. The bumps 5 are joined via compressed bumps 5'. Hereinafter, the reference numerals with "'" indicate those that have been compressed and deformed.

Even after the bump 5' is mounted, it is composed of three constituent parts: the tapered part 5a', the stress relaxation part 5b', and the columnar part 5c', as before the bump 5' is mounted.

Note that a sealing resin 11 is filled between the semiconductor device U and the circuit board B.

<Method for manufacturing semiconductor devices>
2A to 2J are cross-sectional views illustrating a method for manufacturing the semiconductor device U according to the first embodiment.

First, the seed layer forming process shown in FIG. 2A will be described.

A plurality of electrode pads 2 are formed on the upper surface of the device main body 1. Further, an insulating film 3 is formed on the electrode pad 2 and has an opening through which a part of the electrode pad 2 is exposed. The insulating film 3 is formed by, for example, plasma CVD or solution spin coating. The insulating film 3 is then subjected to heat treatment, and then an opening is formed by a photolithography process. As a result, the upper surface of the electrode pad 2 is exposed through the opening formed in the insulating film 3.

Further, a seed layer 4 is formed to cover the exposed portions of the insulating film 3 and the electrode pads 2. The semiconductor device U is supplied, for example, in the form of a wafer. For example, it is 6 inches, 8 inches, or 12 inches round.

The seed layer 4 is a thin conductive layer that is formed on the entire upper surface of the device body 1 so as to cover the plurality of electrode pads 2, and is used as an electrode in the metal filling process. If the metal filling process is an electroplating process, the seed layer 4 is also used as a base layer for forming the electroplating. The material of the seed layer 4 may be, for example, Ni, W, Cr, Cu, Co, Ti, Au, or the like. The thickness of the seed layer 4 may be, for example, 0.02 to 2 μm.

The resist forming process shown in FIG. 2B will be described.

After the seed layer 4 is formed, a resist 8 is formed on the seed layer 4. The resist 8 is, for example, a chemically amplified negative resist. The resist 8 is formed using, for example, spin coating, a bar coater, spraying, jet dispensing, etc. so that the film is uniform.

Next, the resist opening step shown in FIG. 2C will be described. Alignment is performed so that the position of the protrusion 9a provided on the nanoimprint mold 9 matches the position of the electrode pad 2 provided on the semiconductor device U, and the protrusion 9a is placed in the resist 8 softened by heating and pressurizing means. Push it in. Furthermore, the nanoimprint mold 9 is stopped at a position where the resist 8 remains between the protrusion 9a and the electrode pad 2. Next, the nanoimprint mold 9 is pulled up, and an opening 8c (see FIG. 2D) is formed in the resist 8. The opening 8c formed by the nanoimprint mold 9 opens vertically. Note that the nanoimprint mold 9 has a plurality of protrusions 9a so that openings 8c are formed at positions corresponding to the plurality of electrode pads 2, respectively. The plurality of openings 8c formed by the nanoimprint mold 9 are each formed in the same shape.

Here, the nanoimprint mold 9 is a transfer mold in which minute protrusions 9a having the same size and shape as the openings 8c formed in the resist 8 are provided on one side at predetermined intervals. A protrusion 9 a is formed on the nanoimprint mold 9 at a position facing the electrode pad 2 . The shape of the protrusion 9a may be, for example, a circle, a square, or an octagon.

The nanoimprint mold 9 may be formed from, for example, one of quartz, glass, electroformed nickel, silicon, and silicone resin, or may be formed by laminating a plurality of them. For example, it is preferable to use a flexible silicone resin on the upper surface of the nanoimprint mold 9 because it can absorb the warpage and waviness of the semiconductor device U. The nanoimprint mold 9 may be formed, for example, by producing an original plate and then causing the material of the nanoimprint mold 9 to flow and harden.

Here, the original plate to be produced has a plurality of recesses at intervals equal to the intervals between the openings 8c formed in the resist 8 and having dimensions equivalent to the opening diameter of the openings 8c. The original plate may be formed, for example, by etching or electrical discharge machining of silicon, quartz, or glass. The external dimensions of the nanoimprint mold 9 need only be larger than the external dimensions of the semiconductor device U. Further, the shape of the nanoimprint mold 9 is, for example, a rectangle.

Next, the resist curing process shown in FIG. 2D will be described. As shown in FIG. 2D, light energy with which the resist 8 reacts is applied to the entire surface of the resist 8 in which the opening 8c is formed. First, the resist 8 is irradiated with light, for example, ultraviolet light, and then the resist 8 is heated. Here, in the resist 8, the portion near the top surface of the resist 8 receives a larger amount of light energy irradiation than the portion near the seed layer 4, so more acid generator reacts and the acid concentration becomes higher. Next, a crosslinking reaction is caused by heating means. Depending on the acid concentration, the closer to the upper surface of the resist 8 the higher the degree of crosslinking becomes, and the closer to the seed layer 4 the lower the degree of crosslinking becomes. Here, as the heating means, for example, a batch type oven, a reflow oven, induction heating, infrared heating, a hot plate, etc. are used.

Next, in the developing step shown in FIG. 2E, the semiconductor device U is immersed in a developer. As the developer enters the opening 8c, the inner wall of the opening 8c of the resist 8 progresses, expands in the radial direction (that is, widens the opening width), and defines the outer shape of the stress relaxation section 5b and the tapered section 5a. Openings 8b and 8a are formed. The details of the process of forming the openings 8b and 8a by the development process will be described later. Here, the developer has the effect of dissolving the resist 8. The developer may be, for example, an aqueous solution of tetramethylammonium hydroxide or trimethyl-2-hydroxyethylammonium hydroxide. Furthermore, the residue of the developer that has entered the openings 8a, 8b, and 8c is removed by the cleaning solution. The cleaning liquid is, for example, pure water.

Next, in the plating step shown in FIG. 2F, the seed layer 4 of the semiconductor device U is connected to a power source, immersed in an electrolytic plating bath, and subjected to an energization process. As a result, the openings 8a, 8b, 8c shown in FIG. 2E are filled with plating. The plating solution may be a bottom-up type filled plating solution made of Cu, Co, Au, etc., for example. When these plating solutions are used, the wettability of the inner walls of the openings 8a, 8b, and 8c increases due to the catalytic effects of Cu, Co, Au, etc., making it easy to inject the plating solution even into minute openings. Therefore, it is suitable for forming plating from the bottom up. By controlling the plating time so that the plating height does not exceed the upper surface of the resist 8, a plating bump 5 consisting of a tapered portion 5a, a stress relaxation portion 5b, and a columnar portion 5c is formed.

Next, in the resist stripping step shown in FIG. 2G, the resist 8 is immersed in a resist stripping solution and stripped from the semiconductor device U. As the resist stripping solution, for example, acetone, toluene, N,N-dimethylacetamide, etc. are used.

Next, in the seed layer removal step shown in FIG. 2H, when the seed layer 4 is removed by wet etching or ashing processing, bumps 5 are formed.

Here, if a material with a faster etching rate than the bumps 5 is used for the seed layer 4, the amount of etching of the bumps 5 can be reduced in the seed layer removal process, and the bump shape after the resist stripping process can be maintained. suitable. The seed layer 4 under the bump 5 is left as a conductive film.

Next, in the semiconductor mounting process shown in FIG. 2I, the semiconductor device U and the circuit board B, which have been diced by a singulation means such as dicing, are made to face each other, and the bumps 5 of the semiconductor device U and the circuit board B are separated. Alignment is performed so that the electrode pads 7 are aligned, and the bumps 5 and the electrode pads 7 are metal diffusion bonded using pressure means. Here, in addition to pressurization, heating means or ultrasonic application means may be added. By adding heating means or ultrasonic application means, the bonding strength can be increased. Here, as the bumps 5 are compressively deformed, the stress applied to the insulating layer 10 can be alleviated. Furthermore, a conductive material may be supplied to the electrode pad 7. By using the conductive material, the bonding temperature and bonding load can be lowered, and the stress applied to the insulating layer 10 during bonding can be further reduced. As the conductive material, for example, nanopaste made of gold ink, silver ink, copper ink, etc., solder paste such as SnAgCu, SnAg, Sn, SnBi, SnAgBiIn, SnIn, etc. are used.

Finally, in the sealing step shown in FIG. 2J, the sealing resin 11 is injected between the semiconductor device U and the circuit board B, and is cured by heating means or ultraviolet light means to form the sealing resin 11. A mounting structure is formed. The sealing resin 11 is made of, for example, epoxy, acrylic, silicone resin, or the like.

Note that in the first embodiment of the present invention, the resist 8 is described as a chemically amplified resist, but is not limited to this. It may be a photosensitive type, a thermosetting type, or a combined photothermal type resist.

<Resist opening formation process>
3A to 3D are conceptual diagrams of cross-sectional views of the semiconductor device U detailing the developing process shown in FIG. 2E.

As shown in FIG. 3A, the opening 8c of the resist 8 is provided with a constant width and depth within the plane of the semiconductor device U, leaving a residual film of the resist 8 on the electrode pad 2 without penetrating it. It will be done.

Next, as shown in FIG. 3B, when the semiconductor device U is immersed in the developer, the developer enters the opening 8c at a uniform speed within the surface of the semiconductor device U. Thereafter, the dissolution of the resist 8 progresses depending on the degree of crosslinking of the resist 8. Since the portions of the resist 8 with a low degree of crosslinking dissolve faster than the portions of the resist 8 with a high degree of crosslinking, by controlling the degree of crosslinking of the resist 8, the shape of the opening 8b can be controlled. Here, the resist 8 is hardened by light energy irradiated from its upper surface side in the resist hardening process shown in FIG. 2D. Therefore, the degree of crosslinking of the resist 8 decreases from the upper surface toward the electrode pad 2. As a result, the developer dissolves the resist 8 closer to the bottom surface of the opening 8c, and the opening 8c of the resist 8 expands not only in the vertical direction but also in the planar direction. This forms an opening 8b that defines the outer shape of the stress relaxation section 5b.

Furthermore, as shown in FIG. 3C, the openings 8b, 8c reach even the seed layer 4.

Thereafter, as shown in FIG. 3D, due to the ease with which the developer and the seed layer 4 wet in the vicinity of the seed layer 4, the developer wets and spreads radially around the opening 8b on the seed layer 4, and the tapered portion An opening 8a corresponding to the outer shape of 5a is formed.

As described above, according to the present embodiment, the openings 8a, 8b, which define the external shapes of the tapered part 5a, the stress relaxation part 5b, and the columnar part 5c of the bump 5, are formed in a series of processes without interrupting the process. Form 8c. As a result, when the tapered part 5a, stress relaxation part 5b, and columnar part 5c are formed in the subsequent process, there is no interface between them, there is no positional shift, and a stable shape is ensured within the U plane of the semiconductor device. can do.

<Bump shape>
4A and 4B are enlarged views of bumps 5 of semiconductor device U. FIG. 4A shows the state of the semiconductor device U before mounting, and FIG. 4B shows the state of the semiconductor device U after mounting.

<Tapered portion 5a>
Tapered portion 5 a is provided on seed layer 4 . The tapered portion 5a has a truncated cone shape in which the bottom area is larger than the top area. The tapered portion 5a has the effect of increasing the shear strength between the bump 5 and the seed layer 4.

The tapered portion 5a has a surface area closer to the electrode pad 2, that is, a bottom surface, which has a larger area than an upper surface, and the side surfaces have slopes. Further, the diameter of the bottom surface of the tapered portion 5a is preferably greater than or equal to the diameter of the electrode pads 2 and less than 0.95 times the pitch of the electrode pads 2. If the diameter is less than the diameter of the electrode pad 2, the bonding strength of the bump will decrease, and there will be an increased risk of breakage due to repeated high and low temperatures after bonding. If the pitch is 0.95 times or more than the pitch of the electrode pads 2, there is a risk that the bumps 5 will be compressed after bonding and the adjacent bumps 5 will be connected, resulting in an electrical short circuit. The thickness of the tapered portion 5a is preferably 0.2 to 3 μm. If it is thinner than 0.2 μm, no effect of improving bonding strength will be observed, and if it is 3 μm or more, the amount of compressive deformation during bonding will increase, increasing the risk of short-circuit failure.

<Stress relaxation part 5b>
The stress relaxation part 5b is provided such that the bottom surface of the stress relaxation part 5b is in close contact with the tapered part 5a, and the top surface of the stress relaxation part 5b is in close contact with the columnar part 5c.

The stress relaxation part 5b has a truncated cone shape in which the bottom diameter D2 (i.e., bottom area) is larger than the top diameter D1 (i.e., top area), and the slope is curved inward. Since the stress relaxation portion 5b has a top surface diameter D1 smaller than a bottom surface diameter D2, when compressive stress is applied to the bump 5, the stress relaxation portion 5b can be deformed more greatly than when the diameters are the same.

Note that the stress relaxation portion 5b has a shape in which the bottom side (near the boundary with the tapered portion 5a) expands in the lateral direction. Further, the top surface diameter D1 of the stress relaxation section 5b is approximately the same as the bottom surface diameter of the columnar section 5c, and the bottom surface diameter D2 of the stress relaxation section 5b is approximately the same as the top surface diameter of the tapered section 5a.

It is desirable that the height H2 of the stress relaxation part 5b is 1/2 or more of the height H of the bump 5.

<Columnar part 5c>
The columnar portion 5c is provided so as to be in close contact with the upper surface of the stress relief portion 5b, and has a cylindrical shape that stands upward from the upper surface of the stress relief portion.The diameter of the columnar portion 5c is the upper surface diameter D1 of the stress relief portion 5b. The columnar portion 5c is formed with the diameter D1 in the height direction. Note that the diameter of the columnar portion 5c is smaller than the top surface diameter of the tapered portion 5a (ie, the bottom surface diameter D2 of the stress relaxation portion 5b). The shape of the columnar portion 5c may be, for example, a polygonal columnar shape or an elliptical columnar shape instead of a cylindrical shape.

FIG. 4B shows an enlarged view of the mounting structure of the semiconductor device U. Of the bump 5', the stress relaxation part 5b' and the columnar part 5c' are both compressed and expanded in the plane direction. The height H2' of the stress relaxation part 5b' after mounting is lower than the height H2 of the stress relaxation part 5b before mounting, and the bottom diameter D2' of the stress relaxation part 5b after mounting is lower than the height H2' of the stress relaxation part 5b before mounting. is larger than the bottom diameter D2. Further, the height H1' of the columnar part 5c' after mounting is lower than the height H1 of the columnar part 5c before mounting, and the bottom diameter (i.e., the top diameter of the stress relaxation part) D1 of the columnar part 5c after mounting. ' is larger than the bottom diameter of the columnar portion 5c before mounting.

From this point of view, the diameter of the columnar part 5c before mounting (i.e., the top surface diameter D1 of the stress relaxation part 5b) is preferably smaller than the diameter of the electrode pad 2, and preferably 1/2 or less of the diameter of the electrode pad 2. Even better. The deformation of the bumps 5 not only reduces the load on the fragile insulating layer 10, but also has the effect of not being electrically connected to the adjacent bumps 5 after compression.

<Effect>
As described above, according to the first embodiment, it is possible to mount the semiconductor device U on the circuit board B without destroying the fragile insulating layer 10 formed on the surface of the circuit board B. This makes it possible to improve manufacturing yield.

[Embodiment 2]
The second embodiment differs from the first embodiment in that the tip of the bump 5 is provided with a hemispherical dome-shaped hemispherical portion 5d. Items not explained are the same as in the first embodiment.

<Structure of semiconductor device>
5A and 5B are cross-sectional views illustrating the structure of a semiconductor device U according to the second embodiment. 5A shows the structure of the semiconductor device U before mounting, and FIG. 5B shows the structure of the semiconductor device U after mounting.

As shown in FIG. 5A, the bump 5 includes, in order from the electrode pad 2 side, a tapered part 5a, a stress relaxation part 5b, a columnar part 5c, and a hemispherical part 5d.

After the semiconductor device U is mounted on the circuit board B, the tip of the hemispherical portion 5d' becomes flat, the diameter of the hemispherical portion 5d' becomes larger than before mounting, and the height of the hemispherical portion 5d' becomes lower. At this time, the hemispherical portion 5d' and the electrode pad 7 of the circuit board B are joined by metal diffusion.

Since the portion inside the bump 5 that is compressed and deformed increases, stress applied to the insulating layer 10 during semiconductor mounting can be reduced. Furthermore, since the stress concentration point after mounting is at the narrowest columnar portion 5c', the stress applied to the insulating layer 10 due to thermal stress due to heating and cooling can be greatly reduced.

The hemisphere portion 5d has a rounded top surface and a flat bottom surface, and is part of a sphere. The bottom surface of the hemispherical portion 5d is provided in close contact with the tip of the columnar portion 5c. The diameter of the hemispherical portion 5d is larger than the diameter of the columnar portion 5c.

<Method for manufacturing semiconductor devices>
6A to 6J are cross-sectional views illustrating a method of manufacturing a semiconductor device U according to the second embodiment.

The method for manufacturing a semiconductor device according to the present embodiment is that in the plating process shown in FIG. This is different from the manufacturing method of device U. The other steps in FIGS. 6A to 6E and 6G to 6J are the same as the steps in FIGS. 2A to 2E and 2G to 2J.

<Effect>
As described above, according to the second embodiment, when the semiconductor device U is mounted on the circuit board B, the stress acting on the insulating layer 10 formed on the surface of the circuit board B can be further alleviated. is possible. This makes it possible to improve manufacturing yield.

According to the semiconductor device according to the present disclosure, it is possible to alleviate stress applied to the circuit board side in the mounting process.

U Semiconductor device 1 Device body 2 Electrode pad 3 Insulating film 4 Seed layer 5, 5' Bump 5a, 5a' Taper part 5b, 5b' Stress relaxation part 5c, 5c' Column part 5d, 5d' Hemisphere part B Circuit board 6 Substrate Main body 7 Electrode pad (substrate side electrode pad)
8 Resist 8a, 8b, 8c Opening 9 Nanoimprint mold 9a Projection 10 Insulating layer 11 Sealing resin

Claims (8)

A semiconductor device including a plurality of electrode pads,
having a bump on each of the plurality of electrode pads ;
The bump has a tapered part, a stress relaxation part, and a columnar part in order from the electrode pad side,
The tapered portion has a straight slope;
The stress relaxation part has a truncated cone shape in which the bottom area is larger than the top area and the slope is curved inward,
The stress relaxation part has a shape in which a side surface of the stress relaxation part bulges laterally from a bottom surface of the stress relaxation part,
The bump has a constricted shape on the ground plane of the tapered part and the stress relaxation part,
Semiconductor equipment. The tapered portion has a truncated cone shape in which the bottom area is larger than the top area.
The semiconductor device according to claim 1. The height of the stress relaxation part is 1/2 or more of the height of the entire bump,
The semiconductor device according to claim 1 or 2 . The columnar portion has a cylindrical shape that stands upward from the upper surface of the stress relaxation portion.
The semiconductor device according to any one of claims 1 to 3 . The bump has a hemispherical part at the tip of the columnar part,
The semiconductor device according to any one of claims 1 to 4 . The diameter of the hemispherical part is larger than the diameter of the columnar part,
The semiconductor device according to claim 5 . A semiconductor device according to any one of claims 1 to 6 ,
a circuit board disposed to face the semiconductor device and having a plurality of board-side electrode pads;
the plurality of electrode pads of the semiconductor device and the plurality of substrate-side electrode pads of the circuit board are respectively connected via the bumps;
Mounting structure of semiconductor devices. A method of manufacturing a semiconductor device including a plurality of electrode pads, the method comprising:
a seed layer forming step of forming a seed layer so as to cover the plurality of electrode pads;
a resist forming step of forming a resist covering the seed layer;
A resist in which a nanoimprint mold is pressed from an upper surface side of the resist against a region of the resist where the plurality of electrode pads are formed, and a plurality of openings that do not reach the electrode pads are formed in the resist. opening process,
a resist curing step of applying light energy to the resist from the upper surface side of the resist, and then performing heat treatment to harden the resist;
a developing step of causing the resist to react with a developer and causing the opening to reach the electrode pad so that the opening width of the opening increases toward the electrode pad;
a metal filling step of filling the opening with metal to form a bump;
a peeling step of peeling off the resist;
A method of manufacturing a semiconductor device comprising:
The development step includes:
In the vicinity of the seed layer of the resist, the opening width expands radially due to the wettability of the seed layer;
In the resist other than in the vicinity of the seed layer, the opening width is expanded in the vertical and planar directions depending on the degree of crosslinking of the resist,
The bump has a tapered part, a stress relaxation part, and a columnar part in order from the electrode pad side,
The stress relaxation part has a truncated cone shape with a bottom area larger than the top area and an inwardly curved slope.
A method for manufacturing a semiconductor device.

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