JP7360968B2 - DC voltage generation circuit - Google Patents

Description

The invention disclosed herein relates to a DC voltage generation circuit.

Conventionally, reference voltage generation circuits using depletion type NMOSFETs and enhancement type NMOSFETs have been known. A general configuration is such that a depletion type NMOSFET and an enhancement type NMOSFET are connected in a totem pole configuration, and the voltage between VGS and VGS of the depletion type NMOSFET is set to 0V.

Note that Patent Document 1 can be mentioned as an example of the conventional technology related to the above.

Patent No. 6317269 specification

However, in the technique described in Patent Document 1, there is room for further improvement regarding the temperature characteristics of the DC voltage.

In view of the above problems discovered by the inventor of the present application, the invention disclosed herein aims to provide a DC voltage generation circuit that can suppress variations in temperature characteristics. .

The DC voltage generation circuit disclosed herein includes a differential pair configured of a first depletion type MOSFET and a second enhancement type MOSFET, and a current source that drives the differential pair, A configuration (first configuration) may be adopted in which a DC voltage is generated based on a threshold voltage difference between the first MOSFET and the second MOSFET.

Further, in the DC voltage generation circuit having the first configuration, a configuration (second configuration) may be adopted in which a first resistor is provided between the gate of the first MOSFET and the gate of the second MOSFET.

Furthermore, in the DC voltage generation circuit having the second configuration, the first resistor may have a configuration in which the resistance value can be adjusted (third configuration).

Furthermore, in the DC voltage generation circuit having the second or third configuration, a configuration (fourth configuration) may be adopted in which a second resistor is provided between the gate of the first MOSFET and the reference voltage.

Furthermore, in the DC voltage generation circuit having the fourth configuration, the second resistor may have a configuration in which the resistance value can be adjusted (fifth configuration).

Furthermore, in the DC voltage generation circuit having the fourth or fifth configuration, the first resistor and the second resistor may be made of the same material (sixth configuration).

Further, in the DC voltage generation circuit having the first to sixth configurations, a third resistor provided between the source of the first MOSFET and the current source, and a third resistor provided between the source of the second MOSFET and the current source. A configuration (seventh configuration) may be adopted in which at least one of the fourth resistors is provided.

Further, the DC voltage generation circuit having a seventh configuration includes at least the third resistor, and the third resistor has an adjustable resistance value, or includes at least the fourth resistor, and the fourth resistor has an adjustable resistance value. The resistor may have a configuration in which the resistance value can be adjusted (eighth configuration).

Further, in the DC voltage generation circuit having a seventh or eighth configuration, the third resistor and the fourth resistor are both made of the same material (a ninth configuration).

Furthermore, the DC voltage generation circuit having the first to ninth configurations may further include a current mirror circuit that can adjust the ratio of current flowing through the first MOSFET and the second MOSFET (a tenth configuration).

Further, in the DC voltage generation circuit having the first to tenth configurations, the first MOSFET and the second MOSFET may be configured to operate in a weak inversion region (eleventh configuration).

According to the invention disclosed herein, it is possible to generate a DC voltage that does not depend on temperature variations in carrier mobility.

A diagram showing a first embodiment of the DC voltage generation circuit 1 Diagram showing the value of threshold voltage difference ΔVt depending on temperature A diagram showing a second embodiment of the DC voltage generation circuit 1 A diagram showing a third embodiment of the DC voltage generation circuit 1 A diagram showing the amount of temperature fluctuation of the reference voltage Vref when the value of the third resistor R3 is varied. A diagram showing a fourth embodiment of the DC voltage generation circuit 1 A diagram showing an example of an application using the DC voltage generation circuit 1

<(First embodiment)>
FIG. 1 is a diagram showing a first embodiment of a DC voltage generation circuit 1. As shown in FIG. The DC voltage generation circuit 1 of the first embodiment includes a differential pair 10, a current source 20, a reference voltage generation section 30, a load section 40, and a DC voltage output section 50. 40 and a DC voltage output section 50. The DC voltage VDC is output from the DC voltage output section 50 to generate the output voltage of the DC voltage generation circuit 1.

The differential pair 10 is composed of a depletion type MOSFET (hereinafter referred to as the first transistor Tr1) and an enhancement type MOSFET (hereinafter referred to as the second transistor Tr2), and the sources of the first transistor Tr1 and the second transistor Tr2 are connected to the node N1. It is connected. Furthermore, the gates of the first transistor Tr1 and the second transistor Tr2 are connected to the reference voltage generation section 30, forming a differential pair. Furthermore, the drains of the first transistor Tr1 and the second transistor Tr2 are connected to the load section 50. Note that the channel widths W1 and W2 and the channel lengths L1 and L2 of the first transistor Tr1 and the second transistor Tr2 may be adjustable by trimming each value at the time of product shipment according to the specifications of the DC voltage.

Current source 20 sinks current from node N1 and releases current to reference voltage Vst. Although the current source 20 is not particularly specified, it may be a current source configured by a current mirror circuit configured within the same semiconductor chip. Further, the current source 20 may be configured to be adjustable so as to have a current value that causes the first transistor Tr1 and the second transistor Tr2 to operate in the weak inversion region.

The reference voltage generation unit 30 uses the reference voltage Vst as a reference voltage, generates a reference voltage Vref based on a threshold voltage difference ΔVt that is the difference between the threshold voltage of the first transistor Tr1 and the threshold voltage of the second transistor Tr2, and generates a DC voltage. Output to the output section 50.

The load section 40 may be connected to the differential pair 10, generate a load voltage VL according to the current supplied to the differential pair 10, and output it to the DC voltage output section 50.

The DC voltage output section 50 may generate a DC voltage VDC based on the reference voltage Vref and output it as the output voltage of the DC voltage generation circuit 1. Alternatively, the DC voltage VDC may be generated based on the load voltage VL from the load section 40 and the reference voltage Vref from the reference voltage generation section and output as the output voltage of the DC voltage generation circuit 1.

Next, the reference voltage Vref when both the first transistor Tr1 and the second transistor Tr2 operate in the weak inversion region will be explained. In the weak inversion region, the following equations hold true for the drain current Id1 flowing through the first transistor Tr1 and the drain current Id2 flowing through the second transistor Tr2.

Id1=W1/L1×Is1×exp[e×(Vgs1-Vth1)×γ/(Kb×T)]… (1)
Id2=W2/L2×Is2×exp[e×(Vgs2-Vth2)×γ/(Kb×T)]… (2)
Note that in equation (1), W1, L1, Is1, Vgs1, and Vth1 represent the channel width, channel length, saturation current, gate-source voltage, and threshold voltage of the first transistor Tr1, and in equation (2), W2, L2, Is2, Vgs2, and Vth2 indicate similar parameters in the second transistor Tr2. Further, e represents the elementary charge, γ represents the weak inversion slope coefficient, Kb represents the Boltzmann constant, and T represents the absolute temperature.

Furthermore, in the above equations (1) and (2), if Id1=Id2, the following equation holds true.
W1/L1×Is1×exp[e×(Vgs1-Vth1)×γ/(Kb×T)]=
W2/L2×Is2×exp[e×(Vgs2-Vth2)×γ/(Kb×T)]…(3)
(3) If we rearrange the equation, we get
Vgs2-Vgs1=(Vth2-Vth1)+
[(Kb×T)/(e×γ)]×ln[(W1/L1×Is1)/(W2/L2×Is2)] (4).

Furthermore, (Vth2-Vth1) in equation (4) is the threshold voltage difference ΔVt, and if the gate potential of the second transistor Tr2 is the reference voltage Vref, the source potentials of the first transistor Tr1 and the second transistor Tr2 are Since it is a common potential, the following equation holds true.
Vref=ΔVt+Vgs1+
[(Kb×T)/(e×γ)]×ln[(W1/L1×Is1)/(W2/L2×Is2)]
...(5).
From equation (5), a value of the reference voltage Vref can be generated based on the threshold voltage difference ΔVt and the gate-source voltage Vgs1 of the first transistor Tr1.

Furthermore, if the gate-source voltage Vgs1 of the first transistor Tr1 is generated based on the reference voltage Vref and has a proportional relationship, the following equation holds true.
Vgs1=α×Vref…(6)

From equations (5) and (6), the following equation holds for the reference voltage Vref.
Vref=(ΔVt+[(Kb×T)/(e×γ)]×ln[(W1/L1×Is1)/(W2/L2×Is2)])/(1−α)…(7)
Since μ indicating carrier mobility is not included on the right side of equation (7), variations in temperature characteristics of carrier mobility do not affect the reference voltage Vref. Further, all of the values are physical property values, and if there is no variation in the physical property values, it is possible to generate a reference voltage Vref that is not affected by temperature characteristics.

Further, when a transistor is used in a weak inversion region, the threshold voltage difference ΔVt has a characteristic that it does not depend on the temperature of the environment in which the transistor is used, and a substantially constant value can be obtained. FIG. 2 is a diagram showing the value of the threshold voltage difference ΔVt depending on temperature. (In Figure 2, the value of the threshold voltage difference ΔVt at temperatures of 25°C and 125°C is shown as a typical value.) Figure 2 shows that the threshold voltage difference ΔVt has a characteristic with very little temperature dependence (XXX[ V]@25℃≒YYY[V]@125℃). Furthermore, since the transistor is controlled in the weak inversion region, current consumption can be significantly reduced. For example, while the drain current in the strong inversion region is several μA, the drain current in the weak inversion region is 0.01 μA, making it possible to reduce the current by more than two orders of magnitude.

Note that since the DC voltage VDC is generated based on the reference voltage Vref, it can be easily assumed that the DC voltage VDC can also be generated as a temperature-independent voltage like the reference voltage Vref.

<(Second Embodiment)>
FIG. 3 is a diagram showing a second embodiment of the DC voltage generation circuit 1. The DC voltage generation circuit 1 of the second embodiment includes a differential pair 10, a current source 20, a reference voltage generation section 30, a load section 40, and a DC voltage output section 50, similar to the DC voltage generation circuit 1 of the first embodiment. . Since the configuration other than the configuration of the reference voltage generation section 30 is the same as the first embodiment, the explanation will be omitted.

The reference voltage generation unit 30 may include a first resistor R1 and a second resistor R2, and the resistance values of the first resistor R1 and the second resistor R2 may be individually adjustable from the outside. The first terminal of the first resistor R1 is connected to the gate of the second transistor Tr2 and the reference voltage Vref, and the second terminal of the first resistor R1 is connected to the first terminal of the second resistor R2 and the gate of the first transistor Tr1. , the second terminal of the second resistor R2 is connected to the reference voltage Vst.

Vgs1 of the first transistor Tr1 is determined from ΔVt, the first resistor R1, and the second resistor R2, and when the resistance value of the first resistor R1 is Z1 and the resistance value of the second resistor R2 is Z2, the gate of the first transistor Tr1 The source-to-source voltage Vgs1 is expressed by the following equation.
Vgs1=Z2/Z1×ΔVt…(8)

From equations (5) and (8), Vref becomes the following equation.
Vref=ΔVt+Z2/Z1×ΔVt+[(Kb×T)/(e×γ)]×ln[(W1/L1×Is1)/(W2/L2×Is2)] (9).

Similar to equation (7), equation (9) does not include μ indicating carrier mobility on the right side, and temperature characteristic variations in carrier mobility do not affect reference voltage Vref. Further, all of the values are physical property values, and if there is no variation in the physical property values, it is possible to generate a reference voltage Vref that is not affected by temperature characteristics.

Also, to express Vref more simply, the threshold voltage difference ΔVt is the potential across the first resistor R1, so if the resistance value of the first resistor R1 is Z1, the current in the following equation flows through the first resistor R1. flows.
IR1=ΔVt/Z1 (10) Since the current in the above formula (10) similarly flows through the second resistor R2, when the resistance value of the second resistor R2 is Z2, the reference voltage Vref is expressed by the following formula.
Vref=ΔVt/Z1×(Z1+Z2)…(11)

From Equation (11), the reference voltage Vref is determined from the threshold voltage difference ΔVt and the resistance values Z1 and Z2, which have characteristics with little temperature dependence in the weak inversion region. Here, when resistors made of the same material are used as the first resistor R1 and the second resistor R2, the temperature fluctuation ratio of the resistance value is the same, so there is no temperature dependence due to the resistance, and by extension, there is less temperature dependence. It becomes possible to generate the reference voltage Vref.

Note that in equation (11), the resistance value of the second resistor R2 is set to Z2, but the second resistor R2 may be deleted to generate the reference voltage Vref. Further, the resistance values of the first resistor R1 and the second resistor R2 may not be adjustable but may be fixed values.

<(Third Embodiment)>
FIG. 4 is a diagram showing a third embodiment of the DC voltage generation circuit 1. The DC voltage generation circuit 1 of the third embodiment has the same configuration as the second embodiment except for the differential pair 10.

The differential pair 10 of the third embodiment further includes a third resistor R3 and a fourth resistor R4 from the differential pair 10 of the first and second embodiments. The third resistor R3 and the fourth resistor R4 may each have a configuration in which the resistance values can be adjusted individually from the outside.

The first terminal of the third resistor R3 is connected to the source of the first transistor Tr1, the second terminal is connected to the node N1, the first terminal of the fourth resistor R4 is connected to the source of the second transistor Tr2, and the fourth A second terminal of resistor R4 is connected to node N1.

In Equation (7), it was shown that the reference voltage Vref is determined entirely from the physical property values, and it was shown that the reference voltage Vref that is not affected by temperature characteristics can be generated when there is no variation in the physical property values. However, in the actual manufacturing process, variations in manufacturing may occur.

The resistance values of the third resistor R3 and the fourth resistor R4 are adjusted when variations occur in the manufacturing process, and the temperature characteristics of the reference voltage Vref due to variations in physical property values shown in equation (7) are adjusted. This makes it possible to reduce the impact of

FIG. 5 is a diagram showing the amount of temperature fluctuation of the reference voltage Vref when the value of the third resistor R3 is varied, and the horizontal axis (X-axis) shows the temperature (°C), and the vertical axis (Y-axis) indicates the amount of variation (%) in the reference voltage Vref normalized with reference to the voltage value at 25°C. This shows that by adjusting the value of the third resistor R3 to an optimal value, it is possible to improve the amount of temperature variation in the reference voltage Vref due to variations in the manufacturing process. In addition, in FIG. 5, the amount of temperature fluctuation of the reference voltage Vref, which has a positive temperature characteristic, is improved by adjusting the resistance value of the third resistor R3 due to manufacturing variations in the manufacturing process. However, if the fourth resistor R4 is made of the same material as the third resistor R3 and has the same temperature characteristics, then the reference voltage Vref, which has negative temperature characteristics, and the value of the fourth resistor R4 can be set to the optimal value. By adjusting the value, it is possible to improve the amount of temperature fluctuation of the reference voltage Vref. In addition, by individually adjusting the resistance values of the third resistor R3 and the fourth resistor R4, a reference voltage Vref with optimal temperature characteristics is generated for each individual product, not only due to variations in the manufacturing process. It becomes possible to do so.

Note that the resistance values of the third resistor R3 and the fourth resistor R4 are not adjustable and may be fixed values. Moreover, the third resistor R3 and the fourth resistor R4 may include only one of them.

<(4th embodiment)>
FIG. 6 is a diagram showing a fourth embodiment of the DC voltage generation circuit 1. The configuration of the DC voltage generation circuit 1 of the fourth embodiment is the same as that of the third embodiment except for the load section 40 and the DC voltage output section 50.

The load unit 40 of the fourth embodiment includes two enhancement type MOSFETs (hereinafter referred to as a third transistor Tr3 and a fourth transistor Tr4), and the sources of the third transistor Tr3 and the fourth transistor Tr4 are connected to the power supply voltage Vdd. The gates of the third transistor Tr3 and the fourth transistor Tr4 are connected to the drain of the third transistor Tr3, the drain of the third transistor Tr3 is connected to the drain of the first transistor Tr1, and the drain of the fourth transistor Tr4 is connected to It is connected to the drain of the second transistor Tr2, generates a load voltage VL, and outputs it to the DC voltage output section 50.

By connecting the third transistor Tr3 and the fourth transistor Tr4, it is possible to configure a current mirror circuit. For example, when the ratio of the channel width and channel length of the third transistor Tr3 and the fourth transistor Tr4 is the same, the drain currents of the third transistor Tr3 and the fourth transistor Tr4 have the same value, and the drain current of the third transistor Tr3 and the fourth transistor Tr4 have the same value. It becomes possible to supply the same current to the first transistor Tr1 and the second transistor Tr2 and determine the threshold voltage difference ΔVt based on this current.

Note that the case where the ratio of the channel width to the channel length of the third transistor Tr3 and the fourth transistor Tr4 are the same is an example, and the ratio of the channel width to the channel length may be adjusted as necessary, or it may be adjusted externally. It may be configured as possible. Further, although FIG. 6 shows a current mirror circuit composed of the third transistor Tr3 and the fourth transistor Tr4 as an example of the current mirror circuit configuration, a cascode type current mirror circuit may be used. By using a cascode type current mirror circuit, it is possible to generate a current with reduced influence of channel length modulation effects.

The DC voltage output section 50 of the fourth embodiment includes an enhancement type MOSFET (hereinafter referred to as the fifth transistor Tr5) and a fifth resistor R5, and the second terminal of the fifth resistor R5 is connected to the second terminal of the first resistor R1. 1 terminal, the drain of the fifth transistor Tr5 is connected to the power supply voltage Vdd, the gate is connected to the load voltage VL which is the output of the load section 40, and the source is connected to the first terminal of the fifth resistor R5. At the same time, a DC voltage VDC is generated and outputted as the output voltage of the DC voltage generation circuit 1.

Since the DC voltage VDC is supplied by the source of the fifth transistor Tr5, characteristics of high input impedance and low output impedance can be obtained. As a result, more loads can be driven. Although a description of the channel width and channel length of the fifth transistor Tr5 will be omitted here, it may be configured to be adjustable according to the current capability required of the DC voltage VDC.

Since the fifth resistor R5 is connected in series with the first resistor R1 and the second resistor R2, the same current flows through the first resistor R1 and the second resistor R2. When the resistance value of the fifth resistor R5 is set to Z5, the DC voltage VDC is determined by the following equation based on calculations similar to equations (10) and (11).
VDC=ΔVt/Z1×(Z1+Z2+Z5)…(12)
According to equation (12), the DC voltage VDC can generate an output voltage according to the fifth resistor R5, and the voltage value of the DC voltage VDC can be easily changed.

Note that by using a resistor made of the same material as the first resistor R1 and the second resistor R2 for the fifth resistor R5, the temperature fluctuation ratio of the resistance value is the same, making it possible to generate the DC voltage VDC with less temperature dependence. This is the same as the explanation for equation (11) in the first embodiment. Further, the resistance value of the fifth resistor R5 may be externally adjustable, and may be configured to be adjustable in accordance with the voltage value required for the DC voltage VDC.

FIG. 7 is a diagram showing an example of an application using the DC voltage generation circuit 1. As an example, a configuration example of the LDO regulator IC 100 is shown. The LDO regulator IC 100 includes a preregulator (PREREG) 200, the aforementioned DC voltage generation circuit 1, and an LDO output circuit 300, and an external voltage Vext is supplied to the preregulator 200 and the LDO output circuit 300. The preregulator 200 generates a predetermined voltage at which the DC voltage generation circuit 1 and the LDO output circuit 300 can operate based on the external voltage Vext, and outputs it to the DC voltage generation circuit 1 and the LDO output circuit 300. The DC voltage generation circuit 1 generates a DC voltage VDC with little temperature dependence and outputs it to the LDO output circuit 300. The LDO output circuit 300 includes an output transistor and an operational amplifier (both not shown), and steps down the external voltage Vext to generate a desired LDO output voltage Vout. Note that the LDO output circuit 300 may have a configuration in which the feedback resistance value and the like can be adjusted according to the LDO output voltage Vout required of the LDO regulator IC 100. The LDO regulator IC 100 illustrated in FIG. 7 generates the LDO output voltage Vout with less temperature dependence by using the DC voltage VDC with less temperature dependence as the setting value of the LDO output circuit 300 (for example, the target setting value of the LDO output voltage Vout). can be made possible.

<Other variations>
In the above embodiments and figures, the first transistor Tr1 and the second transistor Tr2 are N-channel MOSFETs, and the third transistor Tr3 and the fourth transistor Tr4 are P-channel MOSFETs, which generate the DC voltage VDC as an example. Although the configuration of the present invention is not limited to this, the DC voltage generation circuit is configured of a differential pair of P-channel MOSFETs in which the polarities of the first to fourth transistors are all reversed. It can also be widely applied.

The various technical features disclosed in this specification can be modified in addition to the embodiments described above without departing from the gist of the technical creation. For example, replacement with a P-channel type depletion type MOSFET or enhancement type MOSFET, or inversion of the logic levels of various signals is optional. That is, the above embodiments should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention is not limited to the above embodiments, and the claims shall be understood to include all changes falling within the meaning and range of equivalency.

1 DC voltage generation circuit 10 differential pair 20 current source 30 reference voltage generation section 40 load section 50 DC voltage output section Tr1 depletion type MOSFET (first transistor)
Tr2~5 Enhancement type MOSFET (2nd~5th transistor)
R1~5 Resistance VDC DC voltage Vref Reference voltage ΔVt Threshold voltage difference VL Load voltage Vst Reference voltage Vdd Power supply voltage Vext External power supply Vout LDO output voltage Iout LDO output current W1~2 Channel width L1~2 Channel length Is1~2 Saturation current Vgs1 ~2 Gate-source voltage Vth1~2 Threshold voltage e Elementary charge γ Weak inversion slope coefficient Kb Boltzmann constant T Absolute temperature

Claims (9)

a differential pair composed of a first depletion type MOSFET and a second enhancement type MOSFET;
a current source that drives the differential pair;
Equipped with
A DC voltage generation circuit that generates a DC voltage based on a threshold voltage difference between the first MOSFET and the second MOSFET,
a first resistor provided between the gate of the first MOSFET and the gate of the second MOSFET;
a second resistor provided between the gate of the first MOSFET and a reference voltage;
A DC voltage generation circuit having : The DC voltage generation circuit according to claim 1, wherein the first resistor has an adjustable resistance value. The DC voltage generation circuit according to claim 1 or 2, wherein the second resistor has an adjustable resistance value. The DC voltage generation circuit according to any one of claims 1 to 3, wherein the first resistor and the second resistor are resistors made of the same material. Claims 1 to 4, further comprising at least one of a third resistor provided between the source of the first MOSFET and the current source, and a fourth resistor provided between the source of the second MOSFET and the current source. The DC voltage generation circuit according to any one of the above . The DC according to claim 5, comprising at least the third resistor, the third resistor being adjustable, or comprising at least the fourth resistor, the fourth resistor having an adjustable resistance value. Voltage generation circuit. The DC voltage generation circuit according to claim 5 or 6, comprising both the third resistor and the fourth resistor, the third resistor and the fourth resistor being made of the same material. The DC voltage generation circuit according to any one of claims 1 to 7, further comprising a current mirror circuit capable of adjusting a ratio of currents flowing through the first MOSFET and the second MOSFET. The DC voltage generation circuit according to claim 1, wherein the first MOSFET and the second MOSFET operate in a weak inversion region.

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