JP7363882B2 - switching power supply - Google Patents

Description

The present invention relates to a switching power supply device that converts an input voltage into an output voltage using a plurality of converter sections connected in parallel.

In recent years, multi-phase switching power supplies have become known that have multiple operating phases and drive each operating phase with a different phase in order to achieve larger currents and lower ripples as output loads increase. There is. In such a switching power supply, it is necessary to operate the power supply while equally sharing the current supplied to the load between the operating phases. Therefore, by detecting the current deviation of each operation phase and adding a correction signal that makes this deviation to zero to the conduction rate command value, each operation phase is uniformly distributed without making the device larger or more complicated. A technique has been proposed in which the electric current is shared between the two (for example, see Patent Document 1).

Japanese Patent Application Publication No. 09-215322

However, since the conventional technology performs multiphase based on the value obtained by adding the current correction value to the conduction rate command value, the control circuit itself must be modified, and a microcomputer or dedicated analog control IC is required. The problem with the switching power supply used was that it was difficult to apply. For example, when using a microcomputer, current correction calculations for each phase must be performed within the microcomputer, which requires significant changes to existing control programs. Furthermore, when performing multiphase, it is necessary to use a plurality of PWM counters inside the microcomputer, but the number of counters is limited. Therefore, increasing the number of phases requires a highly functional microcomputer, leading to an increase in cost. When using a dedicated analog control IC, the application circuit is often predetermined, and it is difficult to incorporate a current correction circuit or phase shift conversion circuit to calculate the current correction for each phase. was there.

An object of the present invention is to solve the above-mentioned problems of the prior art and provide a switching power supply device that can easily add multi-phase and current balancing functions without changing the basic control circuit of the control circuit. It is in.

The switching power supply device of the present invention includes a main circuit in which a plurality of power converters having switching elements are connected in parallel to each other, a control circuit that outputs a reference pulse signal based on the output of the entire main circuit, and the entire main circuit. an overall current detection circuit that detects the output current of the plurality of power conversion units as an overall current; and a plurality of individual currents that are provided corresponding to the plurality of power conversion units and detect the output current of each of the plurality of power conversion units as individual currents. a detection circuit, which evenly delays the rise of the reference pulse signal to generate individual pulse signals for each of the plurality of power conversion units, and generates an average current obtained by dividing the overall current by the number of the power conversion units; Based on the respective differences from the individual current detected by each individual current detection circuit , the duty value of the individual pulse signal is corrected so that the individual current for each of the plurality of power conversion units is equalized, The power converter is characterized by comprising a pulse corrector that outputs the individual pulse signal for each power converter to each of the plurality of power converters as a drive signal for the switching element.

According to the present invention, since the pulse corrector can perform current correction and multiphase conversion based on the gate pulse signal output from the control circuit, the control circuit has a multiphase function (interleaving). This has the advantage that interleaving (multi-phase) functionality can be easily provided by simply adding a pulse corrector.

FIG. 1 is a circuit configuration diagram showing a circuit configuration of a first embodiment of a switching power supply device according to the present invention. FIG. 2 is a waveform diagram showing an example of operating waveforms of the pulse corrector shown in FIG. 1; FIG. 2 is a waveform diagram showing another example of operating waveforms of the pulse corrector shown in FIG. 1; FIG. 2 is a circuit configuration diagram showing a circuit configuration of a second embodiment of the switching power supply device according to the present invention. It is a circuit block diagram showing the circuit structure of a 3rd embodiment of the switching power supply device concerning the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in the following embodiments, the same reference numerals are given to the components having the same functions, and the description thereof will be omitted as appropriate.

(First embodiment)
The switching power supply device 1 of the first embodiment is a multiphase DC/DC converter. Referring to FIG. 1, the switching power supply device 1 includes a control circuit 2, a pulse corrector 3, an overall current detection circuit _CT0 , and N converter sections _CH1 to _CHN as main circuits. .

The switching power supply device 1 has a power supply Vin connected to its input side, and a load L connected to its output side. Between the power supply Vin and the load L, N converter sections CH ₁ to CH _N are connected in parallel and driven as each of the first to Nth operation phases.

The N converter sections CH ₁ to CH _N are power conversion sections having switching elements that are controlled to be turned on and off by pulse signals. Each of the N converter sections CH ₁ to CH _N has the same configuration. Therefore, assuming that n is an integer from 1 to N, the converter section CH _n will be described in detail. The converter section CH _n includes a reactor S _n , a diode D _n , a switching element Q _n , a capacitor C _n , and an individual current detection circuit CT _n , and constitutes a non-insulated step-up chopper circuit. In this embodiment, a step-up chopper circuit is taken as an example of the converter section CH _n , but PWM control converters other than the step-up chopper circuit (step-down chopper circuit, buck-boost chopper circuit, etc.) or isolated DC/ It may also be a DC converter.

A series circuit is formed by the reactor S _n and the diode D _n , and one end of the reactor S _n in this series circuit is connected to the power supply Vin, and the cathode of the diode D _n is connected to the load L. The capacitor C _n is connected in parallel with the load L on the output side between the connection point between the cathode of the diode D _n and the load L and the ground terminal.

In this embodiment, the switching element Q _n is composed of a MOS-FET. The switching element Q _n has a drain connected to a connection point between a reactor S _n and a diode D _n , and a source connected to a ground terminal. Thereby, the switching operation of the switching element _Qn is controlled by the drive signal applied to the gate, and the voltage of the power supply Vin is boosted and supplied to the load L.

The individual current detection circuit CT _n detects the current flowing through the reactor S _n , that is, the output current of the converter section CH _n (for example, the average value in the period Ts of the gate pulse signal). The individual current detection circuit _CTn is composed of, for example, a current transformer or a detection resistor.

The overall current detection circuit CT ₀ detects the input current (for example, the average value in the period Ts of the gate pulse signal) that is input from the power supply Vin to the entire main circuit (converter sections CH ₁ to CH _N ). The input current detected by the overall current detection circuit CT ₀ is the output current of the entire main circuit (converter sections CH ₁ to CH _N ), which is the sum of the output currents flowing through each of the converter sections CH ₁ to CH _N . The overall current detection circuit _CT0 is composed of, for example, a current transformer and a detection resistor.

The control circuit 2 is a circuit that generates a gate pulse signal that controls on/off of the switching element Q _n of the converter section CH _n . The control circuit 2 generates a gate pulse signal whose duty ratio (pulse width) is controlled so that the output (input current, output current, output voltage) of the entire main circuit (converter sections CH ₁ to CH _N ) reaches the target value. is output to the pulse corrector 3.

Based on the gate pulse signal input from the control circuit 2, the pulse corrector 3 generates respective drive signals for turning on and off the switching elements Q ₁ to Q _N of the N converter sections CH ₁ to CH _N. do. That is, the control circuit 2 only needs to have the function of controlling a single-phase converter, and does not need to be compatible with multi-phase converters.

The pulse corrector 3 is composed of a field programmable gate array (FPGA), and functions as a divider 4 and drive signal generators 5 ₁ to 5 _N.

The divider 4 calculates an average current by dividing the input current detected by the overall current detection circuit CT ₀ by N, which is the number of operation phases, and supplies the calculated average current to the drive signal generation units 5 ₁ to 5 _n , respectively. Output.

The drive signal generation units 5 ₁ to 5 _N each have the same configuration. Therefore, n=an integer from 1 to N, and the drive signal generating section _5n will be described in detail. The drive signal generation unit 5 _n includes a current deviation calculator 6 _n , a compensator 7 _n , a duty adder 8 _n , and a phase shifter 9 _n .

The current deviation calculator 6 _n is a subtracter that calculates the difference between the average current input from the divider 4 and the output current of the converter section CH _n detected by the individual current detection circuit CT _n as a current deviation.

The compensator 7 _n determines a correction duty value ΔD _n that compensates for the current deviation calculated by the current deviation calculator 6 _n . Note that as the compensator _7n , a proportional controller (P controller), a proportional integral controller (PI controller), a proportional integral derivative controller (PID controller), etc. can be used.

The duty adder _8n adds the correction duty value _ΔDn determined by the compensator _7n to the duty value (pulse width) D of the gate pulse signal input from the control circuit 2, and calculates the gate pulse width as D+ _ΔDn . Generates a drive signal to As a result, a drive signal is generated in which the duty value of the gate pulse signal is corrected so that the output current of the converter section CH _n approaches the average current input from the divider 4 .

The phase shifter _9n delays the drive signal generated by the duty adder _8n by Ts×(n-1)/N, and the converter output to section CH _n . As a result, the drive signals for each operation phase are output at phase angles equally shifted by 360°/N.

Next, a method of current correction and multiphase within the pulse corrector 3 will be described in detail with reference to FIG. 2.
In the pulse corrector 3, the duty adder _8n of the drive signal generation unit _5n converts the time (pulse width) from the rise to the fall of the gate pulse signal input from the control circuit 2 at time _t0 into a duty value Dt. Measure as ₀ . Note that the period Ts of the gate pulse signal output from the control circuit 2 is the switching period of the converter section CH _n .

Further, in parallel with the measurement of the duty value Dt ₀ , the current deviation calculation unit 6 _n calculates the current deviation, and the duty adder 8 _n determines the correction duty value ΔD _n t ₀ .

Then, the duty adder 8 _n generates a drive signal whose gate pulse width is Dt ₀ +ΔD _n t ₀ , which is obtained by adding the correction duty value ΔD _n t ₀ determined by the compensator 7 _n to the measured duty value Dt ₀ . generate. As a result, the gate pulse widths Dt ₀ +ΔD ₁ t ₀ , Dt ₀ +ΔD ₂ t ₀ , . . . , Dt ₀ +ΔD _N t ₀ of the drive signals for each of the first to N-th operation phases are determined, respectively.

Next, the phase shifter 9 _n converts the drive signal generated by the duty adder 8 _n to Ts×(n-1)/N from time t ₁ , that is, the timing at which the next gate pulse signal from the control circuit 2 rises. output to the converter section CH _n with a delay of . As a result, a pulse having a gate pulse width Dt ₀ +ΔD ₁ t ₀ that rises at time t1 is outputted to the converter unit CH ₁ as a first phase drive signal. Then, in the converter section CH ₂ , a pulse with a gate pulse width Dt ₀ +ΔD ₂ t ₀ that rises with a delay of time Ts/N corresponding to a phase of 360°/N from the first phase drive signal is applied to the second phase drive signal. A drive signal is output. Similarly, the third to _Nth phase drive signals generated by the duty adder _8n are outputted to the converter units CH3 to _CHN with their phases shifted at intervals of time Ts/N.

The gate pulse signal inputted from the control circuit 2 to the pulse corrector 3 after time _t1 is also subjected to similar current correction and multi-phase conversion, and is output in the next switching period after time _t2 .

As described above, in the first embodiment, the gate pulse signal output from the control circuit 2 is input to the pulse corrector 3, and the current correction calculation and phase shift operation are performed within the pulse corrector 3. Drive signals for each of the converter units CH ₁ to CH _N are output. As a result, even if a microcomputer or a dedicated analog control IC for a single-phase switching power supply is used, multiphase and current balancing can be easily achieved by simply adding the pulse corrector 3.

Note that in the first embodiment, the configuration is such that multi-phase conversion and current balancing are performed with a control delay of one switching cycle, but multi-phase conversion and current balancing are performed without generating a control delay. You can also. In this case, as shown in FIG. 3, in the pulse corrector 3, the first phase drive signal generator ₅₁ outputs the correction duty value _ΔD1 from the control circuit 2 without calculating the correction duty value ΔD1. The gate pulse signal is directly output as a drive signal for converter section _CH1 . Then, the drive signal generation units 5 ₂ to 5 _N for the second to Nth phases calculate correction duty values ΔD ₂ to ΔD _N , respectively, to execute current balancing.

Referring to FIG. 3, when a gate pulse signal is input from the control circuit 2 at time _t0 , the phase shifter ₉₁ of the drive signal generation section ₅₁ changes the first phase drive signal to be output to the converter section _CH1 . At the same time, the drive signal generation units 5 ₂ to 5 _N calculate a correction duty value ΔD _n t ₀ .

Next, the phase shifter ₉₂ of the drive signal generation unit ₅₂ raises the second phase drive signal at an interval of time Ts/N from the rise of the first phase drive signal. The phase shifters 9 ₃ to 9 _N of the drive signal generation units 5 ₃ to 5 _N also raise the second to Nth phase drive signals at similar intervals.

Next, the phase shifter 9 ₁ of the drive signal generation unit 5 ₁ lowers the first phase drive signal simultaneously with the fall of the gate pulse signal at time t ₀ +DT ₀ . Then, in the drive signal generation units 5 ₂ to 5 _N , as soon as the duty value DT ₀ of the gate pulse signal output from the control circuit 2 is determined, the duty value Dt ₀ and the pre-calculated correction duty value ΔD _n t ₀ is added to determine the gate pulse width DT ₀ +ΔD _n t ₀ to the drive signals of the first to Nth phases, and the second to Nth phases are determined according to the determined gate pulse width DT ₀ +ΔD _n t _0. The respective drive signals are lowered.

The gate pulse signal inputted from the control circuit 2 to the pulse corrector ₃ after time t1 is also subjected to similar current correction and multi-phase conversion, and is output in the same switching period.

As a result, multiphase and current balancing can be achieved without causing control delays. Current correction for current balancing is no longer performed during the first phase operation phase, but current correction for current balancing is performed during the other phase operation phases, so the current is automatically balanced in the first phase operation phase. It looks like this.

(Second embodiment)
A switching power supply device 1a according to the second embodiment is a multi-phase inverter. Referring to FIG. 4, the switching power supply device 1a includes a control circuit 2, a pulse corrector 3, an overall current detection circuit _CT0 , and N inverter units _INV1 to _INVN as main circuits. . Hereinafter, descriptions of configurations similar to those in the first embodiment will be omitted as appropriate.

The switching power supply device 1a has a power supply Vin connected to its input side, and a load L connected to its output side. Between the power supply Vin and the load L, N inverter units INV ₁ to INV _N are connected in parallel and driven as each of the first to Nth operation phases.

The N inverter units INV ₁ to INV _N are power conversion units having switching elements that are turned on and off by pulse signals. Each of the N inverter units INV ₁ to INV _N has the same configuration. Therefore, let n=an integer from 1 to N, and the inverter section INV _n will be described in detail. The inverter unit INV _n includes a capacitor C _n , an inverting buffer NOT _n , a reactor S _n , four switching elements Q _{n-1 to Q n-4} , and an individual current detection circuit CT _n , and is a full-bridge single-phase It constitutes an inverter.

Capacitor C _n is connected in parallel with power supply Vin.

In this embodiment, the four switching elements Q _{n-1 to Q n-4} are composed of MOS-FETs. A series circuit consisting of a switching element Q _n-1 and a switching element Q n-2 is connected between the positive terminal and the negative terminal of the capacitor C _n , and a series circuit consisting of a switching element Q _{n-3 and} a switching element Q _n A series circuit consisting of _-4 is connected.

The connection point between switching element Q _n-1 and switching element Q _n-2 is connected to one end of load L via reactor S _n , and the connection point between switching element Q _n-3 and switching element Q _n-4 is connected to one end of load L via reactor S n. is connected to the other end of the load L. Note that a capacitor C ₀ is connected between both ends of the load L, which functions together with a reactor S _n of the inverter unit INV _n as a filter circuit for removing high frequency components.

The drive signal from the pulse corrector 3 is directly input to the gates of switching element Q _n-1 and switching element Q _n-4 , and an inverting buffer NOT _n is input to the gates of switching element Q _n-2 and switching element Q _n-3. Input via . As a result, the switching elements Q _{n-1 to Q n-4} are turned on and off by the drive signal, and the DC voltage is converted into a desired AC voltage.

In the second embodiment, the individual current detection circuit CT _n detects the current flowing through the reactor S _n , that is, the output current of the inverter unit INV _n . The individual current detection circuit _CTn is composed of, for example, a current transformer or a detection resistor. In the second embodiment, the current deviation calculator 6 _n of the pulse corrector 3 uses the average current input from the divider 4 and the output of the inverter section INV _n detected by the individual current detection circuit CT _n . The difference from the current (for example, the average value in the period Ts of the gate pulse signal) is calculated as a current deviation.

In the second embodiment, the overall current detection circuit CT ₀ detects the output current output from the entire main circuit (inverter sections INV ₁ to INV _N ). The output current detected by the overall current detection circuit CT ₀ is the output current of the entire main circuit (inverter sections INV ₁ to INV _N ), which is the sum of the output currents flowing through each of the inverter sections INV ₁ to INV _N . The overall current detection circuit _CT0 is composed of, for example, a current transformer and a detection resistor. In the second embodiment, the divider 4 of the pulse corrector 3 divides the output current detected by the overall current detection circuit _CT0 (for example, the average value in the period Ts of the gate pulse signal) by the number of operation phases. The average current is calculated by dividing by a certain N, and the calculated average current is output to each of the drive signal generation units 5 ₁ to 5 _n .

As described above, in the second embodiment, the gate pulse signal output from the control circuit 2 is input to the pulse corrector 3, and the current correction calculation and phase shift operation are performed within the pulse corrector 3. Drive signals for each of the inverter units INV ₁ to INV _N are output. As a result, even if a microcomputer or a dedicated analog control IC for a single-phase switching power supply is used, multiphase and current balancing can be easily achieved by simply adding the pulse corrector 3.

(Third embodiment)
Referring to FIG. 5, the switching power supply device 1b of the third embodiment has the configuration of the first embodiment, and in addition, the pulse corrector 3a has an abnormal operation signal input from the converter sections CH ₁ to CH _N. The present invention includes a phase control unit 10 that controls the number of operation phases to be driven based on the following.

The converter section CH _n includes an abnormal operation detection section 11 _n . When the abnormal operation detection section 11 _n detects an abnormal operation such as overheating, short circuit, or failure of the converter section CH _n , it outputs an operation abnormal signal to the phase control section 10 of the pulse corrector 3 a.

Based on the input abnormal operation signal, the phase control unit 10 sets converter section CH _n in which an abnormal operation has been detected as an abnormal phase, and sets converter section CH _n that is operating normally as a normal phase and sets the number of normal phases. Calculate N' (≦N). Then, the phase control unit 10 stops outputting the drive signal to the phase shifters 9a _{to 9n} in the abnormal phase in which an abnormal operation has been detected, and causes the phase shifters 9a _{to 9n} in the normal phase that are operating normally to have a 360° Outputs phase angle commands shifted by /N'. As a result, even if some converter sections CH _n fail, the N' normally operating converter sections CH _n will operate at an equal phase angle using drive signals whose phases are shifted by 360°/N'. This makes it possible to minimize the ripple component of the overall current.

Further, the phase control section 10 outputs the calculated number of normal phases N' to the divider 4a. Then, the divider 4a calculates an average current by dividing the input current detected by the overall current detection circuit _CT0 by the number of operation phases N', and sends the calculated average current to the drive signal generation units 5a ₁ to 5a _n . Output each. Accordingly, in the second embodiment, the divider 4a is changed from 1/N to 1/N'. Since the average current obtained by dividing the total input current by the number of operating phases N' becomes the target current value for each phase, the current balancing function for each phase works even if the number of operating phases to be driven changes.

Furthermore, the phase control section 10 outputs the calculated number of normal phases N' to the control circuit 2a. The control circuit 2a determines the control gain of the entire main circuit (converter sections CH ₁ to CH _N ) based on the number of normal phases N'. That is, since the transfer function of the controlled object differs depending on the number of operating phases to be driven, the control circuit 2a lowers the control gain based on the number N' of normal phases, as the number N' of normal phases decreases. Thereby, the switching power supply device 1a can be controlled with an optimal control gain regardless of the number of operating phases to be driven.

The control circuit 2a also determines the overload protection setting value based on the number of normal phases N'. Specifically, by processing such as multiplying the overload protection threshold by N'/N, as the number of operation phases N' becomes smaller, the overload protection threshold is lowered. As a result, even if a failure occurs in a part of the operation phase, it is possible to safely operate with a reduced load.

Although the third embodiment has been described as an example applied to the configuration of the first embodiment, the third embodiment may also be applied to the second embodiment.

As described above, in the third embodiment, even if one converter section CH _n cannot be used due to malfunction, the remaining normal converter sections CH _n can maintain the phase angles evenly and each phase Operation can be performed while maintaining current balance. Furthermore, it is possible to operate safely with optimal control gain.

As described above, according to the present embodiment, a plurality of power conversion units (converter unit CH _n , inverter unit INV _n ) having switching elements (switching element Q _n , switching elements Q _{n-1 to Q n-4} ) A main circuit connected in parallel with each other, a control circuit 2 that outputs a reference pulse signal based on the output of the entire main circuit, an overall current detection circuit _CT0 that detects the output current of the entire main circuit as an overall current, and a plurality of A plurality of individual current detection circuits CTn are provided corresponding to the power conversion units and detect the output current of each of the plurality of power conversion units as individual currents, and a plurality of individual current detection circuits CT _n are provided corresponding to the power conversion units and detect the output current of each of the plurality of power conversion units as individual currents, a pulse corrector 3 that generates individual pulse signals for each of the power conversion units, and outputs the individual pulse signals for each of the plurality of power conversion units to the plurality of power conversion units as drive signals for switching elements, respectively. There is.
With this configuration, the pulse corrector 3 can perform current correction and multi-phase conversion based on the gate pulse signal output from the control circuit 2, so the control circuit 2 has a multi-phase function. There is no need for this, and the main circuit can be multiphased simply by adding the pulse corrector 3.

Furthermore, according to the present embodiment, the pulse corrector 3 adjusts the duty value of the reference pulse signal so that the individual pulse signals for each of the plurality of power conversion units are equalized. Correct and generate each.
With this configuration, current balancing of the plurality of power converters constituting the main circuit can be realized by simply adding the pulse corrector 3.

Furthermore, according to the present embodiment, the pulse corrector 3 operates the plurality of power converters in multiphase.
With this configuration, an interleave ( multiphase ) function can be easily provided by simply adding the pulse corrector 3.

Furthermore, according to the present embodiment, the pulse corrector 3 outputs the reference pulse signal as it is as a driving signal for the switching element for the first phase operation phase, and outputs the reference pulse signal as it is as a switching element drive signal for the operation phase other than the first phase. , the generated individual pulse signals are outputted with their phase angles equally shifted from the reference pulse signal.
With this configuration, the gate pulse signal duty value D determined when outputting the first phase drive signal can be reflected in the second and subsequent phases, so multi-phase and current balancing can be achieved without causing control delays. realizable.

Further, according to the present embodiment, the abnormal operation detecting section 11 _n is provided to detect abnormal operation of each of the plurality of power converters, and the pulse corrector 3a is configured to detect the abnormal operation of each of the power converters in which the abnormal operation is detected. is set as the abnormal phase, the output of the individual pulse signal is stopped, and the power converter in which no abnormal operation is detected is set as the normal phase, and the duty value of the reference pulse signal is corrected so that the individual currents for each normal phase are equalized. and generate each.
With this configuration, even if some of the power converters that make up the main circuit are malfunctioning and cannot be used, the remaining normal power converters can maintain current balance in each phase while keeping the phase angles equal. can perform actions. Furthermore, since abnormal power converters are excluded from operation, redundant operation is possible.

Further, according to the present embodiment, the pulse corrector 3a outputs the number of normal phases to the control circuit 2a, and the control circuit 2a determines the control gain of the entire main circuit and the overload detection based on the number of normal phases. change either or both of the threshold values.
This configuration further allows safe operation with optimal control gain.

Furthermore, according to this embodiment, the pulse corrector 3 is configured by an FPGA (Field Programmable Gate Array).
With this configuration, the pulse corrector 3 can be easily configured using an FPGA, and a switching power supply circuit with an interleave ( multiphase ) function can be easily constructed using a single-phase control circuit. be able to.

Although the present invention has been described above using specific embodiments, the above-described embodiments are merely examples, and it goes without saying that the present invention can be modified and implemented without departing from the spirit of the present invention.

1, 1a, 1b Switching power supply device Vin Power supply CH ₁ ~ CH _N converter section S ₁ ~ S _N reactor D ₁ ~ D _N diode Q ₁ ~ Q _N , Q _{1-1 ~ 4} ~ Q _{N-1 ~ 4} switching element C ₀ , ₁ ~C _N Capacitor CT ₀ Overall current detection circuit CT ₁ ~CT _N Individual current detection circuit INV ₁ ~ INV _N Inverter section NOT ₁ ~NOT _N Inverting buffer L Load 2, 2a Control circuit 3, 3a Pulse corrector 4, 4a Divider 5 ₁ to 5 _N , 5a ₁ to 5a _N drive signal generation unit 6 ₁ to 6 _N current deviation calculator 7 ₁ to 7 _N compensator 8 ₁ to 8 _N duty adder 9 ₁ to 9 _N , 9 _a1 to 9 _{aN phase} shifter 10 phase control section 11 ₁ to 11 _N abnormal operation detection section

Claims (1)

a main circuit in which a plurality of power conversion units each having a switching element are connected in parallel;
a control circuit that outputs a reference pulse signal based on the output of the entire main circuit;
an overall current detection circuit that detects the output current of the entire main circuit as an overall current;
a plurality of individual current detection circuits that are provided corresponding to the plurality of power conversion units and detect output currents of each of the plurality of power conversion units as individual currents;
A rise of the reference pulse signal is equally delayed to generate individual pulse signals for each of the plurality of power conversion units, and an average current obtained by dividing the overall current by the number of the power conversion units and a plurality of individual current detection circuits. The duty value of the individual pulse signal is corrected so that the individual currents for each of the plurality of power conversion units are equalized based on the respective differences with the individual current detected for each of the plurality of power conversion units. A switching power supply device comprising: a pulse corrector that outputs the individual pulse signals of 1 to each of the plurality of power converters as drive signals for the switching elements.

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