JP7365871B2 - Semiconductor device and its manufacturing method - Google Patents

Description

The present invention relates to a non-lead type semiconductor device and a method for manufacturing the same.

Semiconductor devices mounted on portable devices and IC cards are required to be smaller and thinner. It is well known that the mounting area of a semiconductor device can be reduced by using a non-lead type in which the lead terminal has a length equal to the end surface of the package.

FIG. 8 shows a cross section of a non-lead type semiconductor package. The die pad 121 and the leads 122 are bonded with resin 130, and the semiconductor element 170 mounted on the die pad 121 and the leads 122 on which the plating film 150 is formed are electrically connected via bonding wires 171, and the sealing resin is used. 180, and the outer surface of the lead 122 and the side surface of the sealing resin 180 are on the same surface.

In the illustrated non-lead type semiconductor package, the die pad 121 has a hexagonal cross-sectional shape, and the center portion of the die pad 121 in the thickness direction is bulged. In addition, the lead 122 has a structure in which the width of the top surface connecting the bonding wire 171 is increased in the direction of the die pad 121 and the width of the bottom surface is shortened in its cross section. That is, the upper surface of the lead 122 has a convex eaves portion in the direction facing the die pad 121. The above structure prevents the die pad 121 and the leads 122 from easily falling off from the resin 130 and the sealing resin 180 (for example, see Patent Document 1).

JP2003-309241A

However, in the non-lead type semiconductor package described in Patent Document 1, by providing the leads 122 with convex eaves, the planar area of the top surface of the leads 122 is larger than the planar area of the bottom surface of the leads 122 exposed from the resin 130. It becomes something big. Furthermore, in order to prevent the leads 122 from falling off, it is necessary to make the eaves part a predetermined thickness, thereby making the leads 122 themselves thicker. As described above, providing an eave portion on the lead is an impediment to miniaturization and thinning.
The present invention has been made in view of the above problems, and an object of the present invention is to provide a small and thin semiconductor device while preventing the leads from falling off from the sealing resin.

In order to solve the above problems, the present invention uses the following means.
semiconductor chip,
leads arranged around the semiconductor chip;
a connecting member connecting the semiconductor chip and the lead;
A sealing resin that seals the semiconductor chip, the leads, and the connection member,
The semiconductor device is characterized in that the bottom surface of the lead is exposed from the sealing resin, and the side surface of the lead is provided with a tapered through groove extending from the top surface of the lead to the bottom surface of the lead.

Further, a step of preparing a lead frame including a lead having a through groove;
A process of back-grinding a semiconductor wafer;
half-cut dicing from the back side of the semiconductor wafer;
a step of attaching the back side of the semiconductor wafer to a dicing tape and performing full cut dicing from the front side of the semiconductor wafer;
expanding the dicing tape to widen the dimension between the diced semiconductor chips to the same dimension as the pitch size of the lead frame;
a step of bonding the dicing tape and the lead frame;
connecting the semiconductor chip and the leads with a connecting member;
sealing the semiconductor chip, the leads, and the connection member with a sealing resin;
cutting the sealing resin and the lead;
A method for manufacturing a semiconductor device was used, which includes a step of peeling the dicing tape from the leads, the semiconductor chip, and the sealing resin.

By using the above means, it is possible to obtain a small and thin semiconductor device while preventing the leads and die pad from falling off from the sealing resin.

1 is a cross-sectional view and a bottom view of a semiconductor device according to a first embodiment of the present invention. FIG. FIG. 3 is an enlarged cross-sectional view of a groove portion of the semiconductor device according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view and a bottom view of a semiconductor device according to a second embodiment of the present invention. FIG. 3 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention. FIG. 7 is a schematic diagram showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention. FIG. 6 is a schematic diagram following FIG. 5 illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention. FIG. 7 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention. FIG. 2 is a cross-sectional view of a conventional non-lead type semiconductor package.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device that is an embodiment of the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 is a cross-sectional view and a bottom view of a semiconductor device according to a first embodiment of the present invention. First, the configuration of the semiconductor device 10 will be described with reference to FIG. 1(a) which is a cross-sectional view. A semiconductor chip 1 is fixed onto a die pad 5 via a die attach layer 3. Leads 4 are provided around the die pad 5 at a distance from the die pad 5. Electrode pads (not shown) provided on the top surface of the semiconductor chip 1 and the top surfaces of the leads 4 are electrically connected via bonding wires 2, which are connection members. As the material of the bonding wire 2, gold (Au) or copper (Cu) is used.

The peripheries of the semiconductor chip 1, die pad 5, and bonding wires 2 are covered with a sealing resin 6, and the bottom surface of the die pad 5 is also covered with a thin sealing resin 6 that does not hinder the reduction in the thickness of the semiconductor device 10. The die pad 5 may be designed to have a thinner structure if it hinders the reduction in the thickness of the semiconductor device 10.

On the other hand, in the case of the lead 4, the upper surface of the lead 4 and the inner surface 4b where the lead 4 faces the die pad 5 are covered with the sealing resin 6, and the outer surface 4a where the lead 4 does not face the die pad 5. The bottom surface of the lead 4 is exposed from the sealing resin 6. The semiconductor device 10 has a rectangular cross-sectional shape, and most of the outer surface of the semiconductor device 10 is covered with the sealing resin 6, and the leads 4 are partially exposed from the sealing resin 6. The bottom surface of the lead 4 and the bottom surface of the sealing resin 6 form the same surface, and the outer surface 4a of the lead 4 and the side surface of the sealing resin 6 form the same surface. Furthermore, although not shown, a plating film is applied to the bottom and outer surfaces 4a of the leads 4 exposed from the sealing resin 6 to ensure good bonding between the semiconductor device 10 and the wiring board during mounting. .

A through groove 7 having a tapered side surface in cross-sectional view is formed on the side surface of the lead 4 in the direction toward the front in the drawing. The through groove 7 is a groove that reaches from the top surface to the bottom surface of the lead 4, and is filled with sealing resin 6. The sealing resin 6 filled in the through groove 7 is firmly connected to the sealing resin 6 that covers the upper surface of the lead 4 and the like. Thereby, the lead 4 does not easily fall off from the sealing resin 6, resulting in a structure that improves the ability to prevent the lead 4 from falling off.

The illustrated through groove 7 has a semi-truncated cone shape with forward tapered side surfaces, and the opening width at the top surface of the lead 4 is smaller than the opening width at the bottom surface of the lead 4. That is, the structure is such that the area of the opening on the top surface of the lead 4 is smaller than the area of the opening on the bottom surface of the lead 4 in plan view.

FIG. 1B is a bottom view of the semiconductor device shown in FIG. 1A, viewed from below. Four leads 4 are arranged on one side of the sealing resin 6 having four sides, and the other four leads 4 are arranged on the opposing sides. A semicircular through groove 7 is provided in a side surface 4c that is perpendicular to both the outer surface 4a and inner surface 4b of each lead 4. A semicircle with a large radius of curvature of the through groove 7 shown concentrically indicates a portion that opens on the bottom surface of the lead 4, and a semicircle with a small radius of curvature indicates a portion that opens on the top surface of the lead 4.

Although each lead 4 is provided with two through grooves 7, the number of through grooves 7 may be increased in order to improve the ability to prevent the lead 4 from falling off. The upper surface of the lead 4 to which the bonding wire 2 is bonded need only be outside the semicircle with a small radius of curvature, that is, outside the opening, and should be defined between the semicircle with a small radius of curvature and the semicircle with a large radius of curvature. The bonding wire 2 may be partially bonded to the region. Note that the bottom surface of the die pad 5 is covered with a thin sealing resin 6, so it is not shown in this bottom view.

In order to make semiconductor devices smaller and thinner, it is necessary to reduce the width and thickness of leads. In particular, when the thickness of a semiconductor device is reduced to 200 μm or less, the lead thickness is reduced to 50 μm or less, but in a structure with a convex eaves as shown in FIG. Therefore, it is difficult to reduce the lead thickness to 50 μm or less.

On the other hand, in the semiconductor device 10 according to the first embodiment of the present invention, there is no convex eaves part, and the structure has a lead pullout prevention part such as a concave through groove 7 on the side surface of the lead 4. Since there is no need to increase the width of the leads 4 more than necessary, miniaturization can be achieved. In addition, in a structure with an eaves part, in order for the eaves part to have sufficient fall-off prevention properties, it is necessary to make the eaves part a predetermined thickness, and the lead itself becomes thicker accordingly, which hinders thinning. In the semiconductor device 10 according to the first embodiment of the present invention, since the length of the through groove 7 in the vertical direction is equal to the thickness of the lead, the drop-off prevention property can be ensured without increasing the thickness of the lead 4, and the device can be made thinner. The structure is such that it can be realized.

Although the embodiment in which leads are arranged on the side opposite to one side of the sealing resin 6 having four sides has been described above, it is also possible to apply the present invention to a semiconductor device in which leads are arranged on all four sides.

FIG. 2 is an enlarged cross-sectional view of the groove portion of the semiconductor device according to the first embodiment of the present invention. FIG. 2(a) is an enlarged sectional view of the semi-truncated conical through groove 7 having forward tapered side surfaces shown in FIG. 1(a), and the inside of the through groove 7 is filled with sealing resin 6. has been done. FIG. 2(b) shows a through groove 7 in the shape of an inverted semi-truncated cone having an inverted tapered side surface. The opening width on the top surface of the lead 4 is larger than the opening width on the bottom surface of the lead 4. That is, the structure is such that the area of the opening on the top surface of the lead 4 is larger than the area of the opening on the bottom surface of the lead 4 in plan view. The through groove 7 is filled with a sealing resin 6.

FIG. 2(c) shows a lead 4 having a structure different from that shown in FIG. 2(a) in that a stepped portion 11 is provided on the tapered side surface of the semiconical through groove 7 having a forward tapered side surface. It shows. A stepped portion 11 is provided in the middle of the tapered side surface, and the structure further improves the prevention of falling off. This structure may be applied to FIG. 2(b) to provide a structure in which the stepped portion 11 is provided on the tapered side surface of the through groove 7 in the shape of an inverted semi-truncated cone having an inverted tapered side surface.

FIG. 2(d) shows a lead 4 having a structure different from that shown in FIG. 2(a) in that a spiral groove 12 is provided on the tapered side surface of the semi-truncated conical through groove 7 having a forward tapered side surface. It shows. By forming a plurality of spiral grooves 12 diagonally along the tapered side surface, the sealing resin 6 enters into the spiral grooves 12, further improving the prevention of falling off. This structure may be applied to FIG. 2(b) to provide a structure in which the spiral groove 12 is provided on the tapered side surface of the through groove 7 in the shape of an inverted semi-truncated cone having an inverted tapered side surface.

(Second embodiment)
FIG. 3 is a cross-sectional view and a bottom view of a semiconductor device according to a second embodiment of the present invention. First, the configuration of the semiconductor device 10 will be described with reference to FIG. 3(a) which is a cross-sectional view. A semiconductor chip 1 is fixed onto a die pad 5 via a die attach layer 3. Leads 4 are provided around the die pad 5 at a distance from the die pad 5. Electrode pads (not shown) provided on the top surface of the semiconductor chip 1 and the top surfaces of the leads 4 are electrically connected via bonding wires 2, which are connection members. As the material of the bonding wire 2, gold (Au) or copper (Cu) is used.

The periphery of the semiconductor chip 1, die pad 5, and bonding wire 2 is covered with a sealing resin 6, but the bottom surface of the die pad 5 is exposed from the sealing resin 6. A through groove 8 having a tapered side surface in cross-sectional view is formed on the side surface of the die pad 5 in the direction toward the front in the drawing. The through groove 8 is a groove that reaches from the top surface to the bottom surface of the die pad 5, and is filled with the sealing resin 6. The sealing resin 6 filled in the through groove 8 is firmly connected to the sealing resin 6 that covers the upper surface of the die pad 5 and the like. As a result, the die pad 5 does not easily fall off from the sealing resin 6, resulting in a structure that improves the ability to prevent the die pad 5 from falling off.

In the case of the lead 4, the upper surface of the lead 4 and the inner surface 4b where the lead 4 faces the die pad 5 are covered with the sealing resin 6, and the outer surface 4a, which is the side surface where the lead 4 does not face the die pad 5, and the bottom surface of the lead 4 are covered with the sealing resin 6. is exposed from the sealing resin 6. The semiconductor device 10 has a rectangular cross-sectional shape, and most of the outer surface of the semiconductor device 10 is covered with the sealing resin 6, and the leads 4 are partially exposed from the sealing resin 6. The bottom surface of the die pad 5, the bottom surface of the leads 4, and the bottom surface of the sealing resin 6 form the same surface, and the outer surface 4a of the lead 4 and the side surface of the sealing resin 6 form the same surface. Further, although not shown, a plating film is applied to the bottom surface of the die pad 5 exposed from the sealing resin 6 and the bottom surface and outer surface 4a of the leads 4 to facilitate the bonding between the semiconductor device 10 and the wiring board during mounting. It is considered to be in good condition.

A through groove 7 having a tapered side surface in cross-sectional view is formed on the side surface of the lead 4 in the direction toward the front in the drawing. The through groove 7 is a groove that reaches from the top surface to the bottom surface of the lead 4, and is filled with sealing resin 6. The sealing resin 6 filled in the through groove 7 is firmly connected to the sealing resin 6 that covers the upper surface of the lead 4 and the like. Thereby, the lead 4 does not easily fall off from the sealing resin 6, resulting in a structure that improves the ability to prevent the lead 4 from falling off.

The illustrated through groove 7 has a semi-truncated cone shape with forward tapered side surfaces, and the opening width at the top surface of the lead 4 is smaller than the opening width at the bottom surface of the lead 4. That is, the structure is such that the area of the opening on the top surface of the lead 4 is smaller than the area of the opening on the bottom surface of the lead 4 in plan view.

FIG. 3(b) is a bottom view of the cross-sectional view shown in FIG. 3(a) viewed from below. Four leads 4 are arranged on one side of the sealing resin 6 having four sides, and the other four leads 4 are arranged on the opposing sides. A semicircular through groove 7 is provided in a side surface 4c that is perpendicular to both the outer surface 4a and inner surface 4b of each lead 4. A semicircle with a large radius of curvature of the through groove 7 shown concentrically indicates a portion that opens on the bottom surface of the lead 4, and a semicircle with a small radius of curvature indicates a portion that opens on the top surface of the lead 4.

Each lead 4 is provided with two through grooves 7, but in order to improve the ability to prevent the lead 4 from falling off, the number of through grooves 7 may be increased. A through groove 7 may be formed on the inner side surface 4b of 4. The upper surface of the lead 4 to which the bonding wire 2 is bonded need only be outside the semicircle with a small radius of curvature, that is, outside the opening, and should be defined between the semicircle with a small radius of curvature and the semicircle with a large radius of curvature. The bonding wire 2 may be partially bonded to the region.

A die pad 5 is arranged between the leads 4 arranged on one side and the leads 4 arranged along the other side, spaced apart from them. Of the four sides forming the die pad 5, a through groove 8 is provided on each of two opposing sides. Here, the through groove 8 provided in the die pad 5 is arranged parallel to the through groove 7 provided in the lead 4. The area surrounded by dotted lines inside the die pad 5 is a plane projection area of the semiconductor chip 1, and the through groove 8 is formed outside this area. This is to prevent excess die attach material from leaking and entering the through groove 8 when die bonding the semiconductor chip 1.

In the figure, a total of four through grooves 8 are provided on two opposing sides of the die pad 5, that is, on two opposing sides of the die pad 5, but in order to improve the prevention of the die pad 5 from falling off, the number of through grooves 8 is The number of through grooves 8 may be increased, and the through grooves 8 may be formed on four sides of the die pad 5, that is, on all side surfaces of the die pad 5.

In the semiconductor device 10 of the second embodiment of the present invention, the shape and arrangement of the leads 4 are the same as those of the semiconductor device 10 of the first embodiment shown in FIG. . As explained above, since the die pad 5 is structured to have a lead pull-out prevention part such as the recessed through groove 8, there is no need to increase the width of the die pad 5 more than necessary, resulting in miniaturization. It can be achieved. In addition, since the length in the vertical direction of the through groove 8 provided in the die pad 5 is equivalent to the thickness of the die pad 5, the die pad 5 can be prevented from falling off without having to be made thicker, and the structure can also be made thinner. It has become.

(Third embodiment)
FIG. 4 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention.
The difference from the semiconductor device 10 shown in FIG. 3 is that there is no die pad 5, and the bottom surface of the semiconductor chip 1 is directly exposed from the bottom surface of the sealing resin 6. However, in order to prevent the semiconductor chip 1 from falling out from the sealing resin 6, the bottom edge of the semiconductor chip 1 has a chamfered portion to form an inverted mesa shape. By adopting such a shape, the sealing resin 6 enters the edge of the bottom surface of the semiconductor chip 1 during resin sealing, and the semiconductor chip 1 can be held within the sealing resin 6, thereby preventing the semiconductor chip 1 from falling off. Prevention is improved. The shape of the lead 4 is the same as that of the semiconductor device 10 of the second embodiment of the present invention described above. The bottom surface of the semiconductor chip 1, the bottom surface of the leads 4, and the bottom surface of the sealing resin 6 form the same surface, and the outer surface 4a of the lead 4 and the side surface of the sealing resin 6 form the same surface. Although not shown, a plating film is applied to the bottom surface of the semiconductor chip 1 exposed from the sealing resin 6 and the bottom surface and outer surface 4a of the leads 4, so that the semiconductor device 10 and the wiring board are bonded during mounting. is considered to be in good condition.

Next, an example of a method for manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. 5 and 6.
First, as shown in FIG. 5A, a flat metal plate made of copper or copper alloy is prepared, and tapered through holes are formed at predetermined positions by punching. In the next punching process, the lead frame 20 having the lead 4 having the through groove 7 is completed by cutting across the center of the through hole. The lead 4 is connected to a frame 21 that is a frame of a lead frame 20. Leads 4 within one frame 21 are used as components of one semiconductor device. Therefore, the leads 4 provided adjacent to both sides of the frame frame 21 are components of different semiconductor devices (STEP 1).

Next, as shown in FIG. 5B, the semiconductor wafer 30 is attached to a backgrind tape 51, and the semiconductor wafer 30 is backgrinded to a predetermined thickness. Then, half-cut dicing is performed from the back side of the semiconductor wafer 30 stuck on the back grind tape 51. The first blade 41 used in this case has a wide pyramidal shape with a wide-angle tip, and only the pyramidal portion enters the semiconductor wafer 30 for dicing. The cutting tip angle A of the tip of the first blade 41 is in the range of 80 to 100 degrees, and a cutting groove 13 having a triangular shape in cross section is formed on the back surface of the semiconductor wafer 30 (STEP 2).

Next, as shown in FIG. 5C, the back side of the semiconductor wafer 30 is pasted on a heat-resistant dicing tape 52, and full-cut dicing is performed from the front side of the semiconductor wafer 30 using the second blade 42. A semiconductor chip 1 having an inverted mesa shape is obtained. The dicing tape 52 used is required to have heat resistance such that it does not decompose even at the temperature (200° C.) applied in the subsequent resin sealing process. The second blade 42 is narrower than the first blade 41. The cutting groove 14 formed by the second blade 42 has a straight shape and reaches from the surface of the semiconductor wafer 30 to the top of the cutting groove 13 .

When the thickness of the semiconductor wafer 30 after backgrinding is 100 μm, the thickness of the first blade 41 is in the range of 50 to 100 μm. Further, the thickness of the second blade 42 is preferably in the range of 20 to 40 μm. Furthermore, when the thickness of the semiconductor wafer 30 after backgrinding is 150 μm, the thickness of the first blade 41 is preferably in the range of 100 to 150 μm, and the thickness of the second blade is preferably in the range of 20 to 40 μm (STEP 3).

Next, as shown in FIG. 6(a), after full-cut dicing, the dicing tape 52 is expanded to widen the dimension between the semiconductor chips 1 that have been separated into pieces to the same dimension as the pitch size of the lead frame 20. Thereafter, the lead frame 20 prepared in advance is bonded to the expanded dicing tape 52. Thereby, the semiconductor chip 1 can be placed between the opposing leads 4 of the lead frame 20 (STEP 4).

Next, as shown in FIG. 6(b), the electrode pads provided on the top surface of the semiconductor chip 1 and the top surfaces of the leads 4 are electrically connected using bonding wires 2, which are connecting members, and then the dicing tape is Resin sealing is performed with the semiconductor chip 1 and the leads 4 bonded together on the semiconductor chip 52 (STEP 5).

Next, as shown in FIG. 6C, after resin sealing, the sealing resin 6 and the leads 4 are continuously cut by the third blade 43. At this time, the thickness of the third blade is made thicker than the width of the frame frame 21, and the third blade is cut so that the frame frame 21 connecting the adjacent leads 4 is cut away (STEP 6).
Finally, as shown in FIG. 6(d), after peeling off the dicing tape 52 from the leads 4, the semiconductor chip 1, and the sealing resin 6, the bottom and outer surfaces 4a of the leads 4 exposed from the sealing resin 6, and A plating film (not shown) is formed on the bottom surface of the semiconductor chip 1 to obtain the semiconductor device 10 (STEP 7).

Next, another manufacturing method example will be described.
First, perform the steps shown in STEP 1 and 2 in the previous example.
Next, a heat-resistant tape 53 is attached to the back surface of the lead frame 20.
Next, the process shown in STEP 3 of the previous example is performed.
Next, the semiconductor wafer 30 after full-cut dicing is slightly expanded, and the individualized semiconductor chips 1 are picked up and mounted at a predetermined position on the heat-resistant tape 53 attached to the lead frame 20. A predetermined position of the semiconductor chip 1 is between the opposing leads 4 .

Next, perform the steps shown in STEP 5 to 7 of the previous example.
By performing the steps described above, the semiconductor device 10 of the third embodiment of the present invention is obtained. The semiconductor device 10 obtained by this manufacturing method is small and thin, and has good mountability on a wiring board.

(Fourth embodiment)
FIG. 7 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention. The semiconductor device 10 of this embodiment does not have a die pad 5, and the semiconductor chip 1 is flip-chip connected to the leads 4 via bumps 9. When using the bonding wire 2 as a connection member, the loop height of the bonding wire 2 must be set higher than the top surface of the semiconductor chip 1. If a flip-chip connection is used, the thickness can be reduced by the loop height. Thereby, a thin semiconductor device 10 can be realized.

Further, since the semiconductor chip 1 and the leads 4 are structured to overlap, the distance between the semiconductor chip 1 and the leads 4 can be shortened compared to a wire connection, and a more compact semiconductor device 10 can be realized. As described above, the semiconductor device 10 of the fourth embodiment of the present invention can be further reduced in size and thickness.

The semiconductor device according to the present invention can be used in portable toys, health care products, wearable terminals, mobile terminals, card terminals, home appliances, and the like. It can also be applied to in-vehicle applications and outdoor applications, which have harsh operating environments.

1 Semiconductor chip 2 Bonding wire 3 Die attach layer 4 Lead 4a Outer surface 4b Inner surface 4c Side surface 5 Die pad 6 Sealing resin 7, 8 Penetration groove 9 Bump 10 Semiconductor device 11 Step portion 12 Spiral groove 13, 14 Cutting groove 20 Lead frame 21 Frame frame 30 Semiconductor wafers 41, 42, 43 Blade 51 Back grind tape 52 Dicing tape 53 Heat-resistant tape A Cutting tip angle

Claims (8)

semiconductor chip,
leads arranged around the semiconductor chip;
a connecting member connecting the semiconductor chip and the lead;
A sealing resin that seals the semiconductor chip, the leads, and the connection member,
The bottom surface of the lead is exposed from the sealing resin, and the side surface of the lead is provided with a tapered through groove that reaches from the top surface of the lead to the bottom surface of the lead,
A semiconductor device, wherein an area of the through-groove opening to the top surface of the lead is larger than an area opening to the bottom surface of the lead, and a spiral groove is provided on a side surface of the through-groove. semiconductor chip,
leads arranged around the semiconductor chip;
a connecting member connecting the semiconductor chip and the lead;
A sealing resin that seals the semiconductor chip, the leads, and the connection member,
The bottom surface of the lead is exposed from the sealing resin, and the side surface of the lead is provided with a tapered through groove that reaches from the top surface of the lead to the bottom surface of the lead,
A semiconductor device, wherein an area of the through-groove opening on the top surface of the lead is smaller than an area opening on the bottom surface of the lead, and a spiral groove is provided on a side surface of the through-groove. The semiconductor chip is mounted on a die pad, the bottom surface of the die pad is exposed from the sealing resin, and a tapered through groove extending from the top surface of the die pad to the bottom surface of the die pad is provided on the side surface of the die pad. The semiconductor device according to claim 1 or 2, characterized in that: Claim 1, wherein the semiconductor chip has a chamfered portion at the edge of the bottom surface, the bottom surface of the semiconductor chip is exposed from the sealing resin, and the chamfered portion is covered with the sealing resin. Or the semiconductor device according to 2. 3. The semiconductor device according to claim 1, wherein the semiconductor chip is flip-chip connected to the lead. preparing a lead frame including a lead having a through groove;
A process of back-grinding a semiconductor wafer;
half-cut dicing from the back side of the semiconductor wafer;
a step of attaching the back side of the semiconductor wafer to a dicing tape and performing full cut dicing from the front side of the semiconductor wafer;
expanding the dicing tape to widen the dimension between the diced semiconductor chips to the same dimension as the pitch size of the lead frame;
a step of bonding the dicing tape and the lead frame;
connecting the semiconductor chip and the leads with a connecting member;
sealing the semiconductor chip, the leads, and the connection member with a sealing resin;
cutting the sealing resin and the lead;
A method for manufacturing a semiconductor device, comprising the step of peeling the dicing tape from the leads, the semiconductor chip, and the sealing resin. The step of preparing a lead frame including leads having the through grooves includes:
a step of forming a through hole in a flat metal plate;
7. The method of manufacturing a semiconductor device according to claim 6, further comprising a punching step of cutting across the center of the through hole. 8. The tip of the first blade used in the half-cut dicing step is pyramid-shaped and wider than the width of the second blade used in the full-cut dicing step. A method for manufacturing a semiconductor device.