JP7366678B2 - Drive devices, semiconductor devices and electronic equipment - Google Patents

Description

The present invention relates to a drive device, a semiconductor device, and an electronic device.

2. Description of the Related Art Drive devices that control the state of a target transistor by controlling the voltage of a control electrode (for example, gate) of the target transistor are used in various electronic devices.

Japanese Patent Application Publication No. 2002-311000

FIG. 9 shows a drive device 901 according to a reference configuration. A drive device 901 in FIG. 9 includes transistors 911 and 912 configured as P-channel MOSFETs, transistors 913 to 915 configured as N-channel MOSFETs, a constant current source 921, and a switch 922. The state of the target transistor M900 is controlled by controlling the gate voltage _VG of the target transistor M900 configured as a type MOSFET. In the drive device 901, current mirror circuits CMa and CMb are formed. In the current mirror circuit CMa, a transistor 911 is placed on the current output side, and a transistor 912 is placed on the current input side. In current mirror circuit CMb, transistor 913 is placed on the current output side, and transistor 914 is placed on the current input side. Transistors 912 and 913 are connected in series with each other.

FIG. 10 shows a timing chart of the drive device 901. When the high active control signal G_ON is set to a high level, a constant current _ICC from a constant current source 921 flows as a current Ia to the transistor 914, and a current Ib proportional to the current Ia flows to the transistors 912 and 913. Furthermore, a current Ic proportional to current Ib flows through transistor 911. This current Ic increases the gate voltage _VG of the target transistor M900, thereby turning on the target transistor M900. Thereafter, when the control signal G_ON becomes low level, the transistor 915 is turned on, the gate voltage _VG is lowered to the ground level, and the target transistor M900 is turned off.

As can be seen from FIG. 10, in the drive device 901, the currents Ia and Ib continuously flow in the section where the target transistor M900 is to be turned on, so that corresponding power consumption occurs. It goes without saying that reducing power consumption is important in drive devices.

An object of the present invention is to provide a drive device, a semiconductor device, and an electronic device that contribute to reducing power consumption.

The drive device according to the present invention is a drive device that controls the state of the target transistor by controlling the voltage of the control electrode of the target transistor. a signal generation circuit that generates a second control signal that is active for a predetermined period of time from the start of the on-control period based on the control signal; and a drive transistor connected to the preceding stage circuit and the control electrode of the target transistor; In the period in which the second control signal is active, a predetermined current is caused to flow through the pre-stage circuit to generate a drive current in the drive transistor, and the drive current is supplied to the control electrode of the target transistor, so that the target transistor and a current supply circuit for turning on the target transistor, and a voltage at the control electrode of the target transistor to turn on the target transistor after the interval in which the second control signal is active and until the end of the on-control interval. and a voltage holding circuit that maintains the voltage, and the current supply circuit is configured to cut off the predetermined current in the pre-stage circuit after the period in which the second control signal becomes active (first configuration).

In the drive device according to the first configuration, the current supply circuit has a current mirror circuit, a predrive transistor forming the pre-stage circuit is disposed on the input side of the current mirror circuit, and the current supply circuit has a current mirror circuit. The drive transistor is disposed on the output side, and the current supply circuit generates the drive current in the drive transistor by causing a predrive current to flow through the predrive transistor in a period in which the second control signal is active. A configuration (second configuration) may be adopted in which the predrive current is cut off after a period in which the second control signal becomes active.

In the drive device according to the first configuration, the current supply circuit includes a first current mirror circuit and a second current mirror circuit, the drive transistor is disposed on the output side of the first current mirror circuit, and the current supply circuit includes a first current mirror circuit and a second current mirror circuit. The front-stage circuit includes a first transistor and a second transistor arranged on the input side and output side of the second current mirror circuit, and a predrive transistor arranged on the input side of the first current mirror circuit. , the second transistor and the predrive transistor are connected in series with each other, and the current supply circuit supplies the predrive transistor with a predetermined constant current flowing through the first transistor during the period in which the second control signal is active. generating a pre-drive current proportional to the constant current in a transistor, thereby causing the drive transistor to generate the drive current, and cutting off the constant current after a period in which the second control signal is active; This may also be a configuration (third configuration) in which the predrive current is also interrupted.

In the drive device according to any of the first to third configurations, the voltage holding circuit includes a voltage holding transistor inserted between an application end of a predetermined voltage and a control electrode of the target transistor, Based on the first control signal and the second control signal, after the period in which the second control signal is active, the voltage holding transistor is turned on until the end of the on control period, and the voltage holding transistor is turned on. The target transistor may be in an on state (fourth configuration) when the predetermined voltage is applied to the control electrode of the target transistor.

The drive device according to the fourth configuration further includes an OFF circuit having an OFF transistor inserted between an application terminal of a second predetermined voltage and a control electrode of the target transistor, and The on control period and the off control period in which the target transistor is to be in the off state are set, and the off circuit turns on the off transistor in the off control period and brings the off transistor into the on state. Accordingly, when the second predetermined voltage is applied to the control electrode of the target transistor, the target transistor may be turned off (fifth configuration).

In the drive device according to any one of the first to fifth configurations, the length of the predetermined time may be shorter than the length of the on-control section (sixth configuration).

In the drive device according to any one of the first to sixth configurations, the target transistor may be a field effect transistor (seventh configuration).

A semiconductor device according to the present invention has a configuration (eighth configuration) including one or more drive devices according to any of the first to seventh configurations.

An electronic device according to the present invention has a configuration (ninth configuration) including the semiconductor device according to the eighth configuration, and one or more target transistors whose states are controlled by the semiconductor device.

According to the present invention, it is possible to provide a drive device, a semiconductor device, and an electronic device that contribute to reducing power consumption.

FIG. 1 is a configuration diagram of a drive device and its peripheral circuits according to a first embodiment of the present invention. FIG. 3 is a relationship diagram of two control signals according to the first embodiment of the present invention. 3 is a timing chart of the drive device according to the first embodiment of the present invention. FIG. 2 is a schematic overall configuration diagram of a semiconductor circuit system for electronic equipment according to a second embodiment of the present invention. FIG. 7 is a diagram showing how a semiconductor circuit system is mounted on an electronic device according to a second embodiment of the present invention. FIG. 3 is an external perspective view of an electronic device according to a second embodiment of the present invention. FIG. 3 is an external perspective view of a semiconductor device according to a second embodiment of the present invention. FIG. 7 is a diagram showing a front-stage circuit according to a third embodiment of the present invention. FIG. 2 is a configuration diagram of a drive device and its peripheral circuits according to a reference configuration. 10 is a timing chart of the drive device of FIG. 9. FIG.

Examples of embodiments of the present invention will be specifically described below with reference to the drawings. In each referenced figure, the same parts are given the same reference numerals, and overlapping explanations regarding the same parts will be omitted in principle. In this specification, for the purpose of simplifying the description, by writing symbols or codes that refer to information, signals, physical quantities, elements, parts, etc., information, signals, physical quantities, elements, parts, etc. that correspond to the symbols or codes are indicated. Names such as names may be omitted or abbreviated. For example, the first control signal referred to by "GATE_ON" (see FIG. 1), which will be described later, may be written as first control signal GATE_ON, or may be abbreviated as control signal GATE_ON or signal GATE_ON. However, they all refer to the same thing.

First, some terms used in the description of the embodiments of the present invention will be explained. The ground refers to a conductive part having a reference potential of 0V (zero volts), or refers to the 0V potential itself. The potential of 0V is sometimes referred to as a ground potential. In embodiments of the invention, voltages shown without particular reference represent potentials with respect to ground.

Level refers to the level of potential, and for any signal or voltage, a high level has a higher potential than a low level. For any signal or voltage, a high level of the signal or voltage means that the level of the signal or voltage is high, and a low level of the signal or voltage means that the level of the signal or voltage is low. means that it is in The level of a signal may be expressed as a signal level, and the level of a voltage may be expressed as a voltage level.

For any given signal of interest, when the signal of interest is at a high level, the inverted signal of the signal of interest takes a low level, and when the signal of interest is at a low level, the inverted signal of the signal of interest takes a low level. Take a high level.

In any signal or voltage, switching from a low level to a high level is called an up edge, and the timing of switching from a low level to a high level is called an up edge timing. Similarly, in any signal or voltage, switching from a high level to a low level is called a down edge, and the timing of switching from a high level to a low level is called a down edge timing.

Regarding any signal having a signal level of high level or low level, a section where the level of the signal is high level is called a high level section, and a section where the level of the signal is low level is called a low level section. The same applies to any voltage that takes a high or low voltage level.

Regarding any transistor configured as a FET (field effect transistor) including a MOSFET, an on state refers to a state in which the drain and source of the transistor are in a conductive state, and an off state refers to a state where the drain and source of the transistor are in a conductive state. Refers to a state of non-conduction (blocking state) between the source and the source. The same applies to transistors that are not classified as FETs. The MOSFET may be understood to be an enhancement type MOSFET unless otherwise specified. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor."

Any switch can be composed of one or more FETs (field effect transistors), and when a switch is on, conduction occurs between both ends of the switch, while when the switch is off, the switch is electrically conductive. There is no conduction between both ends.

Hereinafter, the on state and off state of any transistor or switch may be simply expressed as on or off. For any transistor or switch, switching from an off state to an on state is expressed as turn-on, and switching from an on state to an off state is expressed as turn-off.

<<First embodiment>>
A first embodiment of the present invention will be described. FIG. 1 is a configuration diagram of a drive device 1 and its peripheral circuits according to a first embodiment of the present invention.

Connected to the drive device 1 are a control circuit 2 that supplies a control signal GATE_ON to the drive device 1, and a power supply circuit 3 that supplies power supply voltages VCC1 and VCC2 to the drive device 1. However, it may be understood that at least one of the control circuit 2 and the power supply circuit 3 is built into the drive device 1. Power supply voltages VCC1 and VCC2 are positive DC voltages, for example, 10V and 3V, respectively.

Further, a target transistor M0 and a capacitor C0 are connected to a terminal GATE_DRV provided in the drive device 1, and a load device LD is connected to the target transistor M0. In the example of FIG. 1, the target transistor M0 is configured as an N-channel MOSFET (metal-oxide-semiconductor field-effect transistor).

The drive device 1 controls the state (on/off state) of the target transistor M0 by controlling the gate voltage of the target transistor M0. Therefore, the drive device 1 is also called a gate drive device or a gate driver. A positive DC load drive voltage Va generated by a power supply circuit (not shown) is applied to the drain of the target transistor M0. A load device LD is provided between the source of the target transistor M0 and ground. The gate of the target transistor M0 is connected to the terminal GATE_DRV. Capacitor C0 is inserted between the gate of target transistor M0 and ground. Note that capacitor C0 may be omitted. Hereinafter, the gate voltage (gate potential) of the target transistor M0 will be referred to by the symbol "V _GATE ".

When the gate voltage V _GATE of the target transistor M0 is at a high level, the target transistor M0 is in an on state, and the voltage VDD is obtained by subtracting the voltage drop at the target transistor M0 (for example, several tens of millivolts) from the load drive voltage Va (for example, 5 V). is applied to the load device LD. That is, power based on the load drive voltage Va is supplied to the load device LD via the target transistor M0, and the load device LD is driven based on the load drive voltage Va (in other words, the voltage VDD). The high level of the gate voltage V _GATE of the target transistor M0 substantially matches the level of the power supply voltage VCC1 (for example, 10V), and is higher than the sum of the load drive voltage Va and the gate threshold voltage of the target transistor M0. Voltage VCC1 is higher.

When the gate voltage V _GATE of the target transistor M0 is at a low level, the target transistor M0 is turned off, and the supply of power to the load device LD based on the load drive voltage Va is cut off (in other words, the load drive voltage Va is (not supplied to load device LD). The low level of the gate voltage V _GATE of the target transistor M0 substantially matches the ground level.

The internal configuration of the drive device 1 will be explained. The drive device 1 includes a one-shot pulse generation circuit 10, a current supply circuit 20, a voltage holding circuit 30, and an off circuit 40, and also includes a terminal GATE_DRV as an external terminal.

The current supply circuit 20 includes a transistor M1 as a drive transistor and a front-stage circuit 60. The front-stage circuit 60 includes a transistor M2 as a predrive transistor, transistors M3, M4, and M7, a constant current source 61, a switch 62, and an inverter circuit 63. The voltage holding circuit 30 includes a transistor M5 as a voltage holding transistor and a NAND circuit 31. The OFF circuit 40 includes a transistor M6 as an OFF transistor and an inverter circuit 41. In the example of FIG. 1, transistors M1, M2, and M5 are configured as P-channel MOSFETs, and transistors M3, M4, M6, and M7 are configured as N-channel MOSFETs.

The one-shot pulse generation circuit 10 generates the second control signal DRV_ON based on the control signal GATE_ON, which is the first control signal. The second control signal DRV_ON is a one-shot pulse signal that remains at a high level for a predetermined time t _PLS . FIG. 2 shows the relationship between the first and second control signals. The first control signal and the second control signal are digital signals that take either a high level or a low level, respectively.

The first control signal GATE_ON is a signal that sets and specifies the on-control period in which the target transistor M0 is to be in the on state. Here, the first control signal GATE_ON is active when the first control signal GATE_ON is at a high level. (asserted state). In other words, the first control signal GATE_ON becomes active during the ON control period, and the high level period of the first control signal GATE_ON corresponds to the ON control period. The first control signal GATE_ON at a low level is inactive (negate state), and the low level period of the first control signal GATE_ON corresponds to an off control period in which the target transistor M0 is to be in an off state. The first control signal GATE_ON can be understood as a signal for setting and specifying the above-described on control period and off control period.

The one-shot pulse generation circuit 10 basically sets the second control signal DRV_ON to a low level. However, when an up edge occurs in the first control signal GATE_ON, the one shot pulse generation circuit 10 causes an up edge to also occur in the second control signal DRV_ON in synchronization with the up edge of the first control signal GATE_ON, and the second control signal GATE_ON generates an up edge. After keeping the signal DRV_ON at a high level for a predetermined time t _PLS , a down edge is generated in the second control signal DRV_ON.

The second control signal DRV_ON is a signal that controls supplying a current to the gate of the target transistor M0 through the transistor M1 to turn on the target transistor M0. Similarly to the first control signal GATE_ON, the second control signal DRV_ON is also assigned an active state (asserted state) for high level. Therefore, it can be said that the second control signal DRV_ON is a control signal (pulse signal) that is active for a predetermined time t _PLS from the start of the on-control period. As will become clear from the description below, a current for turning on the target transistor M0 is supplied to the gate of the target transistor M0 through the transistor M1 during the high level period of the second control signal DRV_ON, and the current is supplied to the gate of the target transistor M0. It is not supplied during the low level section of DRV_ON.

The length of the predetermined time t _PLS corresponding to the pulse width of the second control signal DRV_ON is much shorter than the length of one ON control section. For example, the length of one on-control section is several milliseconds or more, and may range from several seconds to several hundred seconds or more. On the other hand, the length of the predetermined time t _PLS is on the order of several microseconds or sub-microseconds. Of course, these numbers are just examples.

The configuration of the one-shot pulse generation circuit 10 is arbitrary as long as it can generate the second control signal DRV_ON having the above characteristics based on the first control signal GATE_ON. For example, a logic circuit that operates in synchronization with a clock signal having a predetermined frequency is used to generate, as the second control signal DRV_ON, a digital signal that goes high for a predetermined clock period in synchronization with the rising edge of the first control signal GATE_ON. can do. Alternatively, the second control signal DRV_ON may be generated by an analog circuit.

Referring again to FIG. 1, the connection relationship of the circuit configurations other than the one-shot pulse generation circuit 10 in the drive device 1 will be described.

The sources of transistors M1, M2, and M5 are commonly connected to an application terminal of power supply voltage VCC1 (a terminal to which power supply voltage VCC1 is applied). The drains of transistors M1, M5, and M6 are commonly connected to the terminal GATE_DRV (ie, commonly connected to the gate of target transistor M0). The source of transistor M6 is connected to ground.

The gate of the transistor M1, the gate and drain of the transistor M2, and the drain of the transistor M3 are commonly connected to each other. The gate of transistor M3, the gate and drain of transistor M4, and the drain of transistor M7 are commonly connected to each other. Each source of transistors M3, M4 and M7 is connected to ground. A constant current source 61 is inserted between the application terminal of the power supply voltage VCC2 (the terminal to which the power supply voltage VCC2 is applied) and one end of the switch 62. The other end of switch 62 is connected to the drain of transistor M4.

The second control signal DRV_ON is supplied to the input terminal of the inverter circuit 63, and the output terminal of the inverter circuit 63 is connected to the gate of the transistor M7. Further, the state of the switch 62 is controlled by the second control signal DRV_ON. The first control signal GATE_ON is supplied to the input terminal of the inverter circuit 41, and the output terminal of the inverter circuit 41 is connected to the gate of the transistor M6. The first control signal GATE_ON and the second control signal DRV_ON are input to the NAND circuit 31, and the output terminal of the NAND circuit 31 is connected to the gate of the transistor M5.

A current mirror circuit CM1 is configured by transistors M1 and M2. A transistor M2 is arranged on the current input side of the current mirror circuit CM1, and a transistor M1 is arranged on the current output side of the current mirror circuit CM1. A current mirror circuit CM2 is configured by transistors M3 and M4. A transistor M4 is arranged on the current input side of the current mirror circuit CM2, and a transistor M3 is arranged on the current output side of the current mirror circuit CM2. Transistors M2 and M3 are connected in series with each other.

The current flowing through the transistor M4 (specifically, the current flowing between the drain and source of the transistor M4) is referred to as a current I1. The current flowing through the transistors M2 and M3 (specifically, the current flowing between the drain and source of the transistors M2 and M3, respectively) is referred to as a current I2. The current flowing through the transistor M1 (specifically, the current flowing between the drain and source of the transistor M1) is referred to as a current I3.

The operation of the drive device 1 will be explained. The switch 62 is turned on when the second control signal DRV_ON is at a high level, and turned off when the second control signal DRV_ON is at a low level. The inverter circuit 63 supplies an inverted signal of the second control signal DRV_ON to the gate of the transistor M7. Therefore, the transistor M7 is turned off when the second control signal DRV_ON is at a high level, and turned on when the second control signal DRV_ON is at a low level.

Constant current source 61 generates a constant current I _CONST having a constant current value. During the high-level period of the second control signal DRV_ON, the switch 62 is turned on, so that the constant current I _CONST generated by the constant current source 61 flows as a current I1 between the drain and source of the transistor M4. During the high level period of the second control signal DRV_ON, current I1 (I _CONST ) flows through transistor M4, so current I2 proportional to current I1 (therefore, current I2 proportional to constant current I _CONST ) flows through transistors M2 and M3. Furthermore, a current I3 proportional to the current I2 (therefore, a current I3 proportional to the constant current _ICONST ) flows through the transistor M1.

Here, by adjusting the source area ratio between transistors M3 and M4 and adjusting the source area ratio between transistors M1 and M2, current I2 is set to 16 times the current I1, and current I3 is set to 35 times the current I2. It is assumed that Therefore, for example, if the current I1 is 0.625 μA in the high level section of the second control signal DRV_ON, the currents I2 and I3 are 10 μA and 350 μA, respectively. Of course, these numerical values can be modified in various ways. Note that, as understood from the circuit configuration of FIG. 1, even in the high-level period of the second control signal DRV_ON, the current I3 does not flow after the voltage of the terminal GATE_DRV reaches the power supply voltage VCC1.

During the low level period of the second control signal DRV_ON, the switch 62 is in the off state, so the constant current from the constant current source 61 does not flow to the transistor M4 (that is, "I1=0"), and therefore the currents I2 and I3 It doesn't flow either. Further, in the low level period of the second control signal DRV_ON, the transistor M7 is turned on, so that the gates and sources of the transistors M3 and M4 are short-circuited by the transistor M7.

The NAND circuit 31 supplies a NAND signal of the first control signal GATE_ON and an inverted signal of the second control signal DRV_ON to the gate of the transistor M5, thereby controlling the period in which the signal GATE_ON is at a high level and the signal DRV_ON is at a low level. Transistor M5 is turned on only in this case. Therefore, when the signal GATE_ON is at a low level, the transistor M5 is turned off, and when the signal DRV_ON is at a high level, the transistor M5 is also turned off.

The inverter circuit 41 supplies an inverted signal of the first control signal GATE_ON to the gate of the transistor M6, thereby turning on the transistor M6 during the low level period of the first control signal GATE_ON, and turning on the transistor M6 during the high level period of the first control signal GATE_ON. At this point, transistor M6 is turned off.

FIG. 3 is a timing chart of the drive device 1. The operation of the drive device 1 will be explained in more detail with reference to the timing chart of FIG. Assume that timings T ₁ , T ₂ , T ₃ , and T ₄ occur in this order as time progresses. Before timing _T1 , both signals GATE_ON and DRV_ON are maintained at a low level. Therefore, before timing _T1 , "I1 = I2 = I3 = 0" due to the switch 62 being turned off and the transistor M7 being turned on, and "V _GATE = 0" due to the transistor M5 being turned off and the transistor M6 being turned on. Target transistor M0 is off.

At timing _T1 , the first control signal GATE_ON switches from low level to high level. Then, the second control signal DRV_ON also switches from low level to high level at timing _T1 . At timing T ₃ , which is a predetermined time t _PLS after timing T ₁ , the level of the second control signal DRV_ON returns from high level to low level, and thereafter remains at low level until an up edge occurs again in the first control signal GATE_ON. maintained.

Between timings T ₁ and T ₃ , transistors M5 to M7 are all off. Between timings _T1 and _T3 , which is the high level section of the second control signal DRV_ON, current I1 (I _CONST ) flows through transistor M4, so current I2 is proportional to current I1 (therefore, constant current I _CONST is proportional to A current I2) flows through the transistors M2 and M3, and a current I3 proportional to the current I2 (therefore, a current I3 proportional to the constant current I _CONST ) flows through the transistor M1. However, as described above, even in the high level section of the second control signal DRV_ON, the current I3 does not flow after the voltage of the terminal GATE_DRV (that is, the gate voltage V _GATE ) reaches the power supply voltage VCC1. In the example of FIG. 3, it is assumed that the gate voltage V _GATE reaches the power supply voltage VCC1 at timing T ₂ after timing T ₁ .

More specifically, currents I1 and I2 flow continuously between timings _T1 and _T3 . The current I3 starts to flow from timing _T1 , but when the gate voltage _VGATE monotonically increases from 0V starting from timing _T1 due to this current I3 and reaches the power supply voltage VCC1 at timing _T2 , the flow of current I3 stops. stops. The predetermined time t _PLS or the values of the currents I1 to I3 are designed so that the gate voltage V _GATE reaches the power supply voltage VCC1 by the timing T ₃ due to the current I3. After timing _T3 , currents I1 to I3 do not flow until an up edge occurs again in the first control signal GATE_ON.

The transistor M0 is turned on while the gate voltage V _GATE increases from 0V to the power supply voltage VCC1. By turning on the transistor M5 at timing _T3 , the gate voltage _VGATE is fixed at the level of the power supply voltage VCC1. Therefore, after the target transistor M0 is turned on between timings _T1 and _T2 , the target transistor M0 is maintained in the on state until timing _T4 , which will be described later. Further, since the transistor M7 is turned on at timing _T3 , the voltage between the gates and sources of the transistors M3 and M4 immediately decreases toward 0V at timing _T3 , and the transistors M3 and M4 are turned off. Therefore, the currents I1 and I2 immediately decrease to zero after timing _T3 .

At timing _T4 , the first control signal GATE_ON switches from high level to low level. In response to this, at timing _T4 , transistor M5 is turned off and transistor M6 is turned on. When the transistor M6 turns on, the gate charge of the target transistor M0 is quickly drawn toward the ground through the transistor M6, and the gate voltage V _GATE quickly decreases toward 0V, thereby turning off the target transistor M0.

In comparison with the drive device 901 according to the reference configuration of FIG. Then, currents Ia and Ib) are cut off (ie, "I1=I2=0"). Therefore, power consumption is reduced by that amount. If the predetermined time _tPLS is sufficiently short and ignored, the power consumption will be substantially reduced by "(VCC2 x I1) + (VCC1 x I2)" in each on-control period, which is extremely beneficial. be. Particularly, as will be described later, in a configuration including drive devices for a plurality of channels, the effect of reducing power consumption becomes remarkable.

Note that if the gate voltage V _GATE of the target transistor M0 is abruptly raised, noise generated due to the abrupt voltage change may adversely affect the operation of other circuits. Additionally, if the gate voltage V _GATE is raised steeply, overshoot is likely to occur in the gate voltage V _GATE , and if an overshoot that exceeds the gate breakdown voltage of the target transistor M0 occurs, the target transistor M0 may be destroyed. . Due to these circumstances, the drive device 1 performs slew rate control in which, when turning on the target transistor M0, a constant current I3 is supplied to the gate of the target transistor M0 to gradually increase the gate voltage V _GATE . .

In the drive device 1, when turning off the target transistor M0, the gate voltage _VGATE is immediately lowered to 0V by turning on the transistor M6, but slew rate control is also performed when turning off the target transistor M0. You may also do this. That is, for example, in the drive device 1, a circuit that flows a constant current from the gate of the target transistor M0 to the ground starting from the down edge timing of the first control signal GATE_ON until the gate voltage _VGATE reaches 0V is set to the OFF state in FIG. It may be provided in place of the use circuit 40.

<<Second embodiment>>
A second embodiment of the present invention will be described. The second embodiment and the third and fourth embodiments described later are embodiments based on the first embodiment, and unless there is a contradiction, matters not specifically stated in the second to fourth embodiments are based on the first embodiment. The description of the embodiments also applies to the second to fourth embodiments. When interpreting the description of the second embodiment, the description of the second embodiment may take precedence regarding matters that are inconsistent between the first and second embodiments (the same applies to the third and fourth embodiments described later). . Any plurality of embodiments among the first to fourth embodiments may be combined as long as there is no contradiction.

FIG. 4 is a schematic overall configuration diagram of a semiconductor circuit system SYS for electronic equipment according to a second embodiment of the present invention. As shown in FIG. 5, the semiconductor circuit system SYS is installed in the electronic equipment EE. FIG. 6 shows an example of the external appearance of the electronic device EE. Although the electronic device EE shown in FIG. 6 is a notebook personal computer, the type of electronic device EE on which the semiconductor circuit system SYS is mounted is arbitrary. For example, the electronic device EE may be an information terminal such as a smart phone or a tablet, a game device, a digital video camera, a digital still camera, a car navigation system, a drive recorder, or other in-vehicle device.

The semiconductor circuit system SYS in FIG. 4 includes the semiconductor device 100 and n channels of pairs of target transistors M0 and capacitors C0. Here, n is an integer of 2 or more. The semiconductor device 100 includes n drive devices 1, a control circuit 2 that supplies a control signal GATE_ON to each drive device 1, and a power supply circuit that supplies power supply voltages VCC1 and VCC2 to each drive device 1. 3. The power supply circuit 3 also generates a power supply voltage for the control circuit 2. The n drive devices 1 are drive devices 1 for n channels, and are sometimes referred to as first to n-th channel drive devices 1.

The control circuit 2 generates a control signal GATE_ON for each drive device 1, for example, based on a signal from a higher-level control circuit (not shown) externally connected to the semiconductor device 100. The n-channel control signals GATE_ON for the n-channel drive devices 1 included in the semiconductor device 100 may be different from each other. That is, for example, the high level section of the control signal GATE_ON for the first channel drive device 1 may be different from the high level section of the control signal GATE_ON for the second channel drive device 1 (although they may match).

The power supply circuit 3 generates each power supply voltage including power supply voltages VCC1 and VCC2, for example, based on the output voltage of a battery mounted on the electronic device EE or based on the output voltage of an AC adapter (not shown).

A terminal GATE_DRV is individually provided for each of the first to nth channel drive devices 1. The target transistor M0 and capacitor C0 corresponding to the first channel are connected to the terminal GATE_DRV connected to the drive device 1 of the first channel, and the terminal GATE_DRV connected to the drive device 1 of the second channel is connected to the second A target transistor M0 and a capacitor C0 corresponding to the channel are connected. The same applies to other channels. In each channel, the connection relationship between the terminal GATE_DRV, the target transistor M0, the capacitor C0, and the load device LD is the same as that described in the first embodiment.

The n-channel drive device 1 can individually turn on and off the n-channel target transistors M0 based on the n-channel control signal GATE_ON from the control circuit 2. The load device LD is any hardware that constitutes the electronic device EE, and is, for example, a display device, a hard disk drive motor, a speaker, a logic circuit, or a semiconductor integrated circuit. The types of load devices LD may be different between different channels.

FIG. 7 shows the external appearance of the semiconductor device 100. The semiconductor device 100 is an electronic component formed by enclosing a semiconductor integrated circuit in a housing (package) made of resin. A plurality of external terminals are exposed on the casing of the semiconductor device 100, and the plurality of external terminals include n terminals GATE_DRV (that is, terminals for n channels GATE_DRV). In addition, the plurality of external terminals include a voltage input terminal for receiving the source voltages of the power supply voltages VCC1 and VCC2, a communication terminal for communicating with the upper control circuit, and the like. Note that the number of external terminals of the semiconductor device 100 and the appearance of the semiconductor device 100 shown in FIG. 7 are merely examples, and the type of casing of the semiconductor device 100 is arbitrary.

Note that in the second embodiment, the semiconductor device 100 that includes drive devices 1 for a plurality of channels is described above, but it is also possible to configure the semiconductor device 100 that includes drive devices 1 for only one channel (that is, n= 1).

<<Third Embodiment>>
A third embodiment of the present invention will be described. The pre-stage circuit 60 shown in FIG. 1 can also be represented as shown in FIG. The pre-stage circuit 60 in FIG. 8 includes a transistor M2 as a predrive transistor and a constant current source 66. The constant current source 66 is inserted between the transistor M2 and the ground, and supplies a constant current I2 to the transistor M2 only during the high level period of the second control signal DRV_ON (that is, flows between the drain and source of the transistor M2). . The constant current source 66 is configured so that the current I2 does not flow during the low level section of the second control signal DRV_ON. Therefore, in the low level section of the second control signal DRV_ON, "I2=0" and, as a result, "I3=0".

The block shown in FIG. 1 consisting of the constant current source 61, the switch 62, the transistors M3, M4, and M7, and the inverter circuit 63 is an example of the configuration of the constant current source 66, and the function of the constant current source 66 described above is realized. The configuration of the constant current source 66 is arbitrary as long as it is.

<<Fourth embodiment>>
A fourth embodiment of the present invention will be described. In the fourth embodiment, some applied techniques, modification techniques, etc. will be explained, and the present invention embodied in the first to third embodiments will be considered.

Each circuit element of the drive device 1 is formed in the form of a semiconductor integrated circuit, and the drive device 1 is configured by encapsulating the semiconductor integrated circuit in a case (package) made of resin. However, a circuit equivalent to the circuit inside the drive device 1 may be configured using a plurality of discrete components. Some of the circuit elements described above as being included in the drive device 1 may be provided outside the drive device 1 and externally connected to the drive device 1. Similarly, each circuit element of the semiconductor device 100 is formed in the form of a semiconductor integrated circuit, and the semiconductor device 100 is configured by encapsulating the semiconductor integrated circuit in a casing (package) made of resin. Ru. However, a circuit equivalent to the circuit inside the semiconductor device 100 may be configured using a plurality of discrete components. Some of the circuit elements described above as included in the semiconductor device 100 may be provided outside the semiconductor device 100 and externally connected to the semiconductor device 100.

For any signal or voltage, the relationship between high and low levels may be reversed without detracting from the spirit described above.

The types of channels of FETs (field effect transistors) shown in each embodiment are merely examples, and an N-channel FET may be changed to a P-channel FET, or a P-channel FET may be changed to an N-channel FET. The configuration of the circuit containing the FET can be modified to change the type of FET.

For example, the target transistor M0 may be a P-channel MOSFET. However, in this case, the height relationship of the gate voltage V _GATE of the target transistor M0 in the ON control period and the OFF control period, the direction of the current I3, etc. are opposite to those shown in the first embodiment. That is, when the target transistor M0 is a P-channel MOSFET, the gate voltage V _GATE of the target transistor M0 is made sufficiently high during the low level period of the first control signal GATE_ON to turn the target transistor M0 into an off state, and the current control circuit 20 turns on the target transistor M0 by flowing a current I3 in a direction in which the gate voltage V _GATE decreases during the high level section of the second control signal DRV_ON, and the voltage holding circuit 30 turns on the target transistor M0 when the signal GATE_ON is at a high level and the signal DRV_ON is at a high level. By keeping the gate voltage V _GATE at the ground potential during the low level period, the target transistor M0 is maintained in the on state.

Any transistor mentioned above may be any type of transistor. For example, any transistor described above as a MOSFET can be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor), or a bipolar transistor. Any transistor has a first electrode, a second electrode, and a control electrode. In a FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

However, the above-described target transistor M0 is preferably a voltage-controlled transistor such as an FET including a MOSFET or an IGBT. A voltage-controlled transistor is a transistor whose drain-source is controlled to be conductive or non-conductive depending on the gate-source voltage (in other words, the current flowing between the drain-source is controlled), or , a transistor whose collector-emitter is controlled to be conductive or non-conductive (in other words, the current flowing between the collector-emitter is controlled) according to the gate-emitter voltage.

The drive device W according to one aspect of the present invention is a drive device (1) that controls the state of the target transistor by controlling the voltage of the control electrode of the target transistor (M0), in which the target transistor is turned on. a signal generation circuit (10) that generates a second control signal (DRV_ON) that is active for a predetermined time from the start of the on-control period based on a first control signal (GATE_ON) that is active during the on-control period; A circuit (60) and a drive transistor (M1) connected to the control electrode of the target transistor, and in a section where the second control signal is active, the drive transistor is a current supply circuit (20) that turns on the target transistor by generating a drive current (I3) and supplying the drive current to the control electrode of the target transistor; and a voltage holding circuit (30) that maintains the voltage of the control electrode of the target transistor at a voltage (VCC1) for turning on the target transistor until the end of the on-control period, and supplies the current. The circuit is characterized in that the predetermined current in the pre-stage circuit is cut off after the period in which the second control signal is active.

In the semiconductor device 1 of FIG. 1, the one-shot pulse generation circuit 10 is an example of the signal generation circuit. Cutting off the predetermined current in the pre-stage circuit refers to cutting off (stopping) the flow of the predetermined current in the pre-stage circuit.

Specifically, for example, in the drive device W, the current supply circuit includes a current mirror circuit (CM1), and a predrive transistor (M2) constituting the pre-stage circuit is arranged on the input side of the current mirror circuit. The drive transistor (M1) is disposed on the output side of the current mirror circuit, and the current supply circuit supplies a predrive current (I2) to the predrive transistor in an interval in which the second control signal is active. It is preferable that the drive current (I3) is generated in the drive transistor by causing the predrive current to flow, and that the predrive current is cut off after a period in which the second control signal becomes active.

Or specifically, for example, in the drive device W, the current supply circuit includes a first current mirror circuit (CM1) and a second current mirror circuit (CM2), and the current supply circuit includes a first current mirror circuit (CM1) and a second current mirror circuit (CM2). The drive transistor (M1) is disposed, and the pre-stage circuit includes a first transistor (M4) and a second transistor (M3) disposed on the input side and output side of the second current mirror circuit, and the first current mirror circuit. a predrive transistor (M2) disposed on the input side of the mirror circuit, the second transistor and the predrive transistor are connected in series with each other, and the current supply circuit has a predrive transistor (M2) disposed on the input side of the mirror circuit; By passing a predetermined constant current (I1=I _CONST ) through the first transistor in the interval, the predrive transistor generates a predrive current (I2) proportional to the constant current, thereby The drive current may be generated at , and after a period in which the second control signal becomes active, the constant current may be cut off, and thereby the predrive current may also be cut off.

Cutting off the constant current means cutting off the flow of the constant current, and specifically means cutting off the supply of the constant current to the first transistor. Cutting off the predrive current means cutting off the flow of the predrive current, and specifically means cutting off the supply of the predrive current to the predrive transistor.
In the semiconductor device 1 of FIG. 1, the current I2 is an example of a predrive current, and the current I3 is an example of a drive current.

For example, in the drive device W, the voltage holding circuit (30) includes a voltage holding transistor (M5) inserted between an application end of a predetermined voltage (VCC1) and a control electrode of the target transistor. , based on the first control signal and the second control signal, after the period in which the second control signal is active, the voltage holding transistor is turned on until the end of the on control period, and the voltage holding transistor is turned on. When the target transistor is turned on and the predetermined voltage is applied to the control electrode of the target transistor, the target transistor is preferably turned on.

For example, the circuit further includes an off circuit (40) having an off transistor (M6) inserted between an application end of the second predetermined voltage and a control electrode of the target transistor, and the turn-off circuit (40) includes A control period and an OFF control period in which the target transistor is to be in an OFF state are set, and the OFF circuit turns the OFF transistor into an ON state in the OFF control period, and the OFF transistor is brought into an ON state. When the second predetermined voltage is applied to the control electrode of the target transistor, the target transistor may be turned off.

In the semiconductor device 1 of FIG. 1, the ground voltage (i.e. 0V) corresponds to the second predetermined voltage, but the second predetermined voltage is a voltage different from the ground voltage (for example, a voltage slightly higher than the ground voltage). , or a negative voltage).

The embodiments of the present invention can be appropriately modified in various ways within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present invention, and the meanings of the terms of the present invention and each component are not limited to those described in the above embodiments. The specific numerical values shown in the above-mentioned explanatory text are merely examples, and it goes without saying that they can be changed to various numerical values.

1 Drive device 2 Control circuit 3 Power supply circuit 10 One shot pulse generation circuit 20 Current supply circuit 30 Voltage holding circuit 40 Off circuit 60 Pre-stage circuit 100 Semiconductor device M0 Target transistor M1 Transistor (drive transistor)
M2 transistor (pre-transistor)
M5 transistor (voltage holding transistor)
M6 transistor (off transistor)
GATE_ON control signal (first control signal)
DRV_ON control signal (second control signal)

Claims (7)

In a drive device that controls a state of the target transistor by controlling a voltage of a control electrode of the target transistor,
a signal generation circuit that generates a second control signal that is active for a predetermined time from the start of the on-control period based on a first control signal that is active during the on-control period in which the target transistor is to be in the on-state;
A drive transistor is provided which is connected to a control electrode of a front-stage circuit and the target transistor, and a drive current is supplied to the drive transistor by flowing a predetermined current to the front-stage circuit in an interval in which the second control signal is active. a current supply circuit that turns on the target transistor by generating and supplying the drive current to a control electrode of the target transistor;
a voltage holding circuit that maintains the voltage of the control electrode of the target transistor at a voltage for turning on the target transistor until the end of the on-control interval after the interval in which the second control signal is active; Prepare,
The current supply circuit cuts off the predetermined current in the preceding stage circuit after a period in which the second control signal is active;
The current supply circuit includes a first current mirror circuit and a second current mirror circuit,
The drive transistor is arranged on the output side of the first current mirror circuit,
The pre-stage circuit includes a first transistor and a second transistor arranged on the input side and output side of the second current mirror circuit, and a predrive transistor arranged on the input side of the first current mirror circuit. death,
the second transistor and the predrive transistor are connected in series with each other,
The current supply circuit is
In the period in which the second control signal is active, by flowing a predetermined constant current through the first transistor, the predrive transistor generates a predrive current proportional to the constant current, thereby causing the drive transistor to generate the drive current,
After the period in which the second control signal is active, the constant current is cut off, and thereby the predrive current is also cut off.
, drive device. The voltage holding circuit includes a voltage holding transistor inserted between an application end of a predetermined voltage and a control electrode of the target transistor, and the voltage holding circuit has a voltage holding transistor inserted between an application end of a predetermined voltage and a control electrode of the target transistor. After the period in which the control signal is active, the voltage holding transistor is turned on until the end of the on-control period;
When the voltage holding transistor is turned on and the predetermined voltage is applied to the control electrode of the target transistor, the target transistor is turned on.
, The drive device according to claim 1. further comprising an off circuit having an off transistor inserted between a second predetermined voltage application end and a control electrode of the target transistor;
The first control signal sets the on control period and the off control period in which the target transistor is to be in the off state,
The off circuit turns on the off transistor in the off control period,
When the second predetermined voltage is applied to the control electrode of the target transistor due to the off transistor being in the on state, the target transistor is in the off state.
, The drive device according to claim 2 . The length of the predetermined time is shorter than the length of the on control section.
, A drive device according to any one of claims 1 to 3 . The target transistor is composed of a field effect transistor.
A drive device according to any one of claims 1 to 4 . Consisting of one or more drive devices according to any one of claims 1 to 5.
, semiconductor devices. A semiconductor device according to claim 6;
one or more target transistors whose states are controlled by the semiconductor device;
,Electronics.

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