JP7366869B2 - semiconductor equipment - Google Patents

Description

Embodiments of the present invention relate to semiconductor devices.

Semiconductor devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are used for applications such as power conversion. It is desirable that the power loss of a semiconductor device be small.

JP 2019-12813 Publication

An object of the present invention is to provide a semiconductor device that can reduce power loss.

A semiconductor device according to an embodiment includes a first electrode, a semiconductor layer, a first conductive part, a second conductive part, and a second electrode. The semiconductor layer is provided on the first electrode. The semiconductor layer includes a first semiconductor region of a first conductivity type electrically connected to the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, and a second semiconductor region of a second conductivity type provided on the first semiconductor region. The semiconductor device includes a third semiconductor region of the first conductivity type provided on the second semiconductor region. The first conductive portion includes a buried electrode portion provided in the first semiconductor region via a first insulating portion. The second conductive portion includes a gate electrode portion that is provided on the buried electrode portion with a second insulating portion interposed therebetween and faces the second semiconductor region with the gate insulating portion interposed therebetween. The second electrode is provided on the semiconductor layer and electrically connected to the second semiconductor region and the third semiconductor region. The first conductive part is electrically connected to the second conductive part. The electrical resistance of the first conductive part is greater than the electrical resistance of the second conductive part.

FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. 3 is a sectional view taken along line III-III in FIGS. 1 and 2. FIG. 3 is a sectional view taken along the line IV-IV in FIGS. 1 and 2. FIG. 3 is a graph showing characteristics of a semiconductor device according to a reference example. 3 is a graph showing characteristics of the semiconductor device according to the first embodiment. 3 is a graph showing characteristics of semiconductor devices according to a reference example and a first embodiment. FIG. 3 is a schematic diagram illustrating a method for measuring the capacitance of the semiconductor device according to the first embodiment. FIG. 3 is a schematic diagram showing resistance and capacitance in the semiconductor device according to the first embodiment. FIG. 3 is an equivalent circuit diagram when measuring capacitance. FIG. 3 is a schematic diagram illustrating a method for measuring the capacitance of the semiconductor device according to the first embodiment. FIG. 3 is an equivalent circuit diagram when measuring capacitance. FIG. 3 is a plan view showing a semiconductor device according to a first modification of the first embodiment. 14 is a sectional view taken along line XIV-XIV in FIG. 13. FIG. FIG. 7 is a plan view showing a semiconductor device according to a second modification of the first embodiment. 16 is a sectional view taken along line XVI-XVI in FIG. 15. FIG. FIG. 7 is a plan view showing a semiconductor device according to a third modification of the first embodiment. FIG. 18 is a sectional view taken along line XVIII-XVIII in FIG. 17; FIG. 7 is a cross-sectional view showing a part of a semiconductor device according to a third modification of the first embodiment. FIG. 7 is a schematic diagram showing a semiconductor device according to a fourth modification of the first embodiment. FIG. 7 is a schematic diagram showing a semiconductor device according to a fifth modification of the first embodiment. It is a graph showing the characteristics of a semiconductor device. FIG. 7 is a plan view showing a semiconductor device according to a fifth modification of the first embodiment. FIG. 7 is a cross-sectional view showing a part of a semiconductor device according to a fifth modification of the first embodiment. FIG. 7 is a plan view showing a semiconductor device according to a second embodiment. 26 is a sectional view taken along line XXVI-XXVI in FIG. 25. FIG. FIG. 2 is a schematic diagram showing a semiconductor device according to a second embodiment. 7 is a graph showing characteristics of semiconductor devices according to a reference example and a second embodiment. FIG. 7 is a schematic diagram showing a semiconductor device according to a first modification of the second embodiment. FIG. 7 is a schematic diagram showing a semiconductor device according to a second modification of the second embodiment. 3 is a graph showing characteristics of semiconductor devices according to a reference example, a first embodiment, and a second embodiment. FIG. 7 is a plan view showing a semiconductor device according to a third embodiment. 33 is a cross-sectional view taken along XXXIII-XXXIII in FIG. 32. FIG.

Each embodiment of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be shown differently depending on the drawing.
In the specification of this application and each figure, elements similar to those already explained are given the same reference numerals, and detailed explanations are omitted as appropriate.
In the following description and drawings, n ⁺ , n, n ⁻ and p ⁺ , p represent relative levels of each impurity concentration. In other words, a notation with a "+" has a relatively higher impurity concentration than a notation with neither a "+" nor a "-", and a notation with a "-" Indicates that the impurity concentration is relatively lower than the notation without . When each region contains both p-type impurities and n-type impurities, these notations represent the relative height of the net impurity concentration after these impurities compensate for each other.
Each of the embodiments described below may be implemented by inverting the p-type and n-type of each semiconductor region.

(First embodiment)
1 and 2 are plan views showing the semiconductor device according to the first embodiment.
FIG. 3 is a sectional view taken along line III--III in FIGS. 1 and 2. FIG. 4 is a sectional view taken along the line IV-IV in FIGS. 1 and 2.
In FIG. 2, the source electrode 32 is omitted and the gate electrode portion 21 is shown by a broken line.
The semiconductor device according to the first embodiment is a MOSFET. As shown in FIGS. 1 to 4, the semiconductor device 100 according to the first embodiment includes a semiconductor layer SL, a first conductive part 10, a second conductive part 20, a drain electrode 31 (first electrode), and a source electrode 32. (second electrode), and gate pad 33 (third electrode). The semiconductor layer SL includes an n ⁻ type (first conductivity type) drift region 1 (first semiconductor region), a p type (second conductivity type) base region 2 (second semiconductor region), and an n ⁺ type source region 3 (second semiconductor region). 3 semiconductor region), a p ⁺ type contact region 4, and an n ⁺ type drain region 5.

In the description of the embodiments, an XYZ orthogonal coordinate system is used. The direction from the drain electrode 31 toward the n ⁻ type drift region 1 is defined as the Z direction (first direction). Two directions that are perpendicular to the Z direction and orthogonal to each other are defined as the X direction (second direction) and the Y direction (third direction). Furthermore, for the sake of explanation, the direction from the drain electrode 31 toward the n ^- type drift region 1 is referred to as "up", and the opposite direction is referred to as "down". These directions are based on the relative positional relationship between the drain electrode 31 and the n ^- type drift region 1, and are independent of the direction of gravity.

As shown in FIG. 1, a source electrode 32 and a gate pad 33 are provided on the upper surface of the semiconductor device 100. In the example shown in FIG. 1, a first wiring section 12 and a second wiring section 22 are further provided. The first wiring section 12, the second wiring section 22, and the gate pad 33 are separated from the source electrode 32. In the example shown in FIG. 1, a pair of first wiring portions 12 are provided in the Y direction. A plurality of second wiring parts 22 are provided between the pair of first wiring parts 12. A plurality of source electrodes 32 are provided between adjacent first wiring portions 12 and second wiring portions 22, and between adjacent second wiring portions 22.

As shown in FIG. 3, a drain electrode 31 is provided on the bottom surface of the semiconductor device 100. An n ⁻ type drift region 1 is provided above the drain electrode 31 with an n ⁺ type drain region 5 interposed therebetween. The n ⁻ type drift region 1 is electrically connected to the drain electrode 31 via the n ⁺ type drain region 5 . The p-type base region 2 is provided on the n ^- type drift region 1. An n ⁺ type source region 3 and a p ⁺ type contact region 4 are provided on the p type base region 2 .

Source electrode 32 is provided on n ⁺ type source region 3 and p ⁺ type contact region 4 . Source electrode 32 is electrically connected to p type base region 2, n ⁺ type source region 3, and p ⁺ type contact region 4. In the example shown in FIG. 3, a pair of n ⁺ type source regions 3 are provided on one p-type base region 2, and a plug 32a is provided below the source electrode 32. The plug 32a extends in the Z direction between the n ⁺ type source regions 3. The lower end of the plug 32a is located in the p-type base region 2. P ⁺ type contact region 4 is provided between p type base region 2 and the lower end of plug 32a.

As shown in FIG. 4, the first conductive part 10 includes a buried electrode part 11 and a first wiring part 12. The second conductive section 20 includes a gate electrode section 21 and a second wiring section 22 . As shown in FIG. 3, the buried electrode portion 11 is buried in the n ⁻ type drift region 1 via the first insulating portion 11a. The gate electrode section 21 is provided on the buried electrode section 11 via the second insulating section 11b. Gate electrode portion 21 faces p-type base region 2 via gate insulating portion 21a. In the example shown in FIG. 3, the gate electrode portion 21 further faces a portion of the n ⁻ type drift region 1 and a portion of the n ⁺ type source region 3.

As shown in FIGS. 2 and 3, a plurality of gate electrode sections 21 are provided in the X direction. Each gate electrode section 21 extends along the Y direction. Similarly, a plurality of buried electrode portions 11, p type base regions 2, n ⁺ type source regions 3, and p ⁺ type contact regions 4 are provided in plurality in the X direction and extend along the Y direction.

As shown in FIG. 4, the buried electrode section 11 is electrically connected to a pair of first wiring sections 12 at both ends in the Y direction. The gate electrode section 21 is electrically connected to the plurality of second wiring sections 22 . The first wiring section 12 may be electrically connected to the gate electrode section 21 in addition to the buried electrode section 11 .

As shown in FIGS. 1 and 2, the first wiring section 12 of the first conductive section 10 is electrically connected to the gate pad 33. The second wiring section 22 of the second conductive section 20 is electrically connected to the gate pad 33 . The first conductive part 10 and the second conductive part 20 are electrically connected to each other. The electrical resistance of the first conductive part 10 is greater than the electrical resistance of the second conductive part 20.

The electrical resistance of the first conductive part 10 includes the electrical resistance of the buried electrode part 11, the electrical resistance of the first wiring part 12, the connection resistance between the buried electrode part 11 and the first wiring part 12, and the like. The electrical resistance of the second conductive part 20 includes the electrical resistance of the gate electrode part 21, the electrical resistance of the second wiring part 22, the connection resistance between the gate electrode part 21 and the second wiring part 22, and the like.

The operation of the semiconductor device 100 will be explained.
While a positive voltage is applied to the drain electrode 31 with respect to the source electrode 32, a voltage equal to or higher than the threshold is applied to the gate electrode portion 21 via the gate pad 33. A channel (inversion layer) is formed in a region of p-type base region 2 near gate insulating portion 21a, and semiconductor device 100 is turned on. Electrons flow from the source electrode 32 to the drain electrode 31 through the channel and n ^- type drift region 1 . At this time, a voltage is also applied to the buried electrode section 11. By applying a voltage to the buried electrode portion 11, an accumulation layer is formed in the vicinity of the first insulating portion 11a of the n ⁻ type drift region 1. This reduces the on-resistance of the semiconductor device 100. Thereafter, when the voltage applied to the gate electrode portion 21 becomes lower than the threshold value, the channel in the p-type base region 2 disappears, and the semiconductor device 100 is turned off.

When the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 31 with respect to the buried electrode section 11 and the gate electrode section 21 increases. As the positive voltage increases, the depletion layer spreads from the interface between the first insulating portion 11a and the n ^- type drift region 1 toward the n ^- type drift region 1. This expansion of the depletion layer allows the breakdown voltage of the semiconductor device 100 to be increased. Alternatively, the on-resistance of the semiconductor device 100 can be reduced by increasing the n-type impurity concentration in the n ⁻ type drift region 1 while maintaining the breakdown voltage of the semiconductor device 100.

An example of the material of each component of the semiconductor device 100 will be explained.
The n ⁻ type drift region 1, the p type base region 2, the n ⁺ type source region 3, the p ⁺ type contact region 4, and the n ⁺ type drain region 5 are made of silicon, silicon carbide, gallium nitride, or gallium as a semiconductor material. Contains arsenic. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity.
The buried electrode section 11 and the gate electrode section 21 contain a conductive material such as polysilicon. Impurities may be added to the conductive material.
The first insulating section 11a, the second insulating section 11b, and the gate insulating section 21a include an oxide-based insulating material such as silicon oxide.
The first wiring section 12, the second wiring section 22, the drain electrode 31, the source electrode 32, and the gate pad 33 contain metal such as aluminum or copper. Plug 32a includes metal such as tungsten.

FIG. 5 is a graph showing the characteristics of the semiconductor device according to the reference example.
FIG. 6 is a graph showing the characteristics of the semiconductor device according to the first embodiment.
In FIGS. 5 and 6, the horizontal axis represents time T. The vertical axis represents the voltage Vg of the gate electrode section 21 with respect to the drain electrode 31. Time T and voltage Vg are expressed in arbitrary units. 5 and 6 show simulation results showing changes in the voltage of the gate electrode section 21 when a voltage is applied to the gate pad 33. FIG.

In the semiconductor devices 100a and 100b according to the reference example, the electrical resistance of the first conductive section 10 is the same as the electrical resistance of the second conductive section 20. Furthermore, in the semiconductor device 100a, the first conductive section 10 does not include the first wiring section 12. The buried electrode portion 11 is electrically isolated from the gate pad 33 and electrically connected to the source electrode 32 . In the semiconductor device 100b, the first conductive portion 10 is electrically connected to the gate pad 33, similarly to the semiconductor device 100.

In the semiconductor device 100b, the on-resistance is lower than that in the semiconductor device 100a due to the accumulation layer formed in the n ^- type drift region 1 in the on state. On the other hand, in the semiconductor device 100b, the capacitance Cgd between the drain electrode 31 and the gate pad 33 is increased compared to the semiconductor device 100a.

During a period when the voltage between the drain electrode 31 and the source electrode 32 is changing, a current corresponding to the capacitance Cgd flows through the gate pad 33. In this period (mirror period), a mirror effect occurs that looks like a huge capacitor whose capacitance Cgd is multiplied by Gm is connected between the gate pad 33 and the source electrode 32. Gm is the mutual conductance of the semiconductor device 100. During the mirror period, charging or discharging of this huge capacitor appears to occur, and the voltage Vg becomes approximately constant. As can be seen from FIG. 5, due to the increase in capacitance Cgd, the mirror period P becomes longer in the semiconductor device 100b than in the semiconductor device 100a. As the mirror period P becomes longer, power loss during switching of the semiconductor device increases. Therefore, from the viewpoint of reducing power loss, it is desirable that the mirror period P be short.

In the semiconductor device 100 according to the first embodiment, the electrical resistance of the first conductive part 10 is greater than the electrical resistance of the second conductive part 20. When the voltage of the gate pad 33 changes with respect to the drain electrode 31, the voltage of the buried electrode section 11 changes with a delay compared to the voltage of the gate electrode section 21. As a result, charging or discharging of the capacitance Cgd component generated by the first conductive section 10 occurs later than charging or discharging of the capacitance Cgd component generated by the second conductive section 20. When the voltage of the gate pad 33 changes, the capacitance Cgd component due to the first conductive portion 10 becomes less likely to appear as a mirror effect. In other words, before the charging or discharging of the capacitance Cgd generated by the first conductive part 10 is completed, the channel formed in the region near the gate insulating part 21a of the p-type base region 2 due to the potential of the gate electrode part 21 (The inversion layer) lowers the voltage between the drain electrode 31 and the source electrode 32, and the mirror period ends. As a result, the mirror period P during which the voltage Vg remains substantially constant can be shortened.

FIG. 6 shows changes in the mirror period P when the electrical resistance Rg of the second conductive part 20 is fixed and the electrical resistance Rfp of the first conductive part 10 is varied from twice to 20 times the resistance Rg. There is. From FIG. 6, when the resistance Rfp is twice the resistance Rg, the rise in the voltage Vg at the end of the mirror period P is steeper than when the resistance Rfp and the resistance Rg are equal, and the mirror period P is shortened. I understand. For this reason, the resistance Rfp is preferably twice or more the resistance Rg. When the resistance Rfp is 10 times or more the resistance Rg, the mirror period P is halved and greatly shortened compared to when the resistance Rfp and the resistance Rg are equal. For this reason, it is more preferable that the resistance Rfp is 10 times or more the resistance Rg.

FIG. 7 is a graph showing the characteristics of the semiconductor devices according to the reference example and the first embodiment.
In FIG. 7, the vertical axis represents power loss L. The power loss L is expressed as the sum of the power loss Lon in the on state, the power loss Lton during turn-on, and the power loss Ltoff during turn-off. FIG. 7 shows simulation results when the turn-on time is 20 μs and the output current of the gate driver is 2A. The resistance Rg of each semiconductor device is fixed. In the semiconductor device 100 according to the first embodiment, the resistance Rfp was varied from 60 times the resistance Rg to 200 times the resistance Rg.

A comparison of the semiconductor devices 100a and 100b shows that the semiconductor device 100b has a lower power loss Lon than the semiconductor device 100a. On the other hand, in the semiconductor device 100b, the power losses Lton and Ltoff are increased compared to the semiconductor device 100a. As a result, it can be seen that the overall power loss L in the semiconductor device 100b is increased compared to the semiconductor device 100a.

A comparison of the semiconductor devices 100 and 100a shows that the power loss Lon of the semiconductor device 100 is smaller than that of the semiconductor device 100a. In the semiconductor device 100, similarly to the semiconductor device 100b, the power losses Lton and Ltoff are increased compared to the semiconductor device 100a. However, the amount of increase is suppressed compared to the semiconductor device 100a. As a result, the overall power loss L in the semiconductor device 100 is lower than that in the semiconductor device 100a. It can also be seen that the larger the resistance Rfp is, the smaller the power loss L is.

On the other hand, if the resistance Rfp is excessively large, the potential of the buried electrode section 11 tends to fluctuate when a current flows through the buried electrode section 11 during switching of the semiconductor device 100. For example, the potential difference between the drain electrode 31 and the buried electrode portion 11 temporarily increases, making it easier for avalanche breakdown to occur in the n ⁻ type drift region 1. As a result, the breakdown voltage of the semiconductor device 100 may decrease. In order to suppress a decrease in breakdown voltage, the resistance Rfp is preferably 300 times or less the resistance Rg.

The electrical resistivity of the buried electrode section 11 is preferably greater than the electrical resistivity of the gate electrode section 21 so that the resistance Rfp is greater than the resistance Rg. For example, by reducing the length of the buried electrode portion 11 in the X direction and the length in the Z direction, the electrical resistivity of the buried electrode portion 11 can be increased. When impurities are added to the buried electrode portion 11 and the gate electrode portion 21, the impurity concentration in the buried electrode portion 11 may be lower than the impurity concentration in the gate electrode portion 21. As shown in FIG. 4, the difference between the resistance Rg and the resistance Rfp may be increased by making the number of the second wiring parts 22 larger than the number of the first wiring parts 12.

A method for specifying the resistance Rg and the resistance Rfp will be explained.
8 and 11 are schematic diagrams showing a method for measuring the capacitance of the semiconductor device according to the first embodiment.
FIG. 9 is a schematic diagram showing resistance and capacitance in the semiconductor device according to the first embodiment.
10 and 12 are equivalent circuit diagrams when measuring capacitance.
In FIGS. 8 and 11, the drain electrode 31 corresponds to the terminal D. Source electrode 32 corresponds to terminal S. Gate pad 33 corresponds to terminal G.

An LCR meter is used to specify the resistance Rg and the resistance Rfp. First, the impedance of the output capacitance Coss is measured. The output capacitance Coss is the sum of the capacitance Cfp and the capacitance Cgd. As shown in FIG. 8, terminals G and S are shorted. The high voltage side terminal Hi of the LCR meter 90 is connected to the terminal D. The low voltage side terminal Lo of the LCR meter 90 is connected to the terminals G and S.

At this time, the semiconductor device 100 between the terminal Hi and the terminal Lo includes a capacitor Cgd, a capacitor Cfp, a capacitor Cgs, a resistor Rg, and a resistor Rfp, as shown in FIG. In FIG. 9, capacitance Cfp represents the capacitance between n ⁻ type drift region 1 and buried electrode portion 11. The capacitance Cgd represents the capacitance between the n ⁻ type drift region 1 and the gate electrode portion 21. Capacitance Cgs represents the capacitance between p-type base region 2 and gate electrode section 21. The pn junction capacitance between the n ^- type drift region 1 and the p-type base region 2 is sufficiently smaller than the capacitance Cfp and can therefore be ignored.

Each resistance and each capacitance of the semiconductor device 100 shown in FIG. 9 is equivalently represented by the circuit diagram shown in FIG. In the semiconductor device 100, the resistance Rg is smaller than the resistance Rfp. Therefore, the resistance Rg and the capacitance Cgs are ignored. At this time, the impedance Z of the output capacitance Coss is expressed by Formula 1.

すなわち、インピーダンスの実部（レジスタンス）の測定結果は、抵抗Ｒｆｐとみなすことができる。 Capacitance Cgd is smaller than capacitance Cfp. Therefore, Equation 1 can be expressed as Equation 2.

That is, the measurement result of the real part (resistance) of impedance can be regarded as resistance Rfp.

After specifying the resistance Rfp, the impedance of the input capacitance Ciss is measured. The input capacitance Ciss is the sum of the capacitance Cgd and the capacitance Cgs. As shown in FIG. 11, terminals G and S are shorted. The high voltage side terminal Hi of the LCR meter 90 is connected to the terminal D. The low voltage side terminal Lo of the LCR meter 90 is connected to the terminals G and S.

数式３の実部に、上述した方法で特定した抵抗Ｒｆｐを代入する。代入後の実部の式とインピーダンスの実部の測定結果とを比較することで、抵抗Ｒｇを算出できる。 At this time, each resistance and each capacitance of the semiconductor device 100 shown in FIG. 9 are equivalently represented by the circuit diagram shown in FIG. The impedance Z of the input capacitance Ciss is expressed by Equation 3.

The resistance Rfp specified by the method described above is substituted into the real part of Equation 3. The resistance Rg can be calculated by comparing the equation of the real part after substitution with the measurement result of the real part of the impedance.

(First and second variations)
FIG. 13 is a plan view showing a semiconductor device according to a first modification of the first embodiment. FIG. 14 is a sectional view taken along line XIV-XIV in FIG. 13.
FIG. 15 is a plan view showing a semiconductor device according to a second modification of the first embodiment. FIG. 16 is a sectional view taken along line XVI-XVI in FIG. 15.

In the semiconductor device 110 according to the first modified example shown in FIGS. 13 and 14, the ratio of the number of first wiring parts 12 to the number of second wiring parts 22 is smaller than in the semiconductor device 100. As the number of first wiring sections 12 decreases, the electrical resistance between buried electrode section 11 and gate pad 33 increases. Therefore, in the semiconductor device 110, the electrical resistance of the first conductive portion 10 is greater than that in the semiconductor device 100.

In the semiconductor device 120 according to the second modified example shown in FIGS. 15 and 16, the ratio of the number of second wiring parts 22 to the number of first wiring parts 12 is larger than that in the semiconductor device 110. As the number of second wiring sections 22 increases, the electrical resistance between the gate electrode section 21 and the gate pad 33 decreases. Therefore, in the semiconductor device 120, the electrical resistance of the second conductive portion 20 is smaller than that in the semiconductor device 110.

According to the first modification or the second modification, the difference between the electrical resistance of the first conductive part 10 and the electrical resistance of the second conductive part 20 can be made larger with a simple structure.

By adjusting the sizes of the first wiring section 12 and the second wiring section 22, the difference between the electrical resistance of the first conductive section 10 and the electrical resistance of the second conductive section 20 may be increased. For example, the thickness of the first wiring section 12 in the Z direction may be smaller than the thickness of the second wiring section 22 in the Z direction. The width of the first wiring section 12 may be narrower than the width of the second wiring section 22. The width of each wiring section corresponds to the length of each wiring section in a direction perpendicular to the direction in which each wiring section extends.

(Third modification)
FIG. 17 is a plan view showing a semiconductor device according to a third modification of the first embodiment.
FIG. 18 is a sectional view taken along line XVIII-XVIII in FIG. 17.
FIG. 19 is a cross-sectional view showing a part of a semiconductor device according to a third modification of the first embodiment.
In a semiconductor device 130 according to the third modification, the first conductive section 10 further includes a wiring resistor 13, as shown in FIG.

The wiring resistor 13 is electrically connected between the gate pad 33 and the first wiring section 12 . In the example shown in FIGS. 17 and 19, a wiring portion 33a extending in the Y direction is electrically connected to the gate pad 33. The second wiring section 22 is electrically connected to the gate pad 33 or the wiring section 33a. The wiring resistor 13 is electrically connected between the first wiring section 12 and the wiring section 33a. Furthermore, in order to increase the electrical resistivity of the first conductive part 10 compared to the second conductive part 20, the first wiring part 12 is not connected to the gate electrode part 21, as shown in FIG.

The electrical resistivity of the wiring resistor 13 is higher than the electrical resistivity of each of the first wiring section 12, the second wiring section 22, the gate pad 33, and the wiring section 33a. Accordingly, for example, the electrical resistance of the wiring resistor 13 is higher than the electrical resistance of each of the first wiring section 12, the second wiring section 22, the gate pad 33, and the wiring section 33a. For example, the electrical resistivity of the wiring resistor 13 is higher than that of the embedded electrode portion 11.

The material of the wiring resistor 13 is arbitrary as long as the above-mentioned electrical resistivity relationship can be realized. For example, the wiring resistor 13 includes polysilicon. The impurity concentration in the wiring resistor 13 is lower than the impurity concentration in the buried electrode portion 11.

The wiring resistance 13 may be provided on the semiconductor layer SL or may be provided in the semiconductor layer SL. The wiring resistance 13 is electrically isolated from the semiconductor layer SL. For example, as shown in FIG. 19A, the wiring resistor 13 is provided on the semiconductor layer SL with an insulating layer 13a interposed therebetween. Alternatively, as shown in FIG. 19(b), the wiring resistor 13 is provided in the semiconductor layer SL with an insulating layer 13b interposed therebetween.

In the structure shown in FIG. 19(b), the level difference on the surface of the semiconductor layer SL is reduced compared to the structure shown in FIG. 19(a). When forming a contact above the wiring resistor 13, lithography becomes easier. Moreover, the wiring resistor 13 can be manufactured in the same formation process as the buried electrode part 11 or the gate electrode part 21, and the number of steps required for manufacturing the semiconductor device 130 can be reduced.

By providing the wiring resistance 13, the difference between the electrical resistance of the first conductive part 10 and the electrical resistance of the second conductive part 20 can be further increased.

(Fourth modification)
FIG. 20 is a schematic diagram showing a semiconductor device according to a fourth modification of the first embodiment.
As shown in FIG. 20, the semiconductor device 140 according to the fourth modification further includes a resistor 40 compared to the semiconductor device 100.

The gate pad 33 is electrically connected between the first conductive part 10 and the resistor 40 and between the second conductive part 20 and the resistor 40. The electrical resistance Rext of the resistor 40 is larger than the electrical resistance Rg of the second conductive portion 20, for example. The electrical resistance Rfp of the first conductive part 10 is larger than the resistance Rext. Preferably, the resistance Rfp is 5 times or more and 150 times or less the resistance Rext.

The resistor 40 can be made of any material as long as the above-mentioned electrical resistivity relationship can be achieved. For example, the resistor 40 is formed of polysilicon with an adjusted impurity concentration, single crystal silicon, or metal with an adjusted width. The metal is, for example, at least one selected from the group consisting of aluminum, copper, titanium nitride, and tungsten nitride.

(Fifth modification)
FIG. 21 is a schematic diagram showing a semiconductor device according to a fifth modification of the first embodiment.
FIG. 22 is a graph showing the characteristics of the semiconductor device.
FIG. 23 is a plan view showing a semiconductor device according to a fifth modification of the first embodiment.
FIG. 24 is a cross-sectional view showing a part of the semiconductor device according to the fifth modification of the first embodiment.
As shown in FIG. 21, the semiconductor device 150 according to the fifth modification further includes a bidirectional Zener diode 50, compared to the semiconductor device 100.

Zener diode 50 is electrically connected between first conductive section 10 and gate pad 33 . The Zener diode 50 allows current to flow from one of the first conductive part 10 and the second conductive part 20 to the other when a voltage larger than the other is applied. Thereby, the possibility that the semiconductor device 150 is destroyed due to the application of high voltage to the first conductive part 10 and the gate pad 33 can be reduced.

Zener diode 50 includes, for example, polysilicon or single crystal silicon. The breakdown voltage of Zener diode 50 is arbitrary. When a reverse voltage is applied, a current may flow through the Zener diode 50 due to Zener breakdown, or a current may flow through the Zener diode 50 due to avalanche breakdown.

In FIG. 22, the horizontal axis represents time T. The vertical axis represents the voltage Vg of the gate electrode section 21 with respect to the drain electrode 31. Time T and voltage Vg are expressed in arbitrary units. FIG. 22 shows simulation results showing changes in the voltage of the buried electrode section 11 when the voltage of the gate pad 33 is changed. Specifically, a voltage is applied to the gate pad 33 at time T=0. At time T=0.5, application of voltage to gate pad 33 is stopped.

It can be seen from FIG. 22 that the larger the resistance Rfp is than the resistance Rg, the larger the fluctuation in the voltage of the buried electrode section 11 becomes. When the voltage of the buried electrode part 11 changes, the potential difference between the buried electrode part 11 and the gate electrode part 21 is generated in the second insulating part 11b between the buried electrode part 11 and the gate electrode part 21. join. If the potential difference becomes excessively large, dielectric breakdown may occur in the second insulating portion 11b, and the semiconductor device 150 may be destroyed. By providing the Zener diode 50, it is possible to reduce the possibility that the semiconductor device 150 will be destroyed by the potential difference between the buried electrode section 11 and the gate electrode section 21.

Zener diode 50 is electrically connected between at least a portion of first conductive section 10 and second conductive section 20 . In the example of FIG. 21, the Zener diode 50 is electrically connected between a part of the first conductive part 10 and the second conductive part 20, and is connected in parallel with another part of the first conductive part 10. ing. The Zener diode 50 allows current to flow from one of the first conductive part 10 and the second conductive part 20 to the other when a voltage larger than the other is applied.

More specifically, when the Zener diode 50 is provided, the first conductive portion 10 includes electrical resistances Rfp1 and Rfp2 as shown in FIG. 21. The second conductive part 20 is made of electrical resistance Rg. One end of the Zener diode 50 is electrically connected between resistors Rfp1 and Rfp2. The other end of the Zener diode 50 is electrically connected to a resistor Rg. Zener diode 50 is connected in parallel with resistor Rfp1.

In the semiconductor device 150, the resistance Rfp1 is larger than the resistance Rg. Resistor Rfp1 is larger than resistor Rfp2. Thereby, the difference between the electrical resistance of the first conductive part 10 and the electrical resistance of the second conductive part 20 can be increased, and power loss during switching can be reduced.

For example, as shown in FIG. 23, a wiring resistor 13 and a Zener diode 50 are connected in parallel between the first wiring section 12 and the wiring section 33a. The Zener diode 50 includes a plurality of n-type semiconductor layers 51 and a plurality of p-type semiconductor layers 52 that are alternately provided, as shown in FIGS. 24(a) and 24(b). The Zener diode 50 may be provided on the semiconductor layer SL with an insulating layer 50a interposed therebetween, as shown in FIG. 24(a). Alternatively, as shown in FIG. 24(b), the Zener diode 50 may be provided in the semiconductor layer SL with an insulating layer 50b interposed therebetween.

The modifications described above can be combined as appropriate. For example, the resistor 40 of the semiconductor device 140 or the Zener diode 50 of the semiconductor device 150 may be provided in any of the semiconductor devices 110 to 130. In any of semiconductor devices 110, 120, and 140, first conductive section 10 may include wiring resistor 13.

(Second embodiment)
FIG. 25 is a plan view showing the semiconductor device according to the second embodiment. FIG. 26 is a sectional view taken along line XXVI-XXVI in FIG. 25.
In FIG. 25, the first wiring section 12, the second wiring section 22, the gate pad 33, and the wiring section 33a are represented by broken lines. Further, the source electrode 32 is omitted.
As shown in FIGS. 25 and 26, the semiconductor device 200 according to the second embodiment differs from the semiconductor device according to the first embodiment in that the first conductive section 10 includes a coil 60.

Coil 60 is electrically connected between buried electrode section 11 and gate pad 33 . Coil 60 is connected in series with embedded electrode section 11 . In the example shown in FIG. 25, a wiring portion 33a extending in the Y direction is electrically connected to the gate pad 33. The coil 60 is electrically connected between the first wiring section 12 and the wiring section 33a.

As shown in FIG. 26, the coil 60 is spirally provided along the XY plane in an insulating layer 61 provided on the semiconductor layer SL. The first wiring section 12 and the wiring section 33a are provided on the insulating layer 61. One end of the coil 60 is electrically connected to the wiring section 33a. The other end of the coil 60 is electrically connected to the first wiring section 12 . For example, the buried electrode section 11 or the gate electrode section 21 is not provided under the coil 60.

The coil 60 has a larger inductance than the buried electrode section 11, the first wiring section 12, the gate electrode section 21, the second wiring section 22, and the like. Therefore, the inductance of the first conductive part 10 is larger than the inductance of the second conductive part 20.

For example, when the capacitance Cfp is 2000 pF and the resistance Rfp is 1Ω, the inductance of the coil 60 is greater than 10 nanohenry and less than 1 microhenry. For example, using an LCR meter, terminals are brought into contact with one end and the other end of the coil 60, and the impedance is measured. Inductance can be calculated from the measurement results of the imaginary part of impedance.

Coil 60 includes metal such as aluminum or copper, for example. Insulating layer 61 includes an insulating material such as silicon oxide.

FIG. 27 is a schematic diagram showing a semiconductor device according to the second embodiment.
As shown in FIG. 27, the first conductive section 10 includes an inductance Lfp connected in series with a resistor Rfp. Inductance Lfp is the inductance of coil 60. The resistance Rfp may be the same as the resistance Rg of the second conductive part 20, or may be different from the resistance Rg.

FIG. 28 is a graph showing the characteristics of the semiconductor devices according to the reference example and the second embodiment.
In FIG. 28, the horizontal axis represents time T. The vertical axis represents voltage Vg. Time T and voltage Vg are expressed in arbitrary units. FIG. 28 shows simulation results showing changes in the voltage of the gate electrode section 21 when a voltage is applied to the gate pad 33. As a reference example, the characteristics of the semiconductor device 100b shown in FIG. 5 are shown. Regarding the semiconductor device 200, the resistance Rfp is set smaller than the resistance Rg.

It can be seen from FIG. 28 that the mirror period P of the semiconductor device 200 is shorter than the mirror period P of the semiconductor device 100b. That is, according to the second embodiment, as in the first embodiment, when the voltage of the gate pad 33 with respect to the drain electrode 31 changes, the voltage of the buried electrode section 11 becomes lower than the voltage of the gate electrode section 21. also changes with a delay. As a result, the mirror period P can be shortened compared to the semiconductor device according to the reference example.

As shown in FIG. 27, between the drain electrode 31 and the first conductive portion 10, there is a capacitance Cfp generated between the buried electrode portion 11 and the n ⁻ type drift region 1. When a capacitor Cfp is present in series with the resistor Rfp and the inductance Lfp, an RLC resonant circuit is configured by the resistor Rfp, the inductance Lfp, and the capacitor Cfp. As a result, as shown in FIG. 28, oscillations may occur in the voltage of the gate pad 33 during switching of the semiconductor device 200.

It is preferable that the voltage oscillation period of the gate pad 33 be short. During vibration, the voltage on the gate pad 33 repeatedly increases and decreases. When the voltage of the gate pad 33 is temporarily lowered due to vibration, the electrical resistance of the storage layer formed by the buried electrode part 11 and the electrical resistance of the inversion layer formed by the gate electrode part 21 increase. By shortening the vibration, the period during which the electrical resistance of the storage layer and the electrical resistance of the inversion layer increase can be shortened.

The oscillation period To of the voltage of the gate pad 33 is expressed by Equation 4 below.

The Q value regarding the voltage vibration of the gate pad 33 is expressed by the following equation 5.

It is preferable that the voltage oscillation period of the gate pad 33 be shorter than the turn-on time Ton of the semiconductor device 200. If Ton>QTo, vibrations in the voltage of the gate pad 33 can be damped during the turn-on time Ton. That is, it is sufficient if the following formula 6 is satisfied.

Typical MOSFETs are used, for example, at frequencies above 100 kHz and below 200 kHz. That is, in a typical MOSFET, one turn-on time is longer than 2.5 μs and less than 5.0 μs. 2πLfp/Rfp is preferably less than 2.5×10 ⁻⁶ . That is, the inductance Lfp is preferably less than 0.4×10 ⁻⁶ times the resistance Rfp.

(First modification)
FIG. 29 is a schematic diagram showing a semiconductor device according to the first modification of the second embodiment.
As shown in FIG. 29, the semiconductor device 210 according to the first modification further includes a resistor 40 compared to the semiconductor device 200.

The gate pad 33 is electrically connected between the first conductive part 10 and the resistor 40 and between the second conductive part 20 and the resistor 40. The electrical resistance Rext of the resistor 40 is larger than the electrical resistance Rg of the second conductive portion 20, for example. The electrical resistance Rfp of the first conductive part 10 may be larger or smaller than the resistance Rext.

By providing the resistor 40, the switching speed of the semiconductor device 210 can be adjusted.

(Second modification)
FIG. 30 is a schematic diagram showing a semiconductor device according to a second modification of the second embodiment.
As shown in FIG. 30, the semiconductor device 220 according to the second modification further includes a bidirectional Zener diode 50, compared to the semiconductor device 200.

Zener diode 50 is connected in parallel with inductance Lfp. That is, the Zener diode 50 is connected in parallel with the coil 60. The Zener diode 50 allows current to flow from one of the first conductive part 10 and the second conductive part 20 to the other when a voltage larger than the other is applied. This makes it possible to reduce the possibility that the semiconductor device 220 will be destroyed due to the application of high voltage to the first conductive portion 10 and the gate pad 33, similarly to the fifth modification of the first embodiment.

(Third modification)
In the semiconductor device according to the second embodiment, the resistance Rfp may be larger than the resistance Rg. Due to the increase in resistance Rfp, compared to semiconductor device 200, the change in voltage of buried electrode portion 11 is delayed further than the change in voltage of gate electrode portion 21. This allows the mirror period to be further shortened. Alternatively, by increasing the resistance Rfp, the inductance Lfp can be reduced while maintaining the shortening of the mirror period. Thereby, it is possible to suppress vibrations in the voltage of the gate pad 33 during switching.

FIGS. 31(a) and 31(b) are graphs showing the characteristics of the semiconductor devices according to the reference example, the first embodiment, and the second embodiment.
The horizontal axis in FIGS. 31(a) and 31(b) represents time T. The vertical axis in FIG. 31(a) represents the voltage Vg. The vertical axis in FIG. 31(b) represents the voltage Vd of the drain electrode 31 with respect to the source electrode 32. Time T, voltage Vg, and voltage Vd are expressed in arbitrary units. 31(a) and 31(b) show simulation results showing changes in voltage Vg and voltage Vd when voltage is applied to gate pad 33. FIG. As a reference example, the characteristics of the semiconductor device 100b shown in FIG. 5 are shown. Regarding the semiconductor device 100 according to the first embodiment, the characteristics are shown when the resistance Rfp is set to 10 times the resistance Rg. Regarding the semiconductor device 230 according to the third modification, the characteristics are shown when the resistance Rfp is set to twice the resistance Rg.

From the change in voltage Vg in FIG. 31A, it can be seen that the mirror period P of the semiconductor device 230 is shorter than the mirror period P of the semiconductor device 100b and is equal to the mirror period P of the semiconductor device 100. Moreover, from the change in voltage Vd in FIG. 31(b), the decrease in voltage Vd in semiconductor devices 100 and 230 is steeper than the decrease in voltage Vd in semiconductor device 100b. That is, it can be seen that in the semiconductor devices 100 and 230, when a voltage is applied to the gate pad 33, the transition to the on state occurs more quickly than in the semiconductor device 100b.

Further, from a comparison between FIG. 28 and FIG. 31(a), it can be seen that the period of oscillation of the voltage Vg in the semiconductor device 230 is shorter than the period of oscillation of the voltage Vg in the semiconductor device 200. This indicates that according to the third modification, the period of oscillation of the voltage of the gate pad 33 in the semiconductor device 230 can be shortened compared to the semiconductor device 200.

In the semiconductor device 230, in order to effectively shorten the mirror period P, the resistance Rfp is preferably twice or more the resistance Rg. Furthermore, in order to suppress a decrease in breakdown voltage, the resistance Rfp is preferably 10 times or less the resistance Rg.

The modifications described above can be combined as appropriate. For example, the Zener diode 50 of the semiconductor device 220 may be provided in the semiconductor device 210.

(Third embodiment)
FIG. 32 is a plan view showing a semiconductor device according to the third embodiment. FIG. 33 is a sectional view taken along XXXIII-XXXIII in FIG. 32.
In FIG. 32, the insulating member 75 is represented by a broken line. Source electrode 32 is omitted.
The semiconductor device 300 according to the third embodiment further includes a coil 60, a first metal member 71, a second metal member 72, and a third metal member 73, compared to the semiconductor device according to the first embodiment. Furthermore, instead of the gate pad 33, a first pad 14 and a second pad 24 are provided.

The first metal member 71 is provided below the drain electrode 31. Drain electrode 31 is electrically connected to first metal member 71 . The first metal member 71 includes a first terminal 71a protruding in the Y direction. A plurality of first terminals 71a are provided in the X direction.

The second metal member 72 is separated from the first metal member 71. The second metal member 72 includes a second terminal 72a protruding in the Y direction. The second terminal 72a faces opposite to the first terminal 71a. A plurality of second terminals 72a are provided in the X direction.

The third metal member 73 is separated from the first metal member 71 and the second metal member 72. The third metal member 73 includes a third terminal 73a aligned with the plurality of second terminals 72a in the X direction.

As shown in FIGS. 32 and 33, the first conductive section 10 includes a buried electrode section 11, a first wiring section 12, and a first pad 14. The first pad 14 is provided on the semiconductor layer SL. The buried electrode section 11 and the first wiring section 12 are electrically connected to the first pad 14. The first pad 14 is electrically connected to the metal member 74 via the bonding wire W1. The metal member 74 is separated from the first to third metal members 71 to 73.

The second conductive section 20 includes a gate electrode section 21 , a second wiring section 22 , and a second pad 24 . The second pad 24 is provided on the semiconductor layer SL and is separated from the first pad 14. The gate electrode section 21 and the second wiring section 22 are electrically connected to the second pad 24. The second pad 24 is electrically connected to the third metal member 73 via the bonding wire W2.

The metal member 74 is electrically connected to the third metal member 73 via the chipped coil 60. That is, the first conductive part 10 is electrically connected to the third metal member 73 via the coil 60.

The insulating member 75 is provided on a part of the first metal member 71, a part of the second metal member 72, a part of the third metal member 73, the metal member 74, and the semiconductor layer SL, and seals them. are doing.

The first metal member 71, the second metal member 72, the third metal member 73, and the metal member 74 include metal such as aluminum or copper. The insulating member 75 includes an insulating resin such as polyimide.

According to the third embodiment, due to the coil 60, the change in the voltage of the buried electrode section 11 is delayed relative to the change in the voltage of the gate electrode section 21. Therefore, according to the third embodiment, the mirror period of the semiconductor device 300 can be shortened similarly to the second embodiment.

The embodiments described above can be combined as appropriate. For example, the coil 60 may be provided in any of the semiconductor devices according to the first embodiment, similarly to the semiconductor devices according to the second embodiment or the third embodiment. For any semiconductor device according to the first embodiment, similarly to the semiconductor device 300, a coil 60, a first metal member 71, a second metal member 72, a third metal member 73, a metal member 74, and an insulating member are provided. 75 may be provided.

Embodiments may include the following configurations.
(Configuration 1)
a first electrode;
A semiconductor layer provided on the first electrode,
a first semiconductor region of a first conductivity type electrically connected to the first electrode;
a second semiconductor region of a second conductivity type provided on the first semiconductor region; and
a third semiconductor region of a first conductivity type provided on the second semiconductor region;
The semiconductor layer comprising;
a first conductive portion including a buried electrode portion provided in the first semiconductor region via a first insulating portion;
a second conductive portion including a gate electrode portion provided on the buried electrode portion via a second insulating portion and facing the second semiconductor region via the gate insulating portion;
a second electrode provided on the semiconductor layer and electrically connected to the second semiconductor region and the third semiconductor region;
Equipped with
The first conductive part is electrically connected to the second conductive part,
The semiconductor device, wherein the electrical resistance of the first conductive part is greater than the electrical resistance of the second conductive part.
(Configuration 2)
further comprising a third electrode provided on the semiconductor layer and electrically connected to the first conductive part and the second conductive part,
The first conductive part further includes a first wiring part that is electrically connected between the buried electrode part and the third electrode and provided on the semiconductor layer,
The semiconductor device according to Configuration 1, wherein the second conductive part further includes a second wiring part that is electrically connected between the gate electrode part and the third electrode and provided on the semiconductor layer.
(Configuration 3)
Further equipped with a resistor,
The third electrode is electrically connected between the resistor and the first conductive part and between the resistor and the second conductive part,
The semiconductor device according to configuration 2, wherein the electrical resistance of the first conductive portion is greater than the electrical resistance of the resistor.
(Configuration 4)
The first conductive part further includes a wiring resistance electrically connected between the first wiring part and the third electrode,
The semiconductor device according to configuration 2 or 3, wherein the electrical resistivity of the wiring resistance is higher than the electrical resistivity of the first wiring portion.
(Configuration 5)
5. The semiconductor device according to any one of configurations 1 to 4, wherein the electrical resistance of the first conductive part is 10 times or more and 300 times or less the electrical resistance of the second conductive part.
(Configuration 6)
6. The semiconductor device according to any one of configurations 1 to 5, further comprising a bidirectional Zener diode electrically connected between the first conductive part and the second conductive part.
(Configuration 7)
a first electrode;
A semiconductor layer provided on the first electrode,
a first semiconductor region of a first conductivity type electrically connected to the first electrode;
a second semiconductor region of a second conductivity type provided on the first semiconductor region; and
a third semiconductor region of a first conductivity type provided on the second semiconductor region;
The semiconductor layer comprising;
a second electrode provided on the semiconductor layer and electrically connected to the second semiconductor region and the third semiconductor region;
a third electrode provided on the semiconductor layer;
a buried electrode portion provided in the first semiconductor region via a first insulating portion;
a first wiring part provided on the semiconductor layer and electrically connected to the buried electrode part; and
a wiring resistance electrically connected between the first wiring part and the third electrode;
a first conductive part electrically connected to the third electrode;
a second conductive portion including a gate electrode portion provided on the buried electrode portion via a second insulating portion and facing the second semiconductor region via the gate insulating portion;
Equipped with
In the semiconductor device, the electrical resistivity of the wiring resistance is higher than the electrical resistivity of the first wiring portion.
(Configuration 8)
8. The semiconductor device according to configuration 7, wherein the buried electrode portion has a higher electrical resistivity than the gate electrode portion.
(Configuration 9)
9. The semiconductor device according to configuration 7 or 8, further comprising a bidirectional Zener diode electrically connected between the first conductive part and the second conductive part.
(Configuration 10)
10. The semiconductor device according to any one of configurations 1 to 9, wherein the first conductive part further includes a coil.
(Configuration 11)
a first metal member provided under the first electrode and electrically connected to the first electrode;
a second metal member separated from the first metal member and electrically connected to the second electrode;
a third metal member separated from the first metal member and the second metal member, electrically connected to the second conductive part, and electrically connected to the first conductive part via a coil;
10. The semiconductor device according to any one of Structures 1 and 7 to 9, further comprising:
(Configuration 12)
a first electrode;
A semiconductor layer provided on the first electrode,
a first semiconductor region of a first conductivity type electrically connected to the first electrode;
a second semiconductor region of a second conductivity type provided on the first semiconductor region; and
a third semiconductor region of a first conductivity type provided on the second semiconductor region;
The semiconductor layer comprising;
a first conductive part including a buried electrode part provided in the first semiconductor region via a first insulating part, and a coil connected in series with the buried electrode part;
A gate electrode portion is provided on the buried electrode portion via a second insulating portion and is opposed to the second semiconductor region via the gate insulating portion, and is electrically connected to the first conductive portion. a second conductive part;
a second electrode provided on the semiconductor layer and electrically connected to the second semiconductor region and the third semiconductor region;
A semiconductor device equipped with
(Configuration 13)
further comprising a third electrode provided on the semiconductor layer and electrically connected to the first conductive part and the second conductive part,
13. The semiconductor device according to configuration 12, wherein the coil is electrically connected between the buried electrode section and the third electrode.
(Configuration 14)
a first metal member;
a first electrode provided on the first metal member and electrically connected to the first metal member;
A semiconductor layer provided on the first electrode,
a first semiconductor region of a first conductivity type electrically connected to the first electrode;
a second semiconductor region of a second conductivity type provided on the first semiconductor region; and
a third semiconductor region of a first conductivity type provided on the second semiconductor region;
The semiconductor layer comprising;
a first conductive portion including a buried electrode portion provided in the first semiconductor region via a first insulating portion;
a second conductive portion including a gate electrode portion provided on the buried electrode portion via a second insulating portion and facing the second semiconductor region via the gate insulating portion;
a second electrode provided on the semiconductor layer and electrically connected to the second semiconductor region and the third semiconductor region;
a second metal member separated from the first metal member and electrically connected to the second electrode;
a third metal member separated from the first metal member and the second metal member, electrically connected to the second conductive part, and electrically connected to the first conductive part via a coil;
A semiconductor device equipped with
(Configuration 15)
The first conductive part includes a first pad provided on the semiconductor layer,
The second conductive part includes a second pad provided on the semiconductor layer,
15. The semiconductor device according to configuration 14, wherein the third metal member is electrically connected to the second pad and electrically connected to the first pad via the coil.
(Configuration 16)
16. The semiconductor device according to any one of configurations 12 to 15, further comprising a bidirectional Zener diode connected in parallel with the coil.
(Configuration 17)
17. The semiconductor device according to any one of configurations 12 to 16, wherein the electrical resistance of the first conductive part is 2 times or more and 10 times or less the electrical resistance of the second conductive part.

In each of the embodiments described above, the relative level of impurity concentration between each semiconductor region can be confirmed using, for example, an SCM (scanning capacitance microscope). Note that the carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative height of carrier concentration between each semiconductor region can also be confirmed using SCM. Further, the impurity concentration in each semiconductor region can be measured by, for example, SIMS (secondary ion mass spectrometry).

Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, changes, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included within the scope and gist of the invention, as well as within the scope of the invention described in the claims and its equivalents. Further, each of the embodiments described above can be implemented in combination with each other.

1 n ^- type drift region, 2 p type base region, 3 n ⁺ type source region, 4 p ⁺ type contact region, 5 n ⁺ type drain region, 10 first conductive part, 11 buried electrode part, 11a first insulation part, 11b second insulating part, 12 first wiring part, 13 wiring resistance, 13a, 13b insulating layer, 14 first pad, 20 second conductive part, 21 gate electrode part, 21a gate insulating part, 22 second wiring part , 24 second pad, 31 drain electrode, 32 source electrode, 32a plug, 33 gate pad, 33a wiring section, 40 resistor, 50 Zener diode, 50a, 50b insulating layer, 51 n-type semiconductor layer, 52 p-type semiconductor layer , 60 coil, 61 insulating layer, 71 first metal member, 72 second metal member, 73 third metal member, 74 metal member, 75 insulating member, 90 LCR meter, 100, 100a, 100b, 110 to 150 semiconductor device, L power loss, P mirror period, S terminal, SL semiconductor layer, T time, Vg voltage

Claims (9)

a first electrode;
A semiconductor layer provided on the first electrode,
a first semiconductor region of a first conductivity type electrically connected to the first electrode;
a second semiconductor region of a second conductivity type provided on the first semiconductor region; and
a third semiconductor region of a first conductivity type provided on the second semiconductor region;
The semiconductor layer comprising;
a first conductive portion including a buried electrode portion provided in the first semiconductor region via a first insulating portion;
a second conductive portion including a gate electrode portion provided on the buried electrode portion via a second insulating portion and facing the second semiconductor region via the gate insulating portion;
a second electrode provided on the semiconductor layer and electrically connected to the second semiconductor region and the third semiconductor region;
Equipped with
The first conductive part is electrically connected to the second conductive part,
The semiconductor device, wherein the electrical resistance of the first conductive part is greater than the electrical resistance of the second conductive part. further comprising a third electrode provided on the semiconductor layer and electrically connected to the first conductive part and the second conductive part,
The first conductive part further includes a first wiring part that is electrically connected between the buried electrode part and the third electrode and provided on the semiconductor layer,
The semiconductor device according to claim 1, wherein the second conductive part further includes a second wiring part electrically connected between the gate electrode part and the third electrode and provided on the semiconductor layer. . Further equipped with a resistor,
The third electrode is electrically connected between the resistor and the first conductive part and between the resistor and the second conductive part,
3. The semiconductor device according to claim 2, wherein the electrical resistance of the first conductive portion is greater than the electrical resistance of the resistor. The first conductive part further includes a wiring resistance electrically connected between the first wiring part and the third electrode,
4. The semiconductor device according to claim 2, wherein the electrical resistivity of the wiring resistance is higher than the electrical resistivity of the first wiring part. 5. The semiconductor device according to claim 1, further comprising a bidirectional Zener diode electrically connected between the first conductive part and the second conductive part. The semiconductor device according to claim 1, wherein the first conductive section further includes a coil. a first metal member provided under the first electrode and electrically connected to the first electrode;
a second metal member separated from the first metal member and electrically connected to the second electrode;
a third metal member separated from the first metal member and the second metal member, electrically connected to the second conductive part, and electrically connected to the first conductive part via a coil;
The semiconductor device according to claim 1, further comprising: a first electrode;
A semiconductor layer provided on the first electrode,
a first semiconductor region of a first conductivity type electrically connected to the first electrode;
a second semiconductor region of a second conductivity type provided on the first semiconductor region; and
a third semiconductor region of a first conductivity type provided on the second semiconductor region;
The semiconductor layer comprising;
a first conductive part including a buried electrode part provided in the first semiconductor region via a first insulating part, and a coil connected in series with the buried electrode part;
A gate electrode portion is provided on the buried electrode portion via a second insulating portion and is opposed to the second semiconductor region via the gate insulating portion, and is electrically connected to the first conductive portion. a second conductive part;
a second electrode provided on the semiconductor layer and electrically connected to the second semiconductor region and the third semiconductor region;
A semiconductor device equipped with a first metal member;
a first electrode provided on the first metal member and electrically connected to the first metal member;
A semiconductor layer provided on the first electrode,
a first semiconductor region of a first conductivity type electrically connected to the first electrode;
a second semiconductor region of a second conductivity type provided on the first semiconductor region; and
a third semiconductor region of a first conductivity type provided on the second semiconductor region;
The semiconductor layer comprising;
a first conductive portion including a buried electrode portion provided in the first semiconductor region via a first insulating portion;
a second conductive portion including a gate electrode portion provided on the buried electrode portion via a second insulating portion and facing the second semiconductor region via the gate insulating portion;
a second electrode provided on the semiconductor layer and electrically connected to the second semiconductor region and the third semiconductor region;
a second metal member separated from the first metal member and electrically connected to the second electrode;
a third metal member separated from the first metal member and the second metal member, electrically connected to the second conductive part, and electrically connected to the first conductive part via a coil;
A semiconductor device equipped with

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