JP7367662B2 - Power converter and power converter control method - Google Patents

Description

The present invention relates to a method for controlling a power conversion device.

In a power conversion device that generates pulse voltage by PWM controlling a DC/three-phase AC converter, in order to smooth the pulse voltage, the output is equipped with an ACL (AC reactor) or an LC consisting of a three-phase transformer and a filter capacitor. A filter is used. Furthermore, in a device connected to the grid, an LCL filter composed of an LC filter and an ACL or a three-phase transformer is used.

A power conversion device in which an LC filter or an LCL filter is installed between the output pulse voltage source of the DC/three-phase AC converter and the AC voltage source or load of the system is capable of controlling the output current of the DC/three-phase AC converter. includes harmonic currents caused by PWM. This harmonic component current flows into the filter capacitor, and the harmonic components of the output current flowing to the system or load are reduced.

Patent Document 1 and Patent Document 2 (see FIG. 12) disclose that in a configuration in which an LC filter is installed in the output pulse voltage source of a DC/three-phase AC converter, when controlling the voltage of the converter output, the control system A control system that feeds back capacitor current is disclosed. By using control that feeds back the capacitor current, it is possible to reduce output voltage distortion caused by the resonance of the resonance frequency of the LC filter and the harmonic components contained in the pulse voltage.

Two-level converters, three-level converters, and the like are generally used as DC/three-phase AC converters. Representative circuit configurations of a three-level converter are shown in FIGS. 13 and 14 (Patent Documents 3 and 4).

A three-level converter is a device that is equipped with a voltage source of a voltage E divided into two, and outputs three levels of AC voltage: +E, 0, and -E. In addition, compared to a 2-level converter, a 3-level converter theoretically reduces the frequency (carrier frequency) of the triangular wave carrier signal (reference numeral 34 in FIG. 12) for performing PWM modulation, while reducing output voltage distortion. Can be reduced.

However, near the zero cross of the voltage command value given to the three-level converter, the width of the pulse voltage modulated by PWM becomes narrow, and the pulse voltage may not be output due to dead time.

JP2012-39827A Patent No. 3298441 JP2019-146380A Japanese Patent Application Publication No. 2018-148709

Patent Document 1 and Patent Document 2 disclose that by using control that feeds back the capacitor current, it is possible to reduce output voltage distortion caused by the resonance of the resonance frequency of the LC filter and the harmonic components contained in the pulse voltage. . However, what Patent Document 2 shows is a two-level converter (see FIGS. 1 and 7 of Patent Document 2). There is no mention of application to a three-level converter.

When this is applied to a 3-level converter that operates at a low carrier frequency, the width of the pulse voltage modulated by PWM becomes narrower near the zero cross of the voltage command value given to the 3-level converter, and the pulse voltage is output due to the dead time. It may not be done.

As a result, in the three-level converter, a region may occur near the zero crossing of the voltage command value where output voltage distortion due to resonance between the LC filter and the harmonic components of the pulse voltage cannot be reduced. This was confirmed by a simulation shown in FIG. 2, which will be described later.

Therefore, in this region, it is necessary to take measures to suppress feedback control of the capacitor current (not performing it, lowering the gain, making it variable, etc.).

Based on the above, in a power conversion device, it is possible to reduce distortion in the output voltage by suppressing the gain of the control that feeds back the capacitor current near the zero cross of the voltage command value given to the three-level converter. It becomes a challenge.

The present invention was devised in view of the conventional problems, and one aspect thereof includes: a three-level converter; an LC filter or an LCL filter connected between the three-level converter and a load; A power conversion device comprising: a voltage control unit that outputs a pre-damping compensation voltage command value based on a deviation between a capacitor voltage command value and a capacitor voltage detection value; and a voltage control unit that calculates a damping compensation term based on a capacitor current detection value. a damping compensation unit that multiplies the damping compensation term by a gain and outputs the result as a damping compensation value, and sets the gain to 0 at a zero crossing point of the phase voltage command value; and the voltage command value before damping compensation and the damping compensation value. an adder that adds up the inverter output voltage command value and outputs the inverter output voltage command value; and a PWM control unit that generates a gate signal for the three-level converter based on a PWM comparison between the value and a triangular wave carrier signal.

In one aspect, the damping compensation unit sets the gain to 1 when the minimum value of the absolute values of the phase voltage command values is equal to or higher than the first setting threshold, and sets the gain to 1 so that the minimum value is the first setting threshold. If the gain is less than 0, the gain is set to 0.

In another aspect, the damping compensator sets the gain to 1 when the minimum value of the absolute values of the phase voltage command values is equal to or higher than the first setting threshold, and sets the gain to 1 so that the minimum value is the first setting threshold. If the value is less than 1, the gain is set to a value obtained by dividing the minimum value by the first set threshold.

In another aspect, the damping compensator sets the gain to 1 when the minimum value of the absolute values of the phase voltage command values is equal to or higher than the first setting threshold, and sets the gain to 1 so that the minimum value is the first setting threshold. If it is less than the second setting threshold and greater than or equal to the second setting threshold, the gain is calculated by dividing the value obtained by subtracting the second setting threshold from the minimum value by the value obtained by subtracting the second setting threshold from the first setting threshold. , the gain is set to 0 when the minimum value is less than the second set threshold.

According to the present invention, in a power conversion device, it is possible to reduce distortion of the output voltage by suppressing the gain of the control that feeds back the capacitor current near the zero cross of the voltage command value given to the three-level converter. Become.

FIG. 2 is a block diagram showing the main circuit configuration and control unit of the power conversion device. FIG. 7 is a diagram showing a simulation waveform after damping compensation. FIG. 7 is a diagram showing a simulation waveform without damping compensation. The figure which shows the magnitude|size of the minimum value of the phase voltage command value of three phases. FIG. 3 is a block diagram showing a damping compensator in the first embodiment. FIG. 3 is a diagram showing a gain waveform in the first embodiment. FIG. 3 is a block diagram showing a damping compensator in Embodiment 2. FIG. 7 is a diagram showing a gain waveform in Embodiment 2. FIG. 7 is a block diagram showing a damping compensator in Embodiment 3. FIG. 7 is a diagram showing a gain waveform in Embodiment 3. FIG. FIG. 7 is a diagram showing simulation results in the case where the gain is always set to 1 and in the third embodiment. The figure which shows the main circuit structure of patent document 2. The figure which shows the main circuit structure of patent document 4. The figure which shows the main circuit structure of patent document 4.

Hereinafter, the power conversion device according to the present invention will be described in detail based on FIGS. 1 to 11.

Figure 1(a) shows the main circuit configuration of a power converter in which an LC filter is installed at the output of a DC/three-phase AC converter, and Figure 1(b) is a block diagram of the control section of the voltage control system with added damping compensation. shows. First, the main circuit configuration of FIG. 1(a) will be explained.

The inverter INV converts DC power into AC power and outputs it. The inverter output is output to a load via an LC filter having a reactor L and a capacitor C.

The inverter INV is a three-level converter. Typical circuit configurations of the three-level converter are shown in FIGS. 13 and 14, but other circuit configurations may be used. Further, although an LC filter is shown in FIG. 1(a), an LCL filter may be used.

Here, Ic is a capacitor current detection value, Vc is a capacitor voltage detection value, IL is a load current, and DC is a direct current power supply.

Next, the control section shown in FIG. 1(b) will be explained. The three-phase two-phase converter 1 performs three-phase two-phase conversion on a three-phase (UVW phase) capacitor voltage detection value Vc, and converts it into d-axis and q-axis capacitor voltage detection values. The three-phase two-phase converter 2 performs three-phase two-phase conversion on the three-phase (UVW phase) capacitor current detection value Ic, and converts it into d-axis and q-axis capacitor current detection values.

Vref in FIG. 1(a) is the capacitor voltage command value at point A in FIG. 1(a). Here, the capacitor voltage command value Vref is assumed to be a value on the dq coordinates. The subtracter 3 subtracts the d-axis and q-axis capacitor voltage detection values Vc from the capacitor voltage command value Vref, and outputs the deviation between the capacitor voltage command value Vref and the capacitor voltage detection value Vc.

AVR (voltage control unit) 4 performs PI control or the like based on the deviation between capacitor voltage command value Vref and capacitor voltage detection value Vc, and outputs a pre-damping compensation voltage command value.

The damping compensator 5 outputs a damping compensation value based on the d-axis and q-axis capacitor current detection values Ic. The adder 6 adds the damping compensation value to the pre-damping compensation voltage command value to generate an inverter output voltage command value Vinv* (voltage command at point B in FIG. 1(b)).

The two-phase three-phase converter 7 performs two-phase three-phase conversion on the inverter output voltage command value Vinv*, and outputs three-phase phase voltage command values Vu, Vv, and Vw. The PWM control unit 8 generates a gate signal (on/off command signal) for each switching element in the three-level converter based on a comparison between the three-phase phase voltage command values Vu, Vv, and Vw and the triangular wave carrier signal.

Patent Document 2 (FIG. 2) shown in FIG. 12 discloses a control system that feeds back an LC filter capacitor current. Feedback control is stabilized by adding a capacitor current feedback system.

FIG. 2 shows a simulation waveform in which damping compensation was performed by feeding back only the harmonic components of the filter capacitor current, and FIG. 3 shows a simulation waveform in which damping compensation was not performed. (a) in FIGS. 2 and 3 is the line voltage waveform at point A in FIG. 1, (b) in FIGS. 2 and 3 is the line voltage waveform at point B in FIG. ) is the waveform of the load current IL in FIG.

The substantially sinusoidal waveforms shown in FIGS. 2 and 3(d) are the input signals (three-phase phase voltage command values Vu, Vv, Vw) to the PWM control unit 8 in FIG. The triangular wave shown in FIGS. 2 and 3 (d) is a triangular wave carrier signal used to generate a gate signal in the PWM control section 8 of FIG. 2 and 3 (e) are PWM voltage command waveforms, based on which a gate signal GATE is output from the PWM control section 8. Moreover, these simulations are performed using a three-level converter as a model.

As shown within the dotted line in FIG. 2, pulsation of the carrier frequency component occurs in the voltage waveform around the zero crossing of the voltage command value. This is caused by the thin pulse voltage near the zero cross mentioned above disappearing due to dead time, resulting in a decline in control performance.

On the other hand, in the voltage waveform around the zero cross in which damping compensation is not performed as shown in FIG. 3, the pulsation as shown in FIG. 2 is reduced. Note that the voltage waveforms in FIGS. 2 and 3 indicate line voltages. Therefore, the dotted line portion shifted by 30 degrees from the zero cross of the line voltage corresponds to the vicinity of the zero cross of the phase voltage.

The width of the pulse voltage becomes narrow near the zero crossing of the voltage command value. When performing damping compensation for this narrow pulse voltage, there is likely to be a difference between the theoretical compensation value and the actually compensable value, and due to this difference, the compensation operation may have the opposite effect. It is also possible. As proof of this, the pulsation of the voltage waveform around zero cross is reduced in FIG. 3 without damping compensation than in FIG. 2 with damping compensation.

By the way, the minimum value of the three-phase phase voltage command values Vu, Vv, and Vw shown in FIG. 4 (the phase voltage command value of the phase with the lowest absolute value among the three-phase phase voltage command values Vu, Vv, and Vw) is Since the magnitude (solid line) corresponds to the area around the zero cross, the minimum absolute value of the three-phase phase voltage command values Vu, Vv, and Vw is used as the zero cross detector, and the variable gain to the damping compensation term is A control method for generating and multiplying will be explained in the following embodiments 1 to 3. In the first to third embodiments, the gain Gain multiplied by the damping compensation term is set to 0 at the zero-crossing point of the phase voltage command values Vu, Vv, and Vw.

[Embodiment 1]
FIG. 5 is a block diagram of the damping compensator 5 of the first embodiment. The ABS (absolute value converter) 9 converts the three-phase voltage command values (phase voltage command values Vu, Vv, Vw input to the "PWM control unit 8" in FIG. 1(b)) of the previous control cycle into absolute values. Convert. Note that in the case where the phase voltage command value is subjected to three-phase modulation, the phase voltage command value may be either before or after the three-phase modulation. The minimum value selection unit 10 selects and outputs the lowest value among the three absolute values.

The comparator 11 compares the first set threshold LV_H and the output of the minimum value selection section 10, as shown in FIG. As shown in FIG. 6, the switch 12 outputs 1 as the gain Gain when the output of the minimum value selection unit 10 is equal to or higher than the first set threshold LV_H, and outputs 0 as the gain Gain when the output of the minimum value selection unit 10 is less than the first set threshold LV_H. Output.

The HPF (high pass filter) 13 extracts harmonics of the capacitor current detection value Ic (output of the three-phase two-phase converter 2). Multiplier 14 multiplies the output of HPF 13 by coefficient K. The output of the multiplier 14 becomes the damping compensation term. The multiplier 15 multiplies the output (damping compensation term) of the multiplier 14 by a gain Gain. The output of the multiplier 15 becomes the output (damping compensation value) of the damping compensator 5.

[Embodiment 2]
FIG. 7 is a block diagram of the damping compensator 5 of the second embodiment. Here, the same parts as in Embodiment 1 are given the same reference numerals and explanations are omitted, and only the differences from Embodiment 1 will be explained.

The divider 16 divides the output of the minimum value selection section 10 by the first set threshold value LV_H. The switch 17 inputs 1 and the output of the divider 16, and as shown in FIG. 8, if the output of the minimum value selection unit 10 is equal to or higher than the first set threshold LV_H, it outputs 1 as the gain Gain, and selects the minimum value. If the output of the unit 10 is less than the first set threshold LV_H, the output of the divider 16 (the value obtained by dividing the output of the minimum value selection unit 10 by the first set threshold LV_H) is output as the gain Gain. When the output of the minimum value selection unit 10 is less than the first set threshold LV_H, the gain Gain drops from 1 to 0.

[Embodiment 3]
FIG. 9 is a block diagram of the damping compensator 5 of the third embodiment. Here, the same parts as in Embodiments 1 and 2 are given the same reference numerals and explanations are omitted, and only the differences from Embodiments 1 and 2 will be explained.

The comparator 11 compares the output of the minimum value selection section 10 and the first set threshold LV_H, and outputs a switching signal to the switch 22. The comparator 18 compares the output of the minimum value selection section 10 and the second set threshold LV_L, and outputs a switching signal to the switch 23.

The subtracter 19 subtracts the second set threshold LV_L from the output of the minimum value selection section 10. The subtracter 20 subtracts the second set threshold LV_L from the first set threshold LV_H. Divider 21 divides the output of subtracter 19 by the output of subtracter 20. That is, as shown in FIG. 10, by subtracting the second setting threshold LV_L from the output of the minimum value selection section 10 and dividing it by the difference between the upper and lower limits of the setting threshold, the output of the minimum value selection section 10 becomes the second setting threshold LV_L. As described above, the gain Gain drops from 1 to 0 when it is less than the first set threshold LV_H.

The switch 22 outputs 1 when the output of the minimum value selection unit 10 is equal to or higher than the first set threshold LV_H, and outputs the output of the divider 21 when the output of the minimum value selection unit 10 is less than the first set threshold LV_H. do.

The switch 23 outputs the output of the switch 22 when the output of the minimum value selection section 10 is equal to or higher than the second set threshold LV_L, and outputs 0 when the output of the minimum value selection section 10 is less than the second set threshold LV_L. .

That is, the first and second set thresholds LV_H, LV_L and the output of the minimum value selection unit 10 are compared, and if the output of the minimum value selection unit 10 is greater than or equal to the first set threshold LV_H, the gain is set to 1 and the minimum value is selected. If the output of the unit 10 is less than the second set threshold LV_L, the gain Gain=0, and if the output of the minimum value selector 10 is greater than or equal to the second set threshold LV_L and less than the first set threshold LV_H, the calculated drooping gain Gain is set. Multiply by damping compensation term.

Figure 11 shows the simulation results of the output voltage distortion rate and waveform (line voltage) in damping compensation when (a) the gain is always set to 1 and (b) when the gain is corrected as shown in Embodiment 3. show. (Simulation conditions: output voltage = 270V, output power = 6kW, resistive load, LV_H = 69V, LV_L = 47V). In FIG. 11(b) using Embodiment 3, it can be seen that the output voltage distortion is reduced.

As shown above, according to Embodiments 1 to 3, in a power conversion device that controls the voltage output from a three-level converter, when using control that feeds back a capacitor current to the control system, the voltage applied to the three-level converter is Zero-crossing of the phase voltage command value is detected by simple calculations, and the gain of the control that feeds back the capacitor current is lowered only when control performance deteriorates due to pulse voltage loss at zero-crossing (around zero-crossing), thereby eliminating unnecessary Voltage pulsation can be reduced and voltage distortion can be suppressed.

Although only the specific examples described in the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and modifications can be made within the scope of the technical idea of the present invention. Naturally, such variations and modifications fall within the scope of the claims.

1, 2... Three-phase two-phase converter 3, 19, 20... Subtractor 4... AVR (voltage control section)
5... Damping compensation unit 6... Adder 7... Two-phase three-phase converter 8... PWM control unit 9... ABS (absolute value conversion unit)
10... Minimum value selection section 11, 18... Comparator 12, 17, 22, 23... Switch 13... HPF (high pass filter)
14, 15... Multiplier 16, 21... Divider INV... Inverter L... Reactor C... Capacitor

Claims (5)

A power conversion device comprising a three-level converter, and an LC filter or an LCL filter connected between the three-level converter and a load,
a voltage control unit that outputs a pre-damping compensation voltage command value based on a deviation between the capacitor voltage command value and the capacitor voltage detection value;
a damping compensation unit that calculates a damping compensation term based on a capacitor current detection value, multiplies the damping compensation term by a gain, outputs the result as a damping compensation value, and sets the gain to 0 at a zero-crossing point of the phase voltage command value;
an adder that adds the pre-damping compensation voltage command value and the damping compensation value to output an inverter output voltage command value;
a two-phase three-phase conversion unit that converts the inverter output voltage command value from two to three phases and outputs the phase voltage command value;
a PWM control unit that generates a gate signal for the three-level converter based on a PWM comparison between the phase voltage command value and the triangular wave carrier signal;
A power conversion device characterized by comprising: The damping compensation section is
If the minimum value among the absolute values of the phase voltage command value is equal to or higher than a first setting threshold, the gain is set to 1,
The power conversion device according to claim 1, wherein the gain is set to 0 when the minimum value is less than the first set threshold. The damping compensation section is
If the minimum value among the absolute values of the phase voltage command value is equal to or higher than a first setting threshold, the gain is set to 1,
The power conversion device according to claim 1, wherein when the minimum value is less than the first set threshold, the gain is a value obtained by dividing the minimum value by the first set threshold. The damping compensation section is
If the minimum value among the absolute values of the phase voltage command value is equal to or higher than a first setting threshold, the gain is set to 1,
If the minimum value is less than the first setting threshold and greater than or equal to the second setting threshold, the value obtained by subtracting the second setting threshold from the minimum value is the value obtained by subtracting the second setting threshold from the first setting threshold. The value divided by is the gain,
The power conversion device according to claim 1, wherein the gain is set to 0 when the minimum value is less than the second set threshold. A method for controlling a power conversion device comprising a three-level converter, an LC filter or an LCL filter connected between the three-level converter and a load,
The voltage control unit outputs a voltage command value before damping compensation based on the deviation between the capacitor voltage command value and the capacitor voltage detection value,
a damping compensation unit calculates a damping compensation term based on the capacitor current detection value, multiplies the damping compensation term by a gain and outputs the result as a damping compensation value, and sets the gain to 0 at a zero crossing point of the phase voltage command value,
an adder adds the pre-damping compensation voltage command value and the damping compensation value to output an inverter output voltage command value;
a two-phase three-phase converter converts the inverter output voltage command value into two-phase three-phase and outputs the phase voltage command value,
A method for controlling a power conversion device, wherein a PWM control section generates a gate signal for the three-level converter based on a PWM comparison between the phase voltage command value and a triangular wave carrier signal.

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