JP7369699B2 - Address translation in data processing equipment - Google Patents

Description

The present technique relates to the field of data processing.

Data processing systems may employ two addressing systems: a system of virtual addresses and a system of physical addresses. Virtual addresses are those used by software executed by a data processing device, while physical addresses are used by memory storage hardware such as external RAM. Address translation capabilities are then provided within this hardware to be able to translate between the two memory addressing systems and, in particular, without having to use the physical addressing system used by the hardware. may be provided by the data processing device to enable executing software to access the memory storage location of the data processing device. In other words, virtual to physical address translation can be transparent to software running on the CPU since memory access requests (e.g. loads and stores) are issued using virtual addresses. Yes, the data (when appropriate for memory access) undergoes address translation and is returned from the memory system without the software having to know that the data was accessed at a physical address that is different from the virtual address.

"Some Efficient Architecture Simulation Techniques", Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63

At least some examples include an address translation circuit for translating a virtual address including a virtual tag portion and a virtual address portion to a physical address including a physical tag portion and a physical address portion, the An apparatus is provided, comprising an address-to-tag translation circuit for performing a translation into a tag part, and for selecting a translation to be performed by the address-to-tag translation circuit in dependence on a virtual address.

At least some examples include selecting a translation to a physical address that includes a physical tag portion and a physical address portion to be performed on a virtual address that includes a virtual tag portion and a virtual address portion; A method is provided that includes selecting, depending on an address, and performing a translation to convert a virtual tag part to a physical tag part.

At least some examples are a computer program for controlling a host data processing device to provide an instruction execution environment for execution of instructions of target program code, the computer program comprising: a virtual tag portion and a virtual address; address translation program logic for converting a virtual address containing a part into a physical address including a physical tag part and a physical address part, the address translation program logic converting a virtual tag part into a physical tag part; A computer program product is provided that includes address tag translation program logic for performing an address tag translation program, the address translation program logic selecting a translation to be performed by the address tag translation circuit in dependence on a virtual address.

A storage medium can store the computer program described above. A storage medium can be a non-transitory storage medium.

The present technique will be further described, by way of example only, with reference to embodiments as illustrated in the accompanying drawings, which shall be read in conjunction with the following description.

1 is a diagram schematically showing an example of a data processing device; FIG. FIG. 3 illustrates an example tag-guarded memory access operation that includes checking whether an address tag matches a guard tag. 2 is a flow diagram illustrating a method for performing tag-guarded memory access operations. 1 schematically depicts a virtual address space in which one part is reserved for use by the kernel and another part for user space; FIG. 1 is a diagram schematically showing an example of a data processing device including an address translation circuit and an address/tag translation circuit; FIG. Figure 3 schematically depicts several components of a data processing apparatus in one example illustrating further details of the conversion of a virtual tag part to a physical tag part. 7 schematically depicts some components of the data processing apparatus of FIG. 6 in one example; FIG. 3 is a flowchart illustrating a method of converting a virtual tag part to a physical tag part. FIG. 2 is a diagram illustrating an example of a simulator that supports address translation logic.

In one example, an address translation circuit for translating a virtual address including a virtual tag portion and a virtual address portion to a physical address including a physical tag portion and a physical address portion, the physical tag portion of the virtual tag portion; There is an apparatus comprising an address-to-tag translation circuit for performing a translation to a virtual address and selecting a translation to be performed by the address-to-tag translation circuit in dependence on a virtual address.

A virtual address that is to be translated into a physical address may be defined in a virtual address space that has a bit width wider than strictly necessary to define a unique virtual address for use by a processor core. It is possible. For example, in modern architectures configured to use 64-bit address spaces for instruction sets, processor cores may be limited to using, for example, only the lower 48 bits of the 64-bit address space. The upper bits are reserved in some way. This approach can be advantageous because, for example, user space and kernel space can each have uniquely defined regions of non-overlapping virtual addresses. For example, in a system where user space and kernel space each contain uniquely defined 39-bit address spaces (providing 2 ³⁹ = 512 GB of virtual addresses each), one approach is to then, e.g. Labeling these sets of user virtual addresses and kernel virtual addresses with leading sets of bits such that addresses contain 25 leading zeros and all kernel virtual addresses contain 25 leading ones. It is. For example, they can be set as the sign extension of the most significant "real" address bits (thereby setting the reserved part to all zeros or all ones). Inspection of the first bit portion of the virtual address used by the user or the kernel can verify whether authorized memory accesses are being made and to trap illegal accesses.

Nevertheless, if the result is that (at least a large portion of) the leading bit portion of the virtual address is substantially unused, this provides an opportunity for this bit space to be used for another purpose. However, this also means that the encoding used in the upper part of the virtual address may be influenced by the manner in which the virtual address space is used. In the above example of a virtual address space that includes a portion reserved for user space and a portion reserved for kernel space, the leading portion of the bits of the virtual address (set to all zeros or all ones) is , indicates whether a given address is reserved for user space or kernel space, then the default bit encoding for this upper part of the virtual address is therefore user space and kernel space. Different for kernel space.

Additionally, if this upper portion of the virtual address space is largely unused, it may be advantageous to use this bit space to allow software to signal additional information to the memory system. There is. In this context, the provided apparatus distinguishes between a virtual tag part and a virtual address part of a received virtual address when performing the translation, and translates the virtual address into a physical address comprising a physical tag part and a physical address part. An address conversion circuit is provided for converting a virtual address to a physical address. In other words, the virtual address part is translated into a physical address part to indicate the particular memory address that the software requests access to, but a further part of the virtual address, namely the virtual tag part, is separated into the physical tag part. Once translated, this physical tag portion can then convey further information to the memory addressing system. Furthermore, when performing this translation from a virtual tag part to a physical tag part, the apparatus of the present technique uses the virtual address Take into account the content of In other words, different translations may be used depending on some characteristics of the virtual address.

This reliance on virtual addresses for the translations to be performed by the address-tag translation circuitry can be configured in a variety of ways, but in some instances, the address-tag translation The translation performed by the circuit depends on the most significant bits of the virtual address part. The meaning of this most significant bit of the virtual address part depends on the particular implementation and, indeed, on the choice as to where the boundary between the virtual tag part and the virtual address part in the virtual address is. , it will be recognized that this is subject to change.

The manner in which the selected translation depends on the most significant bits of the virtual address portion may take various forms, but in some instances, when the most significant bits of the virtual address portion include a first value, The selected translation performed by the address tag translation circuit produces a physical tag part that matches the virtual tag part, and when the most significant bit contains the second value, the selected translation performed by the address tag translation circuit produces a physical tag part that matches the virtual tag part; The translation modifies the virtual tag part to generate a physical tag part. Therefore, when the most significant bit contains the first value, the address-to-tag translation circuit does not modify the virtual tag part to generate a physical tag part. However, when the most significant bit contains a second value, modification of the virtual tag part is performed to generate a physical tag part.

As mentioned above, the meaning of the most significant bits of the virtual address portion can change. However, in some instances, the apparatus is designed to allocate virtual addresses for exclusive use by one of a kernel-specific process and a user-specific process, and the value of the most significant bit of the virtual address portion is It may be an indication of whether the virtual address was allocated to kernel-specific processing or to user-specific processing. This could be, for example, as part of a system as described above, where two separate and non-overlapping parts of the full virtual address space are allocated to kernel processing and user-specific processing, respectively; For example, the device populates the upper part of the virtual address with consecutive sets of ones for kernel-space addresses, and populates this same part with consecutive sets of zeros for user-space addresses. Designed to be. In the context of the present technique, this also applies a transformation to the virtual tag part when a virtual address is identified as being allocated within kernel space, while the virtual address allocated as part of user space When it is identified that a virtual tag part forms a part of a virtual tag part, this means that the address translation circuit can be configured so as not to apply translation to the virtual tag part. The virtual tag part does not form part of the real address itself, but rather (in some cases related to a particular memory address, or in some cases a more general command or command to the memory system). If it is possible for other information (as signals) to be used to communicate to the memory system, this approach will result in the determination of whether the address belongs to a kernel-specific or a user-specific process. , so that the generation of the physical tag part can be taken into account.

Although this dependency may be configured differently, in some instances the selected translation performed by the address-to-tag translation circuitry inverts at least a portion of the virtual tag portion to generate the physical tag portion. Including. Such a configuration may be configured such that, for example, the addressing within the device is such that the virtual tag portion is populated by default with consecutive sets of ones for kernel-specific addresses and with consecutive sets of zeros for user-specific addresses. can be used when configured. Therefore, when at least a portion of the virtual tag portion is used to communicate information to the memory address system, inverting this at least portion of the virtual tag portion in this manner ensures that the virtual address is one for kernel-specific processing. The encoding of the information presented to the memory address system can be the same whether it is for user-specific processing or for user-specific processing.

In other examples, the selected translation performed by the address-to-tag translation circuit may include incrementing at least a portion of the virtual tag portion to generate a physical tag portion. This means that addresses in the virtual address space may vary, for example, some addresses may be allocated at the lowest possible value in the address space, while others may be allocated to other processes at the top of the address space. It may be applicable to configurations allocated to processing. For example, in the user space/kernel space delimitation described above for virtual address space, an address containing a complete set of zeros (e.g. 64 bits) can be allocated to user space, while a complete set of ones Addresses containing sets can be allocated in kernel space. If the largest possible address (all 1s) is incremented, this value will wrap around to produce a continuous sequence of 64 zeros (the address that can be modulo 2 ⁶⁴ is be). Note, however, that this conversion only applies to the virtual tag portion, so in this example, a consecutive set of ones in the virtual tag portion will be converted to a consecutive set of zeros in the physical tag portion. A consecutive sequence of 1's in the virtual address part remains a consecutive sequence of 1's in the physical address part.

In some instances, the apparatus further comprises a memory system for receiving the physical address and accessing the storage location identified by the physical address portion, the memory system responsive to receiving the physical address; When a predetermined portion of the physical tag section includes a predetermined value, a predetermined memory operation is performed. Therefore, the physical tag portion, and by extension the virtual tag portion, can be used by the memory system to perform certain memory operations. This provides the processor core with a useful control mechanism over the memory system.

Although the predetermined memory operation can take a wide variety of forms depending on system requirements and the particular implementation, in some instances the predetermined memory operation is associated with a storage location of a physical tag portion. The memory system indicates a fault condition in response to the physical tag portion and the guard tag value not meeting the match condition. Thus, in such devices, a guard tag is provided that is stored in the memory system in association with the memory location specified by the physical address portion, and the physical tag portion and the guard tag value satisfy a match condition. The requirements allow for control to be exerted over access to storage locations. A fault condition indicating that a match condition was not met can be used in a variety of ways. For example, a fault condition may be used to prevent access to this storage location, but this is not the only technique in which a fault condition is used; in other instances, a fault condition may be , it may simply be signaled to another part of the device (eg, back to the processor core) to indicate that the match condition was not met, but access can still proceed. In this way, the conclusion of the comparison of the physical tag part and the guard tag value is used to control whether the memory access can continue or whether subsequent operations can continue. or simply be reported while memory accesses continue as usual.

In such configurations where the memory system is configured to perform such guard tag checking, at least one of the physical tag portions is configured to control the particular manner in which the guard tag comparison is to be performed. can be used. In some instances, when the predetermined portion of the physical tag portion includes the predetermined value, the match condition is a match-all condition such that any guard tag value satisfies the match condition. Therefore, this effectively prevents the fault condition from being signaled because any guard tag value will satisfy the match condition and therefore no fault condition will be generated.

In some instances, when the predetermined portion of the physical tag portion does not contain the predetermined value, the match condition may be such that the predetermined portion of the physical tag portion and the guard tag value must be the same in order to satisfy the match condition. This is a match-one condition. In this way, conversely, a given portion of the physical tag portion may be explicitly required to satisfy the match condition if this portion does not contain the above-mentioned “match-all” value. The predetermined portion of the physical tag portion can therefore be used to specify the particular value that the guard tag value must contain in order to satisfy the match condition. For example, this can be used by the system to categorize memory addresses, e.g. depending on the particular process to which they are allocated, so that certain memory Only the process to which the address was allocated can access this memory address without triggering a fault condition.

Although the predetermined portion of the physical tag portion may be defined differently, in some instances the predetermined portion of the physical tag portion is a predetermined set of bits of the physical tag portion. This predetermined set of bits may be variously defined, but 16 different permutations may be defined, for example, all but one is defined as the "match-all" value mentioned above, and the rest are Then, for example (to take just one illustrative example), 15 different categorizations of memory addresses, when used individually as "match-one" values that can be defined within the system. Can be a set of bits. In general, any number of bits of the physical tag portion can be used in this way, and correspondingly larger or smaller sets of categorizations can be defined.

If it is understood that this above-mentioned "match-all" value is different from the effect on the memory system from the set of "match-one" values, then the address tag translation circuit will be can be designed to force the generation of a predetermined portion of the physical tag part with a predetermined value at . For example, in some implementations, the address-to-tag translation circuitry generates a physical tag portion in response to a predetermined bit of the virtual tag portion that includes a predetermined value, and the predetermined portion of the physical tag portion is different from other portions of the virtual tag portion. Contains a predetermined value that is unrelated to the value of the predetermined bit. Thus, certain bits of the virtual tag portion thus act as control bits to force a "match-all" comparison to be performed by the memory system.

Although the predetermined portion of the physical tag portion that triggers a match-all comparison to be performed may be defined differently, in some embodiments the predetermined portion of the physical tag portion is a predetermined bit of the physical tag portion. The signal to the memory system as to whether or not to perform a match-all comparison is thus transmitted (potentially leaving other bits of the physical tag part to communicate other information to the memory system). ) can be communicated by only a single bit of the physical tag part.

Although a guard tag comparison between a physical tag portion and a guard tag value may be configured in a variety of ways, in some instances, a guard tag comparison may be configured such that all of the physical tag portions are associated with a storage location. It is smaller than the guard tag value.

Further, although the predetermined values of the predetermined portions of the physical tag portion may be variously defined, in some instances the virtual tag portion includes at least one bit included in the physical address, and the memory system includes at least one bit included in the physical address. control overwriting of a guard tag associated with a storage location when a write access is made to the storage location. In this way, the process of defining the bits of the virtual tag portion uses this at least one bit to communicate to the memory system about how a write access is to be made to the storage location. However, in this example, when a write access is made, overwriting of the guard tag associated with the storage location can be controlled. In principle, when a write access is made to a storage location, this should not change if the process accessing the storage location generally respects the defined guard tag distribution. Although it is not mandatory that the guard tag associated with a storage location be updated, the guard tag override control forces the guard tag value to be overwritten when a write access is made. provides an additional level of verification that processes making write accesses are correctly authorized to do so.

In some instances, selecting a translation to a physical address that includes a physical tag portion and a physical address portion to be performed on a virtual address that includes a virtual tag portion and a virtual address portion, the virtual address Depending on the method, the method includes selecting and performing a transformation to convert the virtual tag part to a physical tag part.

In some instances, the address translation program logic includes address translation program logic for translating a virtual address that includes a virtual tag portion and a virtual address portion to a physical address that includes a physical tag portion and a physical address portion; includes an address tag translation program logic for converting a virtual tag part to a physical tag part, and the address translation program logic is performed by the address tag translation circuit depending on the virtual address. There is a computer program that selects the conversion.

In some instances, there is a storage medium that stores the computer program described above, and the storage medium can be a non-transitory storage medium.

Some specific embodiments will now be described with reference to the figures.

FIG. 1 schematically shows an example of a data processing device 2. As shown in FIG. It will be appreciated that this is merely a high-level representation of a subset of the components of the device, and that the device may include many other components not shown. The device 2 includes a processing circuit 4 that performs data processing in response to instructions decoded by an instruction decoder 6. The instruction decoder 6 decodes the instruction fetched from the instruction cache 8 and generates a control signal 10 for controlling the processing circuit 4, thereby performing a corresponding processing operation corresponding to the instruction. Processing circuitry 4 may include one or more execution units for performing operations on values stored in registers 14 to generate resultant values that are to be written back to the registers. For example, an execution unit may include an arithmetic/logic unit (ALU) for performing arithmetic or logical operations, a floating point unit for performing operations using floating point operands, and/or multiple independent data elements. A vector processing unit may be included for performing vector operations on the included operands. The processing circuitry also includes memory access circuitry 15 (eg, including a load/store unit) for controlling the transfer of data between registers 14 and the memory system. In this example, the memory system includes an instruction cache 8, a level 1 (Ll) data cache 16, a level 2 (L2) cache 17 shared between data and instructions, and main memory 18. It will be appreciated that other cache hierarchies are possible and this is just one example. A memory management unit (MMU) 20 is provided to perform address translation functions to support memory accesses triggered by the load/store unit 15. The MMU includes a translation lookaside buffer (TLB) 22 for caching a subset of entries from page tables stored in memory systems 16, 17, 18. Each page table entry can provide an address translation mapping of addresses to the corresponding page, access permissions specifying whether the page is a read-only region or both readable and writable; Alternatively, access control parameters can be specified, such as access permissions that specify which privilege levels can access the page.

FIG. 2 schematically illustrates the concept of tag-guarded memory access. The physical address space used to refer to memory locations within a memory system may be logically partitioned into a number of blocks 30, each containing a certain number of addressable locations. include. For simplicity, in the example of FIG. 2, each block 30 includes four memory locations, but other block sizes may be used as well. Each block 30 is associated with a corresponding guard tag 32. Guard tags associated with a certain number of blocks 30 may be grouped together and placed in different structurally accessible memory locations 34 within the physical address space or not structurally accessible (in the same physical address space). (not mapped to the main memory 18) may be stored in additional storage locations provided within the main memory 18. The use of separate, structurally inaccessible storage for caching guard tag values can sometimes impact normal code execution and make coherence management more complex. It may be advantageous to avoid running out of space in the data caches 16, 17. An additional tag cache 19 is provided in the microarchitecture for caching tag values from storage that is not structurally accessible for faster access than if the tags had to be accessed from main memory 18. It is possible to be provided within. The specific mapping of tag storage locations 34 to each block 30 can be controlled by the load/store unit 15 and can be hardwired or programmable. Although in FIG. 2 each tag 32 is associated with a block of physical addresses, it would also be possible to provide guard tags 32 associated with a virtual memory location within a virtual memory address space. , which may require some additional address translations for each memory access. Therefore, by associating guard tags 32 with physical storage locations, this can improve performance. Generally, this is a particular micro-architectural implementation choice as to exactly how the guard tag 32 is associated with the corresponding block 30 of the physical address space. Generally, all that is required is that the guard tags 32 associated with a given block of memory can be accessed and compared.

Thus, when a tag-guarded memory access is required, the address tag 40 (associated with the target address 42 that identifies the addressed location 44 to be accessed) A guard tag 32 associated with a block at location 30 can be compared. For example, in FIG. 2, target address 42 points to a location B1 in memory marked 44 within the address space of FIG. Accordingly, the guard tag B associated with the block at location B, including location B1, is compared to the address tag 40 associated with the target address 42. As shown at the top of FIG. 2, the address tag 4 can be determined depending on the selected bits of the target address itself. In particular, the address tag may be determined from bits within the portion of the target address that are not used to indicate the particular memory location that is to be selected as the addressing location 44. For example, in some architectures, the most significant part of the bits of the target address may always contain some fixed value (all 0s or all 1s), such as sign extension, so that the address It can be tagged with an address tag 40 by overwriting the bit with an arbitrary tag value. For example, a particular address tag value can be selected by a programmer or compiler. The address tag and guard tag 32 can be a relatively small number of bits, for example 4 bits, so they do not need to occupy much space in memory and in the target address. Providing a 4-bit tag space, or 16 possible values for a tag, can often be sufficient to detect many common types of memory access errors.

Therefore, when a tag-guarded memory access is made, a comparison is made between the address tag 40 and the guard tag 32 associated with the block 30 containing the addressed location 44 to see if they match. A judgment will be made as to whether In the illustrative configuration of FIG. 1, comparisons can be made (and in fact distributed along this path) anywhere between the load/store unit 15 and the physical memory 18. Please note that. However, in this example, the comparison will be described in terms of the comparison being performed by the load/storage unit 15 for simplicity. Load/store unit 15 generates a match indicator indicating whether address tag 40 and guard tag 32 match. For example, this match indicator may be a fault signal 60 generated if there is a mismatch between address tag 40 and guard tag 32, or an indicator in a status register indicating whether there was a match, or an error signal. may be an entry added to the error report to indicate the address where the error was detected and/or the instruction address of the instruction that triggered the error.

FIG. 3 shows a flow diagram for handling tag-guarded memory accesses. Instructions that trigger memory accesses can specify an address tag and a target address. As shown in Figure 2, in some cases the address tag can actually be derived from a subset of the bits of the target address itself, while in other instances it is stored in a separate register. It is possible to specify At step 50, an instruction is generated that triggers a tag-guarded memory access. Accordingly, in step 52, memory access circuit 15 triggers a memory access to the addressed location 44 identified by the target address. Also, in step 54, memory access circuit 15 obtains the guard tag 32 stored in the memory system associated with the block of memory locations 30 that includes the addressed location 44 identified by the target address. do. In step 56, memory access circuit 15 compares guard tag 32 obtained in step 54 with address tag 40. At step 58, an indication as to whether a match is detected between the guard tag and the address tag is generated by the memory access circuit 15 (e.g., any of the types of match/mismatch reporting indicators described above). mosquito). The exact metrics used to report any mismatches may vary depending on implementation.

FIG. 4 schematically shows a diagram of a virtual address space 60 that can be used in an illustrative embodiment. The figure shows the full range of virtual addresses that can be specified in this 64-bit address space, with the upper part 62 shown as being reserved for kernel use, while the lower part 62 64 is shown as being reserved as user space. Thus, a virtual address in kernel space includes a leading (most significant) set of consecutive ones, while a virtual address in user space includes a corresponding consecutive set of leading zeros. As further noted in the figure, references to this virtual address space are made in a modulo ²⁶⁴ manner, resulting in 0xFF. ．． ．． When you increment the reference to the virtual address above FF, the minimum defined address 0x00. ．． ．． The smallest address (0x00...00) and largest address (0xFF...FF) that can be defined in this space are "adjacent" to each other in that they wrap around to 00.

As mentioned above, the virtual addresses used in the processor core (i.e., e.g., in the processing circuit 4) are translated into physical addresses used in the memory system hardware, and FIG. 5 supports this. 1 schematically shows an example circuit provided for the purpose of the present invention; The illustrated device 70 includes a tag translation circuit 72, an address translation circuit 74, and a control circuit 76. The control circuit 76 controls the operations of the tag conversion circuit 72 and the address conversion circuit 74. If necessary, control circuit 76 also references entries in page table 78 that store defined translations between virtual and physical addresses. In this manner, the virtual address 80 received by device 70 is translated into a physical address 82, which is then further passed to memory system 84 for accessing the associated physical address as required. Virtual address 80 is handled in two parts: virtual address part 86 and virtual tag part 88. In the example shown, the virtual address is 64 bits, with bits [55:0] forming the virtual address portion and bits [63:56] forming the virtual tag portion. The largest bit of the virtual tag portion can alternatively be considered to be bits [59], for example, if bits [63:60] of a 64-bit address are simply not used in a particular implementation. Note that FIG. 5 shows that there is. In this way, a virtual address portion is received by address translation circuitry 74 within device 70 and, under the control of control circuitry 76, this virtual address is converted into a corresponding physical address in a manner that should be familiar to those skilled in the art. is converted to However, in addition, virtual tag portion 88 is received by tag translation circuitry 72 of device 70, which circuitry may convert the virtual tag portion to a physical tag portion 92. Further details of this virtual tag to physical tag conversion are explained below with reference to FIGS. 6, 7, and 8.

FIG. 6 schematically illustrates in more detail an example of the circuit provided for converting a virtual tag part into a physical tag part. As in the illustration of FIG. 5, a virtual address 80 is shown including a virtual tag portion (including bits [63:56]) and a virtual address portion (including bits [55:0]). The bits in the virtual tag part can have different uses, as shown in the figure, a minimum of 4 bits of the virtual tag part ([59:56]) labeled "t" are translated. Form a virtual tag part. The remaining bits of the higher virtual tag portion ([63:60]) serve different functions as explained in more detail below. The set of bits "t" of the virtual tag portion is received by tag translation circuit 72, which provides two possible paths for this set of bits. Which of these paths follows is determined by the settings of multiplexers 94, 96 under control of control circuit 76. Essentially this is a direct route through the tag translation circuit or a route via the configurable translation circuit 98. In the illustrated example, control circuit 76 makes the translation selection based on the most significant bit (bit[55]) of the virtual address portion. Thus, when this bit is set, a path through translation circuit 98 is selected, but when this bit is not set, a direct path through tag translation circuit 72 is selected. This control is illustrated on the right side of FIG. 6 by the logic statement if VA[55]=1 PA[t]=t-bar else PA[t]=t. In other words, if bit 55 is set, t is inverted, otherwise t is propagated unchanged. However, inversion is not the only conversion that can be performed, and the conversion performed by conversion circuit 98 can vary depending on configuration settings 100. In another example, the transformation can be an increment of the value represented by the portion t, and other transformations can be envisaged as well. The manner in which the device operates may also be influenced by other bits within the virtual tag portion. As shown in FIG. 6, another bit (labeled m) is also received by control circuit 76. where, under the control of a guard tag control circuit, the physical address is stored for use in a memory system that includes tag guarded memory accesses (e.g., as described above with reference to FIGS. 2 and 3). An example is shown where a tag-guarded memory access is generated, and an additional bit "m" can be used to exert control over the manner in which this tag-guarded memory access is performed. In the example shown in FIG. 6, the "m" bit is the set of four bits 102 generated by the tag translation circuit 72 used by the memory system to define a "match_all" or "match_one" condition. Determine whether or not. In other words, depending on the setting of this m bit, tag-guarded memory accesses include the physical address tag for bit 102 and the stored guard address associated with the associated memory address (in the match_one condition). A match is required between the tags, or any set of address tags of bits is effectively able to satisfy the match (in the match_all condition).

Generally, the remainder of the virtual tag section may be considered "reserve" as labeled in the diagram, but in some instances (e.g., labeled "c" in the diagram) One or more bits of this reserved part can additionally be used to provide one or more additional control bits configurable within the virtual tag part; The memory system may be communicated and/or configuration settings of the device may be influenced. Thus, as shown (alternatively in dashed lines) in the figure, these reserved bits can determine the configuration settings 100, e.g. two additional bits 106 which are passed to the memory system as additional control bits. It can also be provided. Finally, guard tag control circuit 104 is generally configured such that when a particular bit combination of set of bits 102 is received (in a physical tag), a "match_all" condition is set. Please note that. In the example shown, this is when all bits are set. This is also illustrated by the logic statement towards the bottom right of FIG. 6: if PA[t]=0xF match_all else match_one. Virtual addresses may be distributed within a system where a portion of the available virtual address space is reserved for user space and another portion for kernel space (as shown in Figure 4). possible, and recalling that this provides a default meaning for the high-order part of a full (e.g. 64-bit) virtual address, by the translation circuit 72, controlled by the most significant bit (bit[55]) of the virtual address part. The translation that takes place is therefore the same predetermined combination of "match_all" bits (0xF in this example) in the memory control system, regardless of whether the virtual address is allocated for kernel space or for user space. It may be provided that the In other example configurations, a 5-bit physical tag may be used, where one bit is devoted to indicating whether a "match_all" comparison or a "match_one" comparison is to be made. and the other four bits are used for this comparison if "match_one" is configured.

FIG. 7 is another schematic diagram of some of the circuits shown in FIG. 6, in which a variation on the control of conversion circuit 98 by control circuit 76 is shown. Control circuit 76 receives certain bits of the virtual tag portion (labeled “OV” (override)), which means that conversion circuit 98 converts the particular bit (or combination of bits) into the physical tag portion. Can be used to force generation. This can be used, for example, to force a match_all comparison to take place. However, in principle, any forced bits (or Either purpose can be served by a combination of bits) and an override bit (OV) in the virtual tag part can be used to trigger this.

In one example, an approach is taken in which a selection is made for at most one of the virtual tag encodings based on the most significant bits of the virtual address portion, defined as the "match_all" physical tag encoding. . Whether this "match_all" comparison is performed may also be based on other context configurations. For example, this can be configured such that all user tags are 'match_one', user tag '0' can be configured such that it is 'match_all', All kernel tags can be configured to be "match_one" and kernel tags "1111" can be configured to be match all.

FIG. 8 is a flow diagram illustrating a series of steps performed in one example. At step 120, a new virtual address to be translated is received. In step 122, it is determined (eg, using reserved bits in the virtual tag part) whether there is a particular configuration to be applied to the translation circuit, in which case this occurs in step 124. At step 126, the translation to be applied to the virtual tag portion is determined based on the virtual address portion of the virtual address (eg, based on its most significant bits). The selected transformation is then applied to a portion of the virtual tag portion (to generate a corresponding physical tag portion) in step 128. In step 130, it is determined whether bit "m" is 1, which means whether a match_all comparison is to be made (step 132) or a match_one comparison (step 134). judge whether Finally, in step 136, it is determined whether the generated set of bits in the physical address tag portion corresponds to a predetermined special value, which in this example is a continuous set of ones (0xF ). In this case, the flow proceeds to step 140, where this triggers a special operation in the memory system, whereas if not, the flow proceeds through step 138, where it is determined that the ” A tag-guarded memory access is performed and the comparison is checked as match_all or match_one, as determined in step 130. Flow then returns to step 120.

FIG. 9 shows an implementation of a simulator that can be used. Although the previously described embodiments implement the invention in terms of apparatus and methods for operating specific processing hardware that supports the techniques in question, it is also possible to implement the invention through the use of computer programs. An instruction execution environment may also be provided according to the embodiments described herein. Such computer programs are often referred to as simulators insofar as they provide a software-based implementation of a hardware architecture. Various types of simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, a simulator implementation may run on a host processor 230 that supports the simulator program 210 and optionally executes a host operating system 220. In some designs, there may be multiple layers of simulation between the hardware and the provided instruction execution environment and/or multiple separate instruction execution environments provided on the same host processor. be. Historically, powerful processors have been required to provide simulator implementations that run at reasonable speeds, but such approaches have been difficult to implement natively on another processor for compatibility or reuse. may be justified in certain circumstances, such as when there is a desire to execute code. For example, simulator implementations may provide additional functionality to the instruction execution environment not supported by the host processor hardware or may provide instruction execution environments typically associated with different hardware architectures. I can do it. An overview of the simulation is given in "Some Efficient Architecture Simulation Techniques", Robert Bedichek, Winter 1990 USENIX Conference, pages 53-63.

To the extent that embodiments have been described above with reference to particular hardware structures or features, equivalent functionality may be provided by suitable software structures or features in the simulated embodiments. For example, certain circuits may be implemented in simulated embodiments as computer program logic. Similarly, memory hardware such as registers or caches can be implemented in simulated embodiments as software data structures. In designs where one or more of the hardware elements referenced in the previous embodiments reside on host hardware (e.g., host processor 230), some simulated embodiments may・Can use hardware.

The simulator program 210 is stored on a computer readable storage medium 212 (which can be a non-transitory medium) and has the same application program interface of the hardware architecture modeled by the simulator program 210. A programmatic interface to target code 200 (which may include applications, operating systems, and hypervisors) may be provided. In this way, the program instructions of target code 200 can be executed from within the instruction execution environment using simulator program 210, thereby controlling the hardware characteristics of device 2 and Host computer 230, which does not actually include tag translation circuitry 72, in particular, can emulate these features. For example, the simulator program 210 may include address translation logic 214 for translating virtual addresses to physical addresses, and in particular address translation logic 216 for translating virtual address tag portions to physical address tag portions. can include. In this way, the simulator program 210 performs a memory access to perform a comparison between the guard tag and the address tag and report whether any mismatch between the guard tag and the address tag is detected. - Can also include program logic. Simulator program 110 may also include tag setting program logic that includes instructions for setting guard tags in a manner that corresponds to the manner in which the hardware implementation would set the tags.

To briefly summarize, the apparatus includes an address translation circuit for translating a virtual address including a virtual tag part and a virtual address part to a physical address including a physical tag part and a physical address part. The address translation circuit includes an address tag translation circuit for translation of a virtual tag part into a physical tag part, and the translation to be performed by the address tag translation circuit is selected depending on the virtual address. .

In this application, the word "configured to..." is used to mean that an element of a device is equipped with a configuration capable of performing a defined operation. In this context, "configuration" means the design or approach of hardware or software interconnections. For example, an apparatus may include dedicated hardware to perform defined operations, or a processor or other processing device may be programmed to perform the functions. "Configured to" does not imply that elements of the device need to be modified in any way to perform the defined operation.

Although illustrative embodiments have been described in detail herein with reference to the accompanying drawings, the invention is not limited to these precise embodiments, but is defined by the appended claims. It will be appreciated that various changes, additions, and modifications may be made by those skilled in the art without departing from the scope of the invention. For example, various combinations of the features of the dependent claims can be made with the features of the independent claims without departing from the scope of the invention.

Claims (18)

An apparatus comprising an address conversion circuit for converting a virtual address including a virtual tag part and a virtual address part into a physical address including a physical tag part and a physical address part, the apparatus comprising:
The address conversion circuit includes an address/tag conversion circuit for converting the virtual tag part into the physical tag part,
the address translation circuit selects the translation to be performed by the address tag translation circuit in dependence on the virtual address portion;
the translation performed by the address tag translation circuit depends on the most significant bit of the virtual address part;
Device. when the most significant bit of the virtual address portion includes a first value, the selected translation performed by the address-to-tag translation circuit produces the physical tag portion that matches the virtual tag portion;
2. When the most significant bit includes a second value, the selected translation performed by the address tag translation circuit modifies the virtual tag portion to generate the physical tag portion . equipment. The apparatus is designed to allocate a virtual address for exclusive use by one of a kernel-specific process and a user-specific process, and the value of the most significant bit of the virtual address portion indicates that the virtual address is a kernel-specific process. The apparatus according to claim 1 or 2 , wherein the apparatus indicates whether the processing is allocated to specific processing or user-specific processing. Any one of claims 1 to 3 , wherein the selected translation performed by the address-to-tag translation circuit comprises inverting at least a portion of the virtual tag part to generate the physical tag part. Equipment described in Section. 4. The method of claim 1 , wherein the selected translation performed by the address tag translation circuit comprises incrementing at least a portion of the virtual tag portion to generate the physical tag portion. Equipment described in Section. further comprising a memory system for receiving the physical address and accessing the storage location identified by the physical address portion, the memory system responsive to receiving the physical address, identifying the physical tag portion of the physical tag portion; 6. Apparatus according to any one of claims 1 to 5 , wherein the device performs a predetermined memory operation when the predetermined portion contains a predetermined value. the predetermined memory operation is a guard tag comparison of the physical tag portion with a guard tag value associated with the memory location; 7. The apparatus of claim 6 , wherein the apparatus indicates a fault condition in response to not meeting a match condition. 8. The apparatus according to claim 7 , wherein when the predetermined portion of the physical tag section includes a predetermined value, the match condition is a match-all condition such that any guard tag value satisfies the match condition. When the predetermined portion of the physical tag portion does not include the predetermined value, the predetermined portion of the physical tag portion and the guard tag value must be the same in order to satisfy the match condition. 9. The apparatus according to claim 8 , wherein the match-one condition is such that: 10. The apparatus according to claim 8 or 9 , wherein the predetermined portion of the physical tag portion is a predetermined set of bits of the physical tag portion. The address/tag conversion circuit generates the physical tag portion in response to a predetermined bit of the virtual tag portion including a predetermined value, and the predetermined portion of the physical tag portion is configured to correspond to another predetermined bit of the virtual tag portion. 11. The device according to any one of claims 8 to 10 , wherein the predetermined value is independent of the value of . The device according to claim 8 or 9 , wherein the predetermined portion of the physical tag portion is a predetermined bit of the physical tag portion. 13. The guard tag comparison is for comparing some of the physical tag portions with the guard tag value associated with the storage location. equipment. 14. The apparatus according to any one of claims 8 to 13 , wherein the predetermined value of the predetermined portion of the physical tag portion includes all bits of the same bit value. the virtual tag portion includes at least one bit included in the physical address, and the memory system is configured to access the memory location when a write access is made to the memory location in response to the at least one bit; 15. Apparatus according to any one of claims 7 to 14 , controlling the overwriting of the guard tag value associated with. selecting a translation to a physical address including a physical tag part and a physical address part to be performed on a virtual address including a virtual tag part and a virtual address part, the selection of the translation being performed on a virtual address including a virtual tag part and a virtual address part; a step that depends on the address part;
performing the conversion to convert the virtual tag portion to the physical tag portion;
the translation depends on the most significant bits of the virtual address part;
Method. A computer program for controlling a host data processing device to provide an instruction execution environment for execution of instructions of target program code, the computer program comprising:
Address conversion program logic for converting a virtual address including a virtual tag part and a virtual address part to a physical address including a physical tag part and a physical address part, the address translation program logic comprising:
including address tag conversion program logic for converting the virtual tag part to the physical tag part;
the address translation program logic selects the translation to be performed by the address tag translation program logic depending on the virtual address portion ;
the translation performed by the address tag translation program logic depends on the most significant bits of the virtual address portion;
computer program. A storage medium storing a computer program according to claim 17 .