JP7370302B2 - Imaging device - Google Patents

Description

The present disclosure relates to an imaging device. The present disclosure particularly relates to an imaging device including an image sensor suitable for use in fields such as remote sensing.

A TDI (Time Delay Integration)-CCD type image sensor has been developed that is mounted on a flying object such as an artificial satellite and is intended to image the earth's surface from above.
Furthermore, an imaging device is known in which a plurality of the above image sensors are arranged so that the horizontal transfer direction of each image sensor corresponds to the CT (Cross Track) direction and the vertical transfer direction of each image sensor corresponds to the AT (Along Track) direction. It is being

When such an imaging device is tilted in the CT direction to capture an image diagonally downward, the larger the tilt angle of the light receiving direction of each pixel, the larger the range imaged by that pixel (light receiving range or imaging range), and the larger the image capturing range. There is a problem that the sharpness deteriorates.
Patent Document 1 proposes that the output period can be set separately for each image sensor, and that the wider the light receiving range (that is, the farther the image sensor is located in the CT direction), the longer the output period. has been done.

Japanese Patent Application Publication No. 2011-024167

However, in the imaging device shown in Patent Document 1, even if it is possible to increase the sharpness of pixels at a certain position in the CT direction within the same image sensor, the sharpness of pixels at other positions is high. There is a problem in that images may not be obtained.

An object of the present disclosure is to solve the above problems and provide an imaging device that can obtain sharp images for all pixels regardless of their position in the CT direction within an image sensor.

An imaging device according to the present disclosure includes:
An imaging device that includes a plurality of TDI image sensors and captures images while moving in an AT direction with respect to the ground surface,
The plurality of image sensors are arranged at mutually different positions in the CT direction on the focal plane of the imaging device,
Each of the image sensors includes a plurality of pixels arranged in a plurality of pixel columns, each pixel generates a charge by photoelectric conversion, and the generated charge is vertically transferred in accordance with the speed of the movement. The pixel array includes a transfer electrode that performs time-delay integration, and a horizontal transfer section that horizontally transfers the time-delay integrated charges.
The farther the image sensor is placed from the reference line extending in the AT direction on the focal plane, the smaller the size of the pixel,
When the imaging device is in a state of imaging a part of the ground surface that is farther away in one of the CT directions than the direction directly below, and the pointing angle of the imaging device is larger than a predetermined value;
Of the plurality of image sensors, the image sensor is located on a side corresponding to the side where the imaged portion is located with respect to the reference line, and is arranged at a position away from the reference line, Control is performed such that the farther a pixel is located from the reference line, the greater the number of stages of the time delay integration for the charge generated at the pixel.

According to the present disclosure, a sharp image can be obtained for all pixels regardless of the position in the CT direction within the image sensor.

1 is a functional block diagram showing an imaging device according to a first embodiment together with a ground station; FIG. FIG. 2 is a layout diagram showing an example of the configuration of the focal plane detector in FIG. 1; FIG. 3 is a schematic diagram showing a configuration example of each of a plurality of image sensors shown in FIG. 2. FIG. (a) and (b) show the light receiving direction of a pixel and the range on the ground surface imaged by the pixel (imaging range) when the imaging device shown in FIGS. 1 and 2 images the ground surface. FIG. (a) is a schematic diagram showing how the imaging device shown in FIGS. 1 and 2 images directly below, and (b) is a schematic diagram showing the image sensor and the ground surface in the state of FIG. FIG. 2 is a diagram schematically showing the correspondence relationship between the image capturing range and the imaging range. (a) is a schematic diagram showing how the imaging device shown in FIGS. 1 and 2 images diagonally downward, and (b) is a schematic diagram showing the image sensor and the ground surface in the state of FIG. 6(a). FIG. 2 is a diagram schematically showing the correspondence relationship between the image capturing range and the imaging range. FIG. 6 is a schematic diagram showing the relationship between pixels at different positions of the image sensor located at the center and the corresponding imaging range when the imaging device is imaging in the direction directly below. FIG. 6 is a schematic diagram showing the relationship between pixels at different positions of the image sensor located at the left end and the corresponding imaging range when the imaging device is imaging diagonally downward to the left. (a) to (c) are diagrams showing pixel sizes of an image sensor. 3 is a diagram showing a pixel array, a vertical transfer section, and a TDI stage number setting circuit in an example of the image sensor located on the left side of FIG. 2. FIG. 11 is a diagram showing a configuration example of the TDI stage number setting circuit of FIG. 10. FIG. 3 is a diagram showing a pixel array, a vertical transfer section, and a TDI stage number setting circuit in an example of the image sensor located on the right side of FIG. 2. FIG. 13 is a diagram showing a configuration example of the TDI stage number setting circuit of FIG. 12. FIG. 3 is a diagram showing a pixel array, a vertical transfer section, and a TDI stage number setting circuit in another example of the image sensor located on the left side of FIG. 2. FIG. 3 is a diagram showing a pixel array, a vertical transfer section, and a TDI stage number setting circuit in another example of the image sensor located on the right side of FIG. 2. FIG. (a) and (b) are waveform diagrams showing signals used for horizontal transfer and readout processing when horizontal integration is not performed in the image sensor of the imaging device; d) is a waveform diagram showing signals used for horizontal transfer and readout processing when horizontal integration is performed while changing the number of integration stages in an image sensor of an imaging device. (a) and (b) are waveform diagrams showing signals used for horizontal transfer and readout processing when horizontal integration is performed while maintaining a constant number of integration stages in an image sensor of an imaging device. It is. (a) is a diagram schematically showing a part of the horizontal transfer section and the readout circuit, and (b) is a diagram showing the state transition of the potential well and the charge transfer in the horizontal transfer section when horizontal integration is not performed. FIG. 2C is a waveform diagram showing the transfer clock applied to the transfer electrode and the reset pulse applied to the readout circuit when horizontal integration is not performed. (a) is a diagram schematically showing a part of the horizontal transfer section and the readout circuit, and (b) is a diagram showing the state transition of the potential well and charge transfer in the horizontal transfer section when horizontal integration is performed. FIG. 5C is a waveform diagram showing a transfer clock applied to the transfer electrode and a reset pulse applied to the readout circuit when horizontal integration is performed. 3 is a diagram showing the positional relationship of a plurality of image sensors shown in FIG. 2. FIG. 7 is a layout diagram showing a configuration example of a focal plane detector used in an imaging device according to a second embodiment. FIG. 22 is a diagram showing the positional relationship of a plurality of image sensors shown in FIG. 21. FIG. FIG. 7 is a layout diagram showing a configuration example of a focal plane detector used in an imaging device according to Embodiment 3;

Embodiment 1.
FIG. 1 is a functional block diagram showing an imaging device according to a first embodiment together with a ground station. The imaging device 100 in FIG. 1 is mounted on a flying object, for example, an artificial satellite, and images the ground surface as a subject.
The ground station 200 transmits various control signals for remotely controlling the imaging device 100 to the imaging device 100, and also indicates the imaging data obtained by imaging and the state of the imaging device 100 from the imaging device 100. Receive various status signals.

The illustrated imaging device 100 includes an optical system 110, a focal plane detector 120, an integral stage number control section 130, an attitude detection section 140, a transmission/reception processing section 150, and an attitude control section 160.

As shown in FIG. 2, the focal plane detector 120 includes a plurality of TDI image sensors 1C, 2L, 2R, 3L, and 3R arranged on the focal plane 122. Each of the image sensors 1C, 2L, 2R, 3L, and 3R has a pixel array 30.
Each of the image sensors 1C, 2L, 2R, 3L, and 3R may be, for example, a CCD image sensor or a CMOS image sensor. The following description assumes that each image sensor is a CCD image sensor. Furthermore, hereinafter, the image sensor may be simply referred to as a "sensor".

FIG. 2 is a diagram of the focal plane 122 viewed from the ground surface side. In FIG. 2, the AT direction is from bottom to top, and the CT direction is from left to right. The AT direction is the direction of movement of the flying object relative to the ground surface, and is also called the scanning direction.

The optical system 110 focuses the incident light on a focal plane 122 . Optical system 110 includes, for example, a telescope made up of optical elements such as lenses and mirrors.

The integration stage number control unit 130 determines the method of reading out the captured image, specifically, the number of TDI stages in the sensor of the focal plane detector 120 and the number of integration stages in horizontal transfer, and performs control based on the determination.
The attitude detection unit 140 detects the attitude of the imaging device 100. The posture here means the imaging direction, that is, the pointing angle of the imaging device 100.

The transmission/reception processing unit 150 transmits the attitude control signal transmitted from the ground station 200 to the attitude control unit 160.
The attitude control unit 160 controls the attitude of the imaging device 100 based on the attitude control signal received by the transmission/reception processing unit 150 and information indicating the attitude detected by the attitude detection unit 140. The posture control includes controlling the imaging direction, that is, the pointing angle of the imaging device 100.

Imaging data obtained by imaging with the focal plane detector 120 is transmitted to the ground station 200 by the transmission/reception processing section 150.
Information indicating the attitude detected by the attitude detection section 140 is also transmitted to the ground station 200 by the transmission/reception processing section 150.

The attitude control unit 160 transmits information indicating the attitude detected by the attitude detection unit 140 to the integration stage number control unit 130.

The integration stage number control unit 130 controls the number of TDI stages in the plurality of sensors forming the focal plane detector 120 and the number of integration stages in horizontal transfer based on information indicating the attitude of the imaging device 100 transmitted from the attitude control unit 160. . For control, the integration stage number control section 130 outputs a control signal specifying the number of TDI stages and a control signal specifying the number of integration stages.

In one or more of the plurality of sensors, integration in horizontal transfer is controlled to be performed in different stages depending on the position of the pixel in the pixel array 30.
Furthermore, as will be described later, in one or more of the sensors, the pixel array 30 is divided into a plurality of regions, and the TDI is controlled so that the number of stages independently set for each divided region is performed. Ru.

For example, as shown in FIG. 3, each of the sensors 2L, 2R, 3L, and 3R includes a pixel array 30, a plurality of vertical transfer units 40, a horizontal transfer unit 50, a readout circuit 60, and a number of TDI stages. It includes a setting circuit 70 and a drive signal generation circuit 80.

The pixel array 30 includes a plurality of pixels Pp arranged in a grid pattern, ie, in a plurality of pixel columns.

The plurality of vertical transfer units 40 integrate the signal charges generated in the pixels of the pixel array 30 with a time delay and transfer the signal charges in the vertical direction and downward in the drawing.
The vertical transfer section 40 is configured within the pixel array 30 and can also be seen as a part of the pixel array 30. The plurality of vertical transfer units 40 constitute a TDI execution unit.

The horizontal transfer unit 50 horizontally transfers the signal charges transferred in the vertical direction by the vertical transfer unit 40. The horizontal transfer section 50 is composed of a horizontal CCD.
The readout circuit 60 reads and outputs the signal charges transferred by the horizontal transfer section 50.

The TDI stage number setting circuit 70 sets the TDI stage number based on a control signal from the integral stage number control section 130 that specifies the TDI stage number.

The drive signal generation circuit 80 generates a horizontal transfer clock and a reset pulse based on a control signal from the integration stage number control section 130 that specifies the number of integration stages.

As will be described later, the sensor 1C has a fixed number of TDI stages and does not perform integration in horizontal transfer. The sensor 1C may have the same configuration as shown in FIG. 3, with the number of TDI stages fixed and the number of integration stages in horizontal transfer fixed at one.
Here, regarding the number of TDI stages and the number of integral stages in horizontal direction transfer, "fixed" means that they do not change depending on the attitude of the imaging device 100, and may change due to other factors. .

Each of the sensors 1C, 2L, 2R, 3L, and 3R is arranged such that the vertical transfer direction matches the AT direction (however, the direction is opposite), and the horizontal transfer direction matches the CT direction. There is.

The sensors 1C, 2L, 2R, 3L, and 3R are arranged at different positions in the CT direction on the focal plane 122.
For example, the sensor 1C is arranged at the center in the CT direction on the focal plane 122, the sensors 2L and 2R are arranged at positions slightly apart from the center in the CT direction, and the sensors 3L and 3R are arranged at the center in the CT direction. It is located further away from the center.

Specifically, the sensor 1C is arranged such that the horizontal center of its pixel array 30 is located on the reference line 123 of the focal plane 122, and the sensors 2L and 2R are arranged so that the horizontal center of their pixel array 30 is located on the reference line 123 of the focal plane 122. The sensors 3L and 3R are arranged so that the distances from the center of the pixel array 30 to the reference line 123 are equal to each other, and the sensors 3L and 3R are arranged so that the distances from the horizontal center of their pixel array 30 to the reference line 123 are equal to each other. It is located in

The reference line 123 passes, for example, through the center of the focal plane 122 in the CT direction and extends in the AT direction.
Therefore, it can be said that the sensors 3L, 2L, 1C, 2R, and 3R are arranged mirror-symmetrically about a plane (reference plane) that includes the reference line 123 and is perpendicular to the CT direction.

When the imaging device 100 shown in FIG. 1 images the ground surface, the imaging data of the plurality of sensors 3L, 2L, 1C, 2R, and 3R mounted on the focal plane detector 120 are used to determine the position of the pixel in the CT direction. A series of imaging data is generated by sequentially connecting the images. In this connection, the imaging data output from the sensor 2L is placed next to the imaging data output from the sensor 3L, the data output from the sensor 1C is placed next to the imaging data output from the sensor 2L, The image data output from the sensor 2R is placed next to the image data output from the sensor 1C, and the image data output from the sensor 3R is placed next to the image data output from the sensor 2R. That is, the imaging data output from the sensors 3L, 2L, 1C, 2R, and 3R are connected in the order of the positions of the sensors 3L, 2L, 1C, 2R, and 3R in the CT direction.

When the sensors 3L, 2L, 1C, 2R, and 3R are arranged at the same position in the AT direction and arranged along a straight line in the CT direction, gaps are created between the sensors, and imaging data is lost in the gaps. Therefore, the sensors 3L, 2L, 1C, 2R, and 3R are shifted in the AT direction and arranged so that their ends in the CT direction overlap to prevent missing imaging data.

An example of such an arrangement is the staggered arrangement shown in FIG.
In the example shown in FIG. 2, sensors 1C, 3L, and 3R are located at the same position in the AT direction and are arranged (aligned) on a straight line extending in the CT direction, and sensors 2L and 2R are in the same position in the AT direction. Sensors 1C, 3L, and 3R are located at the same position and are arranged on a straight line extending in the CT direction (aligned with each other), and sensors 2L and 2R have different positions in the AT direction and are arranged in the CT direction. do not overlap.

Furthermore, the ends of the sensors 3L and 2L, especially their pixel array 30, in the CT direction overlap in the AT direction, and the ends of the sensors 2L and 1C, especially their pixel array 30, in the CT direction overlap in the AT direction. The sensors 3R and 2R, especially their pixel arrays 30, have their CT direction ends overlapped in the AT direction, and the sensors 2R and 1C, especially their pixel arrays 30, have their CT direction ends overlapped in the AT direction. Overlap.
"Overlapping in the AT direction" means that one is hidden by the other when viewed in the AT direction.

In the example shown in FIG. 2, the focal plane detector 120 includes five sensors, but the number of sensors forming the focal plane detector 120 may be other than five.

Below, we will explain how the range on the ground surface imaged by each pixel (imaging range) changes depending on the pointing angle when the pixels of sensors 3L, 2L, 1C, 2R, and 3R have the same size. and explain the problems caused by it.
Here, the pointing angle of each pixel means the angle formed by the light receiving direction of the pixel with respect to the direction directly below the imaging device 100. The light receiving direction of each pixel is the direction of the center of the range on the ground surface (imaging range) imaged by the pixel.

4(a) and (b) show the light receiving direction DL of a specific pixel and the ground surface imaged by the pixel when the imaging device 100 shown in FIGS. 1 and 2 images the ground surface 210. The relationship with the above range (imaging range) is shown. FIG. 4(a) shows a state in which the imaging device 100 is imaging directly below, and FIG. 4(b) shows a state in which the imaging device 100 is imaging diagonally below.

In the state shown in FIG. 4(a), the light receiving direction DL of the pixel located at the horizontal center of the pixel array 30 of the sensor 1C is the vertical direction (directly downward direction) VL, and in that case, the imaging range G-1Cp is relatively small. The imaging range of not only the pixel located at the horizontal center of the pixel array 30 of the sensor 1C but also the pixel with a small pointing angle is relatively small.

In the state shown in FIG. 4B, the light receiving direction DL of the pixel at the left end (the farthest position from the center in the horizontal direction) of the pixel array 30 of the sensor 3L is tilted with respect to the vertical direction (directly below) VL. There is. In the illustrated example, the image is tilted in the CT direction, and a position farther to the left in the figure than the part directly below is imaged. In that case, the imaging range G-3Lp of the above pixel is larger than the imaging range G-1Cp shown in FIG. 4(a), and the dimensions of the imaging range in the CT direction and in the AT direction are also larger. It has become.
The imaging range of not only the leftmost pixel of the pixel array 30 of the sensor 3L but also of pixels with a large pointing angle is relatively large.

The above points will be discussed in more detail below.
5(a) and 6(a) schematically show how the imaging device 100 shown in FIGS. 1 and 2 images the ground surface 210, and FIG. 5(b) and FIG. 6(b) , Correspondence between sensors 3L, 2L, 1C, 2R, and 3R and imaging ranges G-3L, G-2L, G-1C, G-2R, and G-3R on the ground surface 210 during imaging. The outline is shown below.

In the examples shown in FIGS. 5(b) and 6(b), it is assumed that a portion of the ground surface 210 on the left side in these figures is imaged by a sensor located further on the left side in FIG. There is.
Note that, in reality, depending on the configuration of the imaging optical system, the left side portion of the ground surface 210 is not necessarily located on the left side of the focal plane 122. Here, "left" on the focal plane 122 means the side on which the image of the left portion of the ground surface 210 is formed. In other words, "left side" on focal plane 122 means the side corresponding to the left portion of ground surface 210.

In FIGS. 5(b) and 6(b), the sensors 3L, 2L, 1C, 2R, and 3R have the same dimensions in the CT direction of their pixel arrays 30, and the edges of their pixel arrays 30 in the CT direction. It is assumed that the parts do not overlap each other.

FIG. 5A shows how the imaging device 100 images a portion of the ground surface 210 directly below, that is, a portion 212 centered on a point 211 directly below (a portion directly below).
FIG. 5(b) shows the sensors 3L, 2L, 1C, 2R, and 3R and the imaging ranges G-3L, G-2L, G-1C, and G- on the ground surface 210 in the state of FIG. 5(a). An outline of the correspondence with 2R and G-3R is shown.
In Fig. 5(b), there is no large difference between the dimensions of the imaging ranges G-3L, G-2L, G-1C, G-2R, and G-3R in the CT direction, and they are considered to be equal to each other. be able to.

FIG. 6A shows how the imaging device 100 images the diagonally lower left portion of the ground surface 210, that is, the diagonally lower left portion 214. The diagonally lower left portion 214 is an area centered on a point 213 that is away from the point 211 directly below in the left direction. Here, "left" indicates the direction on FIG. 6(a). Therefore, "left" means the side (the side corresponding to) where the sensors 3L and 2L located on the left side in FIG. 2 are located.
Further, in the following, it is assumed that the object is tilted only in the CT direction and not in the AT direction. Therefore, the pointing angle indicates the tilt in the CT direction.

In FIG. 6A, the pointing angle of the imaging device 100 is indicated by the symbol θ1. The pointing angle of the imaging device 100 is equal to the pointing angle of a pixel located at the center of the imaging device 100, that is, a pixel on the reference line 123.

FIG. 6(b) shows the sensors 3L, 2L, 1C, 2R, and 3R and the imaging ranges G-3L, G-2L, G-1C, and G- on the ground surface 210 in the state of FIG. 6(a). An outline of the correspondence with 2R and G-3R is shown.
In FIG. 6(b), among the dimensions in the CT direction of the imaging ranges G-3L, G-2L, G-1C, G-2R, and G-3R, the dimension of the imaging range G-3L is the largest, and the imaging range G-3R has the smallest dimensions. Among the imaging ranges G-3L, G-2L, G-1C, G-2R, and G-3R, the further left the imaging range, the larger the dimension in the CT direction. However, the differences between the dimensions of the imaging ranges G-1C, G-2R, and G-3R are small, and they can be considered to be equal to each other.

As mentioned above, it is assumed here that the pixels of the sensors 3L, 2L, 1C, 2R, and 3R have the same size. In that case, the imaging range of each pixel of each of the sensors 3L, 2L, 1C, 2R, and 3R has the same tendency as the imaging range of the sensor.
For example, in a state where images are taken directly below as shown in FIG. 5A, the imaging ranges of the pixels of the sensors 3L, 2L, 1C, 2R, and 3R are equal to each other.

FIG. 7 shows the pixel P-1CL located at the left end of the sensor 1C, the pixel P-1CC located at the center of the sensor 1C, and the right end of the sensor 1C in a state where the image is taken directly below as shown in FIG. 5(a). The pixel P-1CR located at , and the CT direction dimensions G-1CL, G-1CC, and G-1CR of the corresponding imaging range are shown. There is no significant difference between the dimensions G-1CL, G-1CC, and G-1CR. For example, the dimensions G-1CL, G-1CC, and G-1CR are approximately 10 m. The imaging range of each pixel of the sensors 3L, 2L, 2R, and 3R is also not significantly different from the imaging range of each pixel of the sensor 1C.

In a state where the image is captured diagonally downward to the left as shown in FIG. 6(a), the imaging range of each pixel of sensors 3L and 2L is wider than the imaging range of each pixel of sensor 1C, There is no significant difference in the imaging range of each pixel of the sensor 1C. Furthermore, the imaging range of each pixel of the sensor 3L is wider than the imaging range of each pixel of the sensor 2L.

FIG. 8 shows a pixel P-3LL located at the left end of the sensor 3L, a pixel P-3LC located at the center of the sensor 3L, and a pixel P-3LC located at the center of the sensor 3L, in a state where the image is taken diagonally downward to the left as shown in FIG. 6(a). The pixel P-3LR located at the right end of the figure and the CT direction dimensions G-3LL, G-3LC, and G-3LR of the corresponding imaging range are shown. Among the dimensions G-3LL, G-3LC, and G-3LR, G-3LR is the smallest, G-3LC is larger than G-3LR, and G-3LL is larger than G-3LC. That is, the closer a pixel is located to the center of the focal plane 122, the narrower the imaging range is, and the further outside the pixel is located, the wider the imaging range. Here, "the center side of the focal plane 122" means a side closer to the reference line 123, and "outside" means a side farther from the reference line 123.

The difference in imaging range between pixels increases as the pointing angle of the imaging device 100 increases.
The imaging range corresponding to each pixel of the sensor 3L increases as the pointing angle of the pixel increases.
The imaging range of each pixel of the sensor 2L also has the same tendency as the sensor 3L. However, the extent of this is relatively small.

As described above, in the states shown in FIGS. 5A and 5B, as explained with reference to FIG. There is no big difference between the imaging ranges, and they can be seen as being equal.

On the other hand, in the states shown in FIGS. 6(a) and 6(b), as described with reference to FIG. 8, the imaging range corresponding to each pixel of sensors 3L and 2L corresponds to each pixel of sensor 1C. There is a big difference in the imaging range. The difference in the imaging range corresponding to each pixel of the sensor 3L with respect to the imaging range corresponding to each pixel of the sensor 1C is the difference in the imaging range corresponding to each pixel of the sensor 2L with respect to the imaging range corresponding to each pixel of the sensor 1C. larger than On the other hand, there is no large difference between the imaging range corresponding to each pixel of sensors 2R and 3R and the imaging range corresponding to each pixel of sensor 1C, and they can be considered to be equal.

From the recognition of the states shown in FIGS. 6(a) and 6(b), the following can be said about the state in which the image is taken diagonally downward to the right, contrary to the states shown in FIGS. 6(a) and 6(b).
The imaging range corresponding to each pixel of the sensors 3R and 2R is significantly different from the imaging range corresponding to each pixel of the sensor 1C. The difference in the imaging range corresponding to each pixel of sensor 3R with respect to the imaging range corresponding to each pixel of sensor 1C is the difference in the imaging range corresponding to each pixel of sensor 2R with respect to the imaging range corresponding to each pixel of sensor 1C. larger than On the other hand, there is no large difference between the imaging range corresponding to each pixel of the sensors 2L and 3L and the imaging range corresponding to each pixel of the sensor 1C, and they can be considered to be equal.

Although the dimension in the CT direction of the imaging range corresponding to each pixel has been described above, the same tendency exists for the dimension in the AT direction of the imaging range corresponding to each pixel.

If the imaging range corresponding to each pixel is wide, there is a problem that the sharpness of the image deteriorates. This is because, as explained with reference to FIG. 6 in Patent Document 1, for example, the imaging range in the AT direction includes an area that becomes noise.

The problems when the pixel sizes are the same between sensors have been explained above. In order to solve such a problem, in this embodiment, the pixel size in the AT direction and the CT direction of the sensor located on the outer side of the sensors is made smaller. Specifically, the pixel sizes of the sensors 2L and 2R are made smaller than the pixel size of the sensor 1C. Furthermore, the pixel sizes of the sensors 3L and 3R are made smaller than the pixel sizes of the sensors 2L and 2R.
Here, "pixel size" may mean the pixel size (dimension) in the horizontal direction, or may mean the pixel size (dimension) in the vertical direction.

For example, the pixel size H2 in the AT direction of each pixel of the sensors 2L and 2R shown in FIG. 9(b) is set to an integer fraction of the pixel size H1 in the AT direction of the sensor 1C shown in FIG. 9(a). , the pixel size W2 in the CT direction of each pixel of the sensors 2L and 2R shown in FIG. 9(b) is set to an integer fraction of the pixel size W1 in the CT direction of the sensor 1C shown in FIG. 9(a). The integer here is an integer greater than or equal to 2, for example 2.

Furthermore, the pixel size H3 in the AT direction of each pixel of the sensors 3L and 3R shown in FIG. 1, and the pixel size W3 in the CT direction of each pixel of the sensors 3L and 3R shown in FIG. 9(c) is an integer of the pixel size W2 in the CT direction of the sensors 2L and 2R shown in FIG. Set to 1. The integer here is an integer greater than or equal to 2, for example 2.

Conversely, the pixel sizes H1 and W1 of the sensor 1C are set to an integral multiple of the pixel sizes H2 and W2 of the sensors 2L and 2R, and the pixel sizes H2 and W2 of the sensors 2L and 2R are set to the pixel size H3 of the sensors 3L and 3R. , W3 is an integer multiple. Preferably, the integer is 2 or more.

To generalize, the pixel size of the sensor placed on the center side in the CT direction (the sensor closer to the reference line 123) on the focal plane 122 among a pair of adjacent sensors in the CT direction is It is set as an integral multiple of the pixel size of the sensor on the outer side (the side far from the reference line 123). Preferably, the integer is 2 or more.
By using an integer multiple, it becomes easy to generate image data by connecting the image data output from a plurality of sensors arranged in the CT direction.

As described above, in addition to changing the size of each pixel, in this embodiment, as described later, the number of TDI stages and the number of integration stages in horizontal transfer are controlled depending on the imaging direction.
That is, the number of TDI stages and the number of horizontal integration stages in the sensors 3L, 2L, 2R, and 3R means that the area in the pixel array 30 corresponding to each signal charge obtained as a result of TDI and horizontal integration is the area of one pixel of the sensor 1C. is controlled to be close to .

Therefore, the number of TDI stages and the number of horizontal integration stages are configured to differ depending on the position within each pixel array of the sensors 3L, 2L, 2R, and 3R.
This point will be explained below with reference to FIGS. 10 to 15, FIGS. 16(a) to (d), and FIGS. 17(a) and (b).

FIG. 10 shows a pixel array 30, a vertical transfer section 40, and a TDI stage number setting circuit 70 in an example of a sensor 2L arranged to the left of a reference line 123 among the sensors shown in FIGS. 1 and 2. .

The pixel array 30 is divided into a plurality of, for example, first to fourth divided regions 30-1 to 30-4. The divided regions 30-1 to 30-4 are numbered in order from those located outside the pixel array 30.
Each of the divided regions 30-1 to 30-4 consists of a plurality of, for example, four, pixel columns.
In the illustrated example, the vertical transfer section 40 is composed of a four-phase drive CCD.

A plurality of sets, for example, first to fourth sets of metal wirings 70-1 to 70-4 extend in the vertical direction within the pixel array 30, and one end (upper end) thereof is connected to the TDI stage number setting circuit 70. It is connected to the.
Each of the first to fourth sets of metal wirings 70-1 to 70-4 includes a plurality of, for example, first to fourth metal wirings 71 to 74.

The first set of metal interconnects 70-1 includes metal interconnects 71 to 74 extending vertically within the first divided region 30-1. The second set of metal wires 70-2 includes metal wires 71 to 74 extending vertically within the second divided region 30-2. The third set of metal wires 70-3 includes metal wires 71 to 74 extending vertically within the third divided region 30-3. The fourth set of metal interconnects 70-4 includes metal interconnects 71 to 74 extending vertically within the fourth divided region 30-4.

Further, a plurality of sets, for example, first to fourth sets of vertical transfer electrodes 80-1 to 80-4 are provided to extend horizontally within the pixel array 30. Each of the first to fourth sets of vertical transfer electrodes 80-1 to 80-4 includes four vertical transfer electrodes 81 to 84.

The first set of vertical transfer electrodes 80-1 are connected to the first set of metal interconnections 70-1 via through holes 75, and are connected to the first divided region 30-1 and the second divided region 30-2. It is cut off at the border.
The second set of vertical transfer electrodes 80-2 are connected to the second set of metal interconnections 70-2 via the through holes 75, and are connected to the second divided region 30-2 and the third divided region 30-3. It is cut off at the border.

The third set of vertical transfer electrodes 80-3 are connected to the third set of metal interconnections 70-3 via the through holes 75, and are connected to the third divided region 30-3 and the fourth divided region 30-4. It is cut off at the border.
The fourth set of vertical transfer electrodes 80-4 is connected to the fourth set of metal wiring 70-4 via a through hole 75.

Note that the portions of the first set of vertical transfer electrodes 80-1 that extend within the second to fourth divided regions 30-2 to 30-4 are not used and may be omitted. Similarly, the portions of the second set of vertical transfer electrodes 80-2 that extend within the third and fourth divided regions 30-3 and 30-4 are not used and may be omitted. Similarly, the portion of the third set of vertical transfer electrodes 80-3 that extends within the fourth divided region 30-4 is not used and may be omitted.

Vertical transfer clocks φV1 to φV4 output from the TDI stage number setting circuit 70 are applied to the first set of vertical transfer electrodes 80-1 via the first set of metal interconnections 70-1.
Vertical transfer clocks φV1 to φV4 output from the TDI stage number setting circuit 70 are applied to the second set of vertical transfer electrodes 80-2 via the second set of metal interconnections 70-2.
Vertical transfer clocks φV1 to φV4 output from the TDI stage number setting circuit 70 are applied to the third set of vertical transfer electrodes 80-3 via the third set of metal interconnections 70-3.
Vertical transfer clocks φV1 to φV4 output from the TDI stage number setting circuit 70 are applied to the fourth set of vertical transfer electrodes 80-4 via the fourth set of metal interconnections 70-4.

In the first divided region 30-1, up to four stages of TDI are possible using the first to fourth sets of vertical transfer electrodes 80-1 to 80-4. In the second divided region 30-2, up to three stages of TDI are possible using the second to fourth sets of vertical transfer electrodes 80-2 to 80-4. In the third divided region 30-3, TDI of up to two stages is possible using the third and fourth sets of vertical transfer electrodes 80-3 and 80-4. Within the fourth divided region 30-4, only vertical transfer using the fourth set of vertical transfer electrodes 80-4, that is, "one stage" TDI can be performed.

TDI (time delay integration) operation can be realized by matching the transfer speed of the vertical transfer unit 40 with the moving speed of the subject image as the satellite advances.

In this way, the pixel array 30 is configured such that the maximum value of the number of TDI stages increases as it moves to the left (that is, as it moves away from the reference line 123).

The TDI stage number setting circuit 70 is capable of outputting the vertical transfer clocks φV1 to φV4 to all or only some of the first to fourth metal wirings 70-1 to 70-4. Which of the first to fourth sets of metal wirings 70-1 to 70-4 are to be outputted with the vertical transfer clocks φV1 to φV4 is determined according to the control signal Sv from the integration stage number control section 130. The number of TDI stages in each part of the pixel array 30 can be controlled depending on which of the first to fourth sets of metal wirings 70-1 to 70-4 the vertical transfer clocks φV1 to φV4 are outputted to.

In a state in which vertical transfer clocks φV1 to φV4 are output from the TDI stage number setting circuit 70 to all of the first to fourth sets of metal wirings 70-1 to 70-4, there are four stages in the first divided region 30-1. , three-stage TDI is performed in the second divided region 30-2, two-stage TDI is performed in the third divided region 30-3, and third-stage TDI is performed in the fourth divided region 30-4. One stage of TDI is performed within.

Vertical transfer clocks φV1 to φV4 are output from the TDI stage number setting circuit 70 to the second to fourth metal wirings 70-2 to 70-4, and vertical transfer clocks φV1 to φV4 are output to the first metal wiring 70-1. In the state where is not output, three stages of TDI are performed in the first and second divided regions 30-1 and 30-2, two stages of TDI are performed in the third divided region 30-3, One stage of TDI is performed within the fourth divided region 30-4.

Vertical transfer clocks φV1 to φV4 are output from the TDI stage number setting circuit 70 to the third and fourth sets of metal wirings 70-3 and 70-4, and are output to the first and second sets of metal wirings 70-1 and 70-2. When the vertical transfer clocks φV1 to φV4 are not output, two stages of TDI are performed in the first to third divided regions 30-1 to 30-3, and one stage TDI is performed in the fourth divided region 30-4. A stage TDI is performed.

Vertical transfer clocks φV1 to φV4 are output from the TDI stage number setting circuit 70 to the metal wiring 70-4 of the fourth set, and vertical transfer clocks φV1 to φV4 are output to the metal wiring 70-1 to 70-3 of the first to third sets. In the state where is not output, one stage of TDI is performed in all of the first to fourth divided regions 30-1 to 30-4.

Hereinafter, as described above, control is performed to change which of the first to fourth metal wirings 70-1 to 70-4 the vertical transfer clocks φV1 to φV4 are outputted to, in other words, the first to fourth metal wirings 70-1 to 70-4 are A function is provided to select the metal wiring that outputs the vertical transfer clocks φV1 to φV4 from among the fourth set of metal wirings 70-1 to 70-4, thereby changing the number of TDI stages in each part of the pixel array 30. An example of the configuration of the TDI stage number setting circuit 70 that can perform the following will be described with reference to FIG.

The TDI stage number setting circuit 70 shown in FIG. 11 includes a shift register 76 and a selection circuit 77. The selection circuit 77 includes first to sixteenth selection switches F1 to F16. The first to fourth selection switches F1 to F4 are provided corresponding to the metal wirings 71 to 74 of the first set of metal wirings 70-1, and the fifth to eighth selection switches F5 to F8 are The ninth to twelfth selection switches F9 to F12 are provided corresponding to the metal wirings 71 to 74 of the second set of metal wirings 70-2, and the ninth to twelfth selection switches F9 to F12 are provided corresponding to the metal wirings 71 to 74 of the third group of metal wirings 70-3. The thirteenth to sixteenth selection switches F13 to F16 are provided corresponding to the metal wires 71 to 74 of the fourth set of metal wires 70-4.

The control signal Sv is composed of clock pulses, and the received clock pulses are input to the shift register 76. Depending on the number Q of clock pulses received, the shift register 76 supplies a High signal to the first to Q-th selection switches counting from the right end in FIG. Supply a low signal to the switch.
For example, if the number of clock pulses is 8, a High signal is supplied to the selection switches F9 to F16, and a Low signal is supplied to the selection switches F1 to F8.

The selection switches F1 to F16 serve as gate circuits (not shown in FIG. 11) for the vertical transfer clocks φV1 to φV4, and when each of them is supplied with a high signal, they select the vertical transfer clocks. The vertical transfer clock is output to the corresponding metal wiring. Each selection switch is composed of, for example, an NMOS transistor, and a High or Low signal from the shift register 76 is supplied to the gate electrode. In FIG. 11, ON indicates that the vertical transfer clock can be output, and OFF indicates that the vertical transfer clock cannot be output.

As illustrated in FIG. 11, when a High signal is supplied to the selection switches F9 to F16, the vertical transfer clock is transmitted from the selection switches F9 to F12 to the metal wires 71 to 74 of the third set of metal wires 70-3. φV1 to φV4 are outputted, respectively, and vertical transfer clocks φV1 to φV4 are outputted from the selection switches F13 to F16 to the metal wires 71 to 74 of the fourth set of metal wires 70-4, respectively.

By combining the shift register 76 and the selection circuit 77 that operate as described above, it is possible to select the metal wiring that outputs the vertical transfer clocks φV1 to φV4, thereby changing the number of TDI stages in each part of the pixel array 30. .
By using such a function, for example, as the pointing angle of the imaging device 100 increases, the number of TDI stages in the portion of the pixel array 30 used for imaging can be increased. That is, the number of TDI steps can be changed depending on the pointing angle of the imaging device 100.

For example, when capturing an image directly below, four pulses are supplied as the control signal Sv from the integration stage number control unit 130, and a High signal is supplied only to the selection switches F13 to F16 in FIG. One stage of TDI is performed in all of the first to fourth divided regions 30-1 to 30-4. On the other hand, when imaging diagonally downward to the left, the number of pulses as the control signal Sv increases as the pointing angle of the imaging device 100 increases. As a result, the number of TDI stages in the first to third divided regions 30-1 to 30-3 is gradually increased.

Note that in the above example, each of the divided regions consists of four pixel columns, but the number of pixel columns constituting each divided region is not limited to four.

The sensor 3L is similarly configured. However, the sensor 3L has a smaller pixel size and a greater number of TDI stages than the sensor 2L. The number of divided regions may be the same as that of the sensor 2L, or may be larger.

FIG. 12 shows a pixel array 30, a vertical transfer unit 40, and a TDI stage number setting circuit 70 in an example of a sensor 2R arranged to the right of a reference line 123 among the sensors shown in FIGS. 1 and 2. .
The configuration shown in FIG. 12 is similar to the configuration shown in FIG. 10, but the left and right sides are reversed.

The pixel array 30 is divided into a plurality of, for example, first to fourth divided regions 30-1 to 30-4. The divided regions 30-1 to 30-4 are numbered in order from those located outside the pixel array 30.
Each of the divided regions 30-1 to 30-4 consists of a plurality of, for example, four, pixel columns.
In the illustrated example, the vertical transfer section is composed of a four-phase drive CCD.

A plurality of sets, for example, first to fourth sets of metal wirings 70-1 to 70-4 extend in the vertical direction within the pixel array 30, and one end (upper end) thereof is connected to the TDI stage number setting circuit 70. It is connected to the.
Each of the first to fourth sets of metal wirings 70-1 to 70-4 includes a plurality of, for example, first to fourth metal wirings 71 to 74.

The first set of metal interconnects 70-1 includes metal interconnects 71 to 74 extending vertically within the first divided region 30-1. The second set of metal wires 70-2 includes metal wires 71 to 74 extending vertically within the second divided region 30-2. The third set of metal wires 70-3 includes metal wires 71 to 74 extending vertically within the third divided region 30-3. The fourth set of metal interconnects 70-4 includes metal interconnects 71 to 74 extending vertically within the fourth divided region 30-4.

Further, a plurality of sets, for example, first to fourth sets of vertical transfer electrodes 80-1 to 80-4 are provided to extend horizontally within the pixel array 30. Each of the first to fourth sets of vertical transfer electrodes 80-1 to 80-4 includes four vertical transfer electrodes 81 to 84.

The first set of vertical transfer electrodes 80-1 are connected to the first set of metal interconnections 70-1 via through holes 75, and are connected to the first divided region 30-1 and the second divided region 30-2. It is cut off at the border.
The second set of vertical transfer electrodes 80-2 are connected to the second set of metal interconnections 70-2 via the through holes 75, and are connected to the second divided region 30-2 and the third divided region 30-3. It is cut off at the border.

The third set of vertical transfer electrodes 80-3 are connected to the third set of metal interconnections 70-3 via the through holes 75, and are connected to the third divided region 30-3 and the fourth divided region 30-4. It is cut off at the border.
The fourth set of vertical transfer electrodes 80-4 is connected to the fourth set of metal wiring 70-4 via a through hole 75.

Note that the portions of the first set of vertical transfer electrodes 80-1 that extend within the second to fourth divided regions 30-2 to 30-4 are not used and may be omitted. Similarly, the portions of the second set of vertical transfer electrodes 80-2 that extend within the third and fourth divided regions 30-3 and 30-4 are not used and may be omitted. Similarly, the portion of the third set of vertical transfer electrodes 80-3 that extends within the fourth divided region 30-4 is not used and may be omitted.

Vertical transfer clocks φV1 to φV4 output from the TDI stage number setting circuit 70 are applied to the first set of vertical transfer electrodes 80-1 via the first set of metal interconnections 70-1. Vertical transfer clocks φV1 to φV4 output from the TDI stage number setting circuit 70 are applied to the second set of vertical transfer electrodes 80-2 via the second set of metal interconnections 70-2. Vertical transfer clocks φV1 to φV4 output from the TDI stage number setting circuit 70 are applied to the third set of vertical transfer electrodes 80-3 via the third set of metal interconnections 70-3. Vertical transfer clocks φV1 to φV4 output from the TDI stage number setting circuit 70 are applied to the fourth set of vertical transfer electrodes 80-4 via the fourth set of metal interconnections 70-4.

In the first divided region 30-1, up to four stages of TDI are possible using the first to fourth sets of vertical transfer electrodes 80-1 to 80-4. In the second divided region 30-2, up to three stages of TDI are possible using the second to fourth sets of vertical transfer electrodes 80-2 to 80-4. In the third divided region 30-3, TDI of up to two stages is possible using the third and fourth sets of vertical transfer electrodes 80-3 and 80-4. Within the fourth divided region 30-4, only vertical transfer using the fourth set of vertical transfer electrodes 80-4, that is, "one stage" TDI can be performed.

TDI (time delay integration) operation can be realized by matching the transfer speed of the vertical transfer unit 40 with the moving speed of the subject image as the satellite advances.

In this way, the pixel array 30 is configured such that the maximum value of the number of TDI stages increases toward the right (that is, the farther from the reference line 123).

The TDI stage number setting circuit 70 is capable of outputting the vertical transfer clocks φV1 to φV4 to all or only some of the first to fourth metal wirings 70-1 to 70-4. Which of the first to fourth sets of metal wirings 70-1 to 70-4 are to be outputted with the vertical transfer clocks φV1 to φV4 is determined according to the control signal Sv from the integration stage number control unit 130. The number of TDI stages in each part of the pixel array 30 can be controlled depending on which of the first to fourth sets of metal wirings 70-1 to 70-4 the vertical transfer clocks φV1 to φV4 are outputted to.

In a state in which vertical transfer clocks φV1 to φV4 are output from the TDI stage number setting circuit 70 to all of the first to fourth sets of metal wirings 70-1 to 70-4, there are four stages in the first divided region 30-1. , three-stage TDI is performed in the second divided region 30-2, two-stage TDI is performed in the third divided region 30-3, and third-stage TDI is performed in the fourth divided region 30-4. One stage of TDI is performed within.

Vertical transfer clocks φV1 to φV4 are output from the TDI stage number setting circuit 70 to the second to fourth metal wirings 70-2 to 70-4, and vertical transfer clocks φV1 to φV4 are output to the first metal wiring 70-1. In the state where is not output, three stages of TDI are performed in the first and second divided regions 30-1 and 30-2, two stages of TDI are performed in the third divided region 30-3, One stage of TDI is performed within the fourth divided region 30-4.

Vertical transfer clocks φV1 to φV4 are output from the TDI stage number setting circuit 70 to the third and fourth sets of metal wirings 70-3 and 70-4, and are output to the first and second sets of metal wirings 70-1 and 70-2. When the vertical transfer clocks φV1 to φV4 are not output, two stages of TDI are performed in the first to third divided regions 30-1 to 30-3, and one stage TDI is performed in the fourth divided region 30-4. A stage TDI is performed.

Vertical transfer clocks φV1 to φV4 are output from the TDI stage number setting circuit 70 to the metal wiring 70-4 of the fourth set, and vertical transfer clocks φV1 to φV4 are output to the metal wiring 70-1 to 70-3 of the first to third sets. In the state where is not output, one stage of TDI is performed in all of the first to fourth divided regions 30-1 to 30-4.

Hereinafter, as described above, control is performed to change which of the first to fourth metal wirings 70-1 to 70-4 the vertical transfer clocks φV1 to φV4 are outputted to, in other words, the first to fourth metal wirings 70-1 to 70-4 are A function is provided to select the metal wiring that outputs the vertical transfer clocks φV1 to φV4 from among the fourth set of metal wirings 70-1 to 70-4, thereby changing the number of TDI stages in each part of the pixel array 30. An example of the configuration of the TDI stage number setting circuit 70 that can perform the following will be described with reference to FIG.

The TDI stage number setting circuit 70 shown in FIG. 13 includes a shift register 76 and a selection circuit 77. The selection circuit 77 includes first to sixteenth selection switches F1 to F16. The first to fourth selection switches F1 to F4 are provided corresponding to the metal wirings 71 to 74 of the first set of metal wirings 70-1, and the fifth to eighth selection switches F5 to F8 are The ninth to twelfth selection switches F9 to F12 are provided corresponding to the metal wirings 71 to 74 of the second set of metal wirings 70-2, and the ninth to twelfth selection switches F9 to F12 are provided corresponding to the metal wirings 71 to 74 of the third group of metal wirings 70-3. The thirteenth to sixteenth selection switches F13 to F16 are provided corresponding to the metal wires 71 to 74 of the fourth set of metal wires 70-4.

The control signal Sv is composed of clock pulses, and the received clock pulses are input to the shift register 76. Depending on the number Q of clock pulses received, the shift register 76 supplies a High signal to the first to Qth selection switches counting from the left end in FIG. Supply a low signal to the switch.
For example, if the number of clock pulses is 8, a High signal is supplied to the selection switches F9 to F16, and a Low signal is supplied to the selection switches F1 to F8.

The selection switches F1 to F16 serve as gate circuits for the vertical transfer clocks φV1 to φV4 (not shown in FIG. 13), and when each of them is supplied with a high signal, they select the vertical transfer clocks. The vertical transfer clock is output to the corresponding metal wiring. Each selection switch is composed of, for example, an NMOS transistor, and a High or Low signal from the shift register 76 is supplied to the gate electrode. In FIG. 13, ON indicates a state in which the vertical transfer clock can be output, and OFF indicates a state in which the vertical transfer clock cannot be output.

As illustrated in FIG. 13, when a High signal is supplied to the selection switches F9 to F16, the vertical transfer clock is transmitted from the selection switches F9 to F12 to the metal wires 71 to 74 of the third set of metal wires 70-3. φV1 to φV4 are outputted, respectively, and vertical transfer clocks φV1 to φV4 are outputted from the selection switches F13 to F16 to the metal wires 71 to 74 of the fourth set of metal wires 70-4, respectively.

By combining the shift register 76 and the selection circuit 77 that operate as described above, it is possible to select the metal wiring that outputs the vertical transfer clocks φV1 to φV4, thereby changing the number of TDI stages in each part of the pixel array 30. .
By using such a function, for example, as the pointing angle of the imaging device 100 increases, the number of TDI stages in the portion of the pixel array 30 used for imaging can be increased. That is, the number of TDI steps can be changed depending on the pointing angle of the imaging device 100.

For example, when imaging in the direct downward direction, four pulses are supplied as the control signal Sv from the integration stage number control unit 130, and a High signal is supplied only to the selection switches F13 to F16 in FIG. One stage of TDI is performed in all of the first to fourth divided regions 30-1 to 30-4. On the other hand, when capturing an image diagonally downward to the right, the number of pulses as the control signal Sv increases as the pointing angle of the imaging device 100 increases. As a result, the number of TDI stages in the first to third divided regions 30-1 to 30-3 is gradually increased.

Note that in the above example, each of the divided regions consists of four pixel columns, but the number of pixel columns constituting each divided region is not limited to four.

The sensor 3R is similarly configured. However, the sensor 3R has a smaller pixel size and a greater number of TDI stages than the sensor 2R. The number of divided regions may be the same as that of the sensor 2R, or may be larger.

FIG. 14 shows a pixel array 30, a vertical transfer section 40, and a TDI stage number setting circuit 70 in another example of the sensor 2L. The configuration of FIG. 14 can be used in place of the configuration of FIG. 10, and is generally the same as the configuration of FIG. However, the number of pixels constituting each pixel column of the pixel array is greater, and accordingly, more sets of vertical transfer electrodes are provided.
The following description focuses on the differences between the configuration of FIG. 14 and the configuration of FIG. 10.

N sets, ie, first to Nth sets of vertical transfer electrodes 80-1 to 80-N are provided to extend horizontally within the pixel array 30. Each of the first to Nth sets of vertical transfer electrodes 80-1 to 80-N includes four vertical transfer electrodes 81 to 84. N is an integer greater than the number of pixel columns. In the illustrated example, the number of pixel columns is four, so N is greater than four.

As in the case of FIG. 10, the first to third sets of vertical transfer electrodes 80-1 to 80-3 are connected to the first to third sets of metal wirings 70-1 to 70-3. The first set of vertical transfer electrodes 80-1 is cut at the boundary between the first divided region 30-1 and the second divided region 30-2. The second set of vertical transfer electrodes 80-2 is cut at the boundary between the second divided region 30-2 and the third divided region 30-3. The third set of vertical transfer electrodes 80-3 is cut at the boundary between the third divided region 30-3 and the fourth divided region 30-4.

The fourth to Nth sets of vertical transfer electrodes 80-4 to 80-N are connected to the fourth set of metal interconnections 70-4 via through holes 75.

As in the case of FIG. 10, the vertical transfer clocks φV1 to φV4 output from the TDI stage number setting circuit 70 are applied to the first set of vertical transfer electrodes 80-1 via the first set of metal interconnections 70-1. Vertical transfer clocks φV1 to φV4 output from the TDI stage number setting circuit 70 are applied to the second set of vertical transfer electrodes 80-2 via the second set of metal wiring 70-2, and Vertical transfer clocks φV1 to φV4 output from the TDI stage number setting circuit 70 are applied to the vertical transfer electrode 80-3 via the third set of metal interconnections 70-3.

Vertical transfer clocks φV1 to φV4 output from the TDI stage number setting circuit 70 are applied to the fourth to Nth sets of vertical transfer electrodes 80-4 to 80-N via the fourth set of metal interconnections 70-4. Ru.

In the first divided region 30-1, TDI of up to N stages is possible by the first to Nth sets of vertical transfer electrodes 80-1 to 80-N. In the second divided region 30-2, TDI up to N-1 stages is possible by the second to Nth sets of vertical transfer electrodes 80-2 to 80-N. In the third divided region 30-3, TDI of up to N-2 stages is possible by the third to Nth sets of vertical transfer electrodes 80-3 to 80-N. In the fourth divided region 30-4, TDI of up to N-3 stages is possible using the fourth to Nth sets of vertical transfer electrodes 80-4 to 80-N.

As in the example of FIG. 10, TDI (time delay integration) operation can be realized by matching the transfer speed of the vertical transfer unit 40 with the moving speed of the subject image as the satellite advances.

In this way, in the example of FIG. 14 as well, the pixel array 30 is configured such that the maximum value of the number of TDI stages increases as it moves to the left (that is, as it moves away from the reference line 123).
Further, TDI with a greater number of stages than the configuration of FIG. 10 is possible.

In the configuration of FIG. 14, the number of TDI stages can be changed by changing the number of sets of vertical transfer electrodes used for TDI in each pixel column. For example, when capturing an image directly below, the vertical transfer electrodes 80-1 to 80-N of the first to Nth sets shown in FIG. When performing vertical transfer only with the transfer electrodes 80-N and imaging the diagonally lower left side, as the pointing angle of the imaging device 100 increases, the number of sets of vertical transfer electrodes that perform vertical transfer increases upward. By doing so, the number of TDI stages in each pixel column can be increased as the pointing angle of the imaging device 100 increases. That is, the number of TDI steps can be changed depending on the pointing angle of the imaging device 100.
Note that in order to perform vertical transfer only in part of the vertical transfer electrodes 80-4 to 80-N of the fourth to Nth groups, vertical transfer clocks φV1 to φV4 are individually supplied to each group of vertical transfer electrodes. All you have to do is configure it so that you can do it. A detailed explanation of this point will be omitted.

Note that in the above example, each of the divided regions consists of four pixel columns, but as described in the example of FIG. 10, the number of pixel columns that constitute each divided region is not limited to four.

When the sensor 2L is configured as shown in FIG. 14, the sensor 3L may also be configured in the same manner. However, the sensor 3L has a smaller pixel size and a greater number of TDI stages than the sensor 2L. The number of divided regions may be the same as that of the sensor 2L, or may be larger.

FIG. 15 shows a pixel array 30, a vertical transfer section 40, and a TDI stage number setting circuit 70 in another example of the sensor 2R. The configuration of FIG. 15 can be used in place of the configuration of FIG. 12, and is generally the same as the configuration of FIG. However, the number of pixels constituting each pixel column of the pixel array is greater, and accordingly, more sets of vertical transfer electrodes are provided.
The following will mainly explain the differences between the configuration of FIG. 15 and the configuration of FIG. 12.
Note that, similarly to the configuration shown in FIG. 12, the configuration shown in FIG. 15 is similar to the configuration shown in FIG. 14, but the left and right sides are reversed.

N sets, ie, first to Nth sets of vertical transfer electrodes 80-1 to 80-N are provided to extend horizontally within the pixel array 30. Each of the first to Nth sets of vertical transfer electrodes 80-1 to 80-N includes four vertical transfer electrodes 81 to 84. N is an integer greater than the number of pixel columns. In the illustrated example, the number of pixel columns is four, so N is greater than four.

As in the case of FIG. 12, the first to third sets of vertical transfer electrodes 80-1 to 80-3 are connected to the first to third sets of metal wirings 70-1 to 70-3. The first set of vertical transfer electrodes 80-1 is cut at the boundary between the first divided region 30-1 and the second divided region 30-2. The second set of vertical transfer electrodes 80-2 is cut at the boundary between the second divided region 30-2 and the third divided region 30-3. The third set of vertical transfer electrodes 80-3 is cut at the boundary between the third divided region 30-3 and the fourth divided region 30-4.

The fourth to Nth sets of vertical transfer electrodes 80-4 to 80-N are connected to the fourth set of metal interconnections 70-4 via through holes 75.

As in the case of FIG. 12, vertical transfer clocks φV1 to φV4 output from the TDI stage number setting circuit 70 are applied to the first set of vertical transfer electrodes 80-1 via the first set of metal interconnections 70-1. Vertical transfer clocks φV1 to φV4 output from the TDI stage number setting circuit 70 are applied to the second set of vertical transfer electrodes 80-2 via the second set of metal wiring 70-2, and Vertical transfer clocks φV1 to φV4 output from the TDI stage number setting circuit 70 are applied to the vertical transfer electrode 80-3 via the third set of metal interconnections 70-3.

Vertical transfer clocks φV1 to φV4 output from the TDI stage number setting circuit 70 are applied to the fourth to Nth sets of vertical transfer electrodes 80-4 to 80-N via the fourth set of metal interconnections 70-4. Ru.

In the first divided region 30-1, TDI of up to N stages is possible by the first to Nth sets of vertical transfer electrodes 80-1 to 80-N. In the second divided region 30-2, TDI up to N-1 stages is possible by the second to Nth sets of vertical transfer electrodes 80-2 to 80-N. In the third divided region 30-3, TDI of up to N-2 stages is possible by the third to Nth sets of vertical transfer electrodes 80-3 to 80-N. In the fourth divided region 30-4, TDI of up to N-3 stages is possible using the fourth to Nth sets of vertical transfer electrodes 80-4 to 80-N.

Similar to the example of FIG. 12, TDI (time delay integration) operation can be realized by matching the transfer speed of the vertical transfer unit 40 with the moving speed of the subject image as the satellite advances.

In this way, in the example of FIG. 15 as well, the pixel array 30 is configured such that the maximum value of the number of TDI stages increases as it moves to the right (that is, as it moves away from the reference line 123).
Further, TDI with a larger number of stages than the configuration shown in FIG. 12 is possible.

In the configuration of FIG. 15, the number of TDI stages can be changed by changing the number of sets of vertical transfer electrodes used for TDI in each pixel column. For example, when capturing an image directly below, the vertical transfer electrodes 80-1 to 80-N of the first to Nth sets shown in FIG. When performing vertical transfer only with the transfer electrodes 80-N and imaging the diagonally lower right side, as the pointing angle of the imaging device 100 increases, the number of sets of vertical transfer electrodes that perform vertical transfer increases upward. By doing so, the number of TDI stages in each pixel column can be increased as the pointing angle of the imaging device 100 increases. That is, the number of TDI steps can be changed depending on the pointing angle of the imaging device 100.
Note that in order to perform vertical transfer only in part of the vertical transfer electrodes 80-4 to 80-N of the fourth to Nth groups, vertical transfer clocks φV1 to φV4 are individually supplied to each group of vertical transfer electrodes. All you have to do is configure it so that you can do it. A detailed explanation of this point will be omitted.

Note that in the above example, each divided area consists of four pixel columns, but as described in the example of FIG. 12, the number of pixel columns forming each divided area is not limited to four.

When the sensor 2R is configured as shown in FIG. 15, the sensor 3R may also be configured in the same manner. However, the sensor 3R has a smaller pixel size and a greater number of TDI stages than the sensor 2R. The number of divided regions may be the same as that of the sensor 2R, or may be larger.

16(a) to (d) and FIGS. 17(a) and (b) show signals used for horizontal transfer and readout processing in the sensor.

FIGS. 16A and 16B show a transfer clock φH for horizontal transfer and a reset pulse φR for reading in the sensor 1C when the imaging device 100 captures an image directly below.

The horizontal transfer of charges in the horizontal transfer section 50 is performed by the transfer clock φH shown in FIG. 16(a). That is, the signal charges held in each stage in the horizontal transfer unit 50 are transferred to the right in FIG. 3 by one stage in the horizontal transfer unit 50 every time the transfer clock φH is generated.

The charges transferred to the end (right end in FIG. 3) of the horizontal transfer section 50 are read out by the readout circuit 60. The readout circuit 60 includes an FD (Floating Diffusion) amplifier as described later, and is reset by a reset pulse φR. The number of integration stages in the horizontal direction can be controlled by the generation interval of the reset pulse φR (the period from when one reset pulse is generated until the next reset pulse is generated).

In the example shown in FIG. 16(b), the generation interval of the reset pulse φR is the same as the generation period of the transfer clock φH. Therefore, the signal charges are not integrated in the horizontal direction, and the signal charges transferred from each pixel column to the horizontal transfer section 50 are sequentially read out.

FIGS. 16C and 16D show a transfer clock φH for horizontal transfer and a reset pulse φR for reading in the sensor 3L when the imaging device 100 images the diagonally lower left direction.

The horizontal transfer of charges in the horizontal transfer section 50 is performed by the transfer clock φH shown in FIG. 16(c). That is, the signal charges held in each stage in the horizontal transfer unit 50 are transferred to the right in FIG. 3 by one stage in the horizontal transfer unit 50 every time the transfer clock φH is generated.

Corresponding to the fact that the pixels of the sensor 3L are smaller than the pixels of the sensor 1C, the period of the horizontal transfer clock is shorter than that of the horizontal transfer clock in FIG. 16(a). For example, the pixel size of the sensor 3L is 1/4 of the pixel size of the sensor 1C, and the period of the horizontal transfer clock φH in FIG. 16(c) is the period of the horizontal transfer clock φH in FIG. 16(a). It is 1/4.

The generation interval of the reset pulse φR applied to the readout circuit 60 is longer than the generation cycle of the horizontal transfer clock φH, and is not constant but changes during the horizontal transfer period.
Specifically, the closer to the end of the horizontal transfer period (that is, the more the signal charges generated in the left side of the pixel array 30 are read out), the longer the interval between reset pulses φR is generated. ing.
This is because when the imaging device 100 performs imaging diagonally downward to the left, it is taken into consideration that the imaging range becomes larger as the pixel is located further to the left within the sensor 3L.

In the example shown in FIGS. 16C and 16D, in the first section (first section) Ta of the horizontal transfer period, the reset pulse φR is generated when four pixels have been transferred. As a result, after integration for four pixels is performed, the pixels are read out as signal pixels.
In the next section (second section) Tb, a reset pulse φR is generated when five pixels have been transferred. As a result, after integration for five pixels is performed, the pixels are read out as signal pixels.

In the next section (third section) Tc, a reset pulse φR is generated when six pixels have been transferred. As a result, after integration for six pixels is performed, the pixels are read out as signal pixels.
In the next section (fourth section) Td, a reset pulse φR is generated when seven pixels have been transferred. As a result, after integration for seven pixels is performed, the pixels are read out as signal pixels.
In the next section (fifth section) Te, a reset pulse φR is generated when 8 pixels have been transferred. As a result, after integration for eight pixels is performed, the pixels are read out as signal pixels.

Similarly, as time passes during the horizontal transfer period, the interval between occurrences of the reset pulse φR becomes longer.
Therefore, the period in which the signal charge of a pixel closer to the left end of the sensor 3L is being read, the signal representing the charge generated in a wider area is output.

The process of changing the number of integration stages according to the pixel position takes into consideration that the corresponding imaging range changes depending on the pixel position, that is, the ratio of the imaging range to the pixel size changes. In other words, as the ratio of the imaging range to the pixel size increases, the number of integration stages increases, and the individual signals output from the readout circuit 60 increase in charge generated in a wider area within the pixel array 30 (the corresponding area The total sum of charges generated in the pixels within the pixel.
In this process, the number of integration stages in horizontal transfer is controlled so that the ratio of the imaging range to the pixel size approaches a constant value.

The number of integration stages in horizontal transfer has been described above, but the number of TDI stages is similarly controlled so that the ratio of the imaging range to the pixel size is nearly constant.

In the above example, the first section Ta, the second section Tb, the third section Tc, the fourth section Td, and the fifth section Te correspond to 4 cycles, 5 cycles, 6 cycles, and 6 cycles of the transfer clock, respectively. They have lengths of 7 cycles and 8 cycles, but these are integral multiples (M times: M is an integer of 2 or more) of the 4 cycles, 5 cycles, 6 cycles, 7 cycles, and 8 cycles of the transfer clock, respectively. , the generation interval of the reset pulse φR remains 4 times, 5 times, 6 times, 7 times, and 8 times the period of the transfer clock, so that the signal obtained by integration with the same number of integration stages is output M times. It's okay.

When the imaging device 100 captures an image diagonally downward to the left, the horizontal transfer and readout operations in the sensor 2L are similar to the operations in the sensor 3L.
However, since the pixel size of the sensor 2L is larger than the pixel size of the sensor 3L, the cycle of the horizontal transfer clock φH in the sensor 2L is longer than the cycle of the horizontal transfer clock φH in the sensor 3L. Furthermore, the magnification of the generation interval of the reset pulse φR with respect to the period of the horizontal transfer clock φH in the sensor 2L is smaller than that in the sensor 3L.
For example, the pixel size of the sensor 2L is twice the pixel size of the sensor 3L, the period of the horizontal transfer clock φH in the sensor 2L is twice the period of the horizontal transfer clock φH in the sensor 3L, and the horizontal transfer clock in the sensor 2L is The magnification of the generation interval of the reset pulse φR with respect to the period of the clock φH is 1/2 of that in the case of the sensor 3L.

FIGS. 17A and 17B show a transfer clock φH for horizontal transfer and a reset pulse φR for reading in the sensor 3R when the imaging device 100 images the diagonally lower left direction or directly below.

The horizontal transfer of charges in the horizontal transfer unit 50 is performed by the transfer clock φH of FIG. 17(a), which is similar to that of FIG. 16(c). That is, the signal charges held in each stage in the horizontal transfer unit 50 (signal charges transferred from each pixel column to the horizontal transfer unit 50) are transferred horizontally every time the transfer clock φH is generated. The image is transferred one stage within the unit 50, rightward in FIG.

Corresponding to the fact that the pixels of the sensor 3R are smaller than the pixels of the sensor 1C, the period of the horizontal transfer clock is shorter than that of the horizontal transfer clock in FIG. 16(a). For example, the pixel size of the sensor 3R is 1/4 of the pixel size of the sensor 1C, and the period of the horizontal transfer clock φH in FIG. 17(a) is 1/4 of the horizontal transfer clock φH in FIG. 16(a). It is 4.

The generation interval of the reset pulse φR applied to the readout circuit 60 is longer than the generation cycle of the horizontal transfer clock φH, and is constant during the horizontal transfer period and does not change. This is done because when the imaging device 100 images diagonally downward to the left, the difference in imaging range between pixels within the sensor 3R is small.
The generation interval of the reset pulse φR is fixed to, for example, four times the period of the transfer clock φH. This is because the pixel size of sensor 3R is 1/4 of the pixel size of sensor 1C, so by performing four stages of integration, the image capture range that is the same as (or close to) the pixels of sensor 1C can be obtained. This is to output a signal.

When the imaging device 100 images diagonally downward to the left or directly below, horizontal transfer and readout operations in the sensor 2R are similar to those of the sensor 3R.
However, since the pixel size of the sensor 2R is larger than the pixel size of the sensor 3R, the period of the horizontal transfer clock φH in the sensor 2R is longer than the period of the horizontal transfer clock φH in the sensor 3R. Further, the magnification of the generation interval of the reset pulse φR with respect to the period of the horizontal transfer clock φH in the sensor 2R is smaller than that in the sensor 3R.
For example, the pixel size of the sensor 2R is twice the pixel size of the sensor 3R, the period of the horizontal transfer clock φH in the sensor 2R is twice the period of the horizontal transfer clock φH in the sensor 3R, and the horizontal transfer clock in the sensor 2R is The magnification of the generation interval of the reset pulse φR with respect to the period of the clock φH is 1/2 of that in the case of the sensor 3R.

The horizontal transfer and readout operations in the sensors 3R and 2R when the imaging device 100 images the diagonally lower right direction are similar to the operations of the sensors 3L and 2L when the imaging device 100 images the diagonally lower left direction. . However, in the above explanation, it is necessary to interchange "left" and "right".
Furthermore, the generation interval of the reset pulse φR shown in FIGS. 16(d) and 17(b) needs to be gradually shortened instead of being gradually lengthened as time passes.

Whether or not the image is being captured diagonally downward to the left is determined based on whether the imaging direction of the imaging device 100 is tilted to the left and the (absolute value of) the pointing angle is larger than a predetermined value. .
Whether or not the image is being captured diagonally to the lower right is determined based on whether the imaging direction of the imaging device 100 is tilted to the right and the (absolute value of) the pointing angle is larger than a predetermined value. .
From the above, it can be said that the number of integration stages in the horizontal direction is determined based on the pointing angle of the imaging device 100.

The number of integration stages is also varied depending on where the signal read from the sensor represents the charge generated within the pixel array 30 of the sensor. Specifically, as shown in FIGS. 6(a) and 6(b), when imaging diagonally downward to the left, the sensor used for imaging the more left side is The number of integration stages is increased when a signal representing the charge generated in the pixel corresponding to the imaging range is output.

Generally speaking, the imaging device 100 is in a state where the imaging device 100 is in a state where it images a part of the ground surface that is farther away in the CT direction than the direct direction, and the pointing angle of the imaging device 100 is larger than a predetermined value. When the reference line 123 is large, among the plurality of sensors, a sensor located on the side corresponding to the side where the imaged portion is located with respect to the reference line 123 and located at a position away from the reference line 123, Control is performed so that the farther a pixel is located from the line 123, the greater the number of stages of integration in the horizontal transfer section for the charge generated in the pixel.
In order to enable such processing, the number of integration stages in the horizontal transfer section 50 of each of the sensors placed at a position away from the reference line 123 among the plurality of sensors can be changed during the horizontal transfer period. The imaging device 100 is configured as follows.

The operations of the horizontal transfer section 50 and the readout circuit 60 will be described below with reference to FIGS. 18(a) to 18(c) and FIGS. 19(a) to 19(c).

18(a) and 19(a) schematically show a part of the horizontal transfer section 50 and the readout circuit 60. The readout circuit 60 includes an FD (Floating Diffusion) section 62 and an FD amplifier 64.

FIGS. 18B and 18C and FIGS. 19B and 19C are diagrams showing the operations of the horizontal transfer section 50 and the readout circuit 60.
18(b) and 19(b) show the transition of the state of the potential well and the charge transfer, and FIG. 18(c) and FIG. 19(c) show the transfer clock φH1, which is applied to the transfer electrode. φH2 and the reset pulse φR applied to the readout circuit 60 are shown.
Here, the description will be made assuming that the transfer in the horizontal transfer section 50 is performed using a two-phase drive method.
In that case, as shown in FIGS. 18(c) and 19(c), a pair of transfer clocks φH1 and φH2 having opposite logical states is used. Among φH1 and φH2, φH1 corresponds to φH in FIG. 16(a).

First, the operation when no integration is performed will be described with reference to FIGS. 18(b) and 18(c).
First, at time t1, the potential of the FD section 62 is reset to the reference state by a reset pulse φR.
Next, at time t2, charge is transferred to the end of the horizontal transfer section, that is, to the potential well on the left side of the FD section 62 in FIG. 18(a).
Next, at time t3, the charges are transferred to the FD section 62.
At this time, the potential difference in the FD section 62 is detected by the FD amplifier 64, and a signal indicating the detected potential difference is output.
After t4, the operations from t1 to t3 are repeated.

Next, the operation when performing integration will be described with reference to FIGS. 19(b) and 19(c).
Here, as shown in FIGS. 19(b) and 19(c), it is assumed that the number of integration stages is three.

First, at time t1, the potential of the FD section 62 is reset to the reference state by a reset pulse φR.
Next, at time t2, charge is transferred to the end of the horizontal transfer section, that is, to the potential well on the left of the FD section 62 in FIG. 19(a).
Next, at time t3, the charges are transferred to the FD section 62.
At this time, since the FD amplifier 64 does not detect the potential difference, the reset operation using the reset pulse φR is not performed.

Next, at time t4, the next charge is transferred to the end of the horizontal transfer section, that is, to the potential well to the left of the FD section 62 in FIG. 19(a).
Furthermore, the charge is transferred to the FD section 62 at time t5.
At this time as well, since the FD amplifier 64 does not detect the potential difference, the reset operation using the reset pulse φR is not performed.

Next, at time t6, the next charge is transferred to the potential well on the left side of the FD section 62.
Furthermore, the charge is transferred to the FD section 62 at time t7.
At this time, charges for three stages are accumulated in the potential well of the FD section 62 in the horizontal transfer section 50.
At this time, the potential difference in the FD section 62 is detected by the FD amplifier 64, and a signal indicating the detected potential difference is output.
The output signal represents the result of three stages of horizontal integration.
After time t8, the operations from t1 to t7 are repeated.

The case where the number of integration stages in the horizontal direction is three, as shown in FIGS. 19(b) and 19(c), has been described above.
However, the number of integration stages is not limited to three, and may be two or four or more.
Furthermore, as described with reference to FIGS. 16(d) and 17(b), the values may vary depending on the pointing angle and the position of the pixel in the sensor (the position of the pixel where the charge to be read is generated).

The method for controlling the number of integration stages in horizontal transfer based on the pointing angle of the imaging device 100 has been described above.
As described above, it is also possible to control the number of TDI stages based on the pointing angle. For example, each divided region within each of the sensors 3L, 2L, 2R, and 3R is determined depending on whether the imaging device 100 is imaging directly below, diagonally downward to the left, or diagonally downward to the right. It is also possible to change the number of TDI stages in .
Control in that case can be performed by the TDI stage number setting circuit 70.

Next, the positional relationship in the CT direction and the positional relationship in the AT direction of the plurality of sensors that constitute the focal plane detector 120 will be explained.
When a plurality of sensors are arranged in a staggered manner as shown in FIG. 2, adjacent sensors are not aligned in either the CT direction or the AT direction.

FIG. 20 shows the positional relationship of sensors 3L, 2L, and 1C among the sensors shown in FIG.
As described above, the imaging data of a plurality of sensors arranged at different positions in the CT direction are connected in the order of pixel positions in the CT direction, thereby generating a series of imaging data.
At this time, images of the same part of the ground surface are captured by pixels of different sizes at the ends of adjacent sensors in the CT direction that are close to each other.
Furthermore, in order to prevent image data from being lost, adjacent sensors are arranged so that their adjacent ends overlap in the AT direction.

In such a case, in order to simplify the above-mentioned connection process, the overlap amount (U12 or U23) of the ends of the adjacent pair of sensors that are close to each other must be the same as the pixel of one of the pair of sensors. The horizontal pixel pitch of the sensor located on the center side (closer to the reference line 123) on the focal plane 122 is preferably an integral multiple of the pitch (horizontal pixel pitch). It is particularly desirable to make it an integral multiple of .
Here, the pixel pitch in the horizontal direction is assumed to be equal to the pixel size in the horizontal direction, and is expressed by the same symbol as the pixel size in the horizontal direction.

Specifically, as shown in FIGS. 2 and 20, the upper end of the sensor 2L is the lower end of the sensor 1C (a sensor located closer to the center on the focal plane 122 than the sensor 2L and adjacent to the sensor 2L). The right end of the pixel array 30 of the sensor 2L is located to the right (center side) of the left end of the pixel array 30 of the sensor 1C, and as a result, the ends overlap with each other.
The amount of overlap U12 is preferably an integral multiple of the horizontal pixel pitch W2 or W1 of either sensor 2L or 1C, and preferably an integral multiple of the horizontal pixel pitch W1 of sensor 1C (the sensor located on the center side). Even more desirable.

Similarly, the lower end of the sensor 3L is located above the upper end of the sensor 2L (a sensor located on the center side of the sensor 3L and adjacent to the sensor 3L), and the right end of the pixel array 30 of the sensor 3L is located above the upper end of the sensor 2L. They are located to the right (center side) of the left end of the pixel array 30, and as a result, their ends overlap with each other.
The amount of overlap U23 is preferably an integral multiple of the horizontal pixel pitch W3 or W2 of either sensor 3L or 2L, and preferably an integral multiple of the horizontal pixel pitch W2 of sensor 2L (the sensor located on the center side). Even more desirable.

Regarding the overlap in the AT direction, the same thing applies to the positional relationship between the sensor 1C and the sensor 2R as the positional relationship between the sensor 1C and the sensor 2L, and the same thing applies to the positional relationship between the sensor 2R and the sensor 3R. The same thing applies to the positional relationship with 3L.
However, in the above explanation, it is necessary to interchange "left" and "right".

Furthermore, in the staggered arrangement, sensors adjacent in the CT direction are shifted in the AT direction.
Therefore, when a flying object moves relative to the ground surface, there is a time difference between the times when adjacent sensors image the same position on the ground surface in the CT direction, which corresponds to the position of the adjacent sensors in the AT direction. .

In order to facilitate correction processing that takes this time difference into consideration when connecting imaging data from adjacent sensors, the deviation in the AT direction of a pair of adjacent sensors is determined by the vertical pixel pitch (vertical direction) of either sensor. It is desirable that the distance be an integral multiple of the vertical pixel pitch (pixel pitch), and more preferably an integral multiple of the vertical pixel pitch (vertical pixel pitch) of the sensor located outside in the CT direction (on the side closer to the reference line 123).
Here, the pixel pitch in the vertical direction is assumed to be equal to the pixel size in the vertical direction, and is expressed by the same symbol as the pixel size in the vertical direction.

Here, the deviation in the AT direction between a pair of adjacent sensors refers to the distance from the lowest row of the pixel array 30 of one sensor to the lowest row of the pixel array 30 of the other sensor. means.

Specifically, it is desirable that the deviation S12 between the sensor 2L and the sensor 1C in the AT direction is an integral multiple of the vertical pixel pitch H2 or H1 of either the sensor 2L or 1C; It is more desirable that the pitch be an integral multiple of the vertical pixel pitch H1 of the sensor.
Similarly, the deviation S23 in the AT direction between the sensor 3L and the sensor 2L is preferably an integral multiple of the vertical pixel pitch H3 or H2 of either the sensor 3L or 2L, and the sensor 2L (the sensor located at the center) More preferably, the vertical pixel pitch H2 is an integral multiple of the vertical pixel pitch H2.

Regarding the deviation in the AT direction, the same applies to the positional relationship between the sensor 2R and the sensor 1C as the positional relationship between the sensor 2L and the sensor 1C, and the same applies to the positional relationship between the sensor 3R and the sensor 2R. The same thing applies to the positional relationship with 2L.

According to the first embodiment, a sharp image can be obtained for all pixels regardless of their position in the CT direction within the sensor.
Furthermore, since the sensors are arranged in a staggered manner, the size of the focal plane detector in the AT direction can be made relatively small.

Embodiment 2.
FIG. 21 is a layout diagram showing a configuration example of a focal plane detector used in the imaging device 100 of the second embodiment. The illustrated focal plane detector 120b is generally the same as the focal plane detector 120 of FIG. 2, but differs in the placement of sensors 3L, 2L, 1C, 2R, and 3R.

Specifically, in the focal plane detector 120 of FIG. 2, the sensors 3L, 2L, 1C, 2R, and 3R are staggered on the focal plane 122, but in the focal plane detector 120b of FIG. On the surface 122, the sensors 3L, 2L, 1C, 2R, and 3R are arranged along a straight line (diagonal straight line) extending from the upper left to the lower right. More specifically, the sensor 1C is arranged such that the horizontal center of its pixel array 30 is located on the reference line 123, and the sensor 1C is arranged to the left and right along the above-mentioned diagonal straight line with the sensor 1C as the center. They are placed one by one.

In addition, also in FIG. 21, the AT direction is a direction from bottom to top, and the CT direction is a direction from left to right.

FIG. 22 shows the positional relationship of sensors 3L, 2L, and 1C among the sensors shown in FIG. 21.

As shown in FIGS. 21 and 22, the lower end of the sensor 2L is located above the upper end of the sensor 1C (a sensor located on the center side of the sensor 2L and adjacent to the sensor 2L), and its pixel array The right end of pixel array 30 is located to the right of the left end of pixel array 30 of sensor 1C, and as a result, the ends overlap each other.
The amount of overlap U12 is preferably an integral multiple of the horizontal pixel pitch W2 or W1 of either sensor 2L or 1C, and preferably an integral multiple of the horizontal pixel pitch W1 of sensor 1C (the sensor located on the center side). Even more desirable.

Similarly, the lower end of the sensor 3L is located above the upper end of the sensor 2L (a sensor located on the center side of the sensor 3L and adjacent to the sensor 3L), and the right end of the pixel array 30 is the pixel of the sensor 2L. They are located to the right of the left end of the array 30, so that the ends overlap each other.
The amount of overlap U23 is preferably an integral multiple of the horizontal pixel pitch W3 or W2 of either sensor 3L or 2L, and preferably an integral multiple of the horizontal pixel pitch W2 of sensor 2L (the sensor located on the center side). desirable.

Regarding the overlap in the AT direction, the same thing applies to the positional relationship between the sensor 1C and the sensor 2R as the positional relationship between the sensor 1C and the sensor 2L, and the same thing applies to the positional relationship between the sensor 2R and the sensor 3R. The same thing applies to the positional relationship with 3L.
However, in the above explanation, it is necessary to interchange "left" and "right" and also interchange "upper" and "lower".

In short, similarly to Embodiment 1, the ends of a pair of adjacent sensors that are close to each other overlap, and the amount of overlap is preferably equal to the horizontal pixel pitch of one of the pair of sensors, and the center side More preferably, it is an integral multiple of the horizontal pixel pitch of the sensor located at .

As described above, the imaging data of the plurality of sensors are connected in the CT direction, but the above arrangement simplifies the above-mentioned connection process.

Next, the deviation in the AT direction will be explained. As described in connection with the first embodiment, the deviation in the AT direction between adjacent sensors is defined as the deviation from the lowest row of the pixel array 30 of one sensor to the lowest row of the pixel array 30 of the other sensor. Means the distance to the line.

As shown in FIG. 22, the deviation S12 in the AT direction between the sensor 2L and the sensor 1C is preferably an integral multiple of the vertical pixel pitch H2 or H1 of either the sensor 2L or 1C; It is more desirable that the vertical pixel pitch H1 be an integral multiple of the vertical pixel pitch H1 of the sensor located at .
Similarly, the deviation S23 in the AT direction between the sensor 3L and the sensor 2L is preferably an integral multiple of the vertical pixel pitch H3 or H2 of either the sensor 3L or 2L, and the sensor 2L (the sensor located at the center) More preferably, the vertical pixel pitch H2 is an integral multiple of the vertical pixel pitch H2.

Regarding the deviation in the AT direction, the same applies to the positional relationship between the sensor 2R and the sensor 1C as the positional relationship between the sensor 2L and the sensor 1C, and the same applies to the positional relationship between the sensor 3R and the sensor 2R. The same thing applies to the positional relationship with 2L.

In short, as in Embodiment 1, it is desirable that the deviation in the AT direction between adjacent sensors is an integral multiple of the vertical pixel pitch of either of the adjacent sensors, and the vertical deviation of the sensor located closer to the center is More preferably, it is an integral multiple of the pixel pitch.

The above arrangement simplifies the process of linking sensor imaging data, and improves the continuity of a series of imaging data obtained by linking.
In other words, even in the case of the diagonal arrangement described with reference to FIGS. 21 and 22, when the flying object moves relative to the ground surface (as in Embodiment 1), adjacent sensors are located on the ground surface. There is a time difference between times when the same position in the CT direction is imaged, corresponding to the positions of adjacent sensors in the AT direction. Although the imaging data of the plurality of sensors are connected in the CT direction, the above arrangement facilitates correction processing for the difference in imaging time between the sensors. Therefore, the process of linking becomes simple, and the continuity of a series of imaging data obtained by linking is improved.

In the above example, five sensors are provided, but the number of sensors is not limited to five. In short, it is sufficient if the sensor 1C is placed in the center, and the same number of sensors are placed on the left and right along the diagonal line.

Furthermore, in the above example, the plurality of sensors are arranged along a straight line extending from the upper left to the lower right with sensor 1C as the center, but conversely, the plurality of sensors are arranged along the straight line extending from the upper right to the lower left. It may be placed.

According to the second embodiment, a sharp image can be obtained for all pixels regardless of their position in the CT direction within the sensor.

Embodiment 3.
FIG. 23 is a layout diagram showing a configuration example of a focal plane detector used in the imaging device 100 of the third embodiment. The illustrated focal plane detector 120c is generally the same as the focal plane detector 120 of FIG. 2, except for the placement of sensors 3L, 2L, 1C, 2R, and 3R.

Specifically, in the focal plane detector 120 of FIG. 2, the sensors 3L, 2L, 1C, 2R, and 3R are staggered on the focal plane 122, but in the focal plane detector 120c of FIG. On the surface 122, the sensors 3L, 2L, 1C, 2R, and 3R are arranged in a V-shape.

That is, the sensor 1C is arranged at the position of the reference line 123, that is, at the center, the sensors 2L and 3L are arranged along a straight line passing through the center and rising to the left, and the sensors 2R and 3R are arranged along a straight line passing through the center and rising to the right. is placed along the straight line.

Note that also in FIG. 23, the AT direction is a direction from bottom to top, and the CT direction is a direction from left to right.

The positional relationship of the sensors shown in FIG. 23 is the same as that described with reference to FIG. 22 regarding the second embodiment.

As shown in FIGS. 23 and 22, the lower end of the sensor 2L is located above the upper end of the sensor 1C (a sensor located on the center side of the sensor 2L and adjacent to the sensor 2L), and its pixel array The right end of pixel array 30 is located to the right of the left end of pixel array 30 of sensor 1C, and as a result, the ends overlap each other.
The amount of overlap U12 is preferably an integral multiple of the horizontal pixel pitch W2 or W1 of either sensor 2L or 1C, and preferably an integral multiple of the horizontal pixel pitch W1 of sensor 1C (the sensor located on the center side). Even more desirable.

Similarly, the lower end of the sensor 3L is located above the upper end of the sensor 2L (a sensor located on the center side of the sensor 3L and adjacent to the sensor 3L), and the right end of the pixel array 30 is the pixel of the sensor 2L. They are located to the right of the left end of the array 30, so that the ends overlap each other.
The amount of overlap U23 is preferably an integral multiple of the horizontal pixel pitch W3 or W2 of either sensor 3L or 2L, and preferably an integral multiple of the horizontal pixel pitch W2 of sensor 2L (the sensor located on the center side). Even more desirable.

Regarding the overlap in the AT direction, the same thing applies to the positional relationship between the sensor 1C and the sensor 2R as the positional relationship between the sensor 1C and the sensor 2L, and the same thing applies to the positional relationship between the sensor 2R and the sensor 3R. The same thing applies to the positional relationship with 3L.
However, in the above explanation, it is necessary to interchange "left" and "right".

In short, as in Embodiments 1 and 2, the ends of a pair of adjacent sensors that are close to each other overlap, and the amount of overlap is preferably the horizontal pixel pitch of one of the pair of sensors, More preferably, the pitch is an integral multiple of the horizontal pixel pitch of the sensor located at the center.

As described above, the imaging data of the plurality of sensors are connected in the CT direction, but the above arrangement simplifies the above-mentioned connection process.

Next, the deviation in the AT direction will be explained. As described in connection with the first embodiment, the deviation in the AT direction between adjacent sensors is defined as the deviation from the lowest row of the pixel array 30 of one sensor to the lowest row of the pixel array 30 of the other sensor. Means the distance to the line.

As shown in FIG. 22, the deviation S12 in the AT direction between the sensor 2L and the sensor 1C is preferably an integral multiple of the vertical pixel pitch H2 or H1 of either the sensor 2L or 1C; It is more preferable that the vertical pixel pitch H1 is an integral multiple of the vertical pixel pitch H1 of the sensor located at .
Similarly, the deviation S23 in the AT direction between the sensor 3L and the sensor 2L is preferably an integral multiple of the vertical pixel pitch H3 or H2 of either the sensor 3L or 2L, and the sensor 2L (the sensor located at the center) More preferably, the vertical pixel pitch H2 is an integral multiple of the vertical pixel pitch H2.

Regarding the deviation in the AT direction, the same applies to the positional relationship between the sensor 2R and the sensor 1C as the positional relationship between the sensor 2L and the sensor 1C, and the same applies to the positional relationship between the sensor 3R and the sensor 2R. The same thing applies to the positional relationship with 2L.

In short, as in Embodiments 1 and 2, it is desirable that the deviation in the AT direction between a pair of adjacent sensors be an integral multiple of the vertical pixel pitch of either of the pair of sensors, and More preferably, it is an integral multiple of the vertical pixel pitch of the adjacent sensor.

The above arrangement simplifies the process of linking sensor imaging data, and improves the continuity of a series of imaging data obtained by linking.
That is, even in the case of the V-shaped arrangement described with reference to FIGS. 23 and 22, when the flying object moves relative to the ground surface (as in Embodiments 1 and 2), adjacent sensors There is a time difference between the times at which images are taken of the same position on the ground surface in the CT direction, which corresponds to the positions of adjacent sensors in the AT direction. Although the imaging data of the plurality of sensors are connected in the CT direction, the above arrangement facilitates correction processing for the difference in imaging time between the sensors. Therefore, the process of linking becomes simple, and the continuity of a series of imaging data obtained by linking is improved.

In the above example, five sensors are provided, but the number of sensors is not limited to five. In short, it is sufficient if the sensor 1C is placed in the center and the same number of sensors are placed on the left and right in a V-shape.

Further, in the above example, the plurality of sensors are arranged in a V-shape with the sensor 1C at the center, but they may be arranged in an inverted V-shape. That is, the configuration may include sensors arranged along a straight line extending to the lower left and sensors arranged along a straight line extending to the lower right with the sensor 1C as the center.

According to the third embodiment, a sharp image can be obtained for all pixels regardless of their position in the CT direction within the sensor.

Pp pixel, 1C, 2L, 3L, 2R, 3R image sensor, 30 pixel array, 40 vertical transfer section, 50 horizontal transfer section, 60 readout circuit, 70 TDI stage number setting circuit, 70-1 to 70-4, 71 to 74 metal wiring, 75 through hole, 80 drive signal generation circuit, 80-1 to 80-4, 81 to 84 vertical transfer electrode, 100 imaging device, 110 optical system, 120 focal plane detector, 122 focal plane, 123 reference line, 130 integral stage number control unit, 140 attitude detection unit, 150 transmission/reception processing unit, 160 attitude control unit, 200 ground station.

Claims (17)

An imaging device that includes a plurality of TDI image sensors and captures images while moving in an AT direction with respect to the ground surface,
The plurality of image sensors are arranged at mutually different positions in the CT direction on the focal plane of the imaging device,
Each of the image sensors includes a plurality of pixels arranged in a plurality of pixel columns, each pixel generates a charge by photoelectric conversion, and the generated charge is vertically transferred in accordance with the speed of the movement. The pixel array includes a transfer electrode that performs time-delay integration, and a horizontal transfer section that horizontally transfers the time-delay integrated charge.
The farther the image sensor is placed from the reference line extending in the AT direction on the focal plane, the smaller the size of the pixel,
When the imaging device is in a state of imaging a part of the ground surface that is farther away in one of the CT directions than the direction directly below, and the pointing angle of the imaging device is larger than a predetermined value;
Of the plurality of image sensors, the image sensor is located on a side corresponding to the side where the imaged portion is located with respect to the reference line, and is arranged at a position away from the reference line, The imaging device is controlled such that the farther a pixel is located from the reference line, the greater the number of stages of the time delay integration for the charge generated in the pixel. The imaging device according to claim 1, wherein the reference line is a straight line that includes the center of the focal plane in the CT direction. Of the plurality of image sensors, each of the image sensors arranged at a position away from the reference line each comprises a part of the pixel array, and each image sensor comprises two or more pixel arrays each comprising one or more continuous pixel columns. It has a divided area,
The imaging device according to claim 1 or 2, wherein the number of stages of the time delay integration differs between the divided regions. Of the plurality of image sensors, the number of integration stages in the horizontal transfer section of each of the image sensors arranged at a position away from the reference line can be changed during the horizontal transfer period,
When the imaging device is in a state of imaging a part of the ground surface that is farther away from the direct direction in one of the CT directions, and the pointing angle is larger than a predetermined value,
Of the plurality of image sensors, the image sensor is located on a side corresponding to the side where the imaged portion is located with respect to the reference line, and is arranged at a position away from the reference line, The imaging device according to any one of claims 1 to 3, wherein control is performed such that the farther a pixel is located from the reference line, the greater the number of stages of integration in the horizontal transfer unit for the charge generated in the pixel. . The imaging device according to claim 4, wherein the number of integration stages is changed by changing the generation interval of a reset pulse used to read out the charges horizontally transferred by the horizontal transfer section. Of a pair of image sensors adjacent to each other in the CT direction, the pixel size of the image sensor closer to the reference line is an integral multiple of the pixel size of the image sensor farther from the reference line, and the integer is 2 or more. The imaging device according to any one of claims 1 to 5. A pair of image sensors adjacent to each other in the CT direction among the plurality of image sensors are arranged such that their pixel arrays overlap in the AT direction,
The imaging device according to any one of claims 1 to 6, wherein the amount of overlap of the pixel arrays is an integral multiple of the horizontal pixel pitch of either of the pair of image sensors. The imaging device according to claim 7, wherein the amount of overlap is an integral multiple of the horizontal pixel pitch of the image sensor closer to the reference line of the pair of image sensors. The deviation in the AT direction between a pair of image sensors adjacent in the CT direction among the plurality of image sensors is an integral multiple of the vertical pixel pitch of one of the pair of image sensors. 8. The imaging device according to any one of 8. The imaging device according to claim 9, wherein the deviation is an integral multiple of the vertical pixel pitch of the image sensor closer to the reference line of the pair of image sensors. The imaging device according to any one of claims 1 to 10, wherein the plurality of image sensors are arranged in a staggered manner on the focal plane. The imaging device according to any one of claims 1 to 10, wherein the plurality of image sensors are arranged in a V-shape or an inverted V-shape on the focal plane. The imaging device according to claim 11 or 12, wherein the plurality of image sensors are arranged mirror-symmetrically about a reference plane that includes the reference line and is perpendicular to the CT direction. The plurality of image sensors are arranged on the focal plane along a straight line extending from the upper left to the lower right or a straight line extending from the upper right to the lower left when the focal plane is viewed from the ground surface side. The imaging device according to any one of claims 1 to 10. The imaging device according to any one of claims 1 to 14, further comprising an integration stage number control unit that determines an image readout method in the image sensor according to the pointing angle. The imaging device according to claim 15, wherein determining the image readout method includes at least one of determining the number of stages of time delay integration and determining the number of stages of integration in the horizontal transfer section. The imaging device according to claim 15 or 16, wherein the pointing angle is changed according to a control signal supplied by remote control.

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