JP7375701B2 - Bidirectional isolated DC/DC converter and its control method - Google Patents

Description

The present invention relates to a DC power supply device (bidirectional isolated DC/DC converter) that performs bidirectional power transmission while insulating input and output, and in particular, technology for suppressing the DC component of transformer current during initial drive. Regarding.

The Dual Active Bridge method, which is one method of a bidirectional isolated DC/DC converter, is disclosed in Non-Patent Documents 1 and 2. The Dual Active Bridge system is composed of two full-bridge inverters (a half-bridge may be used), a high-frequency transformer, and an inductor (or only the leakage inductance of the transformer may be used). Each inverter output is a square wave voltage, and the transmitted power is controlled by the phase difference.

Tatsuya Yamagishi, Yasufumi Akagi, Shinichi Kinouchi, Yuji Miyazaki, Masato Koyama "750V, 100kW, 20kHz bidirectional isolated DC/DC converter using SiC-MOSFET/SBD module", IEEJ Transactions D, Vol. 134, No. 5, pp. 544-553 (2014) Kazuto Takagi, Hideaki Fujita "Improvement of transient characteristics of isolated DC-DC converter using dual active bridge" IEEJ Transactions D, Vol. 136, No. 9, p. 622-628 (2016)

In the Dual Active Bridge system, the current flowing through the high frequency transformer and inductor is ideally only an alternating current component. However, in the initial drive, the current flowing through the high frequency transformer or inductor does not become a complete alternating current due to the initial value of the phase difference and the timing of gate enable, and a direct current component is superimposed. The generation of these DC components may reduce efficiency or cause magnetic saturation of the high-frequency transformer, causing inrush current to flow and damaging equipment.

As a countermeasure against these problems, there is a method of suppressing DC superposition by sampling the positive and negative sides of the transformer current and making the sum zero. This method is effective in reducing DC superposition that occurs regularly. However, this method requires expensive hardware to accurately measure high frequencies in order to suppress DC superimposition that occurs transiently.

Furthermore, Non-Patent Document 2 discloses a method for suppressing transient DC superposition that occurs when a phase difference command value changes sharply. This is a method that divides the update timing of the phase difference command value for each arm. However, no consideration has been given to a method for reducing DC superposition during initial drive.

In view of the above, it is an issue to suppress the direct current component during initial drive in a bidirectional isolated DC/DC converter without requiring additional hardware.

The present invention has been devised in view of the above-mentioned conventional problems, and one aspect thereof includes: a first inverter connected to a first DC power supply; a second inverter connected to a second DC power supply; A bidirectional isolated DC/DC converter comprising: a transformer having a primary winding connected to the AC side of the first inverter and a secondary winding connected to the AC side of the second inverter; A phase difference command switching unit outputs a phase difference command by switching between φ* and zero, and outputs zero as the phase difference command when the device is stopped; * A ramp-up unit that gradually increases the phase difference command and outputs it as a corrected phase difference command; a compared wave generation unit that generates a compared wave based on the corrected phase difference command and the rectangular wave; A PWM control unit generates a gate signal based on comparison with a comparison wave, and a gate enable signal is set to zero when the device is stopped, and the device starts initial drive and the carrier signal is set to a peak or a valley. a gate enable signal generation unit that sets and holds the gate enable signal at 1 level when the gate enable signal becomes 1 level; and a gate enable signal generator that outputs the gate signal to the first and second inverters when the gate enable signal is at 1 level; The present invention is characterized by comprising a gate signal output section that does not output the gate signal to the first and second inverters when the signal is at 0 level.

In one aspect, the phase difference command switching section outputs φ* as the phase difference command when the gate enable signal is at 1 level, and outputs φ* as the phase difference command when the gate enable signal is at 0 level. It is characterized by outputting zero as .

Further, as one aspect thereof, the phase difference command switching unit maintains the phase difference command at φ* when the gate enable signal is at 1 level and the carrier signal reaches a peak or a valley peak. The phase difference command is set to zero and held at the time when the gate enable signal is at 0 level and the carrier signal reaches a peak or a valley.

According to the present invention, in a bidirectional isolated DC/DC converter, it is possible to suppress a DC component during initial drive without requiring additional hardware.

FIG. 3 is a circuit configuration diagram of a bidirectional isolated DC/DC converter in Embodiments 1 to 3. FIG. FIG. 2 is a block diagram showing a control unit in a conventional technique. FIG. 3 is a block diagram showing a control unit in Embodiment 1. FIG. 5 is a time chart showing each waveform in the first embodiment. FIG. 3 is a block diagram showing a control unit in Embodiment 2. FIG. 5 is a time chart showing each waveform in Embodiment 2. FIG. 3 is a block diagram showing a control unit in Embodiment 3. 5 is a time chart showing each waveform in Embodiment 3. A time chart showing operation waveforms in the conventional technology. 5 is a time chart showing operation waveforms in the first embodiment. 5 is a time chart showing operation waveforms in Embodiment 2. 5 is a time chart showing operation waveforms in Embodiment 2. 7 is a time chart showing operation waveforms in Embodiment 3.

Embodiments 1 to 3 of the bidirectional isolated DC/DC converter according to the present invention will be described in detail below with reference to FIGS. 1 to 13.

[Embodiment 1]
FIG. 1 shows the main circuit configuration of a dual active bridge bidirectional isolated DC/DC converter to which the control method of the first embodiment is applied.

As shown in FIG. 1, first and second semiconductor switching elements 1a and 1b are connected in series between the positive and negative ends of the first direct current voltage DC1. Furthermore, third and fourth semiconductor switching elements 1c and 1d are connected in series between the positive and negative ends of the first DC voltage DC1. The first to fourth semiconductor switching elements 1a to 1d constitute a first inverter.

A connection point between the first and second semiconductor switching elements 1a and 1b is connected to one end of the primary winding of the transformer Tr via the first inductor L1. A connection point between the third and fourth semiconductor switching elements 1c and 1d is connected to the other end of the primary winding of the transformer Tr. That is, the primary winding of the transformer Tr is connected to the AC side of the first inverter.

Fifth and sixth semiconductor switching elements 2a and 2b are connected in series between the positive and negative ends of the second direct current voltage DC2. Furthermore, seventh and eighth semiconductor switching elements 2c and 2d are connected in series between the positive and negative ends of the second direct current voltage DC2. The fifth to eighth semiconductor switching elements 2a to 2d constitute a second inverter.

A connection point between the fifth and sixth semiconductor switching elements 2a and 2b is connected to one end of the secondary winding of the transformer Tr via the second inductor L2. A connection point between the seventh and eighth semiconductor switching elements 2c and 2d is connected to the other end of the secondary winding of the transformer Tr. That is, the secondary winding of the transformer Tr is connected to the AC side of the second inverter.

Note that the first and second inductors L1 and L2 may be omitted and only the leakage inductance of the transformer Tr may be used. Furthermore, the first and second inverters may be half-bridge inverters as well as full-bridge inverters.

FIG. 2 shows a control block diagram of the conventional method. The phase difference command φ* is a value output from power control, voltage control, or current control. The carrier generation unit 3 generates a carrier signal and a rectangular wave by up/down counting.

The compared wave generating section 20 includes a gain multiplier 1, a limiter 2, multipliers 4a and 4b, and a multiplier 5. The compared wave generation unit 20 generates a compared wave based on the phase difference command φ* and the rectangular wave.

The gain multiplier 1 multiplies the phase difference command φ* by a gain to calculate an output α. Here, the gain is set to 1/π. Limiter 2 limits the output α to a range of -0.5 to 0.5.

Multipliers 4a and 4b multiply the output of limiter 2 by a rectangular wave to generate a comparison wave. Note that the input of the multiplier 4b on one side is multiplied by -1 by the multiplier 5 so that the compared waves of each inverter have a phase difference of 180°. The output of the multiplier 4a is assumed to be a compared wave β, and the output of the multiplier 4b is assumed to be a compared wave γ.

The PWM control section 21 includes comparators 6a to 6d, NOT elements 7a to 7d, and dead time generation sections 8a to 8h. The PWM control unit 21 generates a gate signal based on a comparison between the carrier signal and the compared wave.

Specifically, the comparators 6a to 6d compare the carrier signal and the compared waves β and γ. NOT elements 7a to 7d invert the outputs of comparators 6a to 6d to generate inverted signals in the upper and lower arms. Dead time generators 8a to 8h add dead time to the outputs of comparators 6a to 6d and NOT elements 7a to 7d.

AND elements (gate signal output sections) 9a to 9h calculate the AND of the outputs of the dead time generation sections 8a to 8h and the drive start signal. The outputs of the AND elements 9a to 9h are outputted as gate signals to the first to eighth semiconductor switching elements 1a to 1d, 2a to 2d. When the drive start signal is 0, all semiconductor switching elements are in the OFF state.

FIG. 3 shows a block diagram of the control section in the first embodiment. The first embodiment is characterized by the setting of the phase difference command at the time of initial driving and the method of synchronizing the gate signal output timing. The control unit of the first embodiment has the following configuration added to the control unit of the conventional technology.

A selector (phase difference command switching section) 10 switches and outputs φ* and zero as a phase difference command. The selector 10 outputs zero when the device is stopped, and outputs the phase difference command φ* when the initial drive signal is input.

When the input phase difference command switches from zero to φ*, the moving average unit (ramp up unit) 11 performs a moving average process on the phase difference command at a preset time, and gradually changes the output from zero to φ*. The phase difference command is increased and outputted as a corrected phase difference command.

The carrier generation unit 3 outputs a carrier signal, a rectangular wave, and a trigger signal. The rectangular wave is a signal that becomes -1 when counting up the carrier signal and becomes 1 when counting down. The trigger signal is a signal that becomes High at the timing of the peak and valley peaks of the carrier signal. The compared wave generation unit 20 of the first embodiment generates a compared wave based on the corrected phase difference command and the rectangular wave.

The D flip-flop (gate enable signal generation unit) 12 receives an initial drive signal and a trigger signal, and outputs a gate enable signal flg. When the device is stopped, the gate enable signal is set to 0 level, and when the device starts initial driving and reaches the peak or valley peak of the carrier signal, the gate enable signal is set to 1 level and held. That is, the timing of the level change of the gate enable signal flg is synchronized with the timing of the peak or valley peak of the carrier signal.

In the first embodiment, output of the phase difference command φ* is started at the same timing as the initial drive signal. Furthermore, when the initial drive signal becomes 1 level and the carrier signal reaches the peak or valley peak, output of the gate signal is started. During driving, the Dual Active Bridge is driven so as to always achieve the desired phase difference.

In addition to general voltage control and current control, the phase difference command φ* may be obtained using the following equation (1) for transmission power shown in Non-Patent Document 1.

However, P is the transmission power, E ₁ is the first DC voltage, E ₂ is the second DC voltage, N is the transformer turns ratio, ω is the switching angular frequency, and φ is the phase difference between each inverter output voltage (the phase difference range is - π/2≦φ≦π/2), and L is the sum of the leakage inductance of the inductor and transformer equivalently converted to the primary side.

Thereafter, the output of the moving average section 11 is multiplied by 1/π so that the compared waves β and γ have the amplitude of the carrier signal. Note that by multiplying this value by the rectangular wave, the amplitude of the rectangular wave becomes the phase command value.

In the first embodiment, the D flip-flop 12 is used to synchronize the timing of the gate enable signal with the peak or valley peak of the carrier signal. In order to suppress DC superposition of the excitation current, the timing when the excitation current becomes zero is synchronized with the gate enable signal.

In the Dual Active Bridge method, the output voltage of each inverter is a square wave, so the exciting current is a triangular wave. Therefore, when the rising timing of the square wave is set to θ=0 rad, the excitation current i _Lm can be calculated using the following equation (2).

However, f _sw is the switching frequency, and L _m is the excitation inductance. From equation (2), the phases at which the excitation current i _Lm becomes zero are θ=π/2, 3π/2. This is the midpoint of the positive or negative voltage period of the square wave voltage. Furthermore, the midpoint of the positive period of the square wave voltage is synchronized with the trough and peak of the carrier signal, and the midpoint of the negative period is synchronized with the peak of the carrier signal. Therefore, in the first embodiment, as shown in FIG. 4, the gate enable signal flg is synchronized with the peak or valley peak of the carrier signal.

Furthermore, when the phase difference command φ* changes abruptly, DC superposition occurs in the transformer and inductor currents. Therefore, as shown in Fig. 4, by ramping up the phase difference command from zero to the desired φ*, a steep change in the phase difference command φ* (corrected phase difference command) can be suppressed, and the DC current of the inductor current can be reduced. Superimposition can be reduced.

As described above, according to the first embodiment, it is possible to suppress the DC component of the excitation current flowing through the high frequency transformer during Dual Active Bridge driving. In addition, magnetic saturation of the transformer can be prevented, the cross-sectional area of the transformer core can be reduced and the size can be reduced, and inrush current generation and equipment damage can be suppressed.

[Embodiment 2]
FIG. 5 shows a block diagram of the control section in the second embodiment. In the second embodiment, the output signal of the selector (phase difference command switching unit) 10 is changed using the gate enable signal flg instead of the initial drive signal.

In the first embodiment, as the switching frequency becomes lower, the deviation between the initial drive signal and the gate enable signal flg increases as shown in FIG. A DC component is superimposed on the current.

In the second embodiment, the timing at which the phase difference command is changed from 0 to φ* is synchronized with the gate enable signal flg. That is, when the gate enable signal is at 1 level, φ* is output as the phase difference command, and when the gate enable signal is at 0 level, 0 is output as the phase difference command.

As a result, the gate signal output and the ramp-up start of the phase difference command φ* are synchronized, and it is possible to suppress DC superposition of the excitation current and the inductor current when driving the Dual Active Bridge.

According to the second embodiment, the DC component of the inductor current can be suppressed by synchronizing the change in the phase difference command φ* with the timing of the gate signal output. Copper loss in transformers and inductors, and conduction loss in dual active bridge systems can be reduced. Particularly when the switching frequency is low, the effect of suppressing the DC component is large.

[Embodiment 3]
FIG. 7 shows a block diagram of the control section in the third embodiment. In the third embodiment, a D flip-flop 13 is added between the selector 10 and the moving average section 11 with respect to the control section in the second embodiment. The D flip-flop 13 outputs and holds the phase difference command as φ* when the phase difference command is φ* (the gate enable signal is at 1 level) and the carrier signal reaches the peak or valley peak. . Further, the D flip-flop 13 outputs and holds the phase difference command as 0 when the phase difference command is 0 (the gate enable signal is at 0 level) and the carrier signal reaches the peak or valley peak. . In the third embodiment, the selector 10 and the D flip-flop 13 constitute a phase difference command switching section.

As shown in FIG. 6 of the second embodiment, when the period of the moving average section 11 is short, the magnitude relationship (phase difference command value) between the carrier signal and the compared wave changes immediately after updating the phase difference command, so that the semiconductor switching There is a possibility that the difference between the on period and off period of the element (the difference between Toff_2 and Ton_2 in FIG. 6) becomes large. This difference causes the DC component of the inverter output voltage, leading to an increase in the DC component of the high frequency transformer and inductor current.

In the third embodiment, the D flip-flop 13 synchronizes the timing of updating the phase difference command with the peak and valley peaks of the carrier signal.

According to the third embodiment, as shown in FIG. 8, immediately after the phase difference command is updated (the maximum value of the compared wave is half the peak value of the carrier signal), the current value of the carrier signal is the same as that of the compared wave. , and the amount of change in the on period becomes smaller. Therefore, the DC component of the inductor current can be suppressed.

According to the third embodiment, even under conditions where the period of the moving average is shorter than the switching period, it is possible to suppress the DC component that occurs when changing the phase difference command. Furthermore, the response speed of the Dual Active Bridge can be increased and the performance can be improved.

FIG. 9 shows operating waveforms of the conventional method during initial drive. The timing at which the inverter output voltage is generated, the timing at which the phase difference command is updated, and the timing at which the gate signal is output are not synchronized with the peak or valley peaks of the carrier signal, and DC components are superimposed on the excitation current and inductor current. There is.

FIG. 10 shows operational waveforms of the first embodiment during driving. The timing of ramping up the phase difference command φ* and outputting the gate signal is synchronized with the peak or valley peak of the carrier signal, suppressing the DC component of the excitation current. However, since the timing of changing the gate enable signal and the phase difference command are asynchronous, the average value of the inductor current is not zero, and a DC component is superimposed on the inductor current.

FIGS. 11 and 12 show operational waveforms of the second embodiment during driving. 11 shows a waveform in which the period of the moving average section 11 is twice the switching period, and FIG. 12 shows a waveform in which the period of the moving average section 11 is 0.5 times the switching period. In FIG. 11, the DC superposition of the inductor current is reduced compared to FIG. 10. However, as shown in FIG. 12, when the period of the moving average section 11 becomes short (specifically, one time or less than the switching period), the DC component of the inductor current increases.

FIG. 13 shows operational waveforms of the third embodiment during driving. By synchronizing the update timing of the phase difference command φ* with the peak or valley peak of the carrier signal, the DC component of the inductor current is suppressed even under conditions where the period of the moving average section 11 is short.

Although only the specific examples described in the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and modifications can be made within the scope of the technical idea of the present invention. Naturally, such variations and modifications fall within the scope of the claims.

1... Gain multiplier 2... Limiter 3... Carrier generator 4a, 4b, 5... Multiplier 6a-6d... Comparator 7a-7d... NOT element 8a-8h... Dead time generator 9a-9h... AND element (gate signal output section)
10...Selector (phase difference command switching section)
11...Moving average part (ramp up part)
12...D flip-flop (gate enable signal generation section)
13...D flip-flop 20...Comparison wave generation section 21...PWM control section DC1, DC2...First and second DC voltages 1a to 1d, 2a to 2d...First to eighth semiconductor switching elements

Claims (4)

a first inverter connected to a first DC power supply;
a second inverter connected to a second DC power supply;
A bidirectional isolated DC/DC converter comprising: a transformer having a primary winding connected to the AC side of the first inverter and a secondary winding connected to the AC side of the second inverter,
a phase difference command switching unit that switches and outputs φ* and zero as a phase difference command, and outputs zero as the phase difference command when the device is stopped;
a ramp-up unit that gradually increases the phase difference command from zero to φ* when the phase difference command is switched from zero to φ* and outputs it as a corrected phase difference command;
a compared wave generation unit that generates a compared wave based on the corrected phase difference command and the rectangular wave;
a PWM control unit that generates a gate signal based on a comparison between the carrier signal and the compared wave;
Gate enable signal generation that sets the gate enable signal to zero when the device is stopped, and sets and holds the gate enable signal at 1 level when the device starts initial driving and the carrier signal reaches the peak or valley peak. Department and
A gate that outputs the gate signal to the first and second inverters when the gate enable signal is at 1 level, and does not output the gate signal to the first and second inverters when the gate enable signal is at 0 level. a signal output section;
A bidirectional isolated DC/DC converter characterized by comprising: The phase difference command switching section is
2. The phase difference command according to claim 1, wherein when the gate enable signal is at 1 level, φ* is output as the phase difference command, and when the gate enable signal is at 0 level, zero is output as the phase difference command. Bidirectional isolated DC/DC converter. The phase difference command switching section is
When the gate enable signal is at 1 level and the carrier signal reaches the peak or valley peak, the phase difference command is set to φ* and held;
2. The bidirectional isolated DC according to claim 1, wherein the phase difference command is set to zero and held at the time when the gate enable signal is at 0 level and the carrier signal reaches a peak or a valley peak. /DC converter. a first inverter connected to a first DC power supply;
a second inverter connected to a second DC power supply;
A method for controlling a bidirectional isolated DC/DC converter, comprising: a transformer having a primary winding connected to the AC side of the first inverter and a secondary winding connected to the AC side of the second inverter. There it is,
A phase difference command switching unit outputs a phase difference command by switching between φ* and zero, and outputs zero as the phase difference command when the device is stopped;
When the phase difference command is switched from zero to φ*, the ramp up section gradually increases it from zero to φ* and outputs it as a corrected phase difference command;
a compared wave generation unit generates a compared wave based on the corrected phase difference command and the rectangular wave,
a PWM control unit generates a gate signal based on a comparison between the carrier signal and the compared wave;
The gate enable signal generation section sets the gate enable signal to zero when the device is stopped, and sets the gate enable signal to one level when the device starts initial driving and the carrier signal reaches the peak or valley peak. and hold
A gate signal output section outputs the gate signal to the first and second inverters when the gate enable signal is at 1 level, and outputs the gate signal to the first and second inverters when the gate enable signal is at 0 level. 2. A control method for a bidirectional isolated DC/DC converter characterized by not outputting to two inverters.

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