JP7376385B2 - Motor decoding circuit - Google Patents

Description

The present invention relates to a motor decoding circuit used for data transmission in a motor drive device.

BACKGROUND ART In a motor drive device that drives a motor of a machine tool or the like, data (for example, current data) for monitoring or controlling the state of the motor may be encoded and transmitted. For example, data is transmitted between a current detection circuit and a control circuit within a motor drive device. The motor current data is Manchester encoded on the current detection circuit side and transmitted to the control circuit side. By doing so, the reliability of data transmission between circuits is improved. Furthermore, since the Manchester code includes both data and clock information, the number of wires can be reduced compared to the case where data and clock are transmitted using separate wires.

However, a motor drive device has a lot of noise, and even if it is encoded, the data may be distorted. The current detection circuit is often placed near the main switching element and is susceptible to switching noise. Due to this noise, errors may occur when decoding the transmitted signal.

Japanese Patent Application Publication No. 11-088446

SUMMARY OF THE INVENTION An object of the present invention is to provide a motor decoding circuit with improved resistance to noise.

A motor decoding circuit according to one aspect includes a receiving unit that receives a motor signal including a Manchester encoded signal representing a bit value by level transition within a bit interval, and a clock signal and a clock signal from the motor signal. a decoding unit that reproduces a bit string; a transition extraction unit that extracts a plurality of level transitions from the motor signal; and a time difference between the extracted plurality of level transitions that matches the length of the bit section within an error range. and a determining unit that determines that at least one of the plurality of level transitions is noise if they do not match. The transition extraction unit refers to the decoded bit string and extracts a plurality of level transitions, excluding level transitions at boundaries of the bit sections where bits of the same value are continuous.

According to the present invention, it is possible to provide a motor decoding circuit with improved resistance to noise.

FIG. 1 is a schematic diagram showing a motor drive device according to an embodiment. FIG. 2 is a block diagram showing the internal configuration of a data processing section. 5 is a timing chart showing signals processed by the current detection section. 3 is a timing chart showing signals processed by a data processing section.

Hereinafter, a motor drive device according to an embodiment will be described in detail with reference to the drawings.

FIG. 1 is a schematic diagram showing a motor drive device 10 according to an embodiment. The motor drive device 10 drives the motor 20 and includes an inverter section 11, a current detection section 12 (current detector 13, A/D converter 14, Manchester encoding section 15), a data processing section 16, and a current control section. 17, it has an input section 18.

The inverter section 11 includes, for example, a switching element and its drive circuit, and generates a drive current I that drives the motor 20.

The current detector 12 detects the drive current I and transmits the encoded current signal CD1, and includes a current detector 13, an A/D converter 14, and a Manchester encoder 15.

The current detector 13 is a sensor that detects the drive current I, and outputs an analog signal corresponding to the drive current I.

The A/D converter 14 converts the analog signal from the current detector 13 into a digital signal and generates a pre-encoded current signal CD0. This A/D converter 14 and Manchester encoding section 15 operate with a predetermined clock CL0.

The Manchester encoding unit 15 performs Manchester encoding on the pre-encoded current signal CD0 from the A/D converter 14 to generate an encoded current signal CD1. Encoded current signal CD1 includes a Manchester encoded signal.

The data processing unit 16 decodes the encoded current signal CD1 and generates a decoded current signal CD3. Note that the details will be described later.

Current control unit 17 outputs a switching command to inverter unit 11 based on an external command and decoded current signal CD3. That is, the current control unit 17 controls the motor 20 based on the data of the drive current I detected by the current detector 13.

The input unit 18 inputs information for controlling the data processing unit 16, as described later.

FIG. 2 is a block diagram showing the internal configuration of the data processing section 16. The data processing unit 16 includes a reference clock 21 , a decoding unit 24 , a digital filter 25 , a transition extraction unit 26 , and a determination unit 27 .

The reference clock 21 generates a clock signal CL1 that serves as a reference for processing in the data processing section 16. The frequency of this clock signal CL1 can be, for example, several times to several tens of times the frequency of the clock signal CL0 of the current detection section 12.

The decoding unit 24 generates a clock signal CL2 and a bit string (decoded current signal CD2) based on the encoded current signal CD1 received from the Manchester encoding unit 15 (decoding clock and data). The clock signal CL2 corresponds to the clock signal CL0 of the current detection section 12, and the bit string corresponds to the pre-encoded current signal CD0.

The digital filter 25 is, for example, a Sinc3 filter, and filters the bit string (bit stream) for a predetermined period to remove high frequency fluctuations, and outputs it as, for example, a 16-bit decoded current signal CD3.

The transition extraction unit 26 extracts a plurality of level transitions from the encoded current signal CD1. The determination unit 27 determines whether or not the level transition includes noise based on the time difference Tx between the plurality of extracted level transitions. Note that these details will be described later.

Hereinafter, prior to a detailed explanation of the transition extraction section 26 and the determination section 27, the signals processed by the current detection section 12 and the data processing section 16 will be explained.

FIG. 3 is a timing chart showing signals processed by the current detection section 12. The bits 0 and 1 of the pre-encoded current signal CD0 change corresponding to each bit period Tb0 of the clock signal CL0. Encoded current signal CD1 is generated from pre-encoded current signal CD0.

Since the encoded current signal CD1 is a Manchester code, there is a signal level transition (intermediate transition Sm) in the middle of the bit period Tb. That is, the Manchester code represents the value of a bit by an intermediate transition Sm located in the middle of the bit interval Tb. For example, an intermediate transition Sm from L to H represents a "1" bit, and an intermediate transition Sm from H to L represents a "0" bit. However, conversely, "0" may be represented by the intermediate transition Sm from L to H, and "1" may be represented by the intermediate transition Sm from H to L.

Here, the intermediate transition Sm corresponds to the rising edge of the clock signal CL0. On the other hand, the phase of the clock signal CL0 may be shifted by 180 degrees (H and L are reversed) so that the intermediate transition Sm corresponds to the falling edge of the clock signal CL0.

In addition to the intermediate transition Sm, the Manchester code includes a boundary transition Sp located at the boundary of the bit interval Tb. This boundary transition Sp inevitably occurs when bits of the same value are consecutive. In Manchester codes, bit values are represented by level transitions. Therefore, if bits of the same value (level transitions in the same direction, for example, level transitions from L to H) continue, it is necessary to insert transitions in the opposite direction (for example, level transitions from H to L) between them. . In the Manchester code, this so-called secondary level transition is performed at the boundary between bit sections.

FIG. 4 is a timing chart showing signals processed by the data processing section 16. A clock signal CL1 of the reference clock 21, an encoded current signal CD1 transmitted from the current detection section 12, a clock signal CL2 generated by the decoding section 24, and a decoded current signal CD2 are shown. For reference, the clock signal CL0 used to generate the encoded current signal CD1 is also shown.

Since the bit interval Tb0 of the clock signal CL0 is known in design, the length of the bit interval Tb2 of the generated clock signal CL2 is set to be equal to the bit interval Tb0. However, there is a phase difference between the bit section Tb2 and the bit section Tb0. That is, intermediate transitions Sm0 and Sm1 included in encoded current signal CD1 are located in the middle of bit interval Tb0 of clock signal CL0, but not in the middle of bit interval Tb2 of clock signal CL2.

This shift occurs due to the convenience of signal processing. That is, here, intermediate transitions Sm0 and Sm1 are used to define the starting point of bit section Tb2. Furthermore, a time lag occurs due to processing in the decoding unit 24 and the like. That is, the intermediate transitions Sm0 and Sm1 are arranged closer to the boundary of the bit interval Tb2 with respect to the clock signal CL2.

The fact that the intermediate transitions Sm0 and Sm1 are deviated from the clock signal CL2, etc. in this way does not cause any problem in the processing in the decoding section 24 and the digital filter 25. That is, if the timing (phase) of the generated clock signal CL2 and decoded current signal CD2 match, digital processing is possible.

However, as will be described later, this timing shift may pose a problem in the transition extraction section 26. However, since this timing deviation is a predetermined value determined by the processing content of the decoding unit 24, it is sufficient to process the timing by taking this into consideration.

The above description assumes that the encoded current signal CD1 does not include noise. However, it is possible that the encoded current signal CD1 contains noise and that the intermediate transitions Sm0, Sm1 are actually noise rather than intermediate transitions. In this case, errors occur in the reproduced clock signal CL2 and the decoded bit string. For example, if the starting point of the bit section Tb2 of the reproduced clock signal CL2 is incorrect, the bit string to be decoded may contain continuous errors.

The details of the transition extracting section 26 and the determining section 27 will be explained below. As described above, the transition extractor 26 extracts level transitions from the encoded current signal CD1. The process at this time is A. Initial processing, B. Continuation processing can be divided into two stages.

A. Initial Processing First, initial processing is performed to determine the starting point and ending point of the bit section Tb2. That is, under the following conditions 1 and 2, a plurality of level transitions (intermediate transitions Sm as described later) are extracted.

Condition 1) A plurality of level transitions correspond to consecutive different bit values (for example, "0, 1" or "1, 0") (in other words, a plurality of level transitions do not include a boundary transition Sp) ).
Condition 2) The level transition time difference Tx matches the bit interval Tb0 within an error range.

A level transition that satisfies conditions 1 and 2 is considered to be an intermediate transition Sm. Even if Conditions 1 and 2 are used, it cannot be denied that the extracted level transition may include something caused by noise or the like, but this possibility is generally small. As will be described later, if this possibility cannot be denied, it is preferable to redo the initial processing (initialization).

The details of the processing corresponding to conditions 1 and 2 will be described below. Although it is possible to perform the processing for conditions 1 and 2 together, here, for the sake of clarity, the processing contents will be explained in the order of condition 1 and condition 2.

(1) Processing corresponding to condition 1 In the initial processing, the transition extraction unit 26 extracts a plurality of level transitions and determines whether these level transitions include a boundary transition Sp. If the plurality of level transitions include the boundary transition Sp, for example, the plurality of level transitions are extracted again and it is determined again whether the plurality of level transitions include the boundary transition Sp. In this way, the transition extraction unit 26 can extract a plurality of level transitions that do not include the boundary transition Sp.

By referring to the decoded bit string output from the decoding unit 24, it can be determined whether or not the boundary transition Sp is included. That is, it is determined whether the extracted level transition corresponds to a boundary transition Sp where bits of the same value continue.

As described above, the level transitions such as the intermediate transition Sm have a timing lag with respect to the clock signal CL2 and the decoded current signal CD2. However, since this is determined by the processing content, the determination can be made taking into account the timing difference.

Note that by transmitting from the current detection unit 12 a Manchester encoded signal in which bits of the same value do not continue, that is, a Manchester encoded signal representing repetition of 0 and 1, the boundary transition Sp in the transition extraction unit 26 is transmitted. Exclusion processing can be omitted.

(2) Processing corresponding to condition 2 After processing corresponding to condition 1, the following processing is performed. That is, the determination unit 27 determines whether the time difference Tx between the extracted level transitions matches the bit interval Tb0 within the error range, and if they do not match, at least one of the level transitions is noise. It is determined that

As described above, the interval between the original intermediate transitions Sm matches the bit interval Tb0 (furthermore, the bit interval Tb2). Therefore, if the time difference Tx of the extracted level transitions does not match the bit interval Tb0, it can be determined that at least one of the extracted level transitions is noise.

However, there may be jitter in the clocks CL0 and CL1 and variation in clock frequency due to individual differences. Therefore, in consideration of such an error, it is determined whether the time difference Tx and the bit interval Tb match.

For example, it is assumed that the clock signal CL0 of the current detection unit 12 is 10.7 MHz±5%, and the clock signal CL1 of the reference clock 21 is 131.072 MHz±130 ppm. In this case, the clock signal CL0 is 10.165 to 11.235 MHz, the clock signal CL1 is 131.0549 to 131.0891 MHz, and the clock ratio (=CL0/CL1) is 12.28±0.61 clock. . A mismatch between the time difference Tx and the bit interval Tb that exceeds this range is considered to be caused by noise. Note that reference values and error ranges can be input and set from the input unit 18 to the determination unit 27.

If this determination is made based on the clock signal CL1, it is difficult to determine the time difference Tx within one clock of the clock signal CL1. That is, the determination is performed using ±1 clock instead of ±0.61 clock. Here, by increasing the frequency of the clock signal CL1, the period of one clock can be shortened and time accuracy can be improved.

As described above, a plurality of level transitions (intermediate transitions Sm0, Sm1) that satisfy Conditions 1 and 2 are extracted, and the starting point and ending point of the bit section Tb2 are determined based on the timing of the transition.

B. Continuation Processing After the initial processing, the processing of the transition extraction unit 26 and the determination unit 27 continues. That is, the transition extraction unit 26 extracts one level transition (one or more is possible) that is not the boundary transition Sp. As described above, since the intermediate transitions Sm0 and Sm1 are extracted in the initial processing, it is sufficient to extract only one level transition.

The determination unit 27 determines whether the time difference Tx between the newly extracted level transition and the previously extracted intermediate transition Sm matches the length of the bit section Tb0 within an error range. However, without determining the time difference Tx itself, it may be determined whether the timing of the newly extracted level transition matches the start point and end point of the bit section Tb2 within the error range. Note that immediately after the initial processing, "previously extracted intermediate transition Sm" is the intermediate transition at the time of the initial processing. Furthermore, when level transitions are extracted continuously, the intermediate transition Sm extracted this time is treated as the "previously extracted intermediate transition Sm" next time.

If the time difference Tx does not match the length of the bit section Tb0 within the error range, the transition extraction unit 26 is instructed to extract a level transition of 1 (or more than 1) from the encoded current signal CD1 (motor signal) again. do. In this way, it becomes easy to determine the degree of noise.

The determining unit 27 counts the number of times the time difference Tx does not match the length of the bit section Tb within an error range. This count value can be used as the degree of noise (or the degree to which the decoded current signal CD2 contains errors). In particular, the number of times of consecutive mismatches is considered to represent the degree of possibility that there are consecutive errors in the decoded current signal CD2.

If the time difference Tx does not consecutively match the length of the bit section Tb within the error range and the number of times it does not match within the error range reaches a threshold, the determination unit 27 redoes the initial processing (initialization), and then restarts the continuation processing. . It is possible to deal with cases where the level transition extracted in the first initial processing is incorrect. Note that a threshold value can be input and set from the input section 18 to the determination section 27 .

As described above, in this embodiment, a plurality of level transitions are extracted from a motor signal including a Manchester encoded signal, and noise in the signal is detected based on the time difference Tx, thereby improving resistance to noise. You can improve. For example, it is possible to determine the degree of noise and, depending on the degree of noise, initialize the decoding unit 24 to prevent decoding errors, especially their continuation.

[Technical idea obtained from the embodiment]
The technical idea that can be understood from the above embodiment will be described below.

[1] The motor decoding circuit (data processing unit 16) generates a motor signal (code a decoding unit (24) that decodes a clock signal (CL0) and a bit string from the motor signal (CD1), and a plurality of level transitions from the motor signal (CD1). a transition extracting unit (26) that extracts a plurality of level transitions, and determines whether the time difference (Tx) between the extracted plurality of level transitions matches the length of the bit interval (Tb) within an error range, and if they do not match, A determination unit (27) is provided that determines that at least one of the plurality of level transitions is noise. The transition extraction unit (26) refers to the decoded bit string and extracts a plurality of level transitions excluding a level transition (boundary transition Sp) at the boundary of the bit interval (Tb) where bits of the same value are consecutive. Extract. This makes it possible to detect noise in the motor signal (CD1) and take various measures. By removing the boundary transition (Sp) in the Manchester code, noise detection accuracy can be improved.

[2] If the time difference (Tx) matches the length of the bit interval (Tb) within the error range, the transition extraction unit (26) additionally extracts one or more level transitions, and the determination unit (27) determines whether the time difference (Tx) between the additionally extracted level transition and the previously extracted level transition matches the length of the bit section (Tb) within an error range. This allows the degree of noise to be easily determined after initial processing.

[3] The determination unit (27) counts the number of times the time difference (Tx) does not match the length of the bit section (Tb) within an error range. By counting the number of times, the degree of noise can be determined.

[4] The determination unit (27) counts the number of times the time difference (Tx) does not match the length of the bit section (Tb) consecutively within an error range. Accordingly, the number of consecutive mismatches indicates the degree of possibility that the decoded current signal (CD2) has consecutive errors.

[5] The determination unit (27) determines whether the transition extraction unit ( 26) newly extracts a plurality of level transitions excluding the level transition at the boundary of the bit interval (Tb), and the time difference (Tx) between the newly extracted plurality of level transitions is determined by the time difference (Tx) in the bit interval (Tb). Tb) within the error range, the decoding section (24) additionally extracts one or more level transitions, and the determining section (27) extracts the additionally extracted level transitions. It is determined whether the time difference (Tx) between this and the previously extracted level transition matches the length of the bit section (Tb) within an error range. This makes it possible to deal with cases where the initially extracted level transition is incorrect.

DESCRIPTION OF SYMBOLS 10... Motor drive device 11... Inverter part 12... Current detection part 13... Current detector 14... A/D converter 15... Manchester encoding part 16... Data processing part 17... Current control part 18... Input part 20... Motor 21... Reference clock 24...Decoding section 25...Digital filter 26...Transition extraction section 27...Judgment section

Claims (5)

a receiving unit that receives a motor signal including a Manchester encoded signal representing a bit value by level transition within a bit interval;
a decoding unit that decodes a clock signal and a bit string from the motor signal;
a transition extraction unit that extracts a plurality of level transitions from the motor signal;
Determining whether the time difference between the extracted plurality of level transitions matches the length of the bit interval within an error range, and if they do not match, determining that at least one of the plurality of level transitions is noise. and,
The transition extraction unit refers to the decoded bit string and extracts a plurality of level transitions, excluding level transitions at boundaries of the bit sections where bits of the same value are continuous. The motor decoding circuit according to claim 1,
If the time difference matches the length of the bit interval within an error range, the transition extraction unit additionally extracts one or more level transitions,
The determination unit is a motor decoding circuit that determines whether a time difference between an additionally extracted level transition and a previously extracted level transition matches the length of the bit section within an error range. The motor decoding circuit according to claim 2,
The determination unit is a motor decoding circuit that counts the number of times the time difference does not match the length of the bit section within an error range. The motor decoding circuit according to claim 3,
The determination unit is a motor decoding circuit that counts the number of times that the time difference does not match the length of the bit section consecutively within an error range. The motor decoding circuit according to claim 4,
When the number of times reaches a threshold, the transition extraction unit newly extracts a plurality of level transitions excluding a level transition at the boundary of the bit interval,
If the time difference between the plurality of newly extracted level transitions matches the length of the bit section within an error range, the decoding unit additionally extracts one or more level transitions, and the determining unit . A motor decoding circuit that determines whether a time difference between an additionally extracted level transition and a previously extracted level transition matches the length of the bit section within an error range.

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