JP7383390B2 - Information processing unit, information processing device, information processing method and program - Google Patents

Description

The present invention relates to an information processing apparatus including a programmable information processing unit that reads and executes an arithmetic expression as a program.

Arithmetic operations in computer programs are executed by combining basic instructions that refer to general-purpose registers inside the CPU and assign the result of the operation to the general-purpose registers. At this time, even if the processing in the CPU is pipelined so that one instruction can be executed in one cycle or multiple instructions can be executed in one cycle, the data assigned to the general-purpose register There is some latency before it can be referenced again. Therefore, a wait between assignment and reference (hereinafter referred to as "data hazard") occurs. Particularly in floating-point operations with high latency, a decrease in the operating rate of the computing unit due to data hazards significantly reduces processing performance.

To address this problem, Patent Document 1, for example, discloses a technique for detecting dependencies in a sequence of instructions and stopping part of a circuit until the dependencies can be maintained. Further, Patent Document 2 discloses means for detecting an out-of-order instruction that may violate data coherency and reordering the instruction.

Japanese Patent Application Publication No. 2000-99328 Japanese Patent Application Publication No. 11-272466

However, all of the above conventional techniques such as out-of-order, super scalar, and register renaming not only result in large and complicated circuits, but also require references between general-purpose registers, which causes speed reduction. It is essentially difficult to completely resolve the occurrence of data hazards that occur between and assignments.

An object of the present invention is to provide a technique for improving the operating rate of a computing unit without using a large-scale circuit in an information processing unit that exchanges data with the computing unit.

The information processing unit according to the present invention includes an instruction reading section that sequentially reads instructions from a storage means in which an instruction sequence and data are stored, and an instruction reading section that sequentially reads instructions from a storage means in which an instruction sequence and data are stored, and data from the storage means according to an address field of the instruction read by the instruction reading section. a data reading section that reads the instruction, a data transfer section that transfers the data read by the data reading section to the calculation means according to the type of the instruction read by the instruction reading section, and the storage that stores the calculation result output from the calculation means. a writing section for writing into the instruction means, the instruction read by the instruction reading section does not include a field indicating an address for storing an operation result, and the writing section writes the instruction output from the operation means. The method is characterized in that the calculation results corresponding to are sequentially written to consecutive addresses of the storage means .

According to the present invention, it is possible to improve the operating rate of the computing unit while reducing the circuit scale of the information processing unit that exchanges data with the computing unit.

FIG. 1 is a block diagram showing the basic configuration of an information processing device according to a first embodiment. 2 is a block diagram of the ALU and the structure of data handled by the ALU. FIG. FIG. 2 is a diagram illustrating a bit configuration of an accelerator instruction. FIG. 3 is a diagram showing an example of a configuration of a control register and a memory map. FIG. 3 is a diagram illustrating a method of decomposing an arithmetic expression into a program and executing the program. It is assembler notation and a timing chart of the program of FIG.5(e). FIG. 3 is a diagram illustrating arithmetic processing using intermediate data. FIG. 3 is a block diagram of a circuit in which three accelerators share three ALUs. FIG. 2 is a circuit diagram of an arbiter. 3 is a timing chart showing an example of the operation of an arbiter. FIG. 3 is a circuit diagram of a writing section included in the accelerator. 3 is a flowchart of a compiler that generates a program to be executed on an accelerator. FIG. 3 is a diagram showing an example of program expansion, decomposition, and rearrangement. FIG. 2 is a partial block diagram of an information processing device according to a second embodiment. 12 is a flowchart illustrating a process of generating a machine language program executable by an accelerator using intermediate code in a third embodiment. FIG. 3 is a diagram illustrating a bit field of an intermediate code. FIG. 3 is a block diagram of an information processing device according to a fourth embodiment.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

<First embodiment>
FIG. 1 is a block diagram showing the basic configuration of an information processing apparatus 100 including an accelerator 103 as an information processing unit according to an embodiment of the present invention. The information processing device 100 includes a CPU 101, a DRAM 102, an accelerator 103, an SRAM block 104, an ALU 111, and a data transfer unit 112. Although FIG. 1 shows a configuration including one accelerator 103 and one ALU 111, a configuration including a plurality of accelerators 103 and a plurality of ALUs 111 is also possible, as will be described later.

CPU is an abbreviation for Central Processing Unit. DRAM is an abbreviation for Dynamic Random Access Memory. SRAM is an abbreviation for Static Random Access Memory. ALU is an abbreviation for Arithmetic Logic Unit.

The CPU 101 is a main control circuit, and is a processor that performs overall control of the information processing apparatus 100. The DRAM 102 is a storage medium that stores programs that run on the CPU 101, programs that run on the accelerator 103, and the like.

The SRAM block 104 is a storage medium that stores data necessary for the operation of the CPU 101 and the accelerator 103, calculation results by the ALU 111, and the like. SRAM block 104 includes multiple SRAMs. The CPU 101 and the accelerator 103 can access the SRAM block 104. The ALU 111 is an arithmetic unit that performs floating point arithmetic.

FIG. 2A is a diagram illustrating the structure of 32-bit single-precision data used for calculations performed by the ALU 111. Here, the ALU 111 calculates single-precision floating point numbers. The 32-bit single-precision data has a determined role for each bit, and is composed of a sign bit (SIGN) 200, an exponent bit (EXPONENT) 201, and a mantissa bit (FRACTION) 202.

FIG. 2(b) is a block diagram of the ALU 111. The ALU 111 has an A input section 203 and a B input section 204 for inputting data, and an output section 208 for outputting calculation results. The ALU 111 also includes a mantissa section 205, an exponent section 206, and a sign section 207 for performing floating point operations. The mantissa section 205, exponent section 206, and sign section 207 perform operations on the data input from the A input section 203 and the B input section 204 while exchanging necessary information such as carry due to rounding, and the operation result is It is output from the output unit 208.

Five flip-flops are inserted in each of the mantissa part 205, exponent part 206, and sign part 207. Therefore, in the ALU 111, after data is input from the A input section 203 and the B input section 203, the calculation results from the mantissa section 205, exponent section 206, and sign section 207 reach the output section 208 five cycles later.

In order to increase the operating frequency of the ALU 111, it is necessary to shorten the gate delay occurring between flip-flops, so a flip-flop is inserted in each small operation unit in the design. In the ALU 111, it is assumed that one operation takes five cycles. If there is a valid data input every cycle, a valid output will be obtained every cycle. In other words, one operation can be performed in one cycle.

Note that a cycle in which valid data cannot be input to the ALU 111 is a wasted cycle. Therefore, the rate at which valid data can be input is the operating rate of the ALU 111. One of the objectives of the present invention is to increase the operating rate of the ALU 111, and as described later, the accelerator makes it possible to increase the operating rate of the ALU 111 with a small circuit configuration.

Returning to the explanation of FIG. The accelerator 103 has a control register 105 for controlling the operation of the accelerator 103 from the CPU 101. The control register 105 is a memory mapped IO, and is connected to the address bus of the CPU 101 via a data bus.

The accelerator 103 includes an instruction reading section 110, a data reading section 109, a writing section 113, and a comparison section 116. The instruction reading unit 110, data reading unit 109, and writing unit 113 operate as a queue (QUEUE) that arranges the read elements in a line in the order in which they came in and takes out the elements in accordance with the rule that the element that was entered first is taken out in order. It is configured as follows. The function of the comparison unit 116 will be described later.

The instruction reading unit 110 reads an instruction string from the SRAM block 104. The instruction reading unit 110 has a WAIT address 106. The value of the address specified by a WAIT command, which will be described later, is input to the WAIT address 106. The data reading unit 109 reads data used for calculations from the SRAM block 104. The instruction reading section 110 and the data reading section 109 are bus masters having independent address buses and data buses, respectively. The plurality of SRAMs in the SRAM block 104 are arranged at different addresses, respectively, and are arranged so that instruction sequences and data can be read from other SRAMs. Each of the multiple SRAMs in SRAM block 104 can read both data and instructions in the same cycle.

The data transfer unit 112 transfers instructions and data to the ALU 111. When data is transferred to the ALU 111, the calculation result is output from the ALU 111 to the writing unit 113 after a certain cycle. When the writing unit 113 receives the calculation result from the ALU 111, it writes the received calculation result into the SRAM block 104. Like the instruction reading section 110 and the data reading section 109, the writing section 113 is a bus master having an independent address bus and data bus, and writes data in the same cycle as the instruction reading section 110 and the data reading section 109. be able to.

The writing section 113 has a write address section 114. The value of the address in the SRAM block 104 when the calculation result is written to the SRAM block 104 is output from the write address section 114. The address value written to the write address section 114 is sequentially rewritten in accordance with the operation result written to the SRAM block 104, as shown by 'STORE ADDRESS' in FIG. 7, which will be described later.

FIG. 3A is a diagram illustrating the bit configuration of an instruction of the accelerator 103. An instruction is 16-bit data, and bits 11 to 15 are an operation code (OPECODE) field 301 indicating the type of instruction. Bits 9 and 10 are a base address index (BASE ADDRESS INDEX) field 302 that specifies the type of base address (BASE ADDRESS) of the SRAM block 104 to be accessed. Bits 0-8 are an offset address (OFFSET ADDRESS) field 303 representing the address of data. The 9-bit offset address field 303 can represent 0 to 511, but since a single-precision floating point number is 32 bits, the offset address field 303 is treated as an index value in units of 4 bytes here. In other words, what can be accessed is 0 to 7FC in hexadecimal relative to the base address. There are four base addresses, and each base address is specified by the CPU 101 by writing it into the control register 105.

FIG. 3(b) is an assembler notation (mnemonic) of the instruction. Types of instructions include addition, subtraction, multiplication, and division instructions for arithmetic operators, termination instructions, and several other control instructions. The instruction includes an opcode section 304 that specifies the operation to be executed, an operand 305 that is specified as A or B, and a label 306 that specifies data.

The basic structure of the instruction of the accelerator 103 is to read data into the operand 305 from the address indicated by the label 306, and then perform an arithmetic operation specified by the opcode section 304. For example, the operation 'i÷j' takes 'i' into 'A' with 'FNOP A,i', takes 'j' into 'B' with 'FDIV B,j', and then 'A'. This is accomplished with two instructions: ÷B'. Note that the instruction of the accelerator 103 does not include a field indicating the address where the calculation result is stored. This is because the writing unit 113 has a structure in which the calculation results are sequentially written to consecutive addresses, and the address in which the calculation results are stored cannot be selected.

FIG. 4 is a diagram showing the configuration of a memory map of the control register 105 and the SRAM block 104 in the accelerator 103. The control register 105 has a start register 414, a program address 415, a first base address 401, a second base address 402, a work base address 403, and an output base address 404.

The first base address 401 specifies common data 405. The second base address 402 specifies a parameter area 409 dedicated to accelerator 0. The work base address 403 specifies a work area 410 dedicated to accelerator 0. Note that here, it is assumed that the accelerator 103 includes three accelerators 0, 1, and 2. The work area 410 can secure 512 pieces of data.

The program address 415 specifies the start address 413 of the program. When '1' is written to the start register 414, the accelerator 0 starts reading the program and executes the program sequentially until reading the end instruction.

With reference to FIG. 5, a method of decomposing an arithmetic expression into a program and executing it will be described. FIG. 5(a) shows an example of an arithmetic expression. FIG. 5(b) is a list showing a program in C language for solving the arithmetic expression of FIG. 5(a), and shows a program that performs a product-sum operation in a triple loop for an array of n=3. FIG. 5C shows a modification of the program shown in FIG. 5B, in which accesses are reduced by combining the addressing of b[k][j].

FIG. 5(d) shows the data accessed by the program that has been labeled and expanded. The programs written in C language in Figures 5(c) and (c) calculate i, j, and k, but the numerical values that i, j, and k will change to are determined at the time of compilation. Therefore, each can be expanded to a fixed address in advance. In the expansion expression in Figure 5(d), there are two operators in one expression: '+', which represents addition, and '×' ('*' in Figure 5), which represents multiplication, so in order to expand it into an instruction, requires intervening variables that serve as intermediate nodes (hereinafter referred to as "intermediate variables").

FIG. 5E shows labels assigned to intermediate variables and their order rearranged. In FIG. 5E, multiplication continues from line 001 to line 009, and the instruction to add the result starts from line 010. The first intermediate variable TMP000 is referenced at line 010, and the expression that adds to the variable C00 and returns it to C00 is stored in the new intermediate variable TMP010. When adding to C00 again in line 038, intermediate variable TMP010 is referred to and substituted into a new intermediate variable TMP038. By expanding in this order and rearranging the operation order, the number of cycles from assignment to reference is increased, so no data hazard occurs in the accelerator 103.

FIG. 6(a) is a diagram showing the program of FIG. 5(e) in assembler notation. Line 000 simply loads variable B00 into operand B and does not perform any arithmetic operation. Line 001 loads the variable A00 into the operand A and executes 'A×B' multiplication. Variables A00 and B00 are placed in the parameter area 409, and intermediate variables are placed in the work area 410. Note that in the assembler notation, it seems that the intermediate variable TMP000 is specified as the storage destination, but as mentioned above, there is no field in the instruction that indicates the address that specifies the storage destination, and the label TMP000 indicates the storage destination. Addresses are associated. Line 002 loads the variable A10 into the operand A and executes 'A×B' multiplication.

FIG. 6(b) is a timing chart illustrating input/output in the data transfer unit 112 during execution of the program shown in FIG. 6(a). In the 001st cycle, B00 is loaded into the operand B, and in the 002nd cycle, A00 is loaded into the operand A, and the multiplication request signal FMUL becomes '1', which causes the variable to be added to the multiplication ALU. A00 and variable B00 are output. In this way, transfer occurs continuously from cycle 002 to cycle 004. Note that the multiplication ALU is, for example, the ALU 805 shown in FIG. 8, which will be described later.

Even in an instruction structure where data is loaded from one of operands A and B instead of reading data into both operands A and B, consecutive operations occur so that one is common. This is because the instruction sequence is rearranged. Such commonization of variables is possible with many polynomials, and the compiler rearranges the instruction sequences. The operation result (intermediate variable TMP001) for the operation accepted at the 002nd cycle is output to FMUL_Q at the 007th cycle, and at the same time, a VALID signal (FMUL_VALID) indicating that the data is valid is also output.

FIG. 7 is a diagram illustrating a situation in which calculations are performed while sequentially storing calculation results (intermediate variables) at consecutive addresses. In FIGS. 7A to 7D, it is assumed that a work area 410 dedicated to accelerator 0 that stores intermediate variables is specified by the work base address 403 of accelerator 0, according to FIG. Note that in FIGS. 7A to 7D, the calculation contents are shown as programs and mnemonics for convenience of explanation, but it is sufficient that the DRAM 102 stores a machine language program that can be executed by accelerator 0. .

As shown in FIG. 7A, when the accelerator 0 executes the first instruction 701 'FNOP B, B00', meaningless data is stored at address 000 of the work area 410. When accelerator 0 executes the next instruction 702, 'FMUL TMP000, A, A00', intermediate variable TMP000, which is the calculation result, is stored at address 004. When accelerator 0 executes the next instruction 703, 'FMUL TMP001, A, A10', intermediate variable TMP001, which is the calculation result, is stored at address 008. When the intermediate variable TMP000 is loaded into the operand A with the instruction 704 'FNOP A, TMP000', the value 001 indicating address 004 is stored in the address field of the instruction.

If the calculation results are stored sequentially in this way, the work area 410 will be used up from beginning to end. Therefore, when the instruction 705 'FADD TMP501,A,TMP000' is executed, the operation result will be stored at address 000. Furthermore, when the next instruction is executed, the intermediate variable TMP000 stored at address 004 will be overwritten. In this way, the intermediate variables handled by accelerator 0 have a lifetime, and the intermediate variables end their lifetime after 511 steps of program execution. In other words, the intermediate variable can be referenced during the period in which it is stored in the SRAM block 104.

In many cases, a lifetime longer than 511 steps is not required, but if you want to extend the lifetime of a variable, use instructions for extending the lifetime. For example, in FIG. 7(b), the instruction 706 'FADD TMP502, B, ZERO' adds the value 0 (zero) to the intermediate variable TMP000 and stores the intermediate variable TMP502 which is the new operation result. . As a result, from now on, the intermediate variable TMP000 can continue to exist with the name changed to the intermediate variable TMP502. As a method of extending the lifetime of a variable, instead of adding zero, a method of multiplying by '1' can also be used.

As explained with reference to FIG. 2(b), the calculation result is written to the writing unit 113 for several cycles before it is output from the ALU 111, and then written to the SRAM block 104 for reference. It takes several cycles before this becomes possible. Conversely, even after an instruction that overwrites an existing intermediate variable, the variable before being overwritten can be referenced for several cycles.

In FIG. 7C, the instruction 707 'FADD TMP503,B,TEMP001' refers to the intermediate variable TMP001 even after the above-described overwriting instruction 706 has already been executed. Here, if the assignment result must be referenced immediately, the WAIT instruction 708 represented by 'WAIT TMP501' can be used to wait until it becomes referenceable. The WAIT instruction is an instruction that specifies the address value of a variable to be accessed.

The WAIT instruction inputs a value (reference address) to the WAIT address 106 of the instruction reading section 110 and enables the comparison section 116. The comparator 116 can detect that the address value of the write address section 114 has passed the value of the WAIT address 106. In the first embodiment, the value of the write address 114 is incremented. Therefore, when the write address 114 passes through the WAIT address 106, it means that the write address 114 is larger than the WAIT address 106. Note that when implementing the configuration in which the write address 114 is decremented, when the write address 114 becomes smaller than the WAIT address 106, it is detected that the write address 114 has passed the WAIT address 106. Considering that the write address 114 returns to the initial value when it reaches the end of a predetermined range, the comparison is not a simple comparison of magnitudes, but a comparison that limits the distance between values. In this embodiment, the condition is '((reference address - write address) & 0x7FF) < 0x400'.

The comparison unit 116 monitors the WAIT address 106 and compares the value of the address input to the WAIT address 106 and the value of the write address unit 114. The comparison unit 116 allows the data reading unit 109 to read the next data when writing to the writing unit 113 is not completed (when the value of the write address field 114 has not reached the value of the WAIT address 106). suppress. In this embodiment, the next data read is performed when the relationship '((reference address - write address) & 0x7FF) < 0x400' is established, but if not, the data reading unit 109 stops.

FIG. 7D shows a state in which 'REWIND' of an instruction 710 is executed to clear the address (set it to address 000) before the address for storing the operation result reaches address 7FC. This instruction makes it possible to execute operations with a small work area when sufficient memory map capacity cannot be secured. Note that it is also possible to intentionally extend the lifetime of data near address 7FC.

FIG. 8 is a block diagram of a circuit in which three accelerators 0_801, 1_802, and 2_803 share three ALUs 805, ALUs 806, and ALUs 807. Note that although the block diagram of the information processing device 100 in FIG. 1 shows a configuration including one accelerator 103 and one ALU 111, as shown in FIG. can do. Each of accelerator 0_801, accelerator 1_802, and accelerator 2_803 corresponds to accelerator 103 shown in FIG. Further, each of ALU 805, ALU 806, and ALU 807 corresponds to ALU 111 shown in FIG.

Accelerator 0_801, accelerator 1_802, and accelerator 2_803 are each connected to three arbiters 804. If accelerator 0_801, accelerator 1_802, and accelerator 2_803 simultaneously set their request signals to High, each of the three arbiters 804 sets the GRANT signal to High for the accelerator with a higher priority. In this case, the accelerator waits in that state until the GRANT signal becomes High because the request signal is not accepted if the GRANT signal remains Low even if the request signal becomes High.

ALU 805 performs multiplication operations. ALU 806 performs a division operation. ALU 807 performs an addition operation. ALU 805, ALU 806, and ALU 807 can each independently execute operations simultaneously. If the configuration has one accelerator and three ALUs, two of the three ALUs will not be operating. On the other hand, by configuring the same number of ALUs to execute calculations in parallel from a plurality of accelerators, the utilization rate of the ALUs can be increased.

FIG. 9 is a circuit diagram of arbiter 804. The arbiter 804 has a terminal group 901 connected to accelerator 0_801, a terminal group 902 connected to accelerator 1_802, and a terminal group 903 connected to accelerator 2_803.

Terminal group 901 includes a plurality of terminals 901a to 901f connected to accelerator 0_801. Terminal group 902 includes a plurality of terminals 902a to 902f connected to accelerator 1_802. Terminal group 903 includes a plurality of terminals 903a to 903f connected to accelerator 0_803. The terminal 901a is an input terminal used for inputting a request signal. Terminals 901b and 901c are input terminals used for inputting data of operands A and B. The terminal 901d is an output terminal that outputs the GRANT signal to the accelerator 0_801. The terminal 901e is an output terminal that outputs the VALID signal to the accelerator 0_801. The terminal 901f is an output terminal that outputs the calculation result Q to the accelerator 0_801. Similarly, the terminal group 902 and the terminal group 903 have a plurality of terminals for inputting and outputting signals with the corresponding accelerator. Descriptions of the terminal group 902 and the terminal group 903 will be omitted.

For example, when transferring data to a predetermined ALU, accelerator 0_801 inputs the data of operands A and B to terminals 901b and 901c, sets the request signal to High, and inputs it to terminal 901a. It is assumed that the accelerator 0_801 has the highest priority (highest priority). In this case, the request signal is always accepted and sent to the corresponding ALU through the ALU side terminal 917. Further, a High GRANT signal is output from the terminal 901d.

If the request signal input to the terminal 901a in the same cycle when the request signal of the accelerator 1_802 becomes High is High, the request signal of the accelerator 1_802 is not accepted due to the action of the gate 909. On the other hand, if the request signal input to the terminal 901a in the same cycle when the request signal of accelerator 1_802 becomes High is low, the request signal of accelerator 1_802 is accepted. As a result, data of operands A and B from accelerator 1_802 is input to arbiter 804, passes through gates 910 and 911, and is sent to ALU side terminals 914 and 915.

Further, the request signal received by the gate 909 from the accelerator 1_802 through the terminal 902a is delayed by the delay element 912, and then sent to the writing unit 113 of the accelerator 1_802 as a VALID signal. In the same cycle, the calculation result Q is input from the ALU to the ALU side terminal 916, and the calculation result Q is sent to the writing unit 113 of the accelerator 1_802 through the gate 913.

FIG. 10 is a timing chart showing the operation of the arbiter 804 when request signals are simultaneously input to one arbiter 804 from two accelerators 0_801 and 1_802.

Accelerator 0_801 makes the request signal High in the second cycle, and outputs the GRANT signal in the same cycle. In the same cycle, the request signal of accelerator 1_802 also becomes High, but since the GRANT signal becomes Low, accelerator 1_802 is in a stopped state while holding the signal.

At the fifth cycle when the request signal of accelerator 1_802 becomes Low, the GRANT signal of accelerator 1_802 becomes High, and the program of accelerator 1_802 advances by one cycle. In this way, on the ALU side (not shown), calculations are performed in every cycle. At this time, since the program for accelerator 1_802 includes consecutive multiplication instructions or consecutive addition instructions, the program for accelerator 1_802 is executed a little later than the program for accelerator 0_801.

FIG. 11 is a circuit diagram of the writing unit 113 included in the accelerator 103. The writing unit 113 has an input terminal 1102 for the operation result Q from the multiplication ALU (ALU 805 in FIG. 8) and an input terminal 1103 for the VALID signal indicating a valid data cycle. The writing unit 113 also has an input terminal 1104 for the operation result Q from the division ALU (ALU 806 in FIG. 8) and an input terminal 1105 for the VALID signal. Furthermore, the writing unit 113 has a data input terminal 1106 for the operation result Q from the addition ALU (ALU 807 in FIG. 8) and an input terminal 1107 for the VALID signal.

Since the accelerator 103 issues a request signal to only one of the three ALUs 805 to 807 during one cycle, the VALID signal and the operation result Q are returned from only one of the ALUs 805 to 807. Therefore, the accelerator 103 can receive the VALID signal and the calculation result Q at the OR circuits 1111 and 1112. Further, although there is no data in the FNOP cycle, it is received from the input terminal 1108 as a VALID signal. The data received by OR circuits 1111 and 1112 is written to FIFO buffer 1113.

When data is written to the FIFO buffer 1113, the data is output from an output terminal 1118 and a write request signal is output from an output terminal 1119 to the SRAM block 104. When the SRAM block 104 receives the write request signal, the GRANT signal input from the GRANT signal input terminal 1120 becomes High, and the FIFO buffer 1113 outputs the next signal. When the FIFO buffer 1113 becomes empty, it sets the TMPTY signal to High and stops operating. Every time the GRANT signal input from the GRANT signal input terminal 1120 becomes High, the output of the counter counted up by the counter 1114 is shifted by 2 bits. The count output from the counter 1114 is added to the base address input from the base address input terminal 1109, sent to the address bus terminal 1121, and output from there to the SRAM block 104.

FIG. 12 is a flowchart of a compiler for generating a program executable by the accelerator 103. Note that the S number attached to each process shown in FIG. 12 represents the process order. Note that the compiler (program) itself is created in a system different from the information processing apparatus 100, and the program generated by compilation and executable by the accelerator 103 is stored in the DRAM 102.

In S1201, the source code is read and held as internal intermediate data. Note that although the accelerator 103 in this embodiment does not have a branch instruction in the program, it is assumed that the accelerator 103 operates in a source language such as C language that can express simple loops and arrays.

In S1202, the loop is expanded and symbols are assigned to all variables. FIG. 13(a) shows an example of program expansion, and the program in the left formula is expanded as in the right formula.

In S1203, symbols of intermediate variables are assigned to intermediate nodes of the polynomial. FIG. 13(b) shows an example of polynomial decomposition, and the left equation can be decomposed into two equations as shown in the right equation.

In S1204, a search is made for an instruction in which the number of steps from assignment to reference is shorter than a first threshold value, and it is determined whether or not an instruction can be found. The first threshold value is a value larger than the number of cycles from the start of the calculation until the calculation result can be referenced. If it is determined that the instruction has been found (YES in S1204), the process advances to S1205.

In S1205, the preceding and succeeding instructions are swapped so that the order of assignment and reference is not out of order, and the number of steps from assignment to reference is changed to be longer than the first threshold. FIG. 13(c) is a diagram illustrating an example of rearranging formulas in a program, in which the instruction sequence of the left formula is rearranged as the right formula.

In S1206, it is determined whether the number of steps from assignment to reference continues to be shorter than the first threshold. If the number of steps from assignment to reference is shorter than the first threshold (if it does not become longer than the first threshold) even if the previous and following instructions are swapped so that the order of assignment and reference is not disrupted (YES in S1206), The process advances to S1207.

In S1207, a WAIT command (WAIT command 708 described with reference to FIG. 7C) is inserted, and then the process returns to S1204. On the other hand, if the number of steps from assignment to reference is equal to or greater than the first threshold (NO in S1204), the process returns to S1204.

By repeating the loop from S1204 to S1206 or S1207, if it is determined in S1204 that an instruction whose number of steps from assignment to reference is shorter than the first threshold is no longer found (NO in S1204), the process advances to S1208. .

In S1208, a search is made for an instruction in which the number of steps from assignment to reference is longer than the second threshold, and it is determined whether the instruction can be found. The second threshold value is a value smaller than the number of data that can be stored in the work area of the SRAM block 104, and is a value smaller than 511 in this embodiment. If an instruction with a step count longer than the second threshold is found (YES in S1208), the process advances to S1209.

In S1209, an instruction to extend the lifetime of the variable is inserted, and then the process returns to S1208. By repeating the loop from S1208 to S1209, if an instruction whose number of steps from assignment to reference is longer than the second threshold cannot be found (NO in S1208), the process advances to S1210.

In S1210, the assembler file is output to the SRAM block 104. The generated assembler file is stored in a predetermined SRAM. This ends the process. The assembler allocates addresses in accordance with the structure of the accelerator 103, where the address for securing intermediate variables returns to 0x000 when it reaches 0x7FC.

As described above, according to the first embodiment, the accelerator 103 is configured with the instruction reading section 110, data reading section 109, and writing section 113 as queues, without using general-purpose registers that require a large number of addresses, and the ALU 111 is increasing its utilization rate. In other words, it is possible to reduce the circuit scale of the accelerator 103 and increase the operating rate of the ALU 111.

<Second embodiment>
In the first embodiment, a variable lifetime extension instruction is generated by adding zero (0) or multiplying by one. In contrast, in the second embodiment, by generating an instruction to extend the variable lifetime without using an ALU that performs an addition operation or an ALU that performs a multiplication operation, the ALU that becomes vacant in that cycle is used by another accelerator. possible.

FIG. 14(a) is a partial block diagram of an information processing device according to the second embodiment. Note that in the block diagram of FIG. 14A, the same components as those in the block diagram of FIG. 8 are designated by the same reference numerals as those in FIG. 8, and a description of the contents already described will be omitted here.

As shown in FIG. 14A, a through ALU 1401 that is not shared with other accelerators is connected to each of accelerator 0_801, accelerator 1_802, and accelerator 2_803. FIG. 14(b) is a circuit diagram of the through ALU 1401. When the through ALU 1401 receives a request signal (_REQ), it accepts it as is and outputs a GRANT signal (_GRANT). At the same time, the A input (_A) is delayed by the delay element 1402 by the same amount as the VALID signal (_VALID) delayed by the delay element 1403, and outputted to the Q output (_Q). Since each of the three through ALUs 1401 is a dedicated ALU, accelerator 0_801, accelerator 1_802, and accelerator 2_803 can execute through processing at the same time.

<Third embodiment>
In the first embodiment, the source language is converted into a machine language program that can be executed by the accelerator 103. In contrast, in the third embodiment, a machine language program executable by the accelerator 103 is generated using intermediate code.

FIG. 15(a) is a flowchart of a compiler that generates intermediate code. Among the steps shown in the flowchart of FIG. 15(a), the same steps as those shown in the flowchart of FIG. 12 are given the same reference numerals and the description thereof will be omitted. In S1501 after performing steps S1201 to S1203, a unique number is assigned to a symbol and an intermediate code is output. As a result, the intermediate code shown in FIG. 16 is generated.

FIG. 16 is a diagram illustrating the bit field of the intermediate code generated in S1501. The work address ID 1601 is a 16-bit area that stores a unique number assigned to a variable. The operation code field 301, base address index field 302, and offset address field 303 have the same bit configuration as the instruction of the accelerator 103 described with reference to FIG. Addresses indicating areas other than the work area are written in the offset address field 303.

FIG. 15B is a flowchart showing a flow of reading a program executed by the accelerator 103 by the program loader. Among the steps shown in the flowchart of FIG. 15(b), the same steps as those shown in the flowchart of FIG. 12 are given the same reference numerals and the description thereof will be omitted.

In S1505, the intermediate code generated in S1501 is read into memory. The subsequent steps S1204 to S1209 are the same as described with reference to FIG. 12, so their description will be omitted here.

If the determination in S1208 is NO, the 16-bit variable is assigned to a 9-bit address and converted in S1506. When assigning to a 9-bit address, when it reaches 0x1FF, 0x000 is assigned next. Once the assigned address is stored in the offset address field 303, the 16 bits of the work address ID 1601 are no longer needed, so they are removed and converted into executable machine language.

In subsequent S1507, the machine language program converted in S1506 is placed in a predetermined SRAM of the SRAM block 104, the accelerator 103 is activated, and the machine language program is executed.

Note that in S1506, the 16 bits of the work address ID 1601 are removed to create an executable machine language, but the accelerator may be designed to ignore the upper 16 bits in advance and execute. As a result, even if the implementation of the work area is changed to 8 bits or 10 bits, the binary compatibility of the intermediate code can be guaranteed by simply changing the implementation of the program loader in FIG. 15(b). As a result, the degree of freedom in hardware design can be increased and scalability can be ensured.

<Fourth embodiment>
In the fourth embodiment, a modification of the information processing apparatus 100 according to the first embodiment will be described. FIG. 17 is a block diagram showing a schematic configuration of an information processing device 1700 according to the fourth embodiment. Note that, among the components of the information processing device 1700, the same components as those of the information processing device 100 according to the first embodiment are given the same reference numerals.

The information processing device 1700 includes a CPU 101, a DRAM 102, and a processor block 1702. The processor block 1702 includes an accelerator 103, an SRAM block 104, an ALU 111, and an internal CPU 1701. The internal CPU 1701 is a CPU dedicated to the accelerator. The CPU 101 and the processor block 1702 communicate using a control register in the accelerator 103 and a shared area of the DRAM 102.

In the information processing apparatus 1700, the internal CPU 1701 of the processor block 1702 performs the program loader and instruction insertion processing described in the third embodiment. Note that it is also possible to implement part or all of the program loader's instruction insertion process in hardware. In that case, at least a WAIT instruction or a variable lifetime extension instruction that does not exist in the program given to the processor block 1702 is inserted and executed within the processor block 1702.

Although the present invention has been described above in detail based on its preferred embodiments, the present invention is not limited to these specific embodiments, and the present invention may take various forms without departing from the gist of the present invention. included. Further, each of the embodiments described above is merely one embodiment of the present invention, and each embodiment can be combined as appropriate.

For example, the individual numerical values, the number of referenceable items in the work area, the number of ALUs, the number of accelerators, the bit length of instructions, etc. in the above embodiments can be changed (designed) according to the required performance. The settings are not limited to the above settings. In addition, in the above embodiment, a configuration for performing single-precision floating-point operations was described, but it can also be applied to double-precision operations and integer operations, and it is also possible to add binary operators such as square and square root as an ALU. It is. Furthermore, although the program to be executed by the accelerator is generated by converting the program into machine language using a compiler, a program designer may directly design the machine language program.

The present invention provides a system or device with a program that implements one or more functions of the embodiments described above via a network or a storage medium, and one or more processors in a computer of the system or device reads and executes the program. This can also be achieved by processing. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

100,1700 Information processing device 101 CPU
102 DRAM
103 Accelerator 104 SRAM block 105 Control register 106 WAIT address 109 Reading section 110 Instruction reading section 111 ALU
112 Data transfer section 113 Writing section 114 Write address section 116 Comparison section 1701 Internal CPU
1702 Processor block

Claims (14)

an instruction reading unit that sequentially reads instructions from a storage means in which an instruction sequence and data are stored ;
a data reading section that reads data from the storage means according to the address field of the instruction read by the instruction reading section;
a data transfer unit that transfers the data read by the data reading unit to an arithmetic means according to the type of instruction read by the instruction reading unit;
a writing section for writing the calculation result output from the calculation means into the storage means ,
The instruction read by the instruction reading unit does not have a field indicating an address for storing an operation result,
The information processing unit is characterized in that the writing section sequentially writes the operation results corresponding to the instructions outputted from the operation means into consecutive addresses of the storage means. The information processing unit according to claim 1, wherein the instruction reading section, the data reading section, and the writing section are each configured as a queue. an instruction reading unit that sequentially reads instructions from a storage means in which an instruction sequence and data are stored;
a data reading section that reads data from the storage means according to the address field of the instruction read by the instruction reading section;
a data transfer unit that transfers the data read by the data reading unit to an arithmetic means according to the type of instruction read by the instruction reading unit;
a writing section that sequentially writes the calculation results output from the calculation means into the storage means,
Information processing characterized in that the instructions read by the instruction reading section include an instruction to suppress the next data read from the storage means until the write address of the writing section passes a specified value. unit. When a compiler that generates a program including the instruction sequence detects an instruction that refers to the predetermined operation result before the predetermined operation result is written into the storage means, the compiler generates the program that includes the instruction sequence, and when the compiler detects an instruction that refers to the predetermined operation result before the predetermined operation result is written into the storage means, the next data is sent to the data reading section. 4. The information processing unit according to claim 3, wherein an instruction to suppress reading is inserted into the instruction string. an instruction reading unit that sequentially reads instructions from a storage means in which a sequence of instructions generated by a compiler is stored;
a data reading section that reads data from the storage means according to the address field of the instruction read by the instruction reading section;
a data transfer unit that transfers the data read by the data reading unit to an arithmetic means according to the type of instruction read by the instruction reading unit;
a writing section that sequentially writes the calculation results output from the calculation means into the storage means,
When the compiler detects an instruction that refers to the predetermined computation result written to a predetermined address of the storage means beyond a period until the predetermined computation result is overwritten by a later computation result, the An information processing unit characterized in that an instruction for extending a period during which a predetermined operation result can be referenced is inserted into the instruction sequence. 6. The information processing unit according to claim 1, further comprising control means for controlling operations of the instruction reading section, the data reading section, and the writing section. Accelerator and
a CPU that controls the operation of the accelerator ;
a DRAM that stores a program that runs on the CPU;
an ALU (Alithmetic Logic Unit) that performs calculations based on instructions from the accelerator ;
An information processing device comprising an SRAM ,
The accelerator is
an instruction reading unit that sequentially reads instructions from the SRAM ;
a data reading unit that reads data from the SRAM according to the address field of the instruction;
a data transfer unit that transfers the data read by the data reading unit to the ALU according to the type of instruction read by the instruction reading unit;
a writing unit that writes the calculation result output from the ALU to the SRAM ,
The instruction read by the instruction reading unit does not have a field indicating an address for storing an operation result,
The information processing device is characterized in that the writing unit sequentially writes operation results corresponding to the instructions output from the ALU to consecutive addresses of the SRAM. 8. The information processing apparatus according to claim 7, wherein the instruction reading section, the data reading section, and the writing section are each configured as a queue. 9. The information processing apparatus according to claim 7, wherein the ALU performs floating point calculations. sequentially reading instructions from a storage means in which the instruction sequence and data are stored ;
reading data from the storage means according to the address field of the read instruction;
a step of transferring the read data to an arithmetic means in the order in which it was read according to the type of the instruction;
writing the calculation result output from the calculation means into the storage means;
has
The instruction read in the step of reading the instruction does not have a field indicating an address for storing the operation result,
An information processing method characterized in that, in the step of writing the operation results, the operation results corresponding to the instructions outputted from the operation means are sequentially written to consecutive addresses of the storage means. sequentially reading instructions from a storage means in which the instruction sequence and data are stored;
reading data from the storage means according to the address field of the read instruction;
a step of transferring the read data to an arithmetic means in the order in which it was read according to the type of the instruction;
the step of sequentially writing the calculation results output from the calculation means into the storage means,
An information processing method characterized in that an instruction is inserted into the instruction sequence to suppress the next data read until a write address for writing the operation result in the storage means passes a specified value. The instruction to suppress reading of data is inserted into the instruction string when an instruction that refers to a predetermined operation result is detected before the predetermined operation result is written to the storage means. The information processing method according to claim 11 . sequentially reading instructions from a storage means in which a sequence of instructions generated by a compiler is stored;
reading data from the storage means according to the address field of the read instruction;
a step of transferring the read data to an arithmetic means in the order in which it was read according to the type of the instruction;
the step of sequentially writing the calculation results output from the calculation means into the storage means,
When the compiler detects an instruction that refers to the predetermined computation result stored at a predetermined address of the storage means beyond a period until the predetermined computation result is overwritten by a later computation result, the An information processing method characterized in that an instruction for extending a period during which a predetermined operation result can be referenced is inserted into the instruction sequence . A program for causing a computer to execute each step of the information processing method according to claim 10 .

Images