JP7387232B2 - Semiconductor device, power conversion device, and method for manufacturing semiconductor device - Google Patents

Description

The present disclosure relates to a semiconductor device, a power conversion device, and a method for manufacturing a semiconductor device.

For example, in semiconductor devices for power control (power semiconductor devices), the common method for connecting electrode terminals that serve as external electrodes to an insulating substrate is to solder the electrode terminals onto a circuit pattern formed on an insulating substrate. It is true. Furthermore, power semiconductor devices that use plate-shaped wiring boards as wiring connected to semiconductor chips are increasing. A common method for connecting a semiconductor chip and a wiring board is to directly solder the wiring board to electrode pads formed on the semiconductor chip.

When a circuit pattern and an electrode terminal or an electrode pad and a wiring board are soldered together, cracks may occur in the joint due to distortion caused by temperature changes during the operation of the semiconductor device due to differences in linear expansion coefficients between the components. Occurrence and progression of these defects may lead to the end of the semiconductor device's lifespan. In particular, the effect becomes even greater in a high-temperature operating environment when a wide-gap semiconductor capable of high-temperature operation is mounted. Therefore, in recent years, methods have been proposed to directly bond circuit patterns and electrode terminals, or electrode pads and wiring boards, using ultrasonic bonding or laser welding.This method can extend the life of semiconductor devices. can.

However, the load and ultrasonic vibration during ultrasonic bonding, the heat and fusion depth during welding in laser welding, etc. can be factors that destroy the insulating layer of the insulating substrate and the element structure of the semiconductor chip. As a countermeasure, for example, Patent Document 1 below discloses that a metal plate is pre-soldered onto the circuit pattern, and electrode terminals are laser welded onto the metal plate to prevent the molten part from reaching the insulating layer. , techniques for suppressing breakdown of the insulating layer have been proposed.

Japanese Patent Application Publication No. 2008-205058

As described above, when a circuit pattern and an electrode terminal or an electrode pad and a wiring board are directly bonded by ultrasonic bonding or laser welding, the life of the semiconductor device can be extended. However, the heat and stress caused by ultrasonic bonding and laser welding can cause destruction of the insulating layer of the insulating substrate and the element structure of the semiconductor chip.

The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device that can suppress damage caused by stress and heat caused by ultrasonic bonding or laser welding.

A semiconductor device according to the present disclosure includes an insulating substrate having a circuit pattern, a semiconductor element mounted on the circuit pattern and having an electrode pad, a wiring board bonded to the electrode pad via a buffer layer, and the circuit pattern. at least one of the electrode terminals bonded to via a buffer layer, the thickness of the first conductive member which is the electrode pad or the circuit pattern is T1, and the second conductive member which is the wiring board or the electrode terminal. When the thickness of T2 is T2, and the thickness of the buffer layer interposed between the first conductive member and the second conductive member is T3, the sum of T1 and T3 is 1/2 or more of T2, The buffer layer on the circuit pattern is formed to have the same size and shape as the circuit pattern .

According to the present disclosure, the first conductive member (electrode pad or circuit pattern) and the second conductive member (wiring board or electrode terminal) are joined via the buffer layer, and the thickness of the first conductive member is T1. Since the sum of the thickness T3 of the buffer layer and the thickness T3 of the second conductive member is 1/2 or more of the thickness T2 of the second conductive member, stress and heat during bonding are prevented from damaging the semiconductor chip or the insulating substrate.

1 is a partial cross-sectional schematic diagram showing the structure of a semiconductor device according to Embodiment 1. FIG. FIG. 3 is a schematic partial cross-sectional view showing the structure of a semiconductor device according to a second embodiment. FIG. 7 is a schematic partial cross-sectional view showing the structure of a semiconductor device according to Embodiment 3; FIG. 3 is a block diagram showing the configuration of a power conversion system according to Embodiment 4. FIG.

<Embodiment 1>
FIG. 1 is a schematic partial cross-sectional view showing the structure of a semiconductor device according to a first embodiment. As shown in FIG. 1, the semiconductor device according to the first embodiment includes a semiconductor chip 2 mounted on an insulating substrate 1, a wiring board 5 which is a plate-shaped wiring connected to the semiconductor chip 2, and an external electrode. This is a power semiconductor device including an electrode terminal 8.

In the first embodiment, it is assumed that the semiconductor chip 2 is an IGBT (Insulated Gate Bipolar Transistor) chip using Si as a base material. However, the semiconductor chip 2 is not limited to an IGBT, and may be, for example, a FWD (Free Wheel Diode), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or the like. Further, the base material of the semiconductor chip 2 is not limited to Si, and may be a so-called wide bandgap semiconductor having a larger bandgap than Si, such as SiC (silicon carbide), GaN (gallium nitride-based material), or diamond.

The insulating substrate 1 includes an insulating layer 1a, a circuit pattern 1b formed on the upper surface of the insulating layer 1a, and a lower surface pattern 1c formed on the lower surface of the insulating layer 1a. Here, the material of the insulating layer 1a is ceramic, and the circuit pattern 1b and the lower surface pattern 1c are mainly made of Cu.

The semiconductor chip 2 is bonded onto the circuit pattern 1b of the insulating substrate 1 via a die bonding material 3 containing sinterable Cu particles. Further, the semiconductor chip 2 has electrode pads 2a on the upper surface. Here, it is assumed that the thickness of the electrode pad 2a is 10 μm, and the surface of the electrode pad 2a is plated with Ni/Au.

A buffer layer 4 made of sintered Cu particles is formed on the electrode pad 2a of the semiconductor chip 2. Here, the thickness of the buffer layer 4 is set to 0.5 mm. Hereinafter, the buffer layer 4 formed on the electrode pad 2a will be referred to as "the buffer layer 4 on the electrode pad".

The wiring board 5 is joined to the electrode pad 2a of the semiconductor chip 2 by laser welding via the buffer layer 4 on the electrode pad. Therefore, a wiring board welded portion 6 consisting of the wiring board 5 and the electrode pad buffer layer 4 melted during laser welding is formed at the joint between the wiring board 5 and the electrode pad buffer layer 4. Here, the main material of the wiring board 5 is Cu, and the thickness of the wiring board 5 is 0.8 mm.

A buffer layer 7 formed by sintering sinterable Cu particles is formed in the bonding region with the electrode terminal 8 in the circuit pattern 1b of the insulating substrate 1. Here, the thickness of the buffer layer 7 is 0.5 mm. Hereinafter, the buffer layer 7 formed on the circuit pattern 1b will be referred to as the "buffer layer 7 on the circuit pattern".

The electrode terminal 8 is joined to the circuit pattern 1b of the insulating substrate 1 by laser welding via the buffer layer 7 on the circuit pattern. Therefore, an electrode terminal welded portion 9 consisting of the electrode terminal 8 and the circuit pattern buffer layer 7 melted during laser welding is formed at the joint between the electrode terminal 8 and the circuit pattern buffer layer 7.

Although not shown, the semiconductor device of Embodiment 1 includes a structure that covers at least a portion of the circuit pattern 1b of the insulating substrate 1, the semiconductor chip 2, the wiring board 5, and the electrode terminal 8 in order to protect them. A sealant is provided. Further, the wiring board 5 is connected to another circuit pattern, an external electrode, etc. to constitute an internal circuit of the semiconductor device, and the electrode terminal 8 is connected to the external electrode.

Here, the conventional semiconductor device had a structure without the buffer layer 4 on the electrode pad and the buffer layer 7 on the circuit pattern. That is, in the conventional semiconductor device, the wiring board 5 is directly bonded to the electrode pad 2a of the semiconductor chip 2, and the electrode terminal 8 is directly bonded to the circuit pattern 1b.

In a conventional semiconductor device that does not have a buffer layer 4 on the electrode pad, when the wiring board 5 is laser welded to the electrode pad 2a, as the laser is irradiated, the wiring board welded part 6 generated in the wiring board 5 is attached to the electrode pad 2a. progress inward. At this time, if the wiring board weld 6 reaches the element structure of the semiconductor chip 2, the element structure of the semiconductor chip 2 will be destroyed due to the influence of the heat, and the semiconductor chip 2 may stop functioning or the semiconductor chip 2 may become damaged. A problem arises in that required electrical characteristics cannot be obtained. In order to prevent this, it is possible to reduce the laser output or shorten the irradiation time, but if this is done, the wiring board welded part 6 will not fully penetrate into the electrode pad 2a, and the desired bonding strength will not be obtained. There is a risk.

In conventional semiconductor devices, in order to perform laser welding so as not to destroy the element structure of the semiconductor chip 2 and to obtain the desired bonding strength between the wiring board 5 and the electrode pads 2a, the wiring board welded portion 6 is It is necessary to stop the progression within the electrode pad 2a, but since the electrode pad 2a is generally thinner than the wiring board 5, this control is very difficult and there is almost no latitude in the laser output conditions.

In contrast, in the semiconductor device of the first embodiment, wiring board 5 is bonded to electrode pad 2a via buffer layer 4 on the electrode pad. The buffer layer 4 on the electrode pad is a film obtained by printing or applying a bonding material containing sinterable Cu particles onto the electrode pad 2a and then sintering it by heating or applying heat and pressure. is joined to. Therefore, during laser welding, if the wiring board welded portion 6 is advanced from inside the wiring board 5 to the buffer layer 4 on the electrode pad, the bond between the wiring board 5 and the electrode pad 2a will be strong, and the desired A bonding strength of

In particular, the thickness of the buffer layer 4 on the electrode pad is set such that the total of the thickness of the electrode pad 2a and the thickness of the buffer layer 4 on the electrode pad is 1/2 (1/2) or more of the thickness of the wiring board 5. By adjusting the height, it becomes easy to control the laser output conditions so that the wiring board welded portion 6 does not reach the element structure of the semiconductor chip 2 during laser welding. In other words, the condition latitude for laser welding is expanded.

In addition, in a conventional semiconductor device that does not have a buffer layer 7 on a circuit pattern, when laser welding the electrode terminal 8 to the circuit pattern 1b, as the laser is irradiated, the electrode terminal welded part 9 generated in the electrode terminal 8 is connected to the circuit pattern 1b. It progresses into pattern 1b. At this time, if the electrode terminal welded portion 9 reaches the insulating layer 1a of the insulating substrate 1, the insulating layer 1a will be destroyed under the influence of the heat, and the insulation performance of the insulating substrate 1 will be impaired. In order to prevent this, it is possible to reduce the laser output or shorten the irradiation time, but if this is done, the electrode terminal welded part 9 will not fully penetrate into the circuit pattern 1b, and the desired bonding strength will not be obtained. There is a risk.

In a conventional semiconductor device, in order to perform laser welding so as not to damage the insulating layer 1a of the insulating substrate 1 and to obtain the desired bonding strength between the electrode terminal 8 and the circuit pattern 1b, it is necessary to 9 needs to be stopped within the circuit pattern 1b, but since the circuit pattern 1b is generally thinner than the electrode terminal 8, this control is extremely difficult. Therefore, in conventional semiconductor devices, measures have been taken to make the thickness of the circuit pattern 1b thicker than the optimal thickness for the current flowing through the semiconductor device, but this involves an increase in material costs.

In contrast, in the semiconductor device of the first embodiment, the electrode terminal 8 is bonded to the circuit pattern 1b via the buffer layer 7 on the circuit pattern. The buffer layer 7 on the circuit pattern is a film obtained by printing or applying a bonding material containing sinterable Cu particles on the circuit pattern 1b and then sintering it by heating or applying heat and pressure. is joined to. Therefore, during laser welding, if the electrode terminal welded portion 9 is advanced into the buffer layer 7 on the circuit pattern, the bond between the electrode terminal 8 and the circuit pattern 1b becomes strong, and the desired bond strength can be obtained. .

In particular, by adjusting the thickness of the buffer layer 7 on the circuit pattern so that the sum of the thickness of the circuit pattern 1b and the thickness of the buffer layer 7 on the circuit pattern is 1/2 or more of the thickness of the electrode terminal 8. In laser welding, it becomes easy to control the laser output conditions so that the electrode terminal welded portion 9 does not reach the element structure of the semiconductor chip 2. In other words, the condition latitude for laser welding is expanded.

As described above, in the semiconductor device according to the first embodiment, when the electrode pad 2a or the circuit pattern 1b is defined as the first conductive member and the wiring board 5 or the electrode terminal 8 is defined as the second conductive member, the first conductive member A buffer layer (the buffer layer 4 on the electrode pad or the buffer layer 7 on the circuit pattern) is provided between the member and the second conductive member. Furthermore, if the thickness of the first conductive member is T1, the thickness of the second conductive member is T2, and the thickness of the buffer layer interposed between the first conductive member and the second conductive member is T3, then the sum of T1 and T3 is is 1/2 or more of T2. This configuration provides the effects described above.

Further, as described above, the electrode pad buffer layer 4 is formed directly on the electrode pad 2a by printing or applying a bonding material containing sinterable Cu particles to the electrode pad 2a. Similarly, the buffer layer 7 on the circuit pattern is formed directly on the circuit pattern 1b by printing or applying a bonding material containing sinterable Cu particles to the circuit pattern 1b. Therefore, solder joints, which are factors that affect reliability, are eliminated at the joints between the electrode pads 2a and the wiring board 5, and between the circuit patterns 1b and the electrode terminals 8. Bonding reliability is improved. Further, the buffer layer 4 on the electrode pad and the buffer layer 7 on the circuit pattern have a print pattern, a coating position, a coating shape of the bonding material, etc., depending on the shape of the electrode pad 2a and the bonding position of the electrode terminal 8 in the circuit pattern 1b. It can be formed by changing as appropriate. Therefore, an increase in manufacturing costs can be suppressed compared to changing the thickness of the electrode pad 2a or the thickness of the circuit pattern 1b depending on the type of semiconductor device.

Furthermore, by controlling the Cu particle size and sintering conditions of the bonding material containing sinterable Cu particles used as the material for the electrode pad buffer layer 4 and the circuit pattern buffer layer 7, the electrode pad buffer layer 4 and the circuit pattern buffer layer 7 can be It is possible to intentionally form a void inside the buffer layer 7 on the circuit pattern. By including voids in the buffer layer 4 on the electrode pad and the buffer layer 7 on the circuit pattern, their thermal conductivity is reduced, and the heat during laser welding reaches the element structure of the semiconductor chip 2 and the insulating layer 1a of the insulating substrate 1. Since the transmission becomes difficult, destruction of the semiconductor chip 2 and the insulating layer 1a can be more effectively suppressed.

In this embodiment, a buffer layer (buffer layer 4 on the electrode pad or buffer layer 7 on the circuit pattern) is provided at both the joint between the wiring board 5 and the electrode pad 2a and the joint between the electrode terminal 8 and the circuit pattern 1b. Although a configuration is shown in which the buffer layer is provided, the buffer layer may be formed on only one of them. For example, a buffer layer may be provided only at joints where laser welding is difficult to control, or a buffer layer may be provided only at joints where joint reliability is insufficient.

Further, when the semiconductor chip 2 is based on a wide bandgap semiconductor, it is required to operate in a high temperature environment in order to take advantage of its advantages. This embodiment is effective in guaranteeing the life of the joint in a high-temperature environment, so it can be said to be particularly effective when the semiconductor chip 2 is made of a wide bandgap semiconductor.

In Embodiment 1, an example was shown in which the buffer layer (the buffer layer 4 on the electrode pad and the buffer layer 7 on the circuit pattern) is formed by sintering sinterable Cu particles, but the method for forming the buffer layer is is not limited to this. For example, it is also possible to form the buffer layer by a so-called cold spray method, in which a film is formed by colliding metal powder in a solid phase onto an object at supersonic speed using an inert gas as a working medium. When forming a buffer layer using the cold spray method, the position, thickness, and shape of the buffer layer can be adjusted to suit the type of semiconductor device by changing the mask during spraying and the operating trajectory of the spray gun. . Furthermore, since the cold spray method does not melt the raw metal powder, it is possible to form a buffer layer that is free from oxidation and thermal deterioration that would degrade the quality of the joint. Furthermore, by controlling the particle size of the metal powder material and the spray conditions, it is possible to intentionally form voids inside the buffer layer. Therefore, even when the buffer layer is formed by the cold spray method, the same effect as when using sinterable Cu particles can be obtained.

Note that when the buffer layer is formed by sintering, a metal material that can form a sintered body, such as Ag or Au, is used. When forming the buffer layer by the cold spray method, a metal material such as Al that can be formed into a film by the cold spray method is used.

Further, in the first embodiment, the main material of the wiring board 5 and the electrode terminals 8 is Cu, but the material is not limited to this. The wiring board 5 may be made of a material that can be laser welded to the buffer layer 4 on the electrode pad, and the electrode terminal 8 may be made of a material that can be laser welded to the buffer layer 7 on the circuit pattern. For example, if the main material of the wiring board 5 is the same as the main material of the buffer layer 4 on the electrode pad, the melting points of the buffer layer 4 on the electrode pad and the wiring board 5 will be the same, and the penetration depth of the welded part 6 of the wiring board will be the same. Easy to control. Similarly, if the main material of the electrode terminal 8 is the same as the main material of the buffer layer 7 on the circuit pattern, the melting points of the buffer layer 7 on the circuit pattern and the electrode terminal 8 will be the same, and the penetration depth of the welded part 9 of the electrode terminal will be the same. Easy to control.

Further, in the first embodiment, the surface of the electrode pad 2a of the semiconductor chip 2 is plated with Ni/Au, and the thickness of the electrode pad 2a is 10 μm, but the configuration of the electrode pad 2a is not limited to this. . The electrode pad 2a may be made of any material as long as the electrode pad buffer layer 4 can be bonded thereon.

Further, in the first embodiment, the thickness of the wiring board 5 is 0.8 mm, and the thickness of the buffer layer 4 on the electrode pad is 0.5 mm, but these thicknesses are not limited to these. If the sum of the thickness of the electrode pad 2a and the thickness of the buffer layer 4 on the electrode pad is 1/2 or more of the thickness of the portion of the wiring board 5 that is bonded to the electrode pad 2a, the condition tolerance of laser welding is satisfied. You can get a spreading effect.

Further, in the first embodiment, the thickness of the electrode terminal 8 was set to 0.8 mm, and the thickness of the buffer layer 7 on the circuit pattern was set to 0.5 mm, but these thicknesses are not limited to these. . If the sum of the thickness of the circuit pattern 1b and the thickness of the buffer layer 7 on the circuit pattern is 1/2 or more of the thickness of the part of the electrode terminal 8 that is joined to the circuit pattern 1b, the condition tolerance of laser welding is satisfied. You can get a spreading effect.

Further, in the first embodiment, the material of the insulating layer 1a of the insulating substrate 1 is made of ceramic, but it is not limited to this, and may be made of resin, for example. For example, the insulating substrate 1 may have a structure in which a circuit pattern 1b is provided on an insulating layer 1a of an insulating sheet made of resin.

<Embodiment 2>
FIG. 2 is a schematic partial cross-sectional view showing the structure of the semiconductor device according to the second embodiment. In FIG. 2, elements similar to those shown in FIG. 1 are denoted by the same reference numerals, so detailed explanation thereof will be omitted here.

In the second embodiment, the wiring board 5 is bonded to the electrode pad 2a of the semiconductor chip 2 by ultrasonic bonding via the buffer layer 4 on the electrode pad. Ultrasonic welding is a method of solid-state welding by applying ultrasonic vibrations while pressing a tool against the welding part to cause plastic flow at the welding interface. Therefore, on the upper surface of the joint between the wiring board 5 and the buffer layer 4 on the electrode pad, a wiring board joining part 10 having an uneven shape is formed by transferring the irregularities of the tip of the tool during ultrasonic bonding.

Further, the electrode terminal 8 is bonded to the circuit pattern 1b of the insulating substrate 1 via the buffer layer 7 on the circuit pattern by ultrasonic bonding. Therefore, on the upper surface of the joint between the electrode terminal 8 and the buffer layer 7 on the circuit pattern, an uneven electrode terminal joining part 11 is formed, to which the irregularities of the tip of the tool are transferred during ultrasonic bonding.

The other configurations are the same as in the first embodiment. That is, in the semiconductor device of the second embodiment, by applying ultrasonic power instead of a laser from above the wiring board 5 or the electrode terminal 8, the gap between the wiring board 5 and the buffer layer 4 on the electrode pad or This embodiment is different from the first embodiment in that the electrode terminal 8 and the buffer layer 7 on the circuit pattern are solid phase bonded.

When ultrasonically bonding thick materials such as the wiring board 5 and the electrode terminals 8, it is necessary to increase the bonding conditions of load and ultrasonic power (amplitude and frequency), which reduces mechanical stress due to friction in the bonded area. and thermal stress occurs. Furthermore, in a conventional semiconductor device that does not have the buffer layer 4 on the electrode pad and the buffer layer 7 on the circuit pattern, the element structure of the semiconductor chip 2 and the insulating layer 1a of the insulating substrate 1 are close to the bonding interface. Therefore, in the conventional semiconductor device, when the buffer layer 4 on the electrode pad is ultrasonically bonded onto the electrode pad 2a, the element structure of the semiconductor chip 2 may be destroyed by the heat and mechanical stress of the ultrasonic bond. . Further, when the electrode terminal 8 is ultrasonically bonded onto the circuit pattern 1b, there is a possibility that the insulating layer 1a of the insulating substrate 1 is destroyed by the heat and mechanical stress of the ultrasonic bonding.

In the semiconductor device of the second embodiment, wiring board 5 is bonded to electrode pad 2a via buffer layer 4 on the electrode pad. Since the distance from the bonding interface to the element structure of the semiconductor chip 2 increases by the thickness of the buffer layer 7 on the circuit pattern, the element structure of the semiconductor chip 2 is destroyed by the heat and mechanical stress of ultrasonic bonding. This will be prevented. In particular, it is effective to adjust the thickness of the buffer layer 4 on the electrode pad so that the sum of the thickness of the electrode pad 2a and the thickness of the buffer layer 4 on the electrode pad is 1/2 or more of the thickness of the wiring board 5. It is.

Further, the electrode terminal 8 is connected to the circuit pattern 1b via the buffer layer 7 on the circuit pattern. Since the distance from the bonding interface to the insulating layer 1a of the insulating substrate 1 increases by the thickness of the buffer layer 7 on the circuit pattern, the insulating layer 1a is not likely to be destroyed by the heat or mechanical stress of ultrasonic bonding. Prevented. In particular, it is effective to adjust the thickness of the buffer layer 7 on the circuit pattern so that the sum of the thickness of the circuit pattern 1b and the thickness of the buffer layer 7 on the circuit pattern is 1/2 or more of the thickness of the electrode terminal 8. It is.

<Embodiment 3>
FIG. 3 is a schematic partial cross-sectional view showing the structure of the semiconductor device according to the third embodiment. In FIG. 3, elements similar to those shown in FIG. 1 are denoted by the same reference numerals, so detailed explanation thereof will be omitted here.

In the semiconductor device according to the third embodiment, the buffer layer 7 on the circuit pattern is formed not only in the region of the circuit pattern 1b of the insulating substrate 1 that is bonded to the electrode terminal 8, but also uniformly over the entire circuit pattern 1b. ing. That is, the circuit pattern buffer layer 7 formed on the circuit pattern 1b has the same size and shape as the circuit pattern 1b. The other configurations are the same as in the first embodiment. Note that "the same" as used herein does not necessarily have to be completely the same, but also includes substantially the same. That is, it is sufficient that the buffer layer 7 on the circuit pattern covers almost the entire upper surface of the circuit pattern 1b.

According to the semiconductor device of the third embodiment, the same effect as when the thickness of the circuit pattern 1b on the insulating substrate 1 is increased can be achieved at lower cost. For example, by forming the on-circuit pattern buffer layer 7 on the current-carrying path of the circuit pattern 1b, the cross-sectional area of the current-carrying path becomes large, and the current capacity of the circuit pattern 1b can be increased. Since the buffer layer 7 on the circuit pattern is formed directly below, when the heat generated by the semiconductor chip 2 is radiated to the lower surface pattern 1c of the insulating substrate 1, the heat spreads more easily in the plane direction, improving heat radiation performance. . It is more effective to form the buffer layer 7 on the circuit pattern from Cu, which has high thermal conductivity.

In addition, when the semiconductor chip 2 is made of a wide bandgap semiconductor as a base material, it is possible to operate in a high temperature environment, and the current density can be increased and the size of the semiconductor chip 2 can be reduced. When the semiconductor chip 2 is miniaturized and its area becomes smaller, a problem may arise in which the heat dissipation performance deteriorates, so the effect of improving the heat dissipation performance in the third embodiment becomes more effective.

<Embodiment 4>
In this embodiment, the semiconductor device according to the first to third embodiments described above is applied to a power conversion device. Although the application of the semiconductor devices of Embodiments 1 to 3 is not limited to a specific power conversion device, hereinafter, as Embodiment 4, the semiconductor devices of Embodiments 1 to 3 are applied to a three-phase inverter. Let's explain the case.

FIG. 4 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.

The power conversion system shown in FIG. 4 includes a power source 100, a power conversion device 200, and a load 300. Power supply 100 is a DC power supply and supplies DC power to power conversion device 200. The power source 100 can be composed of various things, for example, it can be composed of a DC system, a solar battery, a storage battery, or it can be composed of a rectifier circuit or an AC/DC converter connected to an AC system. Good too. Moreover, the power supply 100 may be configured with a DC/DC converter that converts DC power output from a DC system into predetermined power.

Power conversion device 200 is a three-phase inverter connected between power supply 100 and load 300, converts DC power supplied from power supply 100 into AC power, and supplies AC power to load 300. As shown in FIG. 4, the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. It is equipped with

The load 300 is a three-phase electric motor driven by AC power supplied from the power converter 200. Note that the load 300 is not limited to a specific application, but is a motor installed in various electrical devices, and is used, for example, as a motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner.

The details of the power conversion device 200 will be explained below. The main conversion circuit 201 includes a switching element and a freewheeling diode (not shown), and when the switching element switches, it converts DC power supplied from the power supply 100 into AC power, and supplies the alternating current power to the load 300. Although there are various specific circuit configurations of the main conversion circuit 201, the main conversion circuit 201 according to the present embodiment is a two-level three-phase full bridge circuit, and has six switching elements and each switching element. It can be constructed from six freewheeling diodes arranged in antiparallel. At least one of each switching element and each freewheeling diode of main conversion circuit 201 is configured by semiconductor module 202 corresponding to any one of the first to third embodiments described above. The six switching elements are connected in series every two switching elements to constitute upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 201, are connected to the load 300.

Further, the main conversion circuit 201 includes a drive circuit (not shown) that drives each switching element, but the drive circuit may be built in the semiconductor module 202 or may be provided separately from the semiconductor module 202. It may be a configuration in which it is provided. The drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies it to the control electrode of the switching element of the main conversion circuit 201. Specifically, according to a control signal from a control circuit 203, which will be described later, a drive signal that turns the switching element on and a drive signal that turns the switching element off are output to the control electrode of each switching element. When keeping the switching element in the on state, the drive signal is a voltage signal (on signal) that is greater than or equal to the threshold voltage of the switching element, and when the switching element is kept in the off state, the drive signal is a voltage signal that is less than or equal to the threshold voltage of the switching element. signal (off signal).

Control circuit 203 controls switching elements of main conversion circuit 201 so that desired power is supplied to load 300. Specifically, based on the power to be supplied to the load 300, the time (on time) during which each switching element of the main conversion circuit 201 should be in the on state is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output. Then, a control command (control signal) is given to the drive circuit included in the main conversion circuit 201 so that an on signal is output to the switching element that should be in the on state at each time, and an off signal is output to the switching element that should be in the off state. Output. The drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.

In the power conversion device according to the present embodiment, since the semiconductor modules according to Embodiments 1 to 3 are applied as the switching elements and free wheel diodes of the main conversion circuit 201, reliability can be improved.

In this embodiment, an example in which the semiconductor devices of Embodiments 1 to 3 are applied to a two-level three-phase inverter is described, but the application of the semiconductor devices of Embodiments 1 to 3 is not limited to this. Therefore, it can be applied to various power conversion devices. In this embodiment, a two-level power converter is used, but a three-level or multi-level power converter may also be used, and in the case of supplying power to a single-phase load, a single-phase inverter is used. It is also possible to apply semiconductor devices 1 to 3. Furthermore, when power is supplied to a DC load or the like, the semiconductor devices of Embodiments 1 to 3 can be applied to a DC/DC converter or an AC/DC converter.

Further, the power conversion device to which the semiconductor devices of Embodiments 1 to 3 are applied is not limited to cases where the above-mentioned load is an electric motor, but is, for example, an electrical discharge machine, a laser processing machine, an induction heating cooker, It can also be used as a power supply device for a non-contact power supply system, and furthermore, it can be used as a power conditioner for a solar power generation system, a power storage system, etc.

Note that it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate.

1 Insulating substrate, 1a Insulating layer, 1b Circuit pattern, 1c Bottom pattern, 2 Semiconductor chip, 2a Electrode pad, 3 Die bond material, 4 Buffer layer on electrode pad, 5 Wiring board, 6 Wiring board welded part, 7 Buffer on circuit pattern layer, 8 electrode terminal, 9 electrode terminal welding part, 10 wiring board joint part, 11 electrode terminal joint part, 100 power supply, 200 power converter, 201 main conversion circuit, 202 semiconductor module, 203 control circuit, 300 load.

Claims (13)

an insulating substrate having a circuit pattern;
a semiconductor element mounted on the circuit pattern and having an electrode pad;
at least one of a wiring board bonded to the electrode pad via a buffer layer, and an electrode terminal bonded to the circuit pattern via a buffer layer;
Equipped with
The thickness of the first conductive member that is the electrode pad or the circuit pattern is T1, the thickness of the second conductive member that is the wiring board or the electrode terminal is T2, and the distance between the first conductive member and the second conductive member. If the thickness of the buffer layer interposed in is T3, the sum of T1 and T3 is 1/2 or more of T2,
The buffer layer formed on the circuit pattern has the same size and shape as the circuit pattern,
Semiconductor equipment. The buffer layer is a layer containing voids,
The semiconductor device according to claim 1. The main material of the buffer layer is the same as the main material of the second conductive member joined to the buffer layer.
The semiconductor device according to claim 1 or 2. The buffer layer is formed of a material having sinterability.
The semiconductor device according to any one of claims 1 to 3. The semiconductor element is formed of a wide bandgap semiconductor,
The semiconductor device according to any one of claims 1 to 4. A main conversion circuit that includes the semiconductor device according to any one of claims 1 to 5 and converts and outputs input power;
a control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit;
A power converter equipped with a step of bonding a semiconductor element to a circuit pattern formed on an insulating substrate;
At least one of the steps of: bonding a wiring board to the electrode pad of the semiconductor element via a buffer layer; and bonding an electrode terminal to the circuit pattern via a buffer layer;
Equipped with
The thickness of the first conductive member that is the electrode pad or the circuit pattern is T1, the thickness of the second conductive member that is the wiring board or the electrode terminal is T2, and the distance between the first conductive member and the second conductive member. If the thickness of the buffer layer interposed in is T3, the sum of T1 and T3 is 1/2 or more of T2,
The buffer layer on the circuit pattern is formed in the same size and shape as the circuit pattern,
A method for manufacturing a semiconductor device. The buffer layer and the second conductive member are joined by ultrasonic joining or laser welding,
The method for manufacturing a semiconductor device according to claim 7 . The buffer layer is a layer containing voids,
A method for manufacturing a semiconductor device according to claim 7 or 8 . The main material of the buffer layer is the same as the main material of the second conductive member joined to the buffer layer.
The method for manufacturing a semiconductor device according to any one of claims 7 to 9 . The buffer layer is formed of a material having sinterability.
The method for manufacturing a semiconductor device according to any one of claims 7 to 10 . The buffer layer is formed by a cold spray method.
The method for manufacturing a semiconductor device according to any one of claims 7 to 10 . The semiconductor element is formed of a wide bandgap semiconductor,
The method for manufacturing a semiconductor device according to any one of claims 7 to 12 .

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