JP7415650B2 - Load fluctuation test program and load fluctuation test method - Google Patents

Description

The present invention relates to a load variation test program and a load variation test method.

In recent years, computer system hardware has become highly densely packaged, and as a result, DC/DC converters (DDCs: Direct current Direct current Converters) have come to be mounted close to each power supply destination such as memory. Therefore, it has become difficult to arrange a circuit for suppressing voltage fluctuations, such as a capacitor, between the DDC and the power supply destination. In such a computer system, when current is supplied from the DDC to the power supply destination, the supply voltage fluctuates due to changes in the load of the DDC, which may have an adverse effect on the power supply destination.

Therefore, there is a need to detect circuit failures in the power supply source caused by DDC load fluctuations in computer systems, and several testing methods have been proposed. For example, there is a conventional technique in which a central processing unit periodically accesses a memory to which power is supplied and a cache memory to which power is not supplied by a program, thereby realizing load fluctuations in voltage. This conventional technology measures time by monitoring a timer at regular intervals, and provides periodicity between the time when the power is turned on and memory access is performed, and the time when the power is turned off and cache access is performed. .

Furthermore, there is a conventional technique in which a test is performed by increasing the current load by switching the access processing to the memory and cache using a timer interrupt. A timer interrupt is an interrupt that occurs when the timer value, which is the number of CPU (Central Processing Unit) clocks during running, becomes greater than the number of CPU clocks set as the timer interrupt value. The timer interrupt value is calculated from the desired period and CPU frequency.

Japanese Patent Application Publication No. 2007-221856 Japanese Patent Application Publication No. 2013-58038

However, in the case of the conventional technique in which a cycle is generated by performing timer monitoring at regular intervals, the frequency of memory access decreases because time monitoring processing is performed at regular intervals while memory access is being executed. As a result, the frequency of power supply from the DDC, which is the power sharing source, to the memory decreases. As described above, it has been difficult to balance time monitoring processing and memory access frequency, and it has been difficult to perform tests to detect power supply circuit failures caused by actual load fluctuations.

In addition, in the case of conventional technology that generates cycles using timer interrupts, if the cycles of load fluctuations are short, interrupt processing takes time, and the timer value set to generate the next interrupt is set to the current timer value. It may become smaller than that. In this case, the generation of subsequent interrupts will stop, making it difficult to continue generating the expected load fluctuation cycle.

The disclosed technology has been developed in view of the above, and aims to provide a load variation test program and a load variation test method that improve the effectiveness of power supply load variation tests.

In one aspect of the load variation test program and load variation test method disclosed in the present application, a computer is caused to execute the following processing. Generate a timer value from the CPU clock. A reference timer value is determined based on the set load fluctuation cycle. Obtain the current timer value at the time of making the determination. Based on the current timer value, it is determined whether or not to delay the occurrence of an interrupt at the timing according to the reference timer value. In the case of delay, the interrupt is generated by delaying the timing according to the reference timer value by a predetermined timer value based on the load fluctuation cycle.

In one aspect, the present invention can improve the effectiveness of power supply load variation tests.

FIG. 1 is a hardware configuration diagram of a computer to be tested in a load variation test. FIG. 2 is a block diagram showing each function generated by the test program for the load variation test. FIG. 3 is a flowchart of load fluctuation test processing. FIG. 4 is a flowchart showing details of the timer interrupt value setting process. FIG. 5 is a diagram for explaining calculation of a timer interrupt value when the next interrupt occurs in time for the next normal load change timing. FIG. 6 is a diagram for explaining calculation of a timer interrupt value when the next interrupt is not generated in time for the next normal load change timing. FIG. 7 is a diagram showing an example of load fluctuation in the entire load fluctuation test when the switching cycle is skipped. FIG. 8 is a diagram of a specific example of a load variation test conducted using the load variation test program according to the first embodiment. FIG. 9 is a diagram illustrating an example of load fluctuation according to the load fluctuation test program according to the second embodiment.

Embodiments of the load variation test program and load variation test method disclosed in the present application will be described in detail below based on the drawings. Note that the load variation test program and load variation test method disclosed in the present application are not limited to the following examples.

FIG. 1 is a hardware configuration diagram of a computer to be tested in a load variation test. The computer 1 is an example of an information processing device on which the load fluctuation test according to this embodiment is executed. The computer 1 has a CPU 10, a memory 20, a hard disk 30, and a DDC 40, as shown in FIG.

The hard disk 30 stores various programs including a test program for executing the load fluctuation test according to this embodiment.

The DDC 40 is a power source and requests power from the CPU 10, memory 20, and hard disk 30. The DDC 40 supplies power to the memory 20 when the CPU 10 accesses the memory 20. In this case, since the load on the memory 20 increases compared to when the cache 11 is accessed, the current flowing through the DDC 40 becomes larger than when the memory 20 is not accessed from the CPU 10.

The CPU 10 has a cache 11. The CPU 10 reads various programs stored in the hard disk 30 and expands them onto the memory 20 to generate various processes. Various functions are realized by processes generated by the CPU 10. For example, the CPU 10 reads a test program, expands it on the memory 20, and generates a load fluctuation test process. By operating this load variation test process, various functions for executing a load variation test, which will be described later, are realized, and the load variation test on the DDC 40 is executed.

Next, each process executed by the test program for executing the load variation test will be described with reference to FIG. 2. FIG. 2 is a block diagram showing each function generated by the test program for the load variation test. Each part described in FIG. 2 is realized through a load variation test process. The load variation test program realizes load variation by generating an interrupt. In the following, the interrupt that occurred immediately before and is currently being processed by the computer 1 will be referred to as the "current interrupt." This current interrupt is an example of a "previous interrupt." Furthermore, the interrupt that is processed next to the current interrupt is called the "next interrupt." This next interrupt is an example of an "interrupt."

The CPU 10 includes a clock generation section 300 and an interrupt register 400. When the test program for the load variation test is executed, a test condition setting section 100 and a test execution section 200 are generated, as shown in FIG.

The clock generation unit 300 generates a clock that is the operating frequency of the CPU 10. The clock generation unit 300 then outputs the generated clock.

Interrupt register 400 is a register that stores interrupts. An interrupt is generated by reading the interrupt stored in the interrupt register 400, and processing corresponding to the interrupt is performed. For example, in the case of an interrupt that switches between access to the memory 20 and access to the cache 11, the access to the memory 20 and the access to the cache 11 are switched by reading from the interrupt register 400 and generating the interrupt. It will be done.

The test condition setting unit 100 sets various conditions for executing a load variation test. The test condition setting section 100 includes a fluctuation period calculation section 101 and a timer interrupt setting section 102.

The fluctuation cycle calculation unit 101 acquires the clock output from the clock generation unit 300 and acquires the frequency of the CPU 10. Further, the fluctuation cycle calculation unit 101 acquires information on the load fluctuation cycle specified for the load fluctuation test. For example, the fluctuation cycle calculation unit 101 acquires information on the load fluctuation cycle input by a worker using an input device (not shown). Here, the load fluctuation cycle is a cycle in which the memory 20 and the cache 11 are accessed, and the total time of the access time to the memory 20 and the access time to the cache 11 is one cycle.

Next, the fluctuation cycle calculation unit 101 calculates a reference timer value, which is a reference for the timing at which an interrupt is generated, from the acquired load fluctuation cycle and the frequency of the CPU 10. Below, the reference timer value may be expressed as "A". This reference timer value (A) is a value expressed in the frequency of the CPU 10 as the normal interval from the timing when the access target is switched due to the occurrence of the current interrupt until the next interrupt occurs. That is, the reference timer value (A) is a value that is half the value expressed by the number of clocks of the CPU 10 representing the load fluctuation cycle.

For example, when the frequency of the CPU 10 is FHz and the specified load fluctuation period is Tp seconds, the fluctuation period calculation unit 101 calculates the reference timer value (A) as (Tp×F)/2. Then, the fluctuation cycle calculation unit 101 outputs the calculated reference timer value (A=(Tp×F)/2) to the timer interrupt setting unit 102 and the timer interrupt value adjustment unit 203 of the test execution unit 200.

The timer interrupt setting unit 102 receives input of the reference timer value (A) from the fluctuation cycle calculation unit 101. Next, the timer interrupt setting unit 102 obtains the start timer value (B) at the start of the load variation test from the clock generation unit 300. Then, the timer interrupt setting unit 102 calculates a timer interrupt value (T=B+A) for generating the next interrupt by adding the reference timer value (A) to the starting timer value (B). Then, the timer interrupt setting unit 102 sets an interrupt in the interrupt register 400 so that an interrupt occurs at the timer interrupt value (T).

Furthermore, the timer interrupt setting unit 102 receives from the timer interrupt value adjustment unit 203 an input of a timer interrupt value, which is the timing for generating the next interrupt after the first interrupt occurs. In the following, the timer interrupt value may be expressed as T. The timer interrupt setting unit 102 sets the next interrupt in the interrupt register 400 so that the next interrupt occurs with the acquired timer interrupt value (T).

For example, when the next interrupt occurs at a normal load fluctuation cycle, the timer interrupt setting unit 102 sets the timer interrupt value (T) by adding the reference timer value (A) to the current interrupt occurrence timing (t). is received from the timer interrupt value adjustment unit 203. Next, the timer interrupt setting unit 102 sets an interrupt in the interrupt register 400 so that the next interrupt occurs at the timer interrupt value (T=t+A).

On the other hand, if the next interrupt does not occur in the normal load fluctuation cycle, the timer interrupt setting unit 102 sets the timer interrupt setting unit 102 to the timer interrupt setting unit 102, which adds the value obtained by adding the delay to the reference timer value (A) to the current interrupt occurrence timing (t). The input of the interrupt value (T) is received from the timer interrupt value adjustment unit 203 . For example, the timer interrupt setting unit 102 calculates the current interrupt occurrence timing (t) by adding "A x 3", which is a value obtained by doubling the reference timer value (A), to the reference timer value (A). The timer interrupt value adjustment unit 203 receives an input of the timer interrupt value (t+A×3) added to the timer interrupt value. Twice the reference timer value (A) corresponds to one cycle of the load fluctuation cycle. Then, the timer interrupt setting unit 102 sets the interrupt so that the next interrupt occurs at the timer interrupt value (t+A×3) obtained by adding the timer value (A×3) to the current interrupt occurrence timing (t). Set the next interrupt in register 400. As a result, switching of the access destination occurs at the timing of the next load change after skipping one load change cycle.

The test execution unit 200 executes a load fluctuation test by periodically accessing the memory 20 and the cache 11 by alternately accessing the memory 20 or the cache 11 every time an interrupt occurs. do. Furthermore, the test execution unit 200 determines whether or not an interrupt can be executed in the next normal load fluctuation cycle, and determines the timer interrupt value for the next interrupt according to the determination result. Details of the test execution unit 200 will be explained below. As shown in FIG. 2, the test execution section 200 includes a memory access switching section 201, a timer value acquisition section 202, a timer interrupt value adjustment section 203, and a test execution time confirmation section 204.

The memory access switching unit 201 manages access to the memory 20 and the cache 11. The memory access switching unit 201 includes a memory access unit 211 and a cache access unit 212. The memory access switching unit 201 obtains an interrupt from the interrupt register 400 and generates the interrupt. At this time, the memory access switching unit 201 notifies the timer value acquisition unit 202 of the occurrence of the interrupt.

When an interrupt occurs, the memory access switching unit 201 switches between access to the memory 20 by the memory access unit 211 and access to the cache 11 by the cache access unit 212.

For example, if an interrupt occurs while the cache access unit 212 is accessing the cache 11, the cache access unit 212 stops accessing the cache 11. Then, the memory access unit 211 starts accessing the address on the memory 20 where data not stored in the cache 11 is stored. In this case, power is supplied to the memory 20 by the DDC 40. Hereinafter, an access to an address on the memory 20 where data not stored in the cache 11 is stored will be simply referred to as an "access to the memory 20." Thereafter, the memory access unit 211 continues accessing the memory 20 until the next interrupt occurs.

On the other hand, if an interrupt occurs while the memory access unit 211 is accessing the memory 20, the memory access unit 211 stops accessing the memory 20. Then, the cache access unit 212 starts accessing the address where the data in the cache 11 is stored. In this case, the cache access unit 212 accesses the cache 11 and does not access the memory 20. Therefore, the power supply to the memory 20 by the DDC 40 is stopped. Hereinafter, an access to an address where data stored in the cache 11 is simply referred to as an "access to the cache 11." Thereafter, the cache access unit 212 continues accessing the cache 11 until the next interrupt occurs.

Since interrupts normally occur at intervals of the reference timer value, the access to the memory 20 by the memory access unit 211 and the access to the cache 11 by the cache access unit 212 are repeated at normal load fluctuation cycles. Further, when a delay is added to the timing of occurrence of an interrupt, switching between access to the memory 20 by the memory access unit 211 and access to the cache 11 by the cache access unit 212 is delayed by the delay.

The timer value acquisition unit 202 receives notification of the occurrence of an interrupt from the memory access switching unit 201. Then, the timer value acquisition unit 202 acquires the timer value at the timing of the notification from the clock generation unit 300. Hereinafter, the timer value acquired by the timer value acquisition unit 220 may be referred to as a "current timer value", with the timing of determination being the current time. Below, the current timer value may be expressed as "C". Then, the timer value acquisition unit 202 outputs the current timer value (C) to the timer interrupt value adjustment unit 203.

The timer interrupt value adjustment unit 203 receives input of the reference timer value (A) from the fluctuation period calculation unit 101. The timer interrupt value adjustment unit 203 then stores the reference timer value (A). Further, the timer interrupt value adjustment unit 203 holds a time interrupt value (T) for generating the next interrupt, which is calculated as described later, as the current interrupt generation timing (t). This current interrupt occurrence timing (t) is an example of the "occurrence timer value".

Thereafter, when determining the next interrupt generation timing, the timer interrupt value adjustment unit 203 receives the current timer value (C) from the timer value acquisition unit 202. Next, the timer interrupt value adjustment unit 203 calculates the timer value of the next interrupt occurrence timing in the normal load fluctuation cycle by adding the reference timer value (A) to the current interrupt occurrence timing (t). . Hereinafter, the timer value of the next interrupt generation timing in the normal load fluctuation cycle may be referred to as the "normal time timer value." The timer interrupt value adjustment unit 203 then compares the current timer value (C) with the normal timer value to determine whether the next interrupt will occur in time for the next load change in the normal load change cycle. Determine whether If the next interrupt occurs in time for the next load change in the normal load change cycle, timer interrupt value adjustment section 203 outputs the normal timer value as a timer interrupt value to timer interrupt setting section 102. .

On the other hand, if the occurrence of the next interrupt is not in time for the timing of the next load change in the normal load variation cycle, the timer interrupt value adjustment unit 203 determines to add a delay to the timing of the occurrence of the next interrupt. . Then, the timer interrupt value adjustment unit 203 uses the reference timer value (A) to determine the amount of delay to be added to generate the next interrupt. Then, the timer interrupt value adjustment unit 203 sets the timer interrupt as the timer interrupt value of the next interrupt by adding the reference timer value (A) and the current interrupt occurrence timing (t) to the determined delay amount. It outputs to section 102.

For example, the timer interrupt value adjustment unit 203 adds the reference timer value (A) to the current interrupt occurrence timing (t) to calculate "t+A" as the normal timer value.

Then, the timer interrupt value adjustment unit 203 determines whether the normal timer value (t+A) is later than the current timer value (C), that is, whether C<t+A. If the normal timer value (t+A) is later than the current timer value (C) (C<t+A), the next interrupt will occur in time for the next load change in the normal load change cycle, so the timer interrupt The input value adjustment unit 203 sets the normal timer value (t+A) as the timer interrupt value. Then, the timer interrupt value adjustment unit 203 outputs the normal timer value (t+A) to the timer interrupt setting unit 102 as a timer interrupt value.

On the other hand, if the normal timer value (t+A) is ahead of the current timer value (C) (C≧t+A), the next interrupt will not occur in time for the next load change in the normal load change cycle. , the timer interrupt value adjustment unit 203 determines the delay in generating the next interrupt. Then, the timer interrupt value adjustment unit 203 adds one cycle to the reference timer value (A) in order to generate the next interrupt at the timing of the next load variation after one cycle of the next load variation cycle has elapsed. A timer value (A x 3) is calculated by adding the timer value (A x 2) of . Then, the timer interrupt value adjustment unit 203 sets the timer interrupt value (T) to t+A×3, which is the timer value obtained by adding the calculated timer value (A×3) to the current interrupt occurrence timing (t). . The timer interrupt value adjustment unit 203 outputs a timer interrupt value having a value of t+A×3 to the timer interrupt setting unit 102.

Here, in the present embodiment, if the occurrence of the next interrupt is not in time for the next normal load fluctuation cycle, the timer interrupt value adjustment unit 203 transmits the next interrupt after one cycle of the load fluctuation cycle has elapsed. It occurred at the timing of the next load change. However, the amount of delay is not limited to this, and the timer interrupt value adjustment unit 203 may generate the next interrupt at another timing as long as the load fluctuation cycle can be maintained. For example, the timer interrupt value adjustment unit 203 may generate the next interrupt at the timing of the next load change after two load change cycles have elapsed. However, if the next interrupt timing is delayed, the load fluctuations performed in the load fluctuation test will be reduced, so it is preferable to generate the next interrupt as early as possible.

The test execution time confirmation unit 204 monitors the elapsed time from the start of the test using the clock output from the clock generation unit 300. Then, if the elapsed time has not reached the predetermined test execution time, the test execution time confirmation unit 204 causes the memory access switching unit 201 to continue periodically accessing the memory 20 and the cache 11 alternately.

On the other hand, when the elapsed time reaches the test execution time, the test execution time confirmation unit 204 stops the memory access switching unit 201 from accessing the memory 20 and the cache 11, and ends the test.

Next, the overall flow of the load fluctuation test process will be explained with reference to FIG. FIG. 3 is a flowchart of load fluctuation test processing.

The fluctuation period calculation unit 101 acquires the CPU frequency (F) from the clock generation unit 300 (step S1).

Next, the fluctuation cycle calculation unit 101 obtains a load fluctuation cycle (Tp) based on input from the operator or the like (step S2).

Next, the fluctuation period calculation unit 101 uses the CPU frequency (F) to obtain a timer value (T×F) representing the load fluctuation period (Tp). Then, the fluctuation cycle calculation unit 101 calculates a reference timer value (A=(T×F)/2), which is the switching interval between access to the memory 20 and access to the cache 11 (step S3). Then, the fluctuation period calculating section 101 outputs the calculated reference timer value (A) to the timer interrupt setting section 102 and the timer interrupt value adjusting section 203. The timer interrupt setting unit 102 and the timer interrupt value adjustment unit 203 receive input of the reference timer value (A) from the fluctuation cycle calculation unit 101.

Next, the timer interrupt setting unit 102 obtains the start timer value (B) from the clock generation unit 300. Further, the timer interrupt setting unit 102 obtains a reference timer value (A) from the fluctuation cycle calculation unit 101. Then, the timer interrupt setting unit 102 calculates the timer interrupt value (T) of the first interrupt by adding the reference timer value (A) to the starting timer value (B). Then, the timer interrupt setting unit 102 sets the interrupt register 400 so that the first interrupt occurs at the timer interrupt value (T). As a result, an interrupt for switching the access destination is started (step S4). The memory access switching unit 201 obtains the interrupt stored in the interrupt register 400 as a timer interrupt value (T), and switches the access destination.

The timer value acquisition unit 202 acquires the current timer value (C) from the clock generation unit 300 (step S5). Then, the timer value acquisition unit 202 outputs the acquired current timer value (C) to the timer interrupt value adjustment unit 203. The timer interrupt value adjustment unit 203 receives input of the current timer value (C) from the timer value acquisition unit 202.

Next, the timer interrupt value adjustment unit 203 adds the reference timer value (A) to the current interrupt occurrence timing (t) to calculate the normal timer value (t+A). Then, the timer interrupt value adjustment unit 203 compares the current timer value (C) and the normal timer value (t+A), and determines whether the next interrupt will occur at the timing of the next load change in the normal load change cycle. It is determined whether or not it will be on time (step S6).

If the occurrence of the next interrupt is in time for the timing of the next load variation in the normal load variation cycle (step S6: affirmative), the timer interrupt value adjustment unit 203 sets the reference timer value to the timing (t) of occurrence of the current interrupt. The normal timer value (t+A) obtained by adding (A) is calculated as the timer interrupt value (T). Then, the timer interrupt value adjustment unit 203 outputs the timer interrupt value (T), which is the normal timer value (t+A), to the timer interrupt setting unit 102. The timer interrupt setting unit 102 obtains the timer interrupt value (T), which is the normal timer value (t+A), from the timer interrupt value adjustment unit 203. In this case, the timer interrupt value (T) is the timing of the next normal load fluctuation cycle. Then, the timer interrupt setting unit 102 sets the next interrupt in the interrupt register 400 so that it will occur at the next normal load fluctuation cycle (step S7).

On the other hand, if the occurrence of the next interrupt is not in time for the timing of the next normal load fluctuation cycle (step S6: negative), the timer interrupt value adjustment unit 203 adjusts the load fluctuation cycle to the reference timer value (A). A×3, which is a timer value with one cycle of delay added, is calculated. Next, the timer interrupt value adjustment unit 203 sets the timer interrupt value (T) to the value (t+A×3) obtained by adding the calculated timer value (A×3) to the current interrupt occurrence timing (t). . That is, in this case, the timer interrupt value (T) is the timing of the next load change after one load change cycle has elapsed. Then, the timer interrupt value adjustment unit 203 outputs the timer interrupt value (T), which is the calculated timer value (t+A×3), to the timer interrupt setting unit 102. The timer interrupt setting unit 102 receives an input of a timer interrupt value (T), which is a timer value (t+A×3), from the timer interrupt value adjustment unit 203. Then, the timer interrupt setting unit 102 sets the next interrupt in the interrupt register 400 so that it occurs at the timing of the next load change after one load change cycle has passed (step S8).

The memory access switching unit 201 obtains the next interrupt from the interrupt register 400 at the set timer interrupt value (T) and generates an interrupt. Then, the memory access switching unit 201 switches between access to the memory 20 by the memory access unit 211 and access to the cache 11 by the cache access unit 212, triggered by the occurrence of an interrupt at the set timer interrupt value (T). The switching is performed (step S9).

The test execution time confirmation unit 204 acquires the elapsed time from the start of the load fluctuation test from the clock generation unit 300. Then, the test execution time confirmation unit 204 determines whether to end the load variation test based on whether the elapsed time from the start of the load variation test has reached the test execution time (step S10).

If the load fluctuation test is not completed (step S10: negative), the test execution time confirmation unit 204 causes the memory access switching unit 201 to continue the process of switching the access destination. Then, the load fluctuation test process returns to step S5.

On the other hand, if the load variation test is to be ended (step S10: affirmative), the test execution time confirmation unit 204 stops the access destination switching process by the memory access switching unit 201 and ends the load variation process.

Next, details of the timer interrupt value setting process will be described with reference to FIG. FIG. 4 is a flowchart showing details of the timer interrupt value setting process.

The fluctuation period calculation unit 101 calculates a reference timer value (A) using the CPU frequency (F) and the load fluctuation period (Tp) (step S101). The timer interrupt setting unit 102 and the timer interrupt value adjustment unit 203 acquire the reference timer value (A) from the fluctuation cycle calculation unit 101.

Next, the fluctuation cycle calculation unit 101 adds the reference timer value (A) to the starting timer value (B) to calculate the first timer interrupt value (T=B+A). Then, the fluctuation cycle calculation unit 101 sets an interrupt in the interrupt register 400 so that it occurs at the first timer interrupt value (T) (step S102).

The next interrupt occurs at the set timer interrupt value (T), and the DDC 40 turns on the power to the memory 20 and starts supplying power. If the cache access unit 212 is accessing the cache 11, it stops the access. The memory access unit 211 then accesses the memory 20 (step S103).

After that, the memory access switching unit 201 obtains an interrupt from the interrupt register 400 and generates the interrupt (step S104). At this time, the memory access switching unit 201 notifies the timer value acquisition unit 202 of the occurrence of the interrupt.

The timer value acquisition unit 202 receives the notification of the occurrence of the interrupt and acquires the current timer value (C) from the clock generation unit 300. The timer interrupt value adjustment unit 203 receives the input of the current timer value (C) from the timer value acquisition unit 202 (step S105).

Next, the timer interrupt value adjustment unit 203 calculates a normal timer value (t+A) by adding the reference timer value (A) to the current interrupt occurrence timing (t). Then, the timer interrupt value adjustment unit 203 determines whether the normal timer value (t+A) is after the current timer value (C), that is, whether C is smaller than t+A (step S106).

Here, the case where C is smaller than t+A will be explained with reference to FIG. FIG. 5 is a diagram for explaining calculation of a timer interrupt value when the next interrupt occurs in time for the next normal load change timing. In FIG. 5, the vertical axis represents current, and the horizontal axis represents the passage of time. The value of the current increases toward the top of the page. A state where the current is high represents a state where the power to the memory 20 by the DDC 40 is on, and a state where the current is low represents a state where the power to the memory 20 by the DDC 40 is off.

In the case of a normal load fluctuation cycle, the access period to the memory 20 corresponds to the reference timer value (A). Similarly, the access period to the cache 11 corresponds to the reference timer value (A). Therefore, as shown in Figure 5, the normal timer value, which is the timer value (t+A) obtained by adding the reference timer value (A) to the current interrupt occurrence timing (t), is the next time in the normal load fluctuation cycle. This is the timing of load fluctuations. In this case, the timing of the next load change is the timing at which the power is turned off. As shown in Figure 5, the current timer value (C) at the time of making this determination is smaller than the timer value (t+A), which means that the timing of the next load change in the normal load change cycle is indicates that a judgment is being made. That is, at present, it is possible to generate the next interrupt at the timing of normal load fluctuations.

Therefore, the explanation will be continued by returning to FIG. 4. If C is smaller than t+A (step S106: affirmative), the timer interrupt value adjustment unit 203 determines that the next interrupt will occur in time for the next load change in the normal load change cycle. Then, the timer interrupt value adjustment unit 203 sets the normal timer value (t+A), which is the timer value (t+A) obtained by adding the reference timer value (A) to the current interrupt occurrence timing (t), as the timer interrupt value. It is output to the set section 102. The timer interrupt setting unit 102 sets the next interrupt in the interrupt register 400 so that it occurs at the acquired timer interrupt value (T=t+A) (step S107). As a result, as shown in FIG. 5, the next interrupt occurs when the timer value reaches t+A, the DDC 40 is powered off, and access to the cache 11 is switched.

Next, the case where C is greater than or equal to t+A will be described with reference to FIG. FIG. 6 is a diagram for explaining calculation of a timer interrupt value when the next interrupt is not generated in time for the next normal load change timing. In FIG. 6, the vertical axis represents the current, and the horizontal axis represents the passage of time.

As shown in FIG. 6, the timing of the timer value (t+A) obtained by adding the reference timer value (A) to the current interrupt generation timing (t) corresponds to the timing of the next load fluctuation in the normal load fluctuation cycle. In this case, the timing of the next load change is the timing at which the power is turned off. The fact that the current timer value (C) at the time of making this determination is greater than or equal to the timer value (t+A) means that the timing of the next load change in the normal load change cycle has already been determined at this point, as shown in Figure 6. It means that it has passed. That is, at present, it is difficult to generate the next interrupt at the timing of the normal load fluctuation cycle. From the current point of view, the timing of the next power off is the timing of the next load fluctuation after one load fluctuation period has elapsed. That is, the timing at which the timer value becomes t+A×3 is the next power-off timing in the load fluctuation cycle.

Therefore, the explanation will be continued by returning to FIG. 4. If C is greater than or equal to t+A (step S106: negative), the occurrence of the next interrupt will not be in time for the timing of the next load change in the normal load change cycle, so the timer interrupt value adjustment unit 203 prevents the occurrence of the next interrupt. Determine timing delays. Next, the timer interrupt value adjustment unit 203 adds the timer value (A x 2) for one cycle of the load fluctuation cycle to the reference timer value (A) and adds the value (A x 3) to the current interrupt value. It is added to the timing (t) and the added value (t+A×3) is set as the timer interrupt value (T) of the next interrupt. Then, the timer interrupt value adjustment unit 203 outputs the calculated timer interrupt value (T=t+A×3) to the timer interrupt setting unit 102. The timer interrupt setting unit 102 sets the next interrupt in the interrupt register 400 so that it occurs at the obtained timer interrupt value (T=t+A×3) (step S108). As a result, as shown in FIG. 6, the next interrupt occurs at the timing when the timer value is t+A×3, the DDC 40 is powered off, and access to the cache 11 is switched. In this case, the load fluctuation represented by the broken line 50 in FIG. 6 is omitted.

An interrupt occurs at the set timer interrupt value (T) of the next interrupt, and the DDC 40 turns off the power to the memory 20 and stops supplying power. The memory access unit 211 stops accessing the memory 20. The cache access unit 212 accesses the cache 11 (step S109).

After that, the memory access switching unit 201 obtains an interrupt from the interrupt register 400 and generates the interrupt (step S110). The memory access switching unit 201 notifies the timer value acquisition unit 202 of the occurrence of an interrupt.

The timer value acquisition unit 202 receives the notification of the occurrence of the interrupt and acquires the current timer value (C) from the clock generation unit 300. The timer interrupt value adjustment unit 203 receives input of the current timer value (C) from the timer value acquisition unit 202. Furthermore, the timer interrupt value adjustment unit 203 acquires the current interrupt occurrence timing (t) from the timer interrupt setting unit 102 (step S111).

Next, the timer interrupt value adjustment unit 203 calculates a normal timer value (t+A) by adding the reference timer value (A) to the current interrupt occurrence timing (t). Then, the timer interrupt value adjustment unit 203 determines whether the normal timer value (t+A) is after the current timer value (C), that is, whether C is smaller than t+A (step S112).

If C is smaller than t+A (step S112: affirmative), the timer interrupt value adjustment unit 203 determines that the next interrupt will occur in time for the next load change in the normal load change cycle. Then, the timer interrupt value adjustment unit 203 adds the reference timer value (A) to the current interrupt occurrence timing (t), and sets the added value (t+A) as the timer interrupt value (T) of the next interrupt. shall be. Timer interrupt value adjustment section 203 outputs the calculated timer interrupt value (T=t+A) to timer interrupt setting section 102. The timer interrupt setting unit 102 sets the next interrupt in the interrupt register 400 so that it occurs at the acquired timer interrupt value (T=t+A) (step S113). The determination process in this case is represented by reversing the on/off state of the power supply in FIG.

On the other hand, if C is greater than or equal to t+A (step S112: negative), the occurrence of the next interrupt will not be in time for the timing of the next load change in the normal load change cycle, so the timer interrupt value adjustment unit 203 Determines the delay for the next interrupt to occur. Then, the timer interrupt value adjustment unit 203 calculates a timer value (A×3) by adding the timer value (A×2) for one cycle of the load fluctuation cycle to the reference timer value (A). Next, the timer interrupt value adjustment unit 203 adds the calculated timer value (A x 3) to the current interrupt occurrence timing (t) and sets the calculated timer value (t+A x 3) to the timer value of the next interrupt. Let it be the interrupt value (T). The timer interrupt value adjustment unit 203 outputs the calculated timer interrupt value (T=t+A×3) to the timer interrupt setting unit 102. The timer interrupt setting unit 102 sets an interrupt in the interrupt register 400 so that it occurs at the acquired timer interrupt value (T=t+A×3) (step S114). The determination process in this case is represented by reversing the on/off state of the power supply in FIG.

Thereafter, the test execution time confirmation unit 204 compares the elapsed time from the start of the test with the test execution time, and determines whether the test execution time has elapsed (step S115). If the test execution time has not elapsed (step S115: negative), the process returns to step S103. On the other hand, if the test execution time has elapsed (step S115: affirmative), the test execution time confirmation unit 204 ends the load variation test.

FIG. 7 is a diagram showing an example of load fluctuation in the entire load fluctuation test when the switching cycle is skipped. When adjusting the timer interrupt value, the timer interrupt value adjustment unit 203 omits switching for one cycle. However, in the load variation test, the memory access switching unit 201 performs access switching tens of thousands of times. Therefore, as shown in FIG. 7, the omitted load variation is small compared to the load variation of the entire load variation test. Furthermore, since the frequency of adjusting the timer interrupt value for the entire load variation test is small, the effect of omitting load variation in the load variation test program according to this embodiment is small, and the load variation test can be performed accurately. .

FIG. 8 is a diagram of a specific example of a load variation test conducted using the load variation test program according to the first embodiment. In FIG. 8, the vertical axis represents the current, and the horizontal axis represents the passage of time. Here, a case will be explained in which the CPU 10 is a single processor with a frequency of 100 MHz, the load fluctuation period to be created is 1 μsec, and the test execution time is 100 seconds.

The fluctuation cycle calculation unit 101 calculates a reference timer value from the frequency of the CPU 10. Here, since the frequency of the CPU 10 is 100 MHz and the load fluctuation cycle to be created is 1 μsec, the fluctuation cycle calculation unit 101 sets the reference timer value to 1×10 ⁻⁶ ×100/2×10 ⁻⁶ = 50. calculate.

The timer interrupt setting unit 102 executes the following process in order to start load fluctuation with a load fluctuation period of 1μ. The timer interrupt setting unit 102 obtains 10 from the clock generation unit 300 as a starting timer value. Next, the timer interrupt setting unit 102 adds the reference timer value to the start timer value and calculates the timer interrupt value for generating the first interrupt by 10+50. Then, the timer interrupt setting unit 102 sets an interrupt in the interrupt register 400 so that it occurs at a timer interrupt value of 60.

The memory access unit 211 repeatedly accesses the memory 20 during a period T2 from timing T1 when the timer value, which is the starting timer value, is 10. During this time, the DDC 40 turns on the power to the memory 20 at timing T3. Then, when the timer value reaches timing T3 of 60, an interrupt occurs and the memory access unit 211 stops accessing the memory 20. The DDC 40 turns off the power to the memory 20 at timing T3.

The cache access unit 212 repeatedly accesses the cache 11 during a period T4 from timing T3 until an interrupt occurs. In this case, the DDC 40 turns off the power to the memory 20.

Next, the timer value acquisition unit 202 acquires 70 as the current timer value at timing T5.

The timer interrupt value adjustment unit 203 starts adjusting the timer interrupt value for the next interrupt at timing T5. Since the current interrupt generation timing is 60 and the reference timer value is 50, the normal timer value is 60+50. Since the current timer value is 70, the current timer value is smaller than the normal timer value because 70<60+50. Therefore, since the next interrupt will occur in time for the next normal load change, the timer interrupt value adjustment unit 203 sets the timer interrupt value of the next interrupt to 60+50=110, which is the normal timer value. .

Then, when the timer value reaches timing T6 of 110, an interrupt occurs and the cache access unit 212 stops accessing the cache 11. The DDC 40 turns on the power to the memory 20 at timing T6.

The memory access unit 211 repeatedly accesses the memory 20 from timing T6. During this time, the DDC 40 turns on the power to the memory 20.

Next, the timer value acquisition unit 202 acquires 180 as the current timer value at timing T8.

The timer interrupt value adjustment unit 203 starts adjusting the timer interrupt value for the next interrupt at timing T8. Since the current interrupt generation timing is 110 and the reference timer value is 50, the normal timer value is 110+50. Since the current timer value is 180, the current timer value is larger than the normal timer value because 180≧110+50. That is, at this point, the timing of the next normal load fluctuation cycle has already passed. Therefore, since the occurrence of the next interrupt will not be in time for the timing of the next normal load fluctuation, the timer interrupt value adjustment unit 203 interrupts the timer interrupt in order to generate an interrupt divided into one cycle of the load fluctuation cycle. Let the value be 110+50×3=260.

The test execution time checking unit 204 acquires the current timer value and checks whether the test execution time of 100 seconds, that is, the timing at which the timer value becomes 1×10 ⁸ has not been exceeded. Since the current timer value is 180 and has not exceeded the test execution time, the test execution time confirmation unit 204 causes the memory access switching unit 201 to continue alternately accessing the memory 20 and the cache 11. Thereafter, when the timer value reaches 260, an interrupt occurs again.

As described above, the load fluctuation test program according to this embodiment causes the computer under test to periodically access the memory or cache using a timer interrupt. Then, when determining the timer interrupt value for the next interrupt, the load change test program compares the timer value at that point with the timing of the next load change in the normal load change cycle, and then determines the timer interrupt value for the next interrupt. The computer determines whether or not the occurrence of the load change is in time for the next load change in the normal load change cycle. If the next interrupt is not generated in time for the next load change in the normal load change cycle, the load change test program will generate the next interrupt at the next load change after one load change cycle. let

As a result, by not performing timer monitoring during memory access, it is possible to reduce the decrease in memory access frequency, and it is possible to synchronize time monitoring processing and memory access processing. Furthermore, even if it is difficult to change the load at the timing of the normal load change cycle, it is possible to continue creating the load change. In other words, it is possible to improve the effectiveness of time monitoring processing and power supply load variation tests.

The load variation test program according to this embodiment executes a load variation test using a plurality of cores. In this embodiment, a case will be explained in which the computer 1 has cores #1 to #3 as the CPU 10, each operating at a frequency of 100 MHz. In this case as well, the load fluctuation period to be created is 1 μsec. Further, the test execution time was 100 seconds.

FIG. 9 is a diagram illustrating an example of load fluctuation according to the load fluctuation test program according to the second embodiment. FIG. 9 is a graph showing load fluctuations for each of cores #1 to #3 in order from the top toward the page. Moreover, the graph at the bottom of FIG. 9 represents the overall load fluctuation of the computer 1 in the load fluctuation test according to this embodiment. In each graph in FIG. 9, the vertical axis represents current, and the horizontal axis represents time passage.

The load variation test program according to this embodiment generates each function shown in FIG. 2 for each core #1 to #3. Then, the load variation test program causes each core #1 to #3 to independently execute the load variation test described in the first embodiment.

Therefore, even if the next interrupt does not occur in time for the next load change in the normal load change cycle in any of cores #1 to #3, the next interrupt will not occur in time for the other cores. It may be possible to arrive in time for the timing of the next load change after the load change cycle.

For example, in FIG. 9, core #1 does not switch to accessing the memory 20 at the time when the timer value is 110, skips one cycle of the load fluctuation cycle, and maintains the normal load fluctuation cycle. Not yet. However, in other cores #2 and #3, an interrupt occurs at the timing when the timer value is 110, switching to accessing the memory 20 is performed, and the normal load fluctuation cycle is maintained.

In this case, as shown in the graph at the bottom of the graph, the load fluctuation of the entire computer 1 is affected by the fact that the core 1 does not access the memory 20 in the second access to the memory 20 in the load fluctuation cycle. decreases. However, as a whole, there is no load on the DDC 40, and even in the second access to the memory 20 in the load variation cycle, the load variation test by the load variation test program is executed, and the test purpose cannot be achieved. ing.

Further, although the present embodiment has been described with reference to the case where there are three cores, the load variation test program according to the present embodiment can perform tests in the same way regardless of the number of cores. As the number of cores increases, the effect of omitting the cycle of load fluctuation in any one core can be reduced.

As described above, the load variation test program according to the present embodiment can independently execute load variation tests on a plurality of cores at the same time. As a result, it is possible to reduce the effect of omitting the load fluctuation cycle on the entire computer to be tested, and it is possible to increase the effectiveness of time monitoring processing and power supply load fluctuation tests.

Note that the load fluctuation test program for realizing the functions of the test condition setting section 100 and the test execution section 200 illustrated in FIG. 2 does not necessarily have to be stored in the hard disk 30 from the beginning as described above. . For example, each program is stored in a "portable physical medium" such as a flexible disk inserted into the computer 1, a so-called CD (Compact Disc), a DVD (Digital Versatile Disc), a magneto-optical disk, an IC (Integrated Circuit) card, etc. let Then, the CPU 10 of the computer 1 may acquire each program from these portable physical media and execute it. In addition, each program may be stored in another computer or server device connected to the computer 1 via a public line, the Internet, a LAN (Local Area Network), a WAN (Wide Area Network), etc., and the computer 1 may store these programs. Alternatively, each program may be obtained from and executed.

1 computer 10 CPU
11 Cache 20 Memory 30 Hard disk 40 DDC
100 Test condition setting section 101 Fluctuation period calculation section 102 Timer interrupt setting section 200 Test execution section 201 Memory access switching section 202 Timer value acquisition section 203 Timer interrupt value adjustment section 204 Test execution time confirmation section 211 Memory access section
212 Cache access section 300 Clock generation section 400 Interrupt register

Claims (6)

Generate a timer value from the CPU clock,
Determine the reference timer value based on the set load fluctuation cycle,
Obtain the current timer value at the time of judgment,
Based on the current timer value, determine whether to delay the occurrence of an interrupt at a timing according to the reference timer value,
In the case of delaying, a load fluctuation test program causes a computer to execute a process of generating an interrupt by delaying the timing according to the reference timer value by a predetermined timer value based on the load fluctuation cycle. 2. The load fluctuation test program according to claim 1, wherein the reference timer value is a half time of the load fluctuation cycle. Get the timer value at the time the previous interrupt occurred,
If a normal timer value obtained by adding the reference timer value to the generation timer value is smaller than the current timer value, it is determined that the occurrence of the interrupt at a timing according to the reference timer value is to be delayed. The load fluctuation test program according to claim 1 or 2, wherein the load fluctuation test program is executed. 4. The load fluctuation test program according to claim 3, wherein the timing according to the reference timer value is the timing indicated by the normal timer value. 5. When the interrupt is delayed, the computer is caused to execute the process of generating the interrupt at a timing delayed by one cycle of the load fluctuation cycle from the timing according to the reference timer value. Load fluctuation test program described in one. Generate a timer value from the CPU clock,
Determine the reference timer value based on the set load fluctuation cycle,
Obtain the current timer value at the time of judgment,
Based on the current timer value, determine whether to delay the occurrence of an interrupt at a timing according to the reference timer value,
In the case of delaying, the load fluctuation test method is characterized by causing a computer to execute a process of generating the interrupt by delaying the timing according to the reference timer value by a predetermined timer value based on the load fluctuation cycle.

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