JP7419781B2 - semiconductor module - Google Patents

Description

The present invention relates to a semiconductor module, and particularly to a power semiconductor module used for power conversion.

A power semiconductor module disclosed in Patent Document 1 is known as a document disclosing a power semiconductor module sealed with resin using wiring using lead terminals. 1 and 2 of Patent Document 1 discloses a structure in which semiconductor elements are electrically connected with lead terminals and sealed with resin.

Furthermore, Patent Document 2 discloses that a first protective film and a plating film are selectively provided on the electrodes of a semiconductor element, and a second protective film that covers a portion in contact with the plating film and the protective film is provided. , has been disclosed to improve the adhesion between the plating film and the solder.

JP2006-202885 JP2017-59720

As in Patent Document 1, in a structure in which a lead terminal made of copper (Cu) or the like is soldered to the top surface of a semiconductor element and sealed with resin, lead terminals are formed on the surface of the semiconductor element due to power cycles caused by heat generation of the semiconductor element. There was a problem that cracks occurred in the Al film electrode and the Al-Si alloy film.

This is due to the stress generated during heat generation, and the difference in thermal expansion coefficient between the lead terminal and silicon (Si) of the semiconductor element (linear expansion coefficient of copper: 16.7 × 10 ^-6 /℃, thermal expansion of Si) coefficient: 3.0×10 ⁻⁶ /°C).

Furthermore, it has been considered that performance and reliability may be adversely affected due to the repeated generation of tensile and compressive forces in the vertical direction on the semiconductor element due to thermal expansion of the rising portions of the lead terminals.

Additionally, guard rings and gate runners patterned with polyimide are placed on the electrodes on the surface of the semiconductor element, and an electrode protective film is formed inside the polyimide pattern, but the adhesion of these materials is not good and thermal history It was thought that performance and reliability would deteriorate as the gap widened due to thermal contraction of the polyimide over time.

In addition, the solder spreads during bonding with lead terminals or during actual operation, which not only causes stress concentration but also becomes a stress magnification point, which may reduce the lifespan.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to reduce thermal stress caused by heat generation of semiconductor elements in a semiconductor module using lead terminal bonding, and to provide a highly reliable semiconductor module. do.

Another object of the present invention is to provide a highly reliable semiconductor module that is capable of high power density, miniaturization, and high output.

The semiconductor module of the present invention includes:
a semiconductor element;
a laminated substrate on which the semiconductor element is mounted;
an electrode layer formed on the surface of the semiconductor element;
a first insulating film formed on the electrode layer and having a first opening;
a metal layer formed within the first opening;
A second opening formed to cover the first insulating film and the metal layer at the edge of the first opening, exposing the metal layer, and having a second opening surrounded by a curved line. an insulating film,
and a solder portion formed within the second opening.

According to the semiconductor module of the present invention, high reliability can be obtained even during continuous high temperature operation. Furthermore, since large currents can be handled in a small space, it becomes possible to increase power density, making it possible to downsize and increase the output of power semiconductor modules.

1 is a sectional view schematically showing a cross section of a power semiconductor module according to a first embodiment of the present invention. 2 is a plan view illustrating a first insulating film 25 provided on the surface of a semiconductor element 14. FIG. 3 is a cross-sectional view illustrating a first insulating film 25 provided on the surface of a semiconductor element 14. FIG. 3 is a plan view illustrating a second insulating film 33 provided on a first insulating film 25. FIG. 3 is a cross-sectional view illustrating a second insulating film 33 provided on a first insulating film 25. FIG. FIG. 2 is a plan view illustrating the electrode structure of the semiconductor element 14 and the connections of the lead terminals 16 of the present embodiment. FIG. 2 is a cross-sectional view illustrating the electrode structure of the semiconductor element 14 and the connection of the lead terminals 16 of the present embodiment. 3 is a diagram showing a case where solder portion 15 is formed with a gap between it and second insulating film 33. FIG. FIG. 7 is a partially enlarged sectional view schematically showing a case in which the solder of the solder portion 15 is configured to cover a part of the tip side surface 16t or the side surface 16s of the joint portion 16a of the lead terminal 16. It is a graph showing the relationship between the ratio (%) of the bonding area to the area of the bonding portion 16a (flat plate portion) of the lead terminal 16 and thermal resistance. FIG. 3 is a diagram showing the results of a reliability test (T _j P/C test) of the semiconductor module of the present embodiment in comparison with a case of a conventional structure. FIG. 7 is a cross-sectional view showing another form of connection between a joint portion 16a of a lead terminal 16 and a plurality of solder portions 15;

Embodiments of the present invention will be described below with reference to the drawings. These can be modified as appropriate and applied in combination. Further, in the following description and the accompanying drawings, substantially the same or equivalent parts are designated by the same reference numerals. Note that the present invention is not limited to the embodiments described below, and can be implemented with appropriate modifications within the scope without changing the gist thereof.

Further, in the following, a case will be described in which the semiconductor module 10 is a power semiconductor module in which a power semiconductor element is mounted as a semiconductor element.
[First embodiment]
FIG. 1 is a cross-sectional view schematically showing a cross section of a power semiconductor module 10 according to a first embodiment of the present invention.

As shown in FIG. 1, the power semiconductor module 10 includes a cooler 19, a laminated substrate 12 provided on the cooler 19 via a solder 11, and a semiconductor layer provided on the laminated substrate 12 via a solder 13. The element 14 and lead terminals 16 that electrically connect the semiconductor element 14 and the laminated substrate 12 via the lead terminal lower solder 15 (hereinafter simply referred to as the solder 15) are erected on the cooler 19. It is housed in a frame-shaped case 17.

Further, the frame-shaped case 17 is filled with a sealing resin 18, and the solder 11, the laminated substrate 12, the semiconductor element 14, and the lead terminals 16 are sealed.

The outer shapes of the case 17 and the sealing resin 18 are substantially rectangular parallelepipeds, and the sealing resin 18 has an upper surface and a lower surface that faces the upper surface and contacts the cooler 19 . The upper surface of the cooler 19, the upper surfaces of the laminated substrate 12, the semiconductor element 14, and the sealing resin 18 are arranged so as to be substantially parallel to each other.

Note that in this specification, the upper surface or the lower surface is a relative term that refers to the upper and lower sides in the attached drawings for the purpose of explanation, and does not limit the upper and lower sides in relation to the usage mode of the power semiconductor module 10. do not have.

The laminated substrate 12 is a substrate in which an insulating substrate and a conductive plate are laminated, and may be a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Blazing) substrate. More specifically, in the laminated board 12, a metal foil 12A is arranged on the lower surface of an insulating substrate 12B made of ceramic or the like, and a circuit layer 12C is arranged on the upper surface. The metal foil and the circuit layer are made of conductive metal such as copper, and may be processed into a predetermined pattern. The insulating substrate is made of ceramics with high thermal conductivity, such as aluminum oxide (alumina), aluminum nitride, silicon nitride, boron nitride, or the like.

The laminated substrate lower solder 11 (hereinafter simply referred to as solder 11) connects the metal foil 12A and the cooler 19 thermally and mechanically. That is, the heat transferred from the semiconductor element 14 to the laminated substrate 12 (DCB substrate) is transferred to the cooler 19. As the solder 11, high-strength solder is suitable for high reliability, and Sn-Sb-based solder or Sn-Sb-Ag-based solder is preferred.

Solder 15 electrically and thermally connects the lower surface of lead terminal 16 and the surface electrode of semiconductor element 14 . If the tensile strength of the solder 15 is high, high stress will be generated on the surface electrode of the semiconductor element 14, so a relatively soft solder with low tensile strength is preferable. Specifically, the tensile strength is preferably 50 MPa or less, more preferably 30 MPa or less. For example, Sn--Cu solder is preferred. The tensile strength is determined by dividing the maximum tensile force of the stress-strain curve by the cross-sectional area of the sample (JIS Z2241).
Lead terminal 16 is electrically and thermally connected to the upper surface of semiconductor element 14 via solder 15 . The lead terminal 16 includes flat joining parts 16a and 16e, a flat rising part 16b rising upward from the joining part 16a, and a flat connecting part 16c connecting the rising part 16b and the falling part 16d. It is composed of.

The lead terminal 16 is manufactured by bending a strip-shaped conductive plate. The lead terminal 16 has a joint portion 16a, which is a flat end portion, joined to the surface electrode of the semiconductor element 14 via the solder 15. Further, the lead terminal 16 has a joint portion 16e joined to the circuit board 12c of the laminated board 12 via solder.

As the material of the lead terminal 16, a metal having low electrical resistance and high thermal conductivity is preferably used, and specifically, Cu or Cu copper alloy, Al or Al alloy, which has low electrical resistance, is preferably used. Further, surface treatment such as Ni plating may be performed. The thickness of the lead terminal 16 having the vertical portion is preferably about 0.3 mm to 0.8 mm in order to obtain a long life.

It is preferable that the sealing resin 18 has a predetermined insulation performance, a low bending modulus, a thermal expansion coefficient adjusted in consideration of the internal material, and good moldability. Resin materials having skeletons such as epoxy resins and maleimide resins are suitable, but are not limited to these. Filler is mixed in these resins in order to improve thermal conductivity, for example, and the coefficient of thermal expansion and modulus of bending elasticity can be adjusted by adjusting the amount of filler.

The cooler 19, which is a heat sink, is hollow inside and includes a plurality of fins. There is a refrigerant passage between the fins. Although the refrigerant is not particularly limited, for example, it is possible to use an ethylene glycol refrigerant or a liquid refrigerant such as water, and air cooling is also possible. The cooler 19 is thermally connected to the metal foil 12A of the DCB board.

The semiconductor element 14 is, for example, a power chip such as an IGBT (Insulated Gate Bipolar Transistor) or a diode chip, but various Si devices, or wide gap semiconductor elements such as a SiC device or a GaN device can also be used. Further, these devices may be used in combination. For example, a hybrid module using a Si-IGBT and a SiC-SBD (Schottky Barrier Diode) can be used.

Note that the number of semiconductor elements 14 to be mounted is not limited to the illustrated form, and a plurality of semiconductor elements 14 may be mounted on the laminated substrate 12.

Further, a structure including a plurality of sets of semiconductor elements 14 and lead terminals 16 may be used. By arranging a plurality of semiconductor elements 14 in parallel connection, the rated output of the semiconductor module 10 can be increased. Further, the types of the plurality of semiconductor elements 14 may be changed to different types of semiconductor elements. For example, a structure may be used in which an IGBT and a FWD (Free Wheeling Diode) are connected in parallel.

Next, the structure of the electrode portion on the surface of the semiconductor element 14 of the semiconductor module 10 according to the first embodiment of the present invention will be described in detail with reference to the drawings. 2A and 2B are a plan view and a cross-sectional view, respectively, illustrating an insulating film 25 (hereinafter referred to as the first insulating film 25) provided on the surface of the semiconductor element 14 and also functioning as a protective film. 3A and 3B are a plan view and a cross-sectional view, respectively, illustrating an insulating film 33 (hereinafter referred to as a second insulating film 33) provided on the first insulating film 25 and also functioning as a protective film. .

More specifically, FIG. 2A is a plan view illustrating the first insulating film 25 provided on the surface of the semiconductor element 14, and FIG. 2B is a plan view illustrating the semiconductor element 14 along the line AA shown in FIG. 2A. FIG. 2 is a cross-sectional view schematically showing a cross section of a surface portion of.

First, as shown in FIG. 2B, a surface electrode 24, which is an electrode layer formed on the surface of the semiconductor layer 23 of the semiconductor element 14, is provided. The surface electrode 24 is, for example, an Al--Si film, but may be made of a plurality of metal layers including an Al--Si film, an Al film, a Ti film, or the like.

As shown in FIGS. 2A and 2B, on the surface electrode 24, a gate runner 31 and a guard ring 32 are arranged, which are covered by patterning a first insulating film 25 such as polyimide. The first insulating film 25 has a plurality of first openings 25A (hereinafter referred to as a plurality of first openings 25A). The gate runner 31 and guard ring 32 are electrically connected to the pad electrode 26.

The guard ring 32 is a p-type or n-type region formed inside the element so as to surround the outside of the element, and is used to prevent electric field concentration. Further, a gate runner is a wiring for applying a voltage to the gate electrode of a transistor, and in a cross-sectional view, it is surrounded by an insulating film and is connected to an extraction terminal. Further, the first insulating film may be an insulating material such as SiO ₂ (silicon oxide) or TEOS (tetraethyl orthosilicate).

3A and 3B are views similar to FIGS. 2A and 2B, and FIG. 3A is a plan view illustrating the second insulating film 33, and FIG. 3B is a view taken along line BB shown in FIG. 3A. 2 is a cross-sectional view schematically showing a cross section of a surface portion of a semiconductor element 14. FIG.

More specifically, with reference to FIGS. 3B and 2B, on the surface electrode 24 in the first opening 25A of the first insulating film 25, that is, on the surface electrode 24 exposed from the first insulating film 25. A metal layer (for example, an electrode protective film) 27 is formed thereon. The metal layer 27 is composed of, for example, a Ni film and an Au film formed on the Ni film, but is not limited thereto.

Referring to FIGS. 3B and 2B, the second insulating film 33 made of polyimide or the like is attached to the edge of the first opening 25A (that is, the edge of the first insulating film 25, which is indicated by a broken line in FIG. 3A). ) is formed so as to cover the first insulating film 25 and the metal layer 27. Further, the second insulating film 33 has a plurality of second openings 33A (hereinafter referred to as a plurality of second openings 33A) each having a shape surrounded by a curved line.

In addition, as a manufacturing method, after forming the first insulating film 25, a Ni film and an Au film are formed on the metal layer 27 by plating, and then the second insulating film 33 is formed between the first insulating film 25 and the metal layer 27. It can be formed to cover the boundaries of layer 27.

In this embodiment, each of the plurality of second openings 33A has an elliptical shape, but the shape of the second opening 33A is not limited to this, and may have a curved shape. That's fine. Moreover, although the case where the second insulating film 33 has a plurality of openings 33A is shown as an example, it may have one opening.

More specifically, the shape of the second opening 33A preferably does not have an angle formed by two straight lines when viewed from the top. For example, if the second opening 33A has a corner formed by two straight lines, such as a quadrangle, stress concentration will occur between the solder material and the second insulating film 33 at the corner, resulting in cracking or peeling. Easy to occur.

Further, the second opening 33A may have a straight portion in part. When the shape of the opening consists of a straight line and a curved line, it is preferable that the angle between the straight line and the curved line is larger than 90 degrees.

Further, it is preferable that all of the second openings 33A are formed in a curved line, and may be an ellipse, a circle, or the like.

Next, the electrode structure of the semiconductor element 14 and the connection of the lead terminals 16 of this embodiment will be described with reference to FIGS. 4A and 4B. A solder portion 15, which is solder under the lead terminal, is formed on the metal layer 27 in the second opening 33A shown in FIG. 3B. The lead terminals 16 of the lead frame are connected to a plurality of solder parts 15.

More specifically, the solder portion 15 is formed in each of the plurality of second openings 33A provided in the second insulating film 33, and the solder portion 15 is formed in each of the plurality of second openings 33A provided in the second insulating film 33. ) is connected to a plurality of solder parts 15 .

In addition, as shown in FIGS. 4A and 4B, the joint portion 16a of the lead terminal 16 is arranged so as not to cover the entire surface of the second opening 33A to which the lead terminal 16 is joined (i.e., the joint portion 16a of the lead terminal 16 is (partially covered so that a portion 15A of the surface of the portion 15 is exposed) is connected to the plurality of solder portions 15.

The reason why it is better for the lead terminal 16 not to cover the entire surface of the solder part 15 is that if the lead terminal 16 protrudes outside the solder part 15 and an overhang is formed, the solder may form an acute angle with the lead terminal 16. This is because the solder is formed at a certain point, and stress is concentrated at that point, causing the solder to peel off.

On the other hand, as shown in FIGS. 4A and 4B, when the lead terminals 16 are connected so that a portion 15A of the surface of the solder portion 15 is exposed, there are no stress concentration points and peeling does not occur. Further, even if a stress concentration point occurs near the center of the solder portion 15, the solder portion 15 will not peel off because the displacement is small.

In addition, the case where the solder part 15 was formed so that the whole 2nd opening 33A was filled was demonstrated above (FIG. 4A). However, as shown in FIG. 4C, the solder portion 15 may be formed to partially cover the second opening 33A, that is, to have a gap between it and the second insulating film 33.

Further, in FIG. 4D, the solder of the solder portion 15 wraps around the outside (side surface) of the tip of the joint portion 16a of the lead terminal 16 or the outside (side surface) of the side portion of the joint portion 16a. 16t or a partially enlarged cross-sectional view schematically showing a case in which it is configured to cover a part of the side surface 16s. The thickness of the lead terminal 16 was defined as TA, and the thickness at which the joint portion 16a was covered with solder was defined as TB.

Here, the ratio (=TB/TA) of the solder covering the tip side surface 16t or the side surface 16s of the lead terminal 16 is preferably 20% or more. This improves the strength and also provides stress relaxation effects.

Further, as described above, it is preferable that the side surface 16s of the lead terminal 16 is formed so that a portion 15A of the surface of the solder portion 15 is exposed, that is, so as to partially cover the solder portion 15 ( Figure 4A). For example, the semiconductor element 14 may be embedded with sealing resin, but if the lead terminals 16 are formed so as to cover the entire surface of the solder portion 15 and cause an overhang, the resin may be buried under the lead terminals 16. The resin that has entered under the end of the lead terminal 16 is likely to peel off due to vertical thermal stress.

FIG. 5 is a graph showing the relationship between the ratio (%) of the bonding area to the area of the bonding portion 16a (flat plate portion) of the lead terminal 16 and the thermal resistance. That is, the vertical axis indicates the thermal resistance as 100 (%) when the joint area of the joint 16a (flat plate part) is 100% (that is, when the entire surface of the joint 16a is soldered to the solder part 15). There is. The horizontal axis indicates the ratio (%) of the bonded area of the bonded portion 16a. From this graph, it is understood that if the ratio of the bonding area to the area of the bonding portion 16a is less than 40%, the thermal resistance increases rapidly, and that it is preferable that the ratio of the bonding area is 40% or more.

In the case shown in FIG. 4B, the joint portion 16a, which is the tip of the lead terminal 16, is joined and connected to two solder portions 15 arranged along the extending direction of the joint portion 16a. In other words, the joint part 16a of the lead terminal 16 is oriented so that the extending direction of the joint part 16a, which is the tip of the lead terminal 16, is along the arrangement direction of the plurality of solder parts 15, and the plurality of solder parts 15 A joint portion 16a is joined to.

According to this embodiment, the second insulating film (protective film) made of polyimide or the like has a curved edge at the opening, and when the semiconductor element generates heat, the second insulating film (protective film) and the solder It is possible to reduce the thermal stress generated between the connecting material and the connecting material, and also to prevent the occurrence of cracks. When the semiconductor element is covered with a sealing resin, thermal stress generated between the protective film, the solder connection material, and the sealing resin can be reduced. In addition, thermal stress caused by a difference in linear expansion coefficient between the solder and the lead frame under the lead frame can also be reduced by forming the lead frame into a curved shape such as an ellipse.

Furthermore, even when guard rings and gate runners patterned with polyimide or the like are provided on the electrodes on the surface of the semiconductor element, it is possible to prevent gaps from widening due to heat shrinkage of the polyimide or the like due to thermal history, thereby improving performance and improving performance. Reliability can be improved.

Further, during bonding with lead terminals or during actual operation, solder spreads, becomes a stress concentration and stress magnification point, and the negative effects of shortening life can be reduced.

The results of the reliability (lifetime) test of the semiconductor module 10 of this embodiment in which the opening 33A of the second insulating film 33 is shaped like an ellipse as the surface structure of the semiconductor element are compared with those in which the opening 33A of the second insulating film has a rectangular shape. FIG. 6 shows a comparison with the conventional structure. The test was conducted with the bonding area between the lead terminal 16 and the solder being the same, and the area of the rectangular opening (conventional structure) and the area of the elliptical opening (this embodiment) being the same.

A TjP/C test was performed as a reliability test, and a temperature cycle test was performed using heat generated by the semiconductor element under a certain amount of heat radiation. Reliability is determined by measuring the number of cycles until a characteristic abnormality is detected, with one cycle being defined as raising the temperature of the semiconductor element from 25°C to 175°C in 1 second and then dropping it to 25°C over 9 seconds. A comparison was made in terms of gender (lifespan).

As shown in FIG. 6, it was confirmed that the reliability (life span) of the semiconductor module of this embodiment was improved by about 45% compared to the case of the conventional structure.
[Second embodiment]
FIG. 7 is a sectional view showing another form of connection between the joint portion 16a of the lead terminal 16 and the plurality of solder portions 15. In this connection form, the joint portion 16a of the lead terminal is joined to the plurality of solder portions 15 so as to be inclined toward the metal layer 27 in the direction of the tip thereof.

Further, the solder portion 15 to which the joint portion 16a of the lead terminal 16 is joined is configured to wrap around the outside of the tip of the joint portion 16a and cover a part of the side surface 16t of the tip of the joint portion 16a. That is, the distal end portion of the joint portion 16a including the distal side surface 16t is at least partially embedded in the solder portion 15F disposed on the distal end side of the lead terminal 16, and the rear end of the joint portion 16a is embedded in the solder portion 15R on the rear end side. It is joined. By holding the lead terminals 16 in this manner, the bonding strength is increased and the occurrence of voids and the like is also reduced.

Further, as shown in FIG. 7, the joint portion 16a of the lead terminal 16 is bent from the rising portion 16b of the lead terminal 16. The angle of the bent portion (the angle between the joint portion 16a and the rising portion 16b) θ of the tip portion of the lead terminal 16 (the flat joining portion 16a and the flat rising portion 16b) shall be 90 degrees or more (obtuse angle). is preferable in terms of bonding strength and bonding stability.

When the lead terminal 16 is subjected to thermal stress such as a heat cycle, thermal stress is generated in the solder in the vertical direction and the shear direction. When the lead terminal 16 is angled, the stress in the vertical direction (vertical component) is reduced. Although the vertical component is reduced with an acute angle, the length of the lead terminal 16 becomes longer, which is not preferable. Further, stress in the vertical direction is undesirable because it pressurizes the surface electrode 24 under the solder.

In addition, when the thickness of the solder of the solder part 15F on the front end side and the solder part 15R on the rear end side of the joint part 16a of the lead terminal 16 is defined as H2 and H1, respectively, it is preferable to set H1>H2 in terms of joint strength. preferable. More specifically, H1 is the thickness measured at the point where the distance between the joint 16a of the lead terminal 16 and the surface electrode 24 (or metal layer 27) is the smallest in the solder portion 15R, and H2 is the thickness of the solder portion 15R. The solder portion 15F on the tip side of the lead terminal 16a has a thickness measured at a point where the distance between the joint portion 16a of the lead terminal 16 and the surface electrode 24 is the smallest.

More specifically, stress in the shearing direction from the lead terminal 16 applies shearing force to the surface electrode 24 due to thermal history. The reason why H1>H2 is preferable is that solder is softer than the lead terminal 16 or the semiconductor element and relieves stress, so increasing the thickness of the solder reduces the horizontal shearing force applied to the electrode.

Note that the lead terminal 16 is connected from the semiconductor element 14 to the terminal of the laminated substrate 12, and both corners of the lead terminal 16 (the angle (θ) between the joint portion 16a and the rising portion 16b and the angle (θ) between the rising portion 16b and the connecting portion 16c) It is preferable to make the angle (angle formed by

According to the semiconductor module of the present embodiment, the bonding strength of the lead terminals can be increased, and when the semiconductor element generates heat, the rising portions of the lead terminals are thermally expanded and contracted in a direction perpendicular to the semiconductor element. Applied thermal stress can be reduced and reliability can be improved.

Moreover, according to the semiconductor module of this embodiment, high reliability can be obtained even during continuous high temperature operation. Furthermore, since large currents can be handled in a small space, it becomes possible to increase power density, making it possible to downsize and increase the output of power semiconductor modules.

10 Semiconductor module 11 Ceramic insulating substrate lower solder 12 Laminated substrate 12A Metal foil 12B Ceramic insulating substrate 12C Circuit layer 13 Semiconductor element lower solder 14 Semiconductor element 15 Lead terminal lower solder 16 Lead terminal 16a Joint part 17 of lead terminal 16 Case 18 Sealing Resin 19 Cooler 23 Semiconductor layer 24 Surface electrode 25 First insulating film 25A First opening 26 Pad electrode 27 Metal layer 31 Gate runner 33 Second insulating film 33A Second opening

Claims (6)

a semiconductor element;
a laminated substrate on which the semiconductor element is mounted;
an electrode layer formed on the surface of the semiconductor element;
a first insulating film formed on the electrode layer and having a first opening;
a metal layer formed within the first opening;
It is formed to cover the first insulating film and the metal layer at the edge of the first opening, and exposes the metal layer, and the shape of the metal layer when viewed from the exposed side has an angle of 90 mm. a second insulating film having a second opening having a shape of a straight line and a curved line, an ellipse, or a circle that is larger than the angle ;
a solder portion formed within the second opening. It further includes a lead terminal having a joint at its tip,
The second opening has a plurality of second openings each having the solder portion formed therein, and the joint portion of the lead terminal has a solder portion of at least one of the plurality of second openings. The semiconductor module according to claim 1, wherein the semiconductor module is connected to. a semiconductor element;
a laminated substrate on which the semiconductor element is mounted;
an electrode layer formed on the surface of the semiconductor element;
a first insulating film formed on the electrode layer and having a first opening;
a metal layer formed within the first opening;
A second opening formed to cover the first insulating film and the metal layer at the edge of the first opening, exposing the metal layer, and having a second opening surrounded by a curved line. an insulating film,
a solder portion formed within the second opening;
It further includes a lead terminal having a joint at its tip,
The second opening has a plurality of second openings each having the solder portion formed therein, and the joint portion of the lead terminal is connected to the solder portion of at least one of the plurality of opening portions. and
In the semiconductor module, the bonding portion of the lead terminal covers a solder portion in the second opening to which the bonding portion is bonded so that a part of the surface thereof is exposed . 4. The semiconductor module according to claim 2, wherein a tip of the joint portion of the lead terminal is at least partially embedded in the solder portion and joined to the solder portion. The semiconductor according to any one of claims 2 to 4, wherein the lead terminal is connected to the solder portion of the plurality of second openings while being inclined in a direction toward the metal layer in the direction of the tip thereof. module. 6. The semiconductor module according to claim 2, wherein the tip of the lead terminal has a bent portion having an angle of more than 90 degrees.

Images