JP7425575B2 - Display control device and display control method, imaging device - Google Patents

Description

The present invention relates to a display control device, a display control method, and an imaging device.

In recent years, imaging devices equipped with an electronic view finder (hereinafter referred to as EVF) as an eyepiece finder have become popular. The use of an EVF has the advantage that it is possible to photograph a subject even when it is difficult to visually recognize the subject with an optical view finder (hereinafter referred to as OVF) due to the shooting environment. On the other hand, unlike an OVF, a steady supply of power is required to visually recognize a subject with an EVF, which also causes the problem of increased power consumption of the imaging device.

To address the above-mentioned problem, a method has been proposed to reduce power consumption when an image is displayed on the EVF by switching the transfer rate of image data transferred to the EVF depending on the operating state of the shutter button. (See Patent Document 1). Furthermore, a technique has been proposed in which the image processing frame rate is lowered by lowering the clock frequency after a non-operation state continues for a predetermined period of time, thereby reducing the power consumption of the imaging device (see Patent Document 2).

Japanese Patent Application Publication No. 2007-019583 Japanese Patent Application Publication No. 2007-096456

However, in the technology disclosed in Patent Document 1, in order to keep the display frame rate of the EVF constant regardless of the transfer rate, it is necessary to lower the resolution of the displayed image when the transfer rate is low, and it is necessary to visually check the subject and additional information for operation. Sexuality decreases. Further, in the technique disclosed in Patent Document 2, in order to switch the display frame rate while preventing display interruption on the display unit, it is necessary to change the operating frequency using a plurality of clock signal oscillators for display processing.

The present invention provides a technology that makes it possible to switch the display frame rate without causing display interruptions while eliminating the need to change the operating frequency for display processing.

A display control device according to one embodiment of the present invention has the following configuration. That is,
Generation of a display blanking signal that alternately repeats a blanking period and a non-blanking period and a display synchronization signal based on a reference synchronization signal corresponding to a first frame rate and a display clock signal for display operation. means and
a control means for driving a display device using the display clock signal, the display blanking signal and the display synchronization signal generated by the generation means,
When changing the frame rate of the display device to a second frame rate that is 1/n (n is a natural number) times the first frame rate, the generating means is configured to change the frame rate of the reference synchronization signal and the display. the blanking of the display blanking signal by generating the display blanking signal and the display synchronization signal using one of the n consecutive reference synchronization signals while maintaining the period of the clock signal; The length of the period and the cycle of the display synchronization signal are changed.

According to the present invention, it is possible to switch the display frame rate without causing display interruption while eliminating the need to change the operating frequency for display processing.

FIG. 1 is a block diagram showing a configuration example of an imaging device according to a first embodiment. 6 is a timing chart of display frame rate switching processing according to the first embodiment. 5 is a timing chart of display frame rate switching processing according to the first embodiment. 6 is a timing chart of display frame rate switching processing according to the first embodiment. 6 is a timing chart of display frame rate switching processing according to the first embodiment. 7 is a flowchart showing display frame rate switching processing according to the first embodiment. FIG. 2 is a block diagram showing a configuration example of an imaging device according to a second embodiment. 7 is a timing chart of display frame rate switching processing according to the second embodiment.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the claimed invention. Although a plurality of features are described in the embodiments, not all of these features are essential to the invention, and the plurality of features may be arbitrarily combined. Furthermore, in the accompanying drawings, the same or similar components are designated by the same reference numerals, and redundant description will be omitted.

<First embodiment>
FIG. 1 is a block diagram showing a configuration example of an imaging device 100 according to the first embodiment. Note that in this embodiment, a digital camera is assumed as the imaging device 100, but the invention is not limited to this. INDUSTRIAL APPLICATION This invention is applicable to the electronic device which has an imaging part, such as a smart phone and a tablet, for example.

In FIG. 1, an optical system 101 includes an optical filter, a focus lens, a zoom lens, an aperture, a shutter, and the like. When an instruction to start imaging is given by the operation unit 113, the optical system 101 forms an optical image of the subject on the imaging surface of the image sensor unit 102. The optical system 101 and the image sensor section 102 are controlled by an image capture control section 110.

The image sensor unit 102 includes a CMOS (Complementary Metal Oxide Semiconductor) image sensor having a plurality of pixels arranged in a two-dimensional array. Red, green, and blue (RGB) color filters are arranged in the plurality of pixels. The imaging sensor unit 102 performs photoelectric conversion processing to convert the light transmitted through the color filter into an analog electrical signal in accordance with the imaging synchronization signal generated by the synchronization signal generation unit 109. Note that other imaging devices such as a CCD (Charge Coupled Device) image sensor may be used instead of the CMOS image sensor.

The imaging processing unit 103 performs an AD conversion process (analog-digital conversion process) that converts an analog electrical signal obtained by the photoelectric conversion process of the imaging sensor unit 102 into image data consisting of a digital electrical signal. Furthermore, the imaging processing unit 103 performs restoration processing on the image data obtained by the AD conversion processing. In the repair process, the imaging processing unit 103 interpolates the pixel value of the pixel to be repaired using surrounding pixel values. The pixel to be repaired is, for example, a missing pixel in the image sensor unit 102, a pixel whose pixel value is maximum (minimum), and whose reliability is determined to be low. Furthermore, in the restoration process, the imaging processing unit 103 subtracts a predetermined offset value such as a dark current correction value from the image data. The imaging processing unit 103 stores the image data after the restoration process in the storage unit 112.

The image processing unit 104 reads out the restored image data stored in the storage unit 112 in response to the image processing synchronization signal generated by the synchronization signal generation unit 109. The image processing unit 104 then performs development processing on the image data, including conversion to a color space consisting of luminance and color difference, noise removal, optical distortion correction, and the like. Further, the image processing unit 104 performs image processing such as white balance adjustment, gamma correction, sharpness correction, brightness level correction, hue correction, and saturation correction on the image data after the development processing based on image processing parameters. Image processing parameters include multiple types of parameters such as white balance, gamma, sharpness, brightness level, hue, and saturation. The image processing unit 104 stores the image data after image processing in the storage unit 112.

The display processing unit 105 reads out the image data after image processing stored in the storage unit 112 according to the display synchronization signal generated by the synchronization signal generation unit 109, resizes the read image data for display, and then Superimposes display information consisting of front characters and icons. Thereafter, the display processing unit 105 performs display image processing such as gamma processing and brightness level correction, and displays images on the first display unit 106 and the second display unit 107.

The first display section 106 and the second display section 107 are used to display the developed image generated by the image processing section 104, an image processed by the image processing section 104, a menu screen, and other various information.

The first display unit 106 is an EVF configured with an organic electroluminescence display device placed in an eyepiece (not shown) of the imaging device 100, and displays an image (for example, , including displaying live view images). The second display unit 107 is a liquid crystal display disposed on the back or side surface of the imaging device 100, and displays images (including, for example, displaying a live view image) according to the image data acquired from the display processing unit 105. . The second display unit 107 also has a touch panel (not shown), and functions as an operation unit 113 (described later) by displaying function icons (function buttons) operated by the user. Functional icons include, for example, shooting start, shooting mode selection, white balance setting, ISO sensitivity setting, and the like.

The eyepiece detection section 108 is arranged at an eyepiece section (not shown) of the imaging device 100. The eyepiece detection unit 108 outputs a signal to the CPU 111 indicating whether or not the user is close to the eyepiece. The CPU 111 controls the display processing unit 105 according to the signal output from the eye proximity detection unit 108. The display processing unit 105 switches the output destination of the signal between the first display unit 106 and the second display unit 107 under the control of the CPU 111. That is, the display processing unit 105 performs display on the first display unit 106 when it is determined that the user is close to the eyepiece based on the signal output of the eyepiece detection unit 108, and when it is determined that the user is not close to the eyepiece. The second display section 107 is controlled to perform display on the second display section 107. Note that the display on the first display section 106 and the display on the second display section 107 may be switched from the operation section 113.

The synchronization signal generation unit 109 generates timing signals necessary for imaging, image processing, and display. For example, the synchronization signal generation unit 109 generates auxiliary synchronization signals such as a vertical synchronization signal, a horizontal synchronization signal, and a vertical blanking signal. Furthermore, the synchronization signal generation unit 109 generates a clock signal used in imaging processing, image processing, and display processing. The synchronization signal generation section 109 and the display processing section 105 function as a display control section that controls display driving of the first display section 106 and the second display section 107. Detailed processing of the synchronization signal generation unit 109 in this embodiment will be described later.

The imaging control unit 110 controls exposure and focus according to user operations on the imaging device 100 and the state of the imaging device 100 obtained via the operation unit 113 described below. For example, exposure is controlled by controlling the aperture, charge accumulation time of the image sensor, etc., and focus is controlled by controlling the drive amount and drive direction of the focus lens. Specifically, the imaging control unit 110 controls the state of the optical system 101, the processing of the imaging sensor unit 102, etc. according to the gain value, shutter speed, and aperture specified by the user. Further, when a transition is made to the AF (autofocus) shooting mode by a user operation, the imaging control unit 110 calculates the contrast shape by referring to an output signal that is a calculation result at a predetermined position of the focus lens. The imaging control unit 110 performs AF control by setting the focus position where the contrast is highest as the position where the light beam is focused on the imaging sensor unit 102.

The CPU 111 is connected to other functional blocks included in the imaging device 100 via an internal bus (not shown). The CPU 111 executes various processes of the imaging apparatus 100 by executing predetermined programs stored in the storage unit 112.

The storage unit 112 includes volatile memory and nonvolatile memory, and is connected to each functional block included in the imaging device 100 via an internal bus (not shown). The storage unit 112 is used by the imaging processing unit 103 and the image processing unit 104 to temporarily store processed image data. Further, the storage unit 112 is used as a work area for the CPU 111, a temporary storage area for temporarily storing various data, and a storage location for firmware and image processing parameters related to processing by the CPU 111.

The operation unit 113 is connected to the CPU 111 in the imaging device 100 via an internal bus (not shown). The operation unit 113 is various operation members as an input unit that accepts user operations. The operation unit 113 includes a shutter button with which the user issues a shooting instruction, a changeover switch with which the focus operation is switched between automatic and manual control, a focus ring with which the user performs a focus adjustment operation, and the like.

Next, switching of the display frame rate according to the first embodiment will be explained using the operation timing charts shown in FIGS. 2A to 2D and the flowchart shown in FIG. 3. Note that in the following embodiment, a case will be described in which the display frame rate is changed from 60 Hz to 30 Hz without changing the frequency of the display clock signal of the first display unit 106. Note that the display clock signal is a clock that defines the operating speed of the first display section 106 and the second display section 107, and the display clock signal determines the time required to display one frame of image.

First, EVF display processing when the display frame rate is 60 Hz, which is the state before switching the display frame rate, will be described.

The synchronization signal generation unit 109 generates a reference synchronization signal that is a synchronization signal that serves as a reference for controlling the imaging device 100. In this embodiment, the reference clock signal is generated from a reference clock signal obtained from a first crystal resonator (not shown), and the frequency of the reference synchronization signal is 60 Hz.

Furthermore, the synchronization signal generation unit 109 generates an imaging synchronization signal and an image processing synchronization signal. The imaging synchronization signal is generated from, for example, an imaging clock signal and a reference synchronization signal, and the imaging clock signal is obtained from a second crystal resonator (not shown). Further, the image processing synchronization signal is generated from, for example, an image processing clock signal and a reference synchronization signal, and the image processing clock signal is obtained from a third crystal resonator (not shown). In this embodiment, the frequency of the imaging synchronization signal and the image processing synchronization signal is 60 Hz. Note that the reference synchronization signal, the imaging synchronization signal, and the image processing synchronization signal are generated using different crystal oscillators, so they are asynchronous even if they have the same frequency. In this embodiment, the imaging synchronization signal and the image processing synchronization signal are used in synchronization with the generation timing of the reference synchronization signal.

Furthermore, the synchronization signal generation unit 109 generates a display blanking signal that alternately repeats blanking periods and non-blanking periods, and a display synchronization signal. The display blanking signal and the display synchronization signal are generated based on the reference synchronization signal and the display clock signal, respectively. The display clock signal is obtained from a fourth crystal resonator (not shown). The display clock signal is a clock that defines the display operation at the maximum frame rate (60 Hz in this embodiment), and is, for example, a dot clock that defines the display speed of pixels in the first display section 106. Note that in the above, the reference clock signal, imaging clock signal, image processing clock signal, and display clock signal were obtained from the first to fourth crystal oscillators, respectively, but all or part of these clock signals may be obtained from a common crystal oscillator. It may be obtained from Note that in this embodiment, the reference synchronization signal, the imaging synchronization signal, the image processing synchronization signal, and the maximum display frame rate are set to 60 Hz, but the present invention is not limited thereto. For example, the reference synchronization signal, the imaging synchronization signal, and the image processing synchronization signal may be set to 120 Hz, and the maximum display frame rate may be set to 60 Hz.

The display processing unit 105 drives the first display unit 106 using the display clock signal generated by the synchronization signal generation unit 109, the display blanking signal, and the display synchronization signal, and displays the image processed by the image processing unit 104. It is displayed on the first display section 106. When changing the frame rate of the first display unit 106, the synchronization signal generation unit 109 changes the length of the blanking period and the cycle of the display synchronization signal while maintaining the cycle of the reference synchronization signal and the cycle of the display clock signal. do. The generation of the display blanking signal and the display synchronization signal by the synchronization signal generation unit 109 will be described below with reference to FIGS. 2A to 2D and FIG. 3.

As shown in FIG. 2A, the synchronization signal generation unit 109 generates a display blanking signal using the counter value of a first internal counter whose initial value is defined according to the display mode. In this embodiment, the display modes include a 60Hz display mode in which display is performed at a frame rate of 60Hz, and a 30Hz display mode in which display is performed at a frame rate of 30Hz. The synchronization signal generation section 109 has a first internal counter and a second internal counter, and uses these counters to generate a display blanking signal and a display synchronization signal for driving the first display section 106 for display.

The first internal counter is a down counter that counts the display clock signal. Further, the initial value of the first internal counter is reset to a value defined by the display mode in a reference synchronization interrupt 202 that occurs in response to a change in the reference synchronization signal. Note that the display blanking signal has two logical values of "0" and "1", a period of "0" is a non-blanking period, and a period of "1" is a blanking period. The value of the display blanking signal is determined according to the counter value of the first internal counter. Further, the reference synchronization signal interrupt is an interrupt signal that changes from "0" to "1" at the timing when the reference synchronization signal changes from "0" to "1". With the reference synchronization signal interrupt 202, settings such as a counter value set by the CPU 111 are reflected and the counter value is reset.

FIG. 2B shows the states of the first internal counter and display blanking signal during EVF display in the 60 Hz display mode. In this embodiment, the CPU 111 sets, in the synchronization signal generation unit 109, a period a from when the counter is reset to when the display blanking signal is changed to 0, and a period b during which the display blanking signal is set to 0. That is, period a represents the time from generation of the reference synchronization signal interrupt to the start of the blanking period, and period b represents the time during which the blanking period continues.

Further, the CPU 111 sets the initial value M of the first internal counter in the synchronization signal generation unit 109 when a reference synchronization signal interrupt occurs. Thereafter, the first internal counter counts the display clock signal, and the synchronization signal generation unit 109 sets the display blanking signal to "0" when the counter value reaches M-a, and sets the display blanking signal to "0" when the counter value becomes M-a-b. At the point in time, the display blanking signal is changed to "1". As a result, a display blanking signal is generated in which the non-blanking period is during the time when the counter value of the first internal counter is from M-a to M-ab. It is assumed that these set values a, b, and M are values defined corresponding to the 60 Hz display mode and are stored in the storage unit 112 in advance.

Returning to FIG. 2A, the display synchronization signal is generated based on the counter value of the second internal counter whose initial value is defined depending on the display mode. The second internal counter is a down counter that counts the display clock signal similarly to the first internal counter. The second internal counter is reset to the initial value defined by the display mode at the timing when the display blanking signal changes from "0" to "1" (timing when switching from the non-blanking period to the blanking period). Note that the display synchronization signal has two values, "0" and "1", which are determined according to the counter value.

FIG. 2C shows the operation of the second internal counter and the timing of the display synchronization signal in the 60Hz display mode. In this embodiment, when the counter value of the second internal counter reaches c, the display synchronization signal changes from 0 to 1, and when the counter value reaches cd, the display synchronization signal changes from 1 to 0. That is, when a predetermined time (Mc) has elapsed from the start of the blanking period, a pulse of the display synchronization signal having a time width d is output. The CPU 111 sets the values of c and d in the synchronization signal generation section 109. Further, the CPU 111 sets the counter value (initial value) of the second internal counter at the time of counter reset (timing of switching from the non-blanking period to the blanking period) in the synchronization signal generation unit 109. In this embodiment, the initial value of the second internal counter is the same value M as the initial value of the first internal counter. It is assumed that the values c and d are also values defined by the 60 Hz display mode and are stored in the storage unit 112 in advance.

The display processing unit 105 transmits the display synchronization signal and the display blanking signal generated by the synchronization signal generation unit 109 to the first display unit 106, and also transmits the image data to the first display unit 106 based on the display synchronization signal. do. The first display unit 106 displays the transmitted image according to the display blanking signal and display synchronization signal transmitted from the display processing unit 105. The operation timing chart of the synchronization signal generation unit 109 in the 60 Hz display mode is a repetition of the operation timing chart shown in FIG. 2A from time t1 to time t2.

Next, FIGS. 3, 2A, and 2D show control for changing the display frame rate on the first display unit 106 from 60 Hz to 30 Hz and from 30 Hz to 60 Hz without changing the frequency of the display clock signal. Explain with reference to.

FIG. 3 is a flowchart illustrating display frame rate switching processing according to the first embodiment. This switching process is executed when, after the user sets the power-saving EVF mode via the operation unit 113, the eyepiece detection unit 108 detects that the user is close to the eyepiece. In this embodiment, the first display section 106 (EVF) starts displaying when the user approaches the eyepiece, and at this time, the synchronization signal generation section 109 causes the first display section 106 to display in the 60Hz display mode. A display synchronization signal and a display blanking signal are generated to perform display. Furthermore, in the present embodiment, the display on the first display unit 106 is a live view image using an image captured by the image sensor unit 102.

The CPU 111 initializes a timer for counting the time when there is no operation on the operation unit 113, and starts counting by the timer (S301). In this embodiment, a timer (hereinafter referred to as a power saving timer) included in the CPU 111 is used. The initial value of the power saving timer is the power saving start time set in minutes when the power saving EVF mode is set. The power saving timer subtracts in seconds, and when the count value of the power saving timer reaches 0, the count stops subtracting, and the CPU 111 determines that the operation unit 113 has not been operated for a certain period of time.

The CPU 111 determines whether a user operation via the operation unit 113 is detected (S302). If it is determined that a user operation has been detected (S302: YES), the process returns to S301. This resets the power saving timer. On the other hand, if it is determined that no user operation has been detected (S302: NO), the CPU 111 determines whether a certain period of time has passed without detecting any user operation (S303). This determination is made based on whether the count value of the power saving timer is zero.

If it is determined that a certain period of time has not elapsed without detecting a user operation (S303: NO), that is, if the count value of the power saving timer is not 0, the process returns to S302 and the above-described process is repeated. If it is determined that a certain period of time has passed without detecting a user operation (S303: YES), that is, if the count value of the power saving timer is 0, the CPU 111 generates a synchronization signal generator to change the display frame rate to 30Hz. 109 is set (S304). Thereby, the synchronization signal generation unit 109 generates a display synchronization signal and a display blanking signal corresponding to the 30Hz display mode.

Here, the operation of the display synchronization signal and the display blanking signal when switching from the 60 Hz table mode to the 30 Hz display mode will be described using the timing chart of FIG. 2A. When the CPU 111 detects at time T201 that a certain period of time has passed without detecting a user operation, it changes the initial values of the first internal counter and the second internal counter of the synchronization signal generation unit 109. When changing the frame rate by 1/n times (n is a natural number of 2 or more) (when increasing the frame period by n times), the initial value of the frame rate before the change is multiplied by n times. In this embodiment, the frequency is switched from 60 Hz to 30 Hz, that is, the frequency is doubled, so the initial value is changed to a value (2×M) that is twice the initial counter value M shown in FIGS. 2B and 2C. be done.

Further, when changing the frame rate to 1/n times, the synchronization signal generation unit 109 generates a display blanking signal and a display synchronization signal using one of the n consecutive reference synchronization signals. This is achieved, for example, by disabling the occurrence of an interrupt caused by a reference synchronization signal (reference synchronization signal interrupt) n-1 times. In this embodiment, the CPU 111 sets an invalid count to the number of times that an interrupt caused by a reference synchronization signal (reference synchronization signal interrupt) is to be thinned out. In this embodiment, since the 60 Hz display mode is changed to the 30 Hz display mode and the frame rate is 1/2, 1 is set in the invalid count of the reference synchronization signal.

Due to the reference synchronization signal interrupt 202 that occurs at time t2, the initial value 2×M of the first internal counter and second internal counter and the invalid count value (1 in this embodiment) of the reference synchronization signal are set as the setting values of the synchronization signal. It is reflected on the generation unit 109. By the reference synchronization signal interrupt 202 (time t2), 2×M is set as the initial value of the first internal counter, and the first internal counter starts counting down. The period when the count value of the first internal counter is between 2×M-a and 2×M-ab is a non-blanking period of the display blanking signal. The start timing of the non-blanking period with respect to the reference synchronous interrupt and the length of the non-blanking period are the same in both the 60Hz display mode and the 30Hz display mode, and one frame of image is displayed during this non-blanking period. be done.

On the other hand, the second internal counter is reset to the initial value 2×M at timing 203 when the display blanking signal rises, and starts counting down. When the count value of the second internal counter reaches c, a synchronization pulse with a time width d is generated. That is, when a predetermined time (2×Mc) has elapsed from the start of the blanking period, a pulse of the display synchronization signal having a time width d is output. In both the 60 Hz display mode and the 30 Hz display mode, the time point at which the pulse of the display synchronization signal is output is a specific time later than the end of the blanking period. Since the invalid count is set to 1, no reference synchronization signal interrupt is generated at time t3, and the first internal counter is not synchronously reset. At time t4, a reference synchronization signal interrupt occurs, so that the first internal counter is synchronously reset.

As described above, the setting values a, b, c, and d shown in FIGS. 2B and 2C are not changed. Therefore, the display blanking signal is a non-blanking period only during the period when the first internal counter value is from 2M-a to 2M-ab, and is a blanking period during the other periods. That is, the length (b) of the non-blanking period of the display blanking signal remains unchanged regardless of changes in the frame rate. On the other hand, the display synchronization signal transitions from 0 to 1 when the counter value is c, and from 1 to 0 when the counter value is cd, as described above. As described above, the change from the display synchronization signal in the 60Hz display mode shown from time t1 to time t2 described in FIG. 2A to the display synchronization signal in the 30Hz display mode shown from time t2 to t4 is realized.

Returning to FIG. 3, the CPU 111 determines whether the shutter button of the operation unit 113 has been pressed halfway (S305). If it is determined that the shutter button is not pressed halfway (S305: NO), the CPU 111 determines whether the user remains close to the eyepiece based on the signal from the eyepiece detection unit 108. Determination is made (S307). If the user remains close to the eyepiece (S307: YES), the process returns to S305. On the other hand, if the user is away from the eyepiece (S307: NO), this process ends. Furthermore, if it is determined that the shutter button has been pressed halfway (S305: YES), in order to change the display frame rate to 60Hz, the CPU 111 sets the synchronization signal generation unit 109 to change the display frame rate ( S306). Thereby, the synchronization signal generation unit 109 generates a 60 Hz display synchronization signal. After that, the process returns to S301, and the above-described process is repeated.

A method of switching the display synchronization signal from the 30Hz display mode to the 60Hz display mode will be described using the timing chart of FIG. 2D. When the CPU 111 detects that the shutter button is pressed halfway at time T204, it sets the invalid count of the reference synchronization signal to 0, and sets the initial values of the first internal counter and the second internal counter to M. As a result, as shown in FIG. 2D, the 30 Hz display synchronization signal between time t10 and time t12 is changed to the 60 Hz display synchronization signal after time t12. In addition, in FIG. 2D, if a half-press of the shutter is detected between t10 and t11, the next reference synchronization signal is ignored, and the next reference synchronization signal is controlled to be valid. Further, when a half-press of the shutter is detected between t11 and t12, control is performed so that the next and subsequent reference synchronization signals become valid. That is, the driving of the first display unit 106 in the changed display mode is started from the next reference synchronization signal after the reference synchronization signal has been ignored the number of times set in the invalid count.

Note that in the first embodiment, when the eyepiece detection unit 108 no longer detects that the user is close to the eyepiece (NO in S307), or when the user performs a power OFF operation, The CPU 111 ends the flow. However, the conditions for ending the flow are not limited to this. Further, although the synchronization signal generation unit 109 generates a 60 Hz display synchronization signal in response to detecting a half-press of the shutter button, the present invention is not limited to this. For example, the display synchronization signal may be changed when an acceleration sensor (not shown) detects a specific movement of the imaging device 100, such as movement in a panning direction.

In this embodiment, the display frame rate is switched for the EVF, which is the first display section 106, but it can also be performed for the liquid crystal display, which is the second display section 107. Furthermore, in this embodiment, each of the above-mentioned clock signals is generated from an independent crystal oscillator, but some of them may be generated via a PLL (Phase Locked Loop) not shown. In addition, in the above embodiment, a digital camera is assumed as the imaging device, and the display frame rate is changed by detecting the user's proximity to the eyepiece and operation of the shutter button, but this is the trigger for changing the display frame rate. It is not limited to. For example, the frame rate of the display on the first display section 106 may be changed depending on the operation state of the operation section 113, or the frame rate of the display on the first display section 106 may be changed depending on the movement of the imaging device detected by the acceleration sensor. You may change the frame rate.

Furthermore, the frequency of each clock signal is not limited either. For example, a case may be considered in which the frequency of the reference synchronization signal, the imaging synchronization signal, and the image processing synchronization signal is set to 240 Hz, and the display frame rate is made variable. For example, the EVF display frame rate in power-saving EVF mode should be a frequency that does not pose a problem for checking the composition of the shot image (e.g. 60Hz), and a frequency that allows you to comfortably follow the movement of the subject after pressing the shutter button halfway (e.g. 240Hz). It is also possible to consider the following operations. In this case, it is assumed that the reference synchronization signal and the display clock are compatible with display at 240 Hz. By setting the number of times the reference synchronization signal is invalidated (invalid count) to 3 and the initial values of the first and second internal counters to 3 x M, it is possible to switch the display frame rate from 240Hz to 60Hz. becomes. Further, by setting the number of times the reference synchronization signal is invalidated (invalidity count) to 2 and the initial values of the first internal counter and the second internal counter to 2×M, it is possible to switch to a display frame rate of 120 Hz.

As described above, according to the first embodiment, it is possible to change the display frame rate without changing the frequency of the display clock signal. Therefore, while eliminating the need to change the operating frequency for display processing, the visibility of the subject and additional information for operation on the display screen is reduced, and the display is not interrupted, reducing the power consumption of the imaging device that has the display section. It becomes possible to do so.

<Second embodiment>
In the first embodiment, a configuration has been described in which the synchronization signal generation unit 109 changes the display frame rate of the first display unit 106 by generating a synchronization signal for changing the display frame rate. In the second embodiment, a configuration will be described in which a function for changing the display frame rate is added to the first display unit 106. The second embodiment will be described below with reference to FIGS. 4 and 5. Note that in FIGS. 4 and 5, functional blocks similar to those in the first embodiment are given the same reference numerals as in the first embodiment.

FIG. 4 is a block diagram showing a configuration example of an imaging device 100 according to the second embodiment. In FIG. 4, the first display unit 106 is an EVF configured with an organic electroluminescent display device disposed in an eyepiece (not shown) of the imaging device 100, and is an EVF configured with an organic electroluminescent display device arranged in an eyepiece unit (not shown) of the imaging device 100. Perform image display (live view). The first display section 106 includes a display control section 401. The display control unit 401 controls the display mode of the first display unit 106.

The display control unit 401 acquires (receives) a display synchronization signal and image data corresponding to a first frame rate (for example, 60 Hz) from the display processing unit 105. The display control unit 401 generates a display unit drive signal based on the acquired (received) display synchronization signal, and uses the display unit drive signal and a display clock signal that defines a display operation corresponding to the first frame rate to generate a display unit drive signal. 1 display section 106 is driven. Here, the display control unit 401 generates a display drive signal with a longer period than the display synchronization signal by ignoring a part of the display synchronization signal, and makes the frame rate of the first display unit 106 lower than the first frame rate. The second frame rate is also lower.

In the second embodiment, the CPU 111 can set the pseudo 30 Hz display mode to the display control unit 401 through serial communication to drive the display at the second frame rate. The display control unit 401 generates a display drive signal for displaying at a pseudo 30Hz display frame rate from the 60Hz display synchronization signal generated by the synchronization signal generation unit 109 so that the first display unit 106 is driven in a pseudo 30Hz display mode. and display the image. Therefore, in the synchronization signal generation unit 109 of the second embodiment, there is no need to switch the operation for the 30Hz display mode.

Here, the pseudo 30 Hz display mode is a display mode in which one frame is thinned out every two frames in the 60 Hz display mode. In this embodiment, the display control unit 401 generates a display unit drive signal by disabling the display synchronization signal every two times, as shown from time t22 to time t26 in FIG. 5, which will be described later. That is, when changing the frame rate to a small value, the display control unit 401 generates a display drive signal having a cycle longer than the cycle of the display synchronization signal by ignoring a part of the display synchronization signal. For example, assume that the frame rate after the change is 1/n times the frame rate before the change (n is a natural number of 2 or more). In this case, in order to drive the first display unit 106 at the changed frame rate, the display control unit 401 generates a display unit drive signal using one of the n consecutive display synchronization signals, and Ignore the display synchronization signal.

FIG. 5 shows an operation timing chart of the pseudo 30 Hz display mode in the second embodiment. At time T501, the CPU 111 sets the pseudo 30 Hz display mode to the display control unit 401 through serial communication. Thereafter, the display control unit 401 shifts to the pseudo 30Hz display mode at time t22, and displays an image using the display drive signal generated by disabling the display synchronization signal acquired from the display processing unit 105 once every two times. . The display control unit 401 also controls the first display unit 106 not to display the image data of the frame corresponding to the ignored display synchronization signal (for example, the image signals indicated by D and F in FIG. 5).

Note that the display processing unit 105 may change the timing of reading image data from the storage unit 112 when changing the display mode of the first display unit 106. For example, when the display mode of the first display unit 106 is changed from the 60Hz display mode to the pseudo 30Hz display mode, the display processing unit 105 reads image data from the storage unit 112 at a rate of once every two display synchronization signals. Processing may also be performed. Further, the display processing unit 105 may output the image data to the first display unit 106 with the value of 0 during a period when the image data is not read.

Note that the display control unit 401 may treat a period during which image data is acquired using a display synchronization signal invalidated when generating a display drive signal as a display blanking period, and may stop emitting light from the organic EL during this period. . Thereby, further power saving can be achieved. Further, the second display section 107 can also have the same function as the first display section 106.

As described above, according to the second embodiment, functional blocks related to display processing can be controlled without changing the frequency of the display clock signal and without regenerating various synchronization signals in the synchronization signal generation unit 109. You can change the display frame rate.

Note that in the first and second embodiments described above, switching of the display frame rate on the first display section 106 has been described, but the display frame rate may be switched on the second display section 107. Furthermore, for example, a configuration in which an EVF having an eyepiece is not provided and a display (for example, a liquid crystal panel) provided on the back of the imaging device is used as the EVF (a configuration in which only the second display unit 107 is provided) may also be used. It is clear that the display mode control described above can be applied. In this case, it is not possible to switch the display mode using the user's proximity to the eyepiece as a trigger, but for example, it is possible to switch the display mode using the shutter switch operation or the duration of no operation as a trigger. Just do it.

(Other examples)
The present invention provides a system or device with a program that implements one or more of the functions of the embodiments described above via a network or a storage medium, and one or more processors in the computer of the system or device reads and executes the program. This can also be achieved by processing. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

The invention is not limited to the embodiments described above, and various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the following claims are hereby appended to disclose the scope of the invention.

100: Imaging device, 101: Optical system, 102: Imaging sensor unit, 103: Imaging processing unit, 104: Image processing unit, 105: Display processing unit, 106: First display unit, 107: Second display unit, 108: Eye proximity detection section, 109, 109a: synchronous signal generation section, 110: imaging control section, 111: CPU, 112: storage section, 113: operation section 402 display control section

Claims (12)

Generating a display blanking signal that alternately repeats a blanking period and a non-blanking period and a display synchronization signal based on a reference synchronization signal corresponding to a first frame rate and a display clock signal for display operation. means and
a control means for driving a display device using the display clock signal, the display blanking signal and the display synchronization signal generated by the generation means,
When changing the frame rate of the display device to a second frame rate that is 1/n (n is a natural number) times the first frame rate, the generating means is configured to change the period of the reference synchronization signal and the display. the blanking of the display blanking signal by generating the display blanking signal and the display synchronization signal using one of the n consecutive reference synchronization signals while maintaining the period of the clock signal; A display control device characterized in that the length of a period and the cycle of the display synchronization signal are changed. 2. The display control device according to claim 1, wherein the length of the non-blanking period of the display blanking signal remains unchanged regardless of a change in the frame rate. The generating means generates the display blanking signal in which a predetermined period is a non-blanking period from the time when a first time has elapsed from the reference synchronization signal, and the predetermined period is a non-blanking period. 2. The display control device according to claim 1 , wherein the display control device remains unchanged regardless of the display control device. A pulse of the display synchronization signal is output at a time point when a second time period has elapsed from the start point of the blanking period, and the point at which the second time period has elapsed is only a specific time period from the end of the blanking period. 4. The display control device according to claim 3 , wherein: 5. The display control device according to claim 4 , wherein the first time and the second time are obtained by counting the display clock signal. A display control device according to any one of claims 1 to 5 ,
the display device driven by the display control device;
comprising an imaging means;
The image capturing apparatus is characterized in that the display control device displays a live view image captured by the image capturing means on the display device. further comprising operation means for accepting user operations;
7. The imaging device according to claim 6 , wherein the display control device changes a frame rate of display on the display device according to an operating state of the operating means. Imaging according to claim 7 , characterized in that when a predetermined operation on the operation means is detected, the display control device controls driving of the display device so as to display at the first frame rate. Device. 3. If the predetermined operation on the operation means is not detected for a certain period of time, the display control device controls driving of the display device to display at the second frame rate. 8. The imaging device according to 8 . Additionally equipped with an acceleration sensor,
The display control device controls driving of the display device so that display is performed at the first frame rate when the acceleration sensor detects a specific movement of the imaging device. The imaging device according to any one of items 6 to 9 . Generating a display blanking signal that alternately repeats a blanking period and a non-blanking period and a display synchronization signal based on a reference synchronization signal corresponding to a first frame rate and a display clock signal for display operation. process and
a control step of driving a display device using the display clock signal, the display blanking signal and the display synchronization signal generated in the generation step,
The generation step includes changing the period of the reference synchronization signal and the display when changing the frame rate of the display device to a second frame rate that is 1/n (n is a natural number) times the first frame rate. the blanking of the display blanking signal by generating the display blanking signal and the display synchronization signal using one of the n consecutive reference synchronization signals while maintaining the period of the clock signal; A display control method comprising changing the length of a period and the cycle of the display synchronization signal. A program for causing a computer to function as each means of the display control device according to claim 1 .

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