JP7439627B2 - CMOS output circuits, semiconductor devices, electronic equipment and mobile objects - Google Patents

Description

The present invention relates to a CMOS output circuit, a semiconductor device, an electronic device, and a mobile object.

In an output circuit of a complementary metal oxide semiconductor (CMOS) transistor, for example, when an overshoot due to noise occurs in the output signal, a forward bias is applied between the drain and the substrate of the pMOS transistor. Then, minority carriers are injected into the substrate. Further, for example, if an undershoot occurs in the output signal due to noise, a forward bias is applied between the drain and the substrate of the nMOS transistor. In this case too, minority carriers are injected into the substrate.

When minority carriers are injected into the substrate, a parasitic thyristor formed in the complementary MOS transistor is turned on, causing a phenomenon in which an excessive current flows (latch-up phenomenon).

Patent Document 1 describes an input/output circuit having a complementary MOS transistor configuration that protects an internal circuit block to be protected, and includes a substrate bias generation circuit that generates a substrate bias at a potential lower than the ground potential, and a substrate bias generation circuit that generates a substrate bias at a potential lower than the power supply voltage. An input/output circuit is disclosed that includes a boosted potential generation circuit that generates a high voltage. In this input/output circuit, the aforementioned substrate bias is supplied to the substrate region of the nMOS transistor of the complementary MOS transistor, and a voltage higher than the aforementioned power supply voltage is supplied to the substrate region of the pMOS transistor of the complementary MOS transistor. be done.

According to such a configuration, a reverse bias is applied between the drain and the substrate of each transistor. Therefore, it is possible to prevent minority carriers from being injected into the substrate from the drain of each transistor. This makes it possible to prevent the latch-up phenomenon from occurring.

Japanese Unexamined Patent Publication No. 6-177335

In the input/output circuit described in Patent Document 1, it is necessary to provide a substrate bias generation circuit and a boosted potential generation circuit connected to complementary MOS transistors. Therefore, there is a problem that the circuit scale of the input/output circuit becomes large.

The CMOS output circuit according to the application example of the present invention is
A CMOS output circuit connected to a first power line, a second power line, an output line, and an input line,
a CMOS circuit including a first PMOS transistor connected to the first power line, the output line and the input line; and a first NMOS transistor connected to the second power line, the output line and the input line;
a first switching circuit that controls the potential of the substrate of the first PMOS transistor;
a second switching circuit that controls the potential of the substrate of the first NMOS transistor;
has
The first switching circuit includes:
a second PMOS transistor having a source connected to the substrate of the first PMOS transistor, a drain connected to the first power supply line, and a gate connected to the output line;
a third PMOS transistor having a source connected to the substrate of the first PMOS transistor, a drain connected to the output line, and a gate connected to the first power supply line;
including;
The second switching circuit includes:
a second NMOS transistor having a source connected to the substrate of the first NMOS transistor, a drain connected to the second power supply line, and a gate connected to the output line;
a third NMOS transistor having a source connected to the substrate of the first NMOS transistor, a drain connected to the output line, and a gate connected to the second power supply line;
It is characterized by including.

A semiconductor device according to an application example of the present invention is characterized by including the CMOS output circuit of the present invention.

An electronic device according to an application example of the present invention is characterized by including the semiconductor device of the present invention.
A moving body according to an application example of the present invention is characterized by being equipped with the semiconductor device of the present invention.

1 is a circuit diagram showing an internal block configuration of a semiconductor device including a CMOS output circuit according to a first embodiment; FIG. FIG. 2 is a vertical cross-sectional view showing the cross-sectional structure of the CMOS output circuit shown in FIG. 1. FIG. FIG. 7 is a vertical cross-sectional view showing a cross-sectional structure of a CMOS output circuit according to a second embodiment. FIG. 7 is a cross-sectional view showing a cross-sectional structure of a CMOS output circuit according to a third embodiment. FIG. 2 is a circuit diagram showing the configuration of an analog switch circuit. FIG. 1 is a block diagram illustrating a configuration example of an electronic device according to an embodiment. FIG. 1 is a perspective view showing an automobile to which a moving body according to an embodiment is applied.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of a CMOS output circuit, a semiconductor device, an electronic device, and a mobile object of the present invention will be described in detail based on the accompanying drawings. Note that each embodiment described below does not unduly limit the contents described in the claims, and not all of the configurations described in each embodiment are essential components.

1. First Embodiment First, a CMOS output circuit and a semiconductor device according to a first embodiment will be described.

1.1. Outline of Semiconductor Device FIG. 1 is a circuit diagram showing an internal block configuration of a semiconductor device including a CMOS output circuit according to the first embodiment.

The semiconductor device 10 shown in FIG. 1 includes a first power line 11, a second power line 12, an output line 13, an input line 14, an internal circuit 17, and a CMOS output circuit 2.

The first power supply line 11 is connected to a power supply terminal 111 at one end, and is a power supply line that supplies, for example, a positive power supply potential VCC. The second power supply line 12 is connected to the GND terminal 121 at one end, and is, for example, a GND line that supplies the GND potential VSS. The output line 13 is connected to an output terminal 131 at one end, and outputs a signal of an output potential VOUT from the CMOS output circuit 16. The input line 14 connects the internal circuit 17 and the CMOS output circuit 2 and inputs an input signal from the internal circuit 17 to the CMOS output circuit 2.

The CMOS output circuit 2 is connected to a first power line 11, a second power line 12, an output line 13, and an input line 14, as shown in FIG. The CMOS output circuit 2 includes a CMOS circuit 20, a first switching circuit 21, and a second switching circuit 22. The CMOS circuit 20 is an output buffer corresponding to the internal circuit 17, and has complementary MOS transistors including a first PMOS transistor MP1 and a first NMOS transistor MN1.

The first PMOS transistor MP1 is connected to the first power supply line 11, the output line 13, and the input line 14. The first NMOS transistor MN1 is connected to the second power line 12, the output line 13, and the input line 14. Note that PMOS refers to P-channel Metal Oxide Semiconductor, and NMOS refers to N-channel Metal Oxide Semiconductor.

The first switching circuit 21 controls the potential of the substrate Sub (back gate) of the first PMOS transistor MP1. The second switching circuit 22 controls the potential of the substrate Sub (back gate) of the first NMOS transistor MN1. Thereby, even if the output potential VOUT exceeds the power supply potential VCC, for example, the potential of the substrate Sub of the first PMOS transistor MP1 can be controlled, and it is possible to suppress the first PMOS transistor MP1 from turning on. . Further, even when the output potential VOUT is lower than the GND potential VSS, for example, the potential of the substrate Sub of the first NMOS transistor MN1 can be controlled, and it is possible to suppress the first NMOS transistor MN1 from turning on. Furthermore, it is possible to suppress the latch-up phenomenon from occurring in the parasitic thyristor formed in the CMOS circuit 20.

1.1.1. Overview of CMOS Output Circuit Next, the CMOS output circuit 2 according to this embodiment will be explained.

As described above, the CMOS output circuit 2 shown in FIG. 1 includes the CMOS circuit 20 including the first PMOS transistor MP1 and the first NMOS transistor MN1.

The gate G of the first PMOS transistor MP1 shown in FIG. 1 is connected to the gate G of the first NMOS transistor MN1 and the internal circuit 17. A source S of the first PMOS transistor MP1 is connected to the first power supply line 11. The drain D of the first PMOS transistor MP1 is connected to the drain D of the first NMOS transistor MN1.

The gate G of the first NMOS transistor MN1 shown in FIG. 1 is connected to the gate G of the first PMOS transistor MP1 and the internal circuit 17. A source S of the first NMOS transistor MN1 is connected to the second power supply line 12. The drain D of the first NMOS transistor MN1 is connected to the drain D of the first PMOS transistor MP1.

Further, the CMOS output circuit 2 shown in FIG. 1 includes the first switching circuit 21 and the second switching circuit 22, as described above.

The first switching circuit 21 includes a second PMOS transistor MP2 and a third PMOS transistor MP3. The source S of the second PMOS transistor MP2 is connected to the substrate Sub of the first PMOS transistor MP1, the drain D of the second PMOS transistor MP2 is connected to the first power supply line 11, and the gate G of the second PMOS transistor MP2 is connected to the output line 13. The source S of the third PMOS transistor MP3 is connected to the substrate Sub of the first PMOS transistor MP1, the drain D of the third PMOS transistor MP3 is connected to the output line 13, and the gate G of the third PMOS transistor MP3 is connected to the first power supply line 11.

The second switching circuit 22 includes a second NMOS transistor MN2 and a third NMOS transistor MN3. The source S of the second NMOS transistor MN2 is connected to the substrate Sub of the first NMOS transistor MN1, the drain D of the second NMOS transistor MN2 is connected to the second power supply line 12, and the gate G is connected to the output line 13. . The source S of the third NMOS transistor MN3 is connected to the substrate Sub of the first NMOS transistor MN1, the drain D of the third NMOS transistor MN3 is connected to the output line 13, and the gate G of the third NMOS transistor MN3 is connected to the second power supply line 12.

1.1.2. Operation of CMOS output circuit 1.1.2.1. Normal Operation Next, the operation of the CMOS output circuit 2 will be explained.

First, a case where the output potential VOUT is within the normal operation voltage range, that is, a case where the output potential VOUT satisfies VSS<VOUT<VCC will be described.

In this case, in the first switching circuit 21, the output potential VOUT is supplied to the gate G of the second PMOS transistor MP2, and the power supply potential VCC is supplied to the gate G of the third PMOS transistor MP3. Therefore, the second PMOS transistor MP2 is turned on, and the third PMOS transistor MP3 is turned off. As a result, the power supply potential VCC is supplied to the substrate Sub of the first PMOS transistor MP1.

Furthermore, in the second switching circuit 22, the output potential VOUT is supplied to the gate G of the second NMOS transistor MN2, and the GND potential VSS is supplied to the gate G of the third NMOS transistor MN3. Therefore, the second NMOS transistor MN2 is turned on, and the third NMOS transistor MN3 is turned off. As a result, the GND potential VSS is supplied to the substrate Sub of the first NMOS transistor MN1.

As a result, in the first PMOS transistor MP1 and the first NMOS transistor MN1, the source S and the substrate Sub have the same potential. Therefore, in this case, the CMOS circuit 20 performs normal operation.

1.1.2.2. Operation when VOUT>VCC Next, a case where the output potential VOUT exceeds the power supply potential VCC, that is, a case where the output potential VOUT satisfies VOUT>VCC will be described.
FIG. 2 is a vertical cross-sectional view showing the cross-sectional structure of the CMOS output circuit 2 shown in FIG.

As an example, the CMOS output circuit 2 shown in FIG. 2 includes a triple well including a P-type semiconductor substrate 600P, an N-impurity region 601N which is an N-type semiconductor region, and a P-impurity region 621P which is a P-type semiconductor region. It has a structure.

In the CMOS output circuit 2 having such a structure, there is a risk that the above-described latch-up phenomenon may occur depending on the arrangement of elements, but according to the present embodiment, the occurrence of such latch-up phenomenon is suppressed, and the twin well structure It is possible to achieve a smaller size.

The first PMOS transistor MP1 shown in FIG. 2 includes a P-type semiconductor substrate 600P, an N- impurity region 601N, P+ impurity regions 602P and 603P, an N+ impurity region 604N, and a gate electrode 605. The N+ impurity region 604N corresponds to the substrate Sub of the first PMOS transistor MP1, the P+ impurity region 602P corresponds to the source S of the first PMOS transistor MP1, and the P+ impurity region 603P corresponds to the drain D of the first PMOS transistor MP1. However, the gate electrode 605 corresponds to the gate G of the first PMOS transistor MP1.

The P-type semiconductor substrate 600P is a semiconductor substrate having P-type polarity. Each region described below is, for example, a region formed by diffusing impurities into this semiconductor substrate.

N- impurity region 601N is a region located adjacent to P-type semiconductor substrate 600P and has N-type polarity.

The N+ impurity region 604N is a region having N type polarity connected to the N− impurity region 601N, and has a higher N type carrier concentration than the N− impurity region 601N.

P+ impurity regions 602P and 603P are each connected to N− impurity region 601N, have P type polarity, and have a higher P type carrier concentration than P− impurity region 621P, which will be described later.

A gate electrode 605 is provided between P+ impurity region 602P and P+ impurity region 603P.

The second PMOS transistor MP2 shown in FIG. 2 includes a P-type semiconductor substrate 600P, an N- impurity region 601N, P+ impurity regions 612P and 613P, and a gate electrode 615. The P+ impurity region 612P corresponds to the drain D of the second PMOS transistor MP2, the P+ impurity region 613P corresponds to the source S of the second PMOS transistor MP2, and the gate electrode 615 corresponds to the gate G of the second PMOS transistor MP2.

The third PMOS transistor MP3 shown in FIG. 2 includes a P-type semiconductor substrate 600P, an N- impurity region 601N, P+ impurity regions 613P and 614P, and a gate electrode 616. The P+ impurity region 614P corresponds to the drain D of the third PMOS transistor MP3, the P+ impurity region 613P corresponds to the source S of the third PMOS transistor MP3, and the gate electrode 616 corresponds to the gate G of the third PMOS transistor MP3.

The P+ impurity regions 612P, 613P, and 614P are each connected to the N− impurity region 601N, have P type polarity, and have a higher P type carrier concentration than the P− impurity region 621P described later. .

A gate electrode 615 is provided between the P+ impurity region 612P and the P+ impurity region 613P, and a gate electrode 616 is provided between the P+ impurity region 613P and the P+ impurity region 614P.

The first NMOS transistor MN1 shown in FIG. 2 includes a P-type semiconductor substrate 600P, an N- impurity region 601N, a P- impurity region 621P, N+ impurity regions 622N, 623N, a P+ impurity region 624P, and a gate electrode 625. have. The P+ impurity region 624P corresponds to the substrate Sub of the first NMOS transistor MN1, the N+ impurity region 622N corresponds to the source S of the first NMOS transistor MN1, and the N+ impurity region 623N corresponds to the drain D of the first NMOS transistor MN1. However, the gate electrode 625 corresponds to the gate G of the first NMOS transistor MN1.

P- impurity region 621P is located adjacent to N- impurity region 601N and has P-type polarity.

The P+ impurity region 624P is a region having P type polarity connected to the P− impurity region 621P, and has a higher P type carrier concentration than the P− impurity region 621P.

N+ impurity regions 622N and 623N are each connected to P− impurity region 621P, have N type polarity, and have a higher N type carrier concentration than N− impurity region 601N.

A gate electrode 625 is provided between the N+ impurity region 622N and the N+ impurity region 623N.

The second NMOS transistor MN2 shown in FIG. 2 includes a P-type semiconductor substrate 600P, an N- impurity region 601N, a P- impurity region 621P, N+ impurity regions 632N and 633N, and a gate electrode 635. The N+ impurity region 632N corresponds to the drain D of the second NMOS transistor MN2, the N+ impurity region 633N corresponds to the source S of the second NMOS transistor MN2, and the gate electrode 635 corresponds to the gate G of the second NMOS transistor MN2.

The third NMOS transistor MN3 shown in FIG. 2 includes a P-type semiconductor substrate 600P, an N- impurity region 601N, a P- impurity region 621P, N+ impurity regions 633N and 634N, and a gate electrode 636. The N+ impurity region 634N corresponds to the drain D of the third NMOS transistor MN3, the N+ impurity region 633N corresponds to the source S of the third NMOS transistor MN3, and the gate electrode 636 corresponds to the gate G of the third NMOS transistor MN3.

N+ impurity regions 632N, 633N, and 634N are each connected to P− impurity region 621P, have N type polarity, and have a higher N type carrier concentration than N− impurity region 601N.

A gate electrode 635 is provided between the N+ impurity region 632N and the N+ impurity region 633N, and a gate electrode 636 is provided between the N+ impurity region 633N and the N+ impurity region 634N.

The operation of the CMOS output circuit 2 when VOUT>VCC will be further described below with reference to the cross-sectional view of FIG. In this case, in the first switching circuit 21, the output potential VOUT is supplied to the gate G of the second PMOS transistor MP2, and the power supply potential VCC is supplied to the gate G of the third PMOS transistor MP3. Therefore, the second PMOS transistor MP2 is turned off, and the third PMOS transistor MP3 is turned on. As a result, the output potential VOUT is supplied to the substrate Sub of the first PMOS transistor MP1.

As a result, in the first PMOS transistor MP1, injection of minority carriers from the drain D into the N- impurity region 601N is suppressed. Then, it is possible to suppress the first PMOS transistor MP1 from turning on. As a result, the current path from the output terminal 131 to the power supply terminal 111 can be cut off, and malfunctions of the internal circuit 17 due to fluctuations in the power supply potential VCC can be suppressed.

In addition, in the CMOS output circuit 2, in order to control the potential of the substrate Sub of the first PMOS transistor MP1 and the potential of the substrate Sub of the first NMOS transistor MN1, the CMOS output circuit 2 uses a substrate bias generation circuit and a boosted potential that are required in the conventional technology. A potential control circuit like a generation circuit is not required. Therefore, it is easy to downsize the CMOS output circuit 2.

Furthermore, in the CMOS output circuit 2, it is possible to suppress the occurrence of a latch-up phenomenon in the parasitic thyristor 7 formed in the CMOS circuit 20 shown in FIG. That is, it is possible to suppress the occurrence of a phenomenon in which the parasitic thyristor 7 is turned on and a large current continues to flow from the first power line 11 to the second power line 12.

Specifically, the CMOS output circuit 2 shown in FIG. 2 has a PNPN structure. Therefore, in the CMOS output circuit 2 shown in FIG. 2, a parasitic thyristor 7 including a parasitic PNP bipolar transistor 71 and a parasitic NPN bipolar transistor 72 is formed. The anode of this parasitic thyristor 7 is, for example, a P+ impurity region 612P, the cathode is, for example, an N+ impurity region 632N, the first gate is an N+ impurity region 604N, and the second gate is a P+ impurity region 624P. .

When the output potential VOUT satisfies VOUT>VCC, that is, when a positive electrostatic surge that makes the output potential VOUT higher than the power supply potential VCC is applied to the output line 13, as described above, the second PMOS transistor MP2 Since the third PMOS transistor MP3 is turned off and turned on, the surge current A1 shown in FIG. 2 flows from the output line 13 to the P+ impurity region 614P and the P+ impurity region 613P. Furthermore, it flows into the N+ impurity region 604N, which is the first gate of the parasitic thyristor 7. Thereby, the potential of the first gate of the parasitic thyristor 7 can be changed to the off side, and the occurrence of latch-up phenomenon can be suppressed.

In addition to the application of a positive electrostatic surge, examples of the output potential VOUT becoming higher than the power supply potential VCC include an overshoot of the output signal and the like.

Furthermore, in the CMOS output circuit 2 shown in FIG. 2, the first PMOS transistor MP1 forming part of the CMOS circuit 20, and the second PMOS transistor MP2 and third PMOS transistor MP3 forming the first switching circuit 21 are identical to each other. It has an N- impurity region 601N (N-type semiconductor region). Furthermore, the first NMOS transistor MN1 constituting the other part of the CMOS circuit 20, the second NMOS transistor MN2 and the third NMOS transistor MN3 constituting the second switching circuit 22 are in the same P- impurity region 621P (P-type semiconductor region ).

According to such a configuration, the area required for the layout of the CMOS output circuit 2 can be reduced compared to the case where regions are separated from each other. Thereby, further miniaturization of the CMOS output circuit 2 can be achieved.

Furthermore, in the CMOS output circuit 2 shown in FIG. 2, a first switching circuit 21 and a second switching circuit 22 are provided between the first PMOS transistor MP1 and the first NMOS transistor MN1. That is, in the CMOS output circuit 2 shown in FIG. 2, the first PMOS transistor MP1, the first switching circuit 21, the second switching circuit 22, and the first NMOS transistor MN1 are arranged in this order.

According to such a configuration, the distance L1 between the emitter and the collector of the parasitic PNP bipolar transistor 71 and the distance L2 between the emitter and the collector of the parasitic NPN bipolar transistor 72 can be ensured to be sufficiently long. Thereby, the current amplification factors of the parasitic PNP bipolar transistor 71 and the parasitic NPN bipolar transistor 72 can be lowered. As a result, the probability that a latch-up phenomenon will occur can be further reduced.

Note that the arrangement of the first PMOS transistor MP1, the first switching circuit 21, the second switching circuit 22, and the first NMOS transistor MN1 is not limited to the arrangement shown in FIG. 2. For example, the first switching circuit 21 and the second switching circuit 22 may be arranged outside the first PMOS transistor MP1 and the first NMOS transistor MN1 instead of being arranged inside them.

1.1.2.3. Operation when VOUT<VSS Next, a case where the output potential VOUT is lower than the GND potential VSS, that is, a case where the output potential VOUT satisfies VOUT<VSS will be described.

Examples of the output potential VOUT being lower than the GND potential VSS include application of a negative electrostatic surge, undershoot of the output signal, and the like. In such a case, in the second switching circuit 22, the output potential VOUT is supplied to the gate G of the second NMOS transistor MN2, and the GND potential VSS is supplied to the gate G of the third NMOS transistor MN3. Therefore, the second NMOS transistor MN2 is turned off, and the third NMOS transistor MN3 is turned on. As a result, the output potential VOUT is supplied to the substrate Sub of the first NMOS transistor MN1.

As a result, in the first NMOS transistor MN1, injection of minority carriers from the drain D into the P- impurity region 621P is suppressed. This turns the first NMOS transistor MN1 off. As a result, the current path from the GND terminal 121 to the output terminal 131 can be cut off, and malfunctions of the internal circuit 17 due to fluctuations in the GND potential VSS can be suppressed.

Furthermore, in the CMOS output circuit 2, a surge current flows from the P+ impurity region 624P, which is the second gate, of the parasitic thyristor 7 formed in the CMOS circuit 20 shown in FIG. It can be changed to the off side. Thereby, the occurrence of latch-up phenomenon can be suppressed. That is, it is possible to suppress the occurrence of a phenomenon in which the parasitic thyristor 7 is turned on and a large current continues to flow from the first power line 11 to the second power line 12.

As described above, the CMOS output circuit 2 according to the present embodiment is a circuit connected to the first power line 11, the second power line 12, the output line 13, and the input line 14, and is connected to the CMOS circuit 20 and the second power line 12. 1 switching circuit 21 and a second switching circuit 22. Of these, the CMOS circuit 20 includes a first PMOS transistor MP1 connected to the first power line 11, the output line 13, and the input line 14, and a first PMOS transistor MP1 connected to the second power line 12, the output line 13, and the input line 14. 1NMOS transistor MN1.

Further, the first switching circuit 21 includes a second PMOS transistor MP2 and a third PMOS transistor MP3, and controls the potential of the substrate Sub of the first PMOS transistor MP1. As described above, the source S of the second PMOS transistor MP2 is connected to the substrate Sub of the first PMOS transistor MP1, the drain D of the second PMOS transistor MP2 is connected to the first power supply line 11, and the source S of the second PMOS transistor MP2 is connected to the substrate Sub of the first PMOS transistor MP1. G is connected to the output line 13. The source S of the third PMOS transistor MP3 is connected to the substrate Sub of the first PMOS transistor MP1, the drain D of the third PMOS transistor MP3 is connected to the output line 13, and the gate G of the third PMOS transistor MP3 is connected to the first power supply line 11.

Furthermore, the second switching circuit 22 includes a second NMOS transistor MN2 and a third NMOS transistor MN3, and controls the potential of the substrate Sub of the first NMOS transistor MN1. As described above, the source S of the second NMOS transistor MN2 is connected to the substrate Sub of the first NMOS transistor MN1, the drain D of the second NMOS transistor MN2 is connected to the second power supply line 12, and the gate G is connected to the output line 13. It is connected to the. The source S of the third NMOS transistor MN3 is connected to the substrate Sub of the first NMOS transistor MN1, the drain D of the third NMOS transistor MN3 is connected to the output line 13, and the gate G of the third NMOS transistor MN3 is connected to the second power supply line 12.

According to such a configuration, fluctuations in the power supply potential VCC and GND potential VSS due to abnormal voltage and the occurrence of latch-up phenomenon in the CMOS output circuit 2 are suppressed, regardless of the polarity of the abnormal voltage due to electrostatic surge or noise. can do. As a result, malfunctions and destruction of the internal circuit 17 due to abnormal voltage can be suppressed, and a highly reliable CMOS output circuit 2 can be realized. Furthermore, with the above configuration, a potential control circuit such as a substrate bias generation circuit or a boosted potential generation circuit, which the prior art had, is not required in order to obtain such an effect. Therefore, it is possible to prevent the circuit scale of the CMOS output circuit 2 from increasing and realize a small CMOS output circuit 2.

The semiconductor device 10 according to this embodiment includes this CMOS output circuit 2. Thereby, by enjoying the effects of the CMOS output circuit 2 described above, the reliability of the semiconductor device 10 can be improved, and the size and cost of the semiconductor device 10 can be reduced.

2. Second Embodiment Next, a CMOS output circuit according to a second embodiment will be described.
FIG. 3 is a vertical cross-sectional view showing the cross-sectional structure of a CMOS output circuit according to the second embodiment.

The second embodiment will be described below. In the following description, differences from the first embodiment will be mainly explained, and descriptions of similar matters will be omitted. Note that in FIG. 3, the same components as in the first embodiment are designated by the same reference numerals.

In the first embodiment described above, as shown in FIG. 2, the potential of the first gate of the parasitic thyristor 7 can be changed to the off side by the surge current A1 flowing into the N+ impurity region 604N. Thereby, the occurrence of latch-up phenomenon can be suppressed.

However, the current flowing into the N+ impurity region 604N changes the potential of the first gate of the parasitic thyristor 7 via the parasitic resistance 81 of the N- impurity region 601N. Therefore, depending on the size of the parasitic resistance 81, etc., there is a possibility that a delay in potential change due to the influence of the parasitic resistance 81 may occur.

Therefore, the CMOS output circuit 2A according to this embodiment includes an N+ impurity region 606N in addition to the N+ impurity region 604N as the substrate Sub of the first PMOS transistor MP1. Further, the CMOS output circuit 2A has a P+ impurity region 626P in addition to the P+ impurity region 624P as a substrate Sub of the first NMOS transistor MN1.

Specifically, the CMOS output circuit 2A has an N+ impurity region 606N (first contact portion) that is electrically conductive to an N- impurity region 601N (N-type semiconductor region) and a P- impurity region 621P (P-type impurity region) that is electrically conductive. P+ impurity region 626P (second contact portion). The N+ impurity region 606N is connected to the source S of the second PMOS transistor MP2 and the source S of the third PMOS transistor MP3. The P+ impurity region 626P is connected to the source S of the second NMOS transistor MN2 and the source S of the third NMOS transistor MN3.

The N+ impurity region 606N and the P+ impurity region 626P are located between the first switching circuit 21 and the second switching circuit 22.

According to such a configuration, the N+ impurity region 606N that controls the potential of the substrate Sub of the first PMOS transistor MP1 can be placed near the parasitic thyristor 7 shown in FIG. In other words, the surge current A2 shown in FIG. 3 flows into the N+ impurity region 606N located near the parasitic thyristor 7. Therefore, the influence of the parasitic resistance 81 of the N- impurity region 601N can be reduced in the time required to change the potential, and the delay when changing the potential of the first gate of the parasitic thyristor 7 can be minimized. can. Thereby, the occurrence of the latch-up phenomenon can be more reliably suppressed.

Similarly, a P+ impurity region 626P that controls the potential of the substrate Sub of the first NMOS transistor MN1 can be placed near the parasitic thyristor 7 shown in FIG. Therefore, the influence of the parasitic resistance 82 of the P- impurity region 621P can be reduced, and as described above, the delay in changing the potential of the second gate of the parasitic thyristor 7 can be minimized. Thereby, the occurrence of the latch-up phenomenon can be more reliably suppressed.

In the second embodiment as described above, the same effects as in the first embodiment can be obtained.
Note that the N+ impurity region 606N is connected to the N- impurity region 601N, has N-type polarity, and has a higher N-type carrier concentration than the N- impurity region 601N. Further, the P+ impurity region 626P is connected to the P− impurity region 621P, has P type polarity, and has a higher P type carrier concentration than the P− impurity region 621P.

3. Third Embodiment Next, a CMOS output circuit according to a third embodiment will be described.
FIG. 4 is a cross-sectional view showing the cross-sectional structure of a CMOS output circuit according to the third embodiment.

The third embodiment will be described below. In the following description, differences from the first embodiment will be mainly explained, and descriptions of similar matters will be omitted. Note that in FIG. 4, the same components as in the first embodiment are designated by the same reference numerals.

In the first embodiment described above, as shown in FIG. 2, the CMOS output circuit 2 has a triple well structure. On the other hand, as shown in FIG. 4, the CMOS output circuit 2B according to the present embodiment includes an N-impurity region 601N which is an N-type semiconductor region and a P-impurity region 621P which is a P-type semiconductor region. It has a twin well structure.

Specifically, in the first embodiment described above, as shown in FIG. 2, the P- impurity region 621P is included in the N- impurity region 601N. In contrast, in this embodiment, as shown in FIG. 4, N- impurity region 601N and P- impurity region 621P are adjacent to each other.

Even the CMOS output circuit 2B having such a twin well structure has the same effect as the CMOS output circuit 2 having a triple well structure.

Note that, unlike the CMOS output circuit 2 having a triple well structure, the CMOS output circuit 2B having a twin well structure has a P+ impurity region 627P for connecting the P− impurity region 621P and the second power supply line 12. ing. This P+ impurity region 627P is connected to the same P− impurity region 621P as the P+ impurity region 624P corresponding to the substrate Sub of the first NMOS transistor MN1. Therefore, a parasitic resistance 83 is formed between P+ impurity region 624P and P+ impurity region 627P. Due to the presence of this parasitic resistance 83, for example, when the output potential VOUT is lower than the GND potential VSS, the substrate Sub of the first NMOS transistor MN1 cannot be made to have the same potential as the output potential VOUT. Then, in the parasitic thyristor 7 shown in FIG. 4, the potential of the second gate becomes higher than the potential of the cathode, and the parasitic thyristor 7 may be turned on.

In such a case, by increasing the parasitic resistance 83, the parasitic thyristor 7 can be made less likely to turn on. Thereby, even in the CMOS output circuit 2B having the twin well structure shown in FIG. 4, the occurrence of latch-up phenomenon can be suppressed well.

Note that in order to increase the parasitic resistance 83, for example, the distance between the P+ impurity region 624P and the P+ impurity region 627P may be increased. However, in that case, the layout area of the CMOS output circuit 2B tends to increase. Therefore, from the viewpoint of reducing the size of the CMOS output circuit 2, it is preferable to adopt a triple well structure.
Also in the third embodiment as described above, the same effects as in the first embodiment can be obtained.

4. Reference Example Next, as a reference example in which a part of the present invention is utilized, an analog switch circuit will be described.
FIG. 5 is a circuit diagram showing the configuration of an analog switch circuit.

Hereinafter, a reference example will be described. In the following explanation, differences from the first embodiment will be mainly explained, and explanations of similar matters will be omitted. Note that in FIG. 5, the same components as in the first embodiment are designated by the same reference numerals.

The analog switch circuits 2C shown in FIG. 5 each have a part of the configuration of the CMOS output circuit 2 according to the first embodiment.

That is, the CMOS output circuit 2 according to the first embodiment includes a CMOS circuit 20, a first switching circuit 21, and a second switching circuit 22. On the other hand, the analog switch circuit 2C according to the reference example has a transmission gate circuit 20C including a parallel circuit of a fourth PMOS transistor MP4 and a fourth NMOS transistor MN4 instead of the CMOS circuit 20. The first switching circuit 21 then controls the potential of the substrate Sub of the fourth PMOS transistor MP4. The second switching circuit 22 controls the potential of the substrate Sub of the fourth NMOS transistor MN4.

Further, the analog switch circuit 2C shown in FIG. 5 further includes an inverter 9 connected to the first power line 11, the second power line 12, and the input line 14. An output terminal 91 of the inverter 9 is connected to the gate G of the fourth PMOS transistor MP4, and an input terminal 92 of the inverter 9 is connected to the input line 14 and the gate G of the fourth NMOS transistor MN4.

One of the source and drain of the fourth PMOS transistor MP4 is connected to the first input/output line 18, and the other is connected to the second input/output line 19. One of the source and drain of the fourth NMOS transistor MN4 is connected to the first input/output line 18, and the other is connected to the second input/output line 19.

The first input/output line 18 is an input/output line to which an input/output terminal 181 is connected at one end. The second input/output line 19 is an input/output line to which the input/output terminal 191 is connected at one end.

The first switching circuit 21 shown in FIG. 5 includes a second PMOS transistor MP2 and a third PMOS transistor MP3. One of the source and drain of the second PMOS transistor MP2 is connected to the first input/output line 18, the other is connected to the substrate Sub of the fourth PMOS transistor MP4, and the gate G of the second PMOS transistor MP2 is connected to the second input/output line 18. Connected to line 19. One of the source and drain of the third PMOS transistor MP3 is connected to the second input/output line 19, the other is connected to the substrate Sub of the fourth PMOS transistor MP4, and the gate G of the third PMOS transistor MP3 is connected to the first input/output line 19. connected to line 18.

The second switching circuit 22 shown in FIG. 5 includes a second NMOS transistor MN2 and a third NMOS transistor MN3. One of the source and drain of the second NMOS transistor MN2 is connected to the second input/output line 19, the other is connected to the substrate Sub of the fourth NMOS transistor MN4, and the gate G of the second NMOS transistor MN2 is connected to the first input/output line 19. connected to line 18. One of the source and drain of the third NMOS transistor MN3 is connected to the first input/output line 18, the other is connected to the substrate Sub of the fourth NMOS transistor MN4, and the gate G of the third NMOS transistor MN3 is connected to the second input/output line 18. Connected to line 19.

In such an analog switch circuit 2C, when an active control signal is input to the input line 14, signals that are mutually inverted by the inverter 9 are input to the gate G of the fourth PMOS transistor MP4 and the gate G of the fourth NMOS transistor MN4. be done. As a result, both the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4 are turned on, making bidirectional conduction between the first input/output line 18 and the second input/output line 19. On the other hand, when an inactive control signal is input to the input line 14, bidirectional conduction is interrupted in the analog switch circuit 2C.

In addition, in the analog switch circuit 2C, overshoot or undershoot of the signal in the first input/output line 18 or the second input/output line 19, as well as positive surge current and negative surge current, cause the fourth PMOS transistor MP4 and the fourth NMOS It is possible to prevent the transistor MN4 from turning on unintentionally. This causes a current to flow from the first input/output line 18 to the second input/output line 19 via the parasitic diode, or from the second input/output line 19 to the first input/output line 18 via the parasitic diode. , can be suppressed from occurring. As a result, for example, potential changes in the power supply connected to the first input/output line 18 or the second input/output line 19 and malfunctions of peripheral circuits caused by the change can be suppressed.

5. Electronic Device Next, an electronic device according to an embodiment will be described.
FIG. 6 is a block diagram showing a configuration example of an electronic device according to an embodiment.

As shown in FIG. 6, this electronic device 100 includes a CPU 220 (central processing unit), an operation section 230, a ROM 240 (read-only memory), a RAM 250 (random access memory), and a communication section 260. It includes a display section 270 and an audio output section 280.

Here, at least some of the CPU 220, ROM 240, RAM 250, communication section 260, display section 270, and audio output section 280 are built into the semiconductor device 10 according to the embodiment, although not shown. That is, the electronic device 100 includes a semiconductor device 10 that includes functional units that implement each function and the above-described CMOS output circuits 2, 2A, and 2B. As a result, in the semiconductor device 10, malfunctions and latch-up phenomena in the CMOS output circuits 2, 2A, and 2B are suppressed, reliability is improved, and the semiconductor device 10 is miniaturized.

Note that some of the components shown in FIG. 6 may be omitted or changed, or other components may be added to the components shown in FIG. 6.

The CPU 220 performs various signal processing and control processing using externally supplied data and the like according to programs stored in the ROM 240 and the like. For example, the CPU 220 performs various types of signal processing according to operation signals supplied from the operation unit 230, controls the communication unit 260 to perform data communication with the outside, and displays various types of information on the display unit 270. It generates an image signal for displaying an image, and generates an audio signal for causing the audio output unit 280 to output various sounds.

The operation unit 230 is, for example, an input device including operation keys, button switches, and the like, and outputs an operation signal to the CPU 220 in accordance with a user's operation. The ROM 240 stores programs, data, etc. for the CPU 220 to perform various signal processing and control processing. The RAM 250 is used as a work area for the CPU 220 and temporarily stores programs and data read from the ROM 240, data input using the operation unit 230, or calculation results executed by the CPU 220 according to the program. .

The communication unit 260 includes, for example, an analog circuit and a digital circuit, and performs data communication between the CPU 220 and an external device. The display unit 270 includes, for example, an LCD (liquid crystal display), and displays various images based on image signals supplied from the CPU 220.

The audio output unit 280 includes, for example, a speaker and the like, and outputs audio based on the audio signal supplied from the CPU 220.

Such electronic devices 100 include, for example, clocks such as wristwatches and table clocks, timers, mobile terminals such as mobile phones, digital still cameras, digital movies, televisions, videophones, security television monitors, head-mounted displays, and personal computers. Examples include computers, printers, network devices, multifunction devices, in-vehicle devices, calculators, electronic dictionaries, electronic game devices, robots, measuring devices, medical devices, etc.

6. Mobile Object Next, a mobile object according to the embodiment will be described.
FIG. 7 is a perspective view showing an automobile to which the moving body according to the embodiment is applied.

An automobile 150 (mobile object) shown in FIG. 7 includes the semiconductor device 10 according to the embodiment. Specifically, the semiconductor device 10 is used in electronic devices such as car navigation systems, anti-lock brake systems (ABS), engine control units, battery control units for hybrid vehicles and electric vehicles, vehicle attitude control systems, and automatic driving systems. It is built into various automotive parts such as control units (ECUs), drive motors, generators, and air conditioner units. In the semiconductor device 10, malfunctions and latch-up phenomena in the CMOS output circuits 2, 2A, and 2B are suppressed, reliability is improved, and the device is miniaturized. Therefore, it is possible to realize a highly reliable automobile 150 with a high degree of freedom in mounting the semiconductor device 10.

In addition to the automobile shown in FIG. 7, the moving object according to this embodiment can also be applied to, for example, a motorcycle, a bicycle, an aircraft, a helicopter, a drone, a ship, a submarine, a railway, a rocket, a spaceship, and the like.

Although the CMOS output circuit, semiconductor device, electronic device, and moving body of the present invention have been described above based on the illustrated embodiments, the present invention is not limited thereto. For example, the CMOS output circuit, semiconductor device, electronic device, and mobile object of the present invention may be obtained by replacing the configuration of each part of the above embodiment with an arbitrary structure having a similar function. An arbitrary component may be added. Further, in the embodiment described above, a P-type semiconductor substrate is used, but an N-type semiconductor substrate may be used.

2... CMOS output circuit, 2A... CMOS output circuit, 2B... CMOS output circuit, 2C... analog switch circuit, 7... parasitic thyristor, 9... inverter, 10... semiconductor device, 11... first power supply line, 12... second power supply line, 13...output line, 14...input line, 16...CMOS output circuit, 17...internal circuit, 18...first input/output line, 19...second input/output line, 20...CMOS circuit, 20C...transmission gate circuit, 21... First switching circuit, 22... Second switching circuit, 71... Parasitic PNP bipolar transistor, 72... Parasitic NPN bipolar transistor, 81... Parasitic resistance, 82... Parasitic resistance, 83... Parasitic resistance, 91... Output end, 92...Input terminal, 100...Electronic device, 111...Power terminal, 121...GND terminal, 131...Output terminal, 150...Automobile, 181...Input/output terminal, 191...Input/output terminal, 220...CPU, 230...Operation unit, 240...ROM, 250...RAM, 260...communication section, 270...display section, 280...audio output section, 600P...P type semiconductor substrate, 601N...N- impurity region, 602P...P+ impurity region, 603P...P+ impurity region, 604N...N+ impurity region, 605...gate electrode, 606N...N+ impurity region, 612P...P+ impurity region, 613P...P+ impurity region, 614P...P+ impurity region, 615...gate electrode, 616...gate electrode, 621P...P- impurity region region, 622N...N+ impurity region, 623N...N+ impurity region, 624P...P+ impurity region, 625... gate electrode, 626P...P+ impurity region, 627P...P+ impurity region, 632N...N+ impurity region, 633N...N+ impurity region, 634N ...N+ impurity region, 635...gate electrode, 636...gate electrode, A1...surge current, A2...surge current, D...drain, G...gate, L1...distance, L2...distance, MN1...first NMOS transistor, MN2...th 2NMOS transistor, MN3...3rd NMOS transistor, MN4...4th NMOS transistor, MP1...1st PMOS transistor, MP2...2nd PMOS transistor, MP3...3rd PMOS transistor, MP4...4th PMOS transistor, S...source, Sub...substrate, VCC... Power supply potential, VOUT...output potential, VSS...GND potential

Claims (8)

A CMOS output circuit connected to a first power line, a second power line, an output line, and an input line,
a CMOS circuit including a first PMOS transistor connected to the first power line, the output line and the input line; and a first NMOS transistor connected to the second power line, the output line and the input line;
a first switching circuit that controls the potential of the substrate of the first PMOS transistor;
a second switching circuit that controls the potential of the substrate of the first NMOS transistor;
has
The first switching circuit includes:
a second PMOS transistor having a source connected to the substrate of the first PMOS transistor, a drain connected to the first power supply line, and a gate connected to the output line;
a third PMOS transistor having a source connected to the substrate of the first PMOS transistor, a drain connected to the output line, and a gate connected to the first power supply line;
including;
The second switching circuit includes:
a second NMOS transistor having a source connected to the substrate of the first NMOS transistor, a drain connected to the second power supply line, and a gate connected to the output line;
a third NMOS transistor having a source connected to the substrate of the first NMOS transistor, a drain connected to the output line, and a gate connected to the second power supply line;
A CMOS output circuit comprising: The CMOS output circuit according to claim 1, having a twin-well structure or a triple-well structure including an N-type semiconductor region and a P-type semiconductor region. The first PMOS transistor, the second PMOS transistor, and the third PMOS transistor have the same N-type semiconductor region,
3. The CMOS output circuit according to claim 2, wherein the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor have the same P-type semiconductor region. a first contact portion connected to the source of the second PMOS transistor and the source of the third PMOS transistor and electrically connected to the N-type semiconductor region;
a second contact portion connected to the source of the second NMOS transistor and the source of the third NMOS transistor and electrically connected to the P-type semiconductor region;
has
4. The CMOS output circuit according to claim 3, wherein the first contact part and the second contact part are located between the first switching circuit and the second switching circuit. 5. The CMOS output circuit according to claim 1, wherein the first switching circuit and the second switching circuit are provided between the first PMOS transistor and the first NMOS transistor. A semiconductor device comprising the CMOS output circuit according to claim 1. An electronic device comprising the semiconductor device according to claim 6. A mobile object comprising the semiconductor device according to claim 6.

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