JP7458824B2 - Printed wiring board and method for manufacturing printed wiring board - Google Patents

Description

The present disclosure relates to a printed wiring board and a method of manufacturing the printed wiring board.

Conventionally, there are printed wiring boards that have multiple circuit layers separated by insulating layers, and these multiple circuit layers are electrically connected by vias or through holes to form a three-dimensional circuit (for example, Patent Document 1). A method for forming such a multilayer printed wiring board is known in which a build-up layer having an insulating layer and a conductor layer is laminated on the surface of a core layer on which a circuit layer is formed. A widely used insulating layer for the build-up layer is a base material such as glass cloth impregnated with resin.

Furthermore, when an antenna circuit for transmitting high-frequency signals is formed on a printed wiring board, there is a technique of forming a waveguide, which is a small, low-loss transmission line, inside the printed wiring board. A waveguide is composed of a tubular conductor extending in the thickness direction of a printed wiring board and a dielectric material filling the inside of this conductor. In the multilayer printed wiring board having the core layer and buildup layer described above, a tubular through hole is formed in the core layer, and a plurality of vias are formed in the buildup layer at positions surrounding the through hole in plan view. In this case, a waveguide can be formed by a through hole, a plurality of vias, and a dielectric inside these.

Japanese Patent Application Publication No. 2017-135357

A printed wiring board according to one embodiment of the present disclosure includes:
The laminated ...
The core layer has a core insulating layer and a through hole,
the through hole is tubular, passes through the core insulating layer, and electrically connects between the conductors provided on both sides of the core insulating layer;
the build-up layer includes an interlayer insulating layer and a plurality of vias;
the interlayer insulating layer contains a base material made of a dielectric,
the vias are electrically connected to the through holes, penetrate the interlayer insulating layer, and are provided at positions surrounding the through holes when viewed from a direction perpendicular to the first surface;
a region of the interlayer insulating layer that is surrounded by the plurality of vias is defined as a first region, and a region excluding the first region is defined as a second region, the first region having a smaller volume ratio of the base material than the second region;
The vias are arranged such that a portion of the periphery of each via runs along the inner wall of the through hole when viewed from a direction perpendicular to the first surface .

In addition, a method for producing a printed wiring board according to another aspect of the present disclosure includes:
forming a first opening in a first prepreg containing a base material made of a dielectric;
a step of laminating the first prepreg on a core layer having a core insulation layer and a tubular through hole penetrating the core insulation layer at a position where the through hole and the first opening overlap when viewed from a direction perpendicular to a first surface of the core layer, and laminating a metal foil on the first prepreg to form a first laminate;
a step of heating and pressurizing the first laminate to fill the inside of the first opening with a molten material of the first prepreg while solidifying the molten material, thereby forming a first interlayer insulating layer on the core layer;
forming a plurality of first vias extending from lands of the through holes, electrically connected to the through holes, and penetrating the first interlayer insulating layer at positions surrounding the through holes when viewed in a direction perpendicular to the first surface;
Including,
In the step of forming the plurality of first vias, each of the first vias is formed at a position where a portion of a periphery of each of the first vias is along an inner wall of the through hole when viewed in a direction perpendicular to the first surface .

FIG. 2 is a cross-sectional view of a printed wiring board. FIG. 2 is a plan view showing the positional relationship between through holes and vias. FIG. 3 is a diagram showing a cross section of the first buildup layer. It is a figure showing the cross section of the 2nd buildup layer. FIG. 2 is a schematic perspective view illustrating a method for manufacturing a printed wiring board. FIG. 2 is a cross-sectional view illustrating a method for manufacturing a printed wiring board. 5A to 5C are cross-sectional views illustrating a method for manufacturing a printed wiring board. FIG. 3 is a cross-sectional view illustrating a method for manufacturing a printed wiring board. It is a sectional view of the printed wiring board concerning a modification.

Hereinafter, embodiments will be described based on the drawings. However, the dimensions of the members in each figure do not faithfully represent the dimensions and dimensional ratios of the actual constituent members.

[Configuration of printed wiring board]
FIG. 1 is a cross-sectional view of a printed wiring board 1 according to this embodiment.
The printed wiring board 1 is a board in which an antenna used for a millimeter wave radar or the like and a transmission line for transmitting a signal received by the antenna are built-in. The printed wiring board 1 includes a core layer C, a first buildup layer B1 and a second buildup layer B2 which are laminated in order on a first surface S1 of the core layer C, and a second buildup layer B1 and a second buildup layer B2 which are laminated in order on a second surface S2 of the core layer C. The first buildup layer B1 and the second buildup layer B2 are provided. Here, in the core layer C, the second surface S2 is a surface located on the opposite side of the first surface S1. Hereinafter, when any one of the first buildup layer B1 and the second buildup layer B2 is referred to, it will be referred to as "buildup layer B." In this embodiment, two buildup layers B are laminated on the front and back sides of the core layer C, respectively.
Further, hereinafter, the orientation of each part of the printed wiring board 1 will be explained using an XYZ orthogonal coordinate system in which the thickness direction of the printed wiring board 1 is the Z direction. The first surface S1 and the second surface S2 of the core layer C are parallel to the XY plane. FIG. 1 is a diagram showing a cross section of printed wiring board 1 perpendicular to the Y direction. Hereinafter, the surface facing the +Z direction of each layer constituting the printed wiring board 1 will also be referred to as the "upper surface", and the surface facing the −Z direction will also be referred to as the "lower surface".

The core layer C has a core insulation layer 20, a core conductor layer 30, and through holes 50, 51.

The core insulating layer 20 here consists of three interlayer insulating layers. However, the structure is not limited to this, and may have two or less layers or four or more layers. The material of the core insulating layer 20 is not particularly limited as long as it has insulating properties. Examples of the material of the core insulating layer 20 include organic resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether (PPE) resin. Two or more of these organic resins may be used in combination. When using an organic resin as the interlayer insulating layer, it is preferable to mix a reinforcing material with the organic resin. Examples of the reinforcing material include glass cloth such as glass fiber and glass nonwoven fabric, aramid cloth such as aramid nonwoven fabric and aramid fiber, and polyester fiber. Two or more of these reinforcing materials may be used in combination. The core insulating layer 20 is preferably formed from an organic resin containing a glass material such as glass cloth. Furthermore, the core insulating layer 20 may contain inorganic fillers such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide.

The core conductor layer 30 consists of four conductor layers. That is, the core conductor layer 30 includes a first layer formed on the upper surface of the core insulating layer 20, second and third layers provided at the two interfaces between the interlayer insulating layers, and a lower surface of the core insulating layer 20. It consists of a fourth layer. Each conductor layer of the core conductor layer 30 forms a wiring pattern. The material of the core conductor layer 30 is, for example, copper, although it is not particularly limited. The number of conductor layers in the core conductor layer 30 is not limited to four layers, and may be three or less or five or more layers depending on the number of interlayer insulating layers included in the core insulating layer 20.

The through holes 50 and 51 are tubular conductors provided on the inner wall surface of the through hole penetrating the core insulating layer 20. The through holes 50 and 51 are also called IVH (Interstitial Via Holes). The through holes 50 and 51 electrically connect the portions of the first to fourth layers of the core conductor layer 30 that are connected to the through holes 50 and 51. Furthermore, lands of the through holes 50 and 51 are formed by parts of the first layer and the fourth layer of the core conductor layer 30. The insides of the through holes 50 and 51 are filled with an insulator that is integrally connected to the first interlayer insulating layer 21. The material of the through holes 50 and 51 is not particularly limited, but may be copper, for example.
The through hole 50 constitutes a part of the waveguide 2 described later. The through hole 50 has a rectangular shape when viewed from the direction (Z direction) perpendicular to the first surface S1 (see FIG. 5).
The through hole 51 is provided for the purpose of electrically connecting each layer of the core conductor layer 30. The through hole 51 has a circular shape when viewed from the Z direction.

The first buildup layer B1 is laminated on the first surface S1 and the second surface S2 of the core layer C. The first buildup layer B1 has a flat first interlayer insulating layer 21, a conductor layer 31, and a via 41 (first via).

The first interlayer insulating layer 21 contains a glass cloth G1 as a base material made of a dielectric material. The glass cloth G1 is, for example, glass fiber. The glass cloth G1 is distributed, for example, in a planar shape (flat plate shape) along the XY plane at the center of the first interlayer insulating layer 21 in the thickness direction. The glass cloth G1 functions as a reinforcing material that reinforces the first interlayer insulating layer 21. The portion of the first interlayer insulating layer 21 excluding the glass cloth G1 is made of resin R1. The resin R1 is also impregnated into the fibers of the glass cloth G1. The material of the resin R1 is not particularly limited as long as it has insulation properties. Examples of the material of the resin R1 include epoxy resin, bismaleimide-triazine resin, polyimide resin, polyphenylene ether (PPE) resin, phenol resin, polytetrafluoroethylene (PTFE) resin, silicon resin, polybutadiene resin, polyester resin, and melamine. resin, urea resin, polyphenylene sulfide (PPS) resin, polyphenylene oxide (PPO) resin, and the like. Two or more types of these resins may be mixed. The second interlayer insulating layer 22 may contain the above-mentioned inorganic filler or an organic filler made of phenol resin or methacrylic resin.

The conductor layer 31 is formed on the surface of the first interlayer insulating layer 21 opposite to the core layer C side, and forms a wiring pattern. The via 41 is made of a conductor that fills the via pilot hole that penetrates the first interlayer insulating layer 21, and electrically connects the conductor layer 31 and the portion of the core conductor layer 30 that forms the land of the through hole 50. are doing. The conductor layer 31 and the via 41 are formed by performing electrolytic plating on the first interlayer insulating layer 21 in which a via pilot hole is formed. A copper foil 70 (see FIG. 8(b)) is interposed between the lower surface of the conductor layer 31 and the upper surface of the first interlayer insulating layer 21, but its illustration is omitted in FIG.

The second buildup layer B2 is laminated on the side opposite to the core layer C side of the two first buildup layers B1. The second buildup layer B2 includes a flat second interlayer insulating layer 22, a conductor layer 32, and a via 42 (second via). The antenna conductor is composed of a conductor layer 32.

The structure of the second interlayer insulating layer 22, like the first interlayer insulating layer 21, includes a glass cloth G2 as a base material made of a dielectric material, and a resin R2 that fills the part other than the glass cloth G2. The glass cloth G2 is, for example, glass fiber. The glass cloth G2 is distributed, for example, in a planar shape (flat plate shape) along the XY plane at the center of the second interlayer insulating layer 22 in the thickness direction. The glass cloth G2 functions as a reinforcing material that reinforces the second interlayer insulating layer 22. The material of the glass cloth G2 can be the same as that of the glass cloth G1, but is not limited thereto. The material of the resin R2 is not particularly limited as long as it has insulation properties. The material of the resin R2 is the same as that of the resin R1, such as epoxy resin, bismaleimide-triazine resin, polyimide resin, polyphenylene ether (PPE) resin, phenol resin, polytetrafluoroethylene (PTFE) resin, silicone resin, and polybutadiene resin. , polyester resin, melamine resin, urea resin, polyphenylene sulfide (PPS) resin, polyphenylene oxide (PPO) resin, and the like. Two or more types of these resins may be mixed. The second interlayer insulating layer 22 may contain the above-mentioned inorganic filler or an organic filler made of phenol resin or methacrylic resin. In this embodiment, a material having a dielectric constant smaller than that of the resin R1 is used as the material for the resin R2. However, the material is not limited to this, and the resin R1 and the resin R2 may be made of the same material.

The conductor layer 32 is formed on the surface of the second interlayer insulating layer 22 opposite to the first build-up layer B1 side, forming a wiring pattern. The via 42 is made of a conductor that fills a via pilot hole penetrating the second interlayer insulating layer 22, and electrically connects the conductor layer 32 to a portion of the conductor layer 31 that forms the land of the via 41. Thus, the via 42 is electrically connected to the through hole 50 through the via 41. The conductor layer 32 and the via 42 are formed by electrolytic plating of the second interlayer insulating layer 22 in which the via pilot hole is formed. The antenna conductor is formed of the conductor layer 32. A copper foil 70 (see FIG. 8B) is interposed between the lower surface of the conductor layer 32 and the upper surface of the second interlayer insulating layer 22, but is omitted in FIG. 1.

Further, the printed wiring board 1 is provided with a through hole 52 that penetrates the core layer C, the pair of first buildup layers B1, and the pair of second buildup layers B2. The through hole 52 is a tubular conductor provided on the inner wall surface of a through hole that penetrates the entire printed wiring board 1, and the inside of the through hole 52 is filled with an insulator 23.

In the printed wiring board 1 , a waveguide 2 is formed by a through hole 50 , a plurality of vias 41 , and a plurality of vias 42 . The configuration of the waveguide 2 will be explained below.

FIG. 2 is a plan view showing the positional relationship between the through hole 50 and the via 42.
FIG. 2 shows the positions of the openings of the through holes 50 and the prepared holes of the vias 42 when the printed wiring board 1 is viewed from the +Z direction. As shown in FIG. 2, in the second buildup layer B2, a plurality of vias 42 are provided at positions surrounding the through hole 50. That is, the formation positions of the vias 42 are determined so that the plurality of vias 42 are lined up along each side of the rectangle formed by the opening of the through hole 50. Here, in order to improve the characteristics as a waveguide, it is better for the vias 42 to be in contact with each other, but they may be spaced apart from each other. In this case, the distance between the vias 42 may be 1/4 or less of the wavelength of the signal to be transmitted.
Further, when the printed wiring board 1 is viewed from above, the plurality of vias 42 are preferably arranged such that a portion of the peripheral edge of each via 42 runs along the inner wall of the through hole 50. For example, even if the through hole 50 is not in a precise rectangular shape (rectangular or square) and the side that becomes the inner wall is curved, a part of the peripheral edge of each via 42 may be arranged along the curved side (inner wall). It is good that it is placed in In particular, it is preferable that all the vias 42 have a portion of their peripheral edge along the curved side of the through hole 50.
Although not shown in FIG. 2, a plurality of vias 41 are provided in positions surrounding the through holes 50 in the first buildup layer B1. That is, the formation positions of the vias 41 are determined so that the plurality of vias 41 are lined up along each side of the rectangle formed by the opening of the through hole 50.

In the printed wiring board 1, the waveguide 2 (see FIG. 1) is formed by arranging the through hole 50, the plurality of vias 41, and the plurality of vias 42 in this manner. That is, the waveguide 2 includes a tubular through hole 50, a plurality of vias 41, a plurality of vias 42, and a dielectric surrounded by these conductors. This waveguide 2 allows signals received by the antenna conductor to be transmitted from the top surface of the printed wiring board 1 to the bottom surface with low loss.

Here, the part of the first interlayer insulating layer 21 corresponding to the inside of the waveguide 2 does not contain the glass cloth G1, and the part of the second interlayer insulating layer 22 corresponding to the inside of the waveguide 2 does not contain the glass cloth G1. The corresponding portion does not contain glass cloth G2. This will be explained below.

FIG. 3 is a diagram showing a cross section of the first buildup layer B1.
As shown in FIG. 3, the portion of the first interlayer insulating layer 21 surrounded by the vias 41 is defined as a first region ra1, and the region excluding the first region ra1 (the region outside the plurality of vias 41) is defined as a first region ra1. When there are two areas ra2, only the second area ra2 contains the glass cloth G1, and the first area ra1 does not contain the glass cloth G1. That is, the first region ra1 has a smaller volume ratio of the glass cloth G1 than the second region ra2. Here, the volume ratio of the glass cloth G1 is the ratio of the volume of the portion occupied by the glass cloth G1 to the total volume of each region. In FIG. 3, the volume ratio of the glass cloth G1 is 0 in the first region ra1. Therefore, the first region ra1 is made of only the resin R1. However, the present invention is not limited to this, and the first area ra1 may include the glass cloth G2 within a range where the volume ratio of the glass cloth G1 in the first area ra1 is smaller than the volume ratio of the glass cloth G1 in the second area ra2. You can leave it there.
In this case, the first region ra1 and the second region ra2 may be made of the same material except for the base material. If the material of the part excluding the base material is the same between the first area ra1 and the second area ra2, the material of the part excluding the base material is continuous between the first area ra1 and the second area ra2. Since such a phase is formed, it is possible to reduce all changes and variations in characteristics between the first region ra1 and the second region ra2.

FIG. 4 is a diagram showing a cross section of the second buildup layer B2.
As shown in FIG. 4, the portion of the second interlayer insulating layer 22 surrounded by the vias 42 is defined as a first region rb1, and the region excluding the first region rb1 (the region outside the plurality of vias 42) is defined as a first region rb1. When there are two regions rb2, only the second region rb2 contains the glass cloth G2, and the first region rb1 does not contain the glass cloth G2. That is, the first region rb1 has a smaller volume ratio of the glass cloth G2 than the second region rb2. In FIG. 4, the volume ratio of the glass cloth G2 is 0 in the first region rb1. Therefore, the first region rb1 is made of only the resin R2. However, the present invention is not limited to this, and the first region rb1 may include the glass cloth G2 within a range where the volume ratio of the glass cloth G2 in the first region rb1 is smaller than the volume ratio of the glass cloth G2 in the second region rb2. You can leave it there. The volume ratio of the glass cloths G1 and G2 is determined by observing the cross section of the printed wiring board 1 using an electron microscope and determining the area ratio per unit area of the glass cloths G1 and G2 seen in the cross section.

Further, as shown in FIG. 1, the inside of the through hole 50 is filled with a resin R1 that is integrally connected to the first interlayer insulating layer 21 and does not contain glass cloth. Therefore, the dielectric inside the waveguide 2 is made of resins R1 and R2 and does not contain glass cloth G1 and G2.
In addition, in the printed wiring board 1 of this embodiment, when two or more buildup layers are laminated on the first surface S1 of the core layer C, all of the buildup layers excluding the topmost buildup layer are stacked on the first surface S1 of the core layer C. The interlayer insulating layer and the insulator filling the inside of the through hole 50 are made of the same material except for the base material, and the interlayer insulating layer of the uppermost buildup layer and the buildup layer adjacent to the uppermost buildup layer The interlayer insulating layer may have a structure in which the materials other than the base material are different from each other. Such a configuration is suitable when the overall electrical properties, overall mechanical properties, and thermal properties can be improved by differentiating the required properties between the surface layer side and the inner layer side of the printed wiring board 1. It is. In addition to antenna applications, the printed wiring board 1 for use in vehicles, which requires high heat resistance and high mechanical strength, can be exemplified.

[Manufacturing method of printed wiring board]
Next, a method for manufacturing printed wiring board 1 will be explained.
FIG. 5 is a schematic perspective view illustrating a method of manufacturing printed wiring board 1. As shown in FIG.
6 to 8 are cross-sectional views illustrating a method of manufacturing printed wiring board 1. FIG.

The method for manufacturing printed wiring board 1 according to this embodiment includes first to sixth steps.
In the first step, as shown in FIGS. 5 and 6(a), a core layer C in which through holes 50 are formed is prepared. At this stage, the inside of the through hole 50 is not filled with an insulator and is in a hollow state.

Furthermore, in the first step, a first opening 21A is formed in the first prepreg 21P, which will become the first interlayer insulating layer 21 in a later second step. Here, the first prepreg 21P is a member obtained by impregnating glass cloth G1 with resin R1 and semi-curing it. The first opening 21A of the first prepreg 21P is formed at a position and size that covers the opening range of the through hole 50 when the first prepreg 21P is stacked on the core layer C when viewed from the Z direction. Next, as shown in FIG. 5, the first prepreg 21P and a copper foil 70 as a metal foil are laid up on each of the upper and lower surfaces of the core layer C. That is, on each of the upper and lower surfaces of the core layer C, the first prepreg 21P is laminated at a position where the through hole 50 and the first opening 21A overlap when viewed from the Z direction, and the copper foil 70 is laminated on the first prepreg 21P. let As a result, a first laminate 81 including the core layer C, the first prepreg 21P, and the copper foil 70 is formed.

In the second step, as shown in FIG. 6(b), the first laminate 81 is heated and pressed in the Z direction. This melts the first prepreg 21P. Then, the molten material of the first prepreg is filled into the first opening 21A and the inside of the through hole 50 while solidifying, forming the first interlayer insulating layer 21 on the core layer C. This results in the first interlayer insulating layer 21 not containing the glass cloth G1 in the portion overlapping the through hole 50 when viewed from the Z direction. In addition, the inside of the through hole 50 is filled with the resin R1 that is continuous with the first interlayer insulating layer 21. The resin R1 occupies the space between the through hole 50 and the first interlayer insulating layer 21. In particular, in a structure in which the first buildup layer B1 and the second buildup layer B2 are provided on both sides of the core layer C, the resin R1 is filled into the through hole 50 and the first opening 21A in a continuous manner. This makes it difficult for the layers to peel off because the through-hole 50 and the first interlayer insulating layer 21 are firmly connected by the resin R1. The continuous resin R1 has directionality from the first interlayer insulating layer 21 to the through-hole 50. The fact that the resin R1 has directionality can be determined by observing this portion and seeing that the resin R1 or the substances contained in the resin R1 (at least one selected from inorganic fillers, flame retardants, antioxidants, weather stabilizers, etc.) are lined up in a line.

In the third step, as shown in FIG. 7A, a conductor layer 31 is formed on the first interlayer insulating layer 21, and a conductor layer 31 is formed from the land of the through hole 50 at a position surrounding the through hole 50 when viewed from the Z direction. A plurality of first vias 41 are formed which extend and are electrically connected to the through holes 50 and penetrate the first interlayer insulating layer 21 . Specifically, via pilot holes are formed in the first interlayer insulating layer 21 and the copper foil 70 using a laser or a drill, and a plating layer that will become the conductor layer 31 and the via 41 is formed by electrolytic panel plating. Thereafter, a part of the conductor layer 31 is removed by a subtractive method to form a circuit pattern. Alternatively, the circuit pattern of the conductor layer 31 and the vias 41 may be selectively formed by MSAP (Modified Semi-Additive Process).

In the fourth step, as shown in FIG. 7B, a second opening 22A is formed in the second prepreg 22P, which will become the second interlayer insulating layer 22 in the subsequent fifth step. Here, the second prepreg 22P is a member obtained by impregnating glass cloth G2 with resin R2 and semi-curing it. The second opening 22A of the second prepreg 22P is formed at a position and with a size that covers the opening range of the through hole 50 when viewed from the Z direction when the second prepreg 22P is stacked on the first interlayer insulating layer 21. Next, the second prepreg 22P and the copper foil 70 are laid up on the side of each first interlayer insulating layer 21 opposite to the core layer C side. That is, the second prepreg 22P is laminated on the side opposite to the core layer C side of the first interlayer insulating layer 21 at a position where the through hole 50 and the second opening 22A overlap when viewed from the Z direction, and the second prepreg 22P is stacked on the second prepreg 22P. Copper foil 70 is laminated. As a result, a second laminate 82 including the core layer C, the first buildup layer B1, the second prepreg 22P, and the copper foil 70 is formed.

In the fifth step, as shown in FIG. 8(a), the second laminate 82 is heated and pressurized in the Z direction. Thereby, the second prepreg 22P is melted. Then, while filling the inside of the second opening 22A with the molten material of the second prepreg, the molten material is solidified to form the second interlayer insulating layer 22 on the side opposite to the core layer C side of the first interlayer insulating layer 21. do. Thereby, the second interlayer insulating layer 22 that does not include the glass cloth G2 in the portion overlapping with the through hole 50 when viewed from the Z direction is obtained.

In the sixth step, as shown in FIG. 8(b), a conductor layer 32 is formed on the second interlayer insulating layer 22, and a plurality of vias 41 are formed at positions surrounding the through hole 50 when viewed from the Z direction. A plurality of second vias 42 are formed to be electrically connected to the through holes 50 and to penetrate the second interlayer insulating layer 22. Further, the conductor layer 32 forms an antenna conductor. Specifically, via pilot holes are formed in the second interlayer insulating layer 22 and the copper foil 70 using a laser or a drill, and a plating layer that will become the conductor layer 32 and the via 42 is formed by electrolytic panel plating. Thereafter, a portion of the conductor layer 32 is removed by a subtractive method to form a circuit pattern. Alternatively, the circuit pattern of the conductor layer 32 and the vias 42 may be selectively formed by MSAP. The antenna conductor is formed simultaneously with the circuit pattern of the conductor layer 32 and the via 42 by a subtractive method or MSAP.
The printed wiring board 1 is completed through the above steps.

[Modifications]
Next, a modification of the above embodiment will be described.
FIG. 9 is a cross-sectional view of a printed wiring board 1 according to a modified example.
The printed wiring board 1 of this modification is different from the above embodiment in that only one first buildup layer B1 is laminated on each of the first surface S1 and the second surface S2 of the core layer C, and the second buildup layer B2 is omitted. Also, an antenna conductor made of a conductor layer 31 is formed on the outermost surface of the first buildup layer B1. In this modification, the waveguide 2 is composed of a tubular through hole 50, a plurality of vias 41, and a dielectric surrounded by these conductors. Also, in this modification, an insulator 24 made of a different material from the resin R1 of the first interlayer insulating layer 21 is filled inside the through hole 50. In detail, an insulator 24 having a smaller relative dielectric constant than the resin R1 is filled inside the through hole 50. However, this is not limited to this, and the inside of the through hole 50 may be filled with a resin R1 that is integrally connected to the first interlayer insulating layer 21, as in the above embodiment.
In this case, the insulator filling the inside of the through hole 50 and the interlayer insulating layer may be made of different materials except for the base material, so long as they satisfy the desired functions and characteristics of the waveguide 2. Also, the resin R1 of the first interlayer insulating layer 21 may permeate from the first buildup layer B1 to the portion of the core conductor layer 30 formed on the surface of the core layer C. Alternatively, the resin R1 may permeate from the first buildup layer B1 beyond the portion of the core conductor layer 30 formed on the surface of the core layer C into the through hole 50.

Note that the number of buildup layers stacked on one side of the core layer C is not limited to one layer (this modification) or two layers (the above embodiment), but may be three or more layers. In this case as well, the waveguide 2 can be formed by providing a plurality of vias in each buildup layer B at positions surrounding the through hole 50 when viewed from the Z direction. Further, in the interlayer insulating layer of each buildup layer B, the volume ratio of the glass cloth in the region surrounded by the plurality of vias may be made smaller than the volume ratio of the glass cloth in the remaining region.

〔effect〕
As described above, the printed wiring board 1 of this embodiment includes a core layer C, and a first buildup layer B1 and a second buildup layer B2 laminated on the first surface S1 of the core layer C. The core layer C has a core insulating layer 20 and a through hole 50, the through hole 50 is tubular and penetrates the core insulating layer 20, and the core conductor layer is provided on both sides of the core insulating layer 20. The first buildup layer B1 includes a first interlayer insulating layer 21 and a plurality of vias 41, and the first interlayer insulating layer 21 is made of glass. The plurality of vias 41 are electrically connected to the through hole 50, penetrate the first interlayer insulating layer 21, and have a through hole when viewed from the direction perpendicular to the first surface S1. A region of the first interlayer insulating layer 21 surrounded by the plurality of vias 41 is a first region ra1, and a region other than the first region ra1 is a second region ra2. When, the first area ra1 has a smaller volume ratio of the glass cloth G1 than the second area ra2. Further, the second buildup layer B2 includes a second interlayer insulating layer 22 and a plurality of vias 42, the second interlayer insulating layer 22 contains glass cloth G2, and the plurality of vias 42 include a glass cloth G2. , is electrically connected to the through hole 50, penetrates the second interlayer insulating layer 22, and is provided at a position surrounding the through hole 50 when viewed from the direction perpendicular to the first surface S1. When a region of the interlayer insulating layer 22 surrounded by the plurality of vias 42 is defined as a first region rb1, and a region excluding the first region rb1 is defined as a second region rb2, the first region rb1 is a second region rb1. The volume ratio of the glass cloth G2 is smaller than that in the region rb2.

In a conventional configuration in which a region of buildup layer B surrounded by multiple vias includes glass cloth similar to other regions, the signal transmitted in the waveguide passes through the glass cloth of buildup layer B. However, each time it passed, signal disturbances occurred due to the glass cloth. Therefore, in the conventional configuration, there was a problem that signal transmission loss in the waveguide became large.

On the other hand, as in the above embodiment, the volume ratio of the glass cloth G1 in the first region ra1 corresponding to the inside of the waveguide 2 in the first interlayer insulating layer 21 is made smaller than that in the second region ra1, and By making the volume ratio of the glass cloth G2 in the second region rb1, which corresponds to the inside of the waveguide 2, of the second interlayer insulating layer 22 smaller than that in the second region rb2, signal disturbance due to the glass cloth can be reduced, and the signal Characteristics can be stabilized. Therefore, while reinforcing the buildup layer B with the glass cloth outside the waveguide 2, the signal transmission loss in the waveguide 2 can be reduced.

Furthermore, by having a configuration in which the first region ra1 and the first region rb1 do not contain the glass cloths G1 and G2, it is possible to significantly reduce the relative dielectric constant inside the waveguide 2 and suppress signal disturbance. . Therefore, signal transmission loss can be reduced more effectively.

Further, it is preferable that the first region ra1 and the second region ra2 are made of the same material (resin R1) except for the base material. Further, it is preferable that the first region rb1 and the second region rb2 are made of the same material (resin R2) except for the base material. In this case, even if the vias 41 and 42 exist from the first regions ra1 and rb1 to the second regions ra2 and rb2, the first buildup layer B1 and the second buildup layer B2 can be made stronger. Furthermore, the adhesive strength between the layers in the stacking direction from the first opening 21A of the first buildup layer B1 to the through hole 50 can be increased.

Further, in the printed wiring board 1 according to the modification, a first buildup layer B1 is laminated on the first surface S1 of the core layer C, and an insulator 24 filling the inside of the through hole 50 and a first interlayer insulation The layers 21 are made of different materials except for the glass cloth G1. As a result, for example, by making the relative permittivity of the resin R1 that constitutes the first interlayer insulating layer 21 lower than the relative permittivity of the insulator 24 in the through hole 50, it is possible to have higher antenna characteristics and improve transmission characteristics. An excellent printed wiring board 1 can be obtained.

Furthermore, in the printed wiring board 1 of the embodiment described above, two buildup layers B (first buildup layer B1 and second buildup layer B2) are laminated on the first surface S1 of the core layer C. According to this, the waveguide 2 can be made longer in accordance with the increase in the thickness of the buildup layer B while suppressing signal transmission loss in the waveguide 2.

In addition, the first interlayer insulating layer 21 of the first build-up layer B1 excluding the second build-up layer B2 of the uppermost layer and the insulator filling the inside of the through hole 50 are made of a material other than the base material (resin R1). are the same, and the second interlayer insulating layer 22 of the second buildup layer B2 as the uppermost layer and the first interlayer insulating layer 21 of the first buildup layer B1 adjacent to the second buildup layer B2 as the uppermost layer are , the materials (resin R2, resin R1) other than the base material are different from each other. As a result, for example, by making the relative permittivity of the resin R2 forming the second interlayer insulating layer 22 lower than the relative permittivity of the resin R1 forming the first interlayer insulating layer 21, higher antenna characteristics can be obtained. A printed wiring board 1 with excellent transmission characteristics can be obtained.

Furthermore, by using glass cloth as the base material, the buildup layer B can be effectively reinforced at low cost.

Further, it is preferable that the resin R1, which is the material of the first interlayer insulating layer 21 excluding the glass cloth G1, is continuous from the first region ra1 to the through hole 50. According to this, since the layer between the through hole 50 and the first interlayer insulating layer 21 is firmly connected by the resin R1, separation between the layers can be made difficult.

Further, the method for manufacturing the printed wiring board 1 according to the above embodiment includes the step of forming the first opening 21A in the first prepreg 21P containing the glass cloth G1, the core insulating layer 20, and the step of forming the first opening 21A in the first prepreg 21P containing the glass cloth G1. A first prepreg 21P is laminated on a core layer C having a tubular through hole 50 at a position where the through hole 50 and the first opening 21A overlap when viewed from a direction perpendicular to the first surface S1 of the core layer C. , a step of laminating the copper foil 70 on the first prepreg 21P to form a first laminate 81; and heating and pressurizing the first laminate 81 to pour the molten material of the first prepreg 21P into the first opening 21A. A process of forming the first interlayer insulating layer 21 on the core layer C by solidifying the molten material while filling the inside, and forming a through hole at a position surrounding the through hole 50 when viewed from the direction perpendicular to the first surface S1. forming a plurality of vias 41 extending from the lands 50, electrically connected to the through holes 50, and penetrating the first interlayer insulating layer 21. According to such a method, the volume ratio of the glass cloth G1 in the first region ra1 corresponding to the inside of the waveguide 2 in the first interlayer insulating layer 21 can be made smaller than that in the second region ra2. Therefore, signal disturbance caused by the glass cloth G1 can be reduced and signal characteristics can be stabilized. Thereby, the first buildup layer B1 can be reinforced by the glass cloth G1 outside the waveguide 2, and the signal transmission loss in the waveguide 2 can be reduced.

Further, the method for manufacturing the printed wiring board 1 according to the above embodiment includes a step of forming the second opening 22A in the second prepreg P2 containing the glass cloth G2, and a step of forming the second opening 22A on the core layer C side of the first interlayer insulating layer 21. On the opposite side, a second prepreg 22P is laminated at a position where the through hole 50 and the second opening 22A overlap when viewed from the direction perpendicular to the first surface S1, and a copper foil 70 is laminated on the second prepreg 22P. The second laminate 82 is formed by heating and pressurizing the second laminate 82 to fill the inside of the second opening 22A with the molten material of the second prepreg 22P, solidifying the molten material, and forming an interlayer between the first layers. A step of forming a second interlayer insulating layer 22 on the side of the insulating layer 21 opposite to the core layer C side, and forming a plurality of The method includes the step of forming a plurality of vias 42 that are electrically connected to the through holes 50 via the vias 41 and that penetrate the second interlayer insulating layer 22 . According to such a method, the volume ratio of the glass cloth G2 in the first region rb1 corresponding to the inside of the waveguide 2 in the second interlayer insulating layer 22 can be made smaller than that in the second region rb2. Therefore, signal disturbance caused by the glass cloth G2 can be reduced and signal characteristics can be stabilized. Thereby, the buildup layer B2 can be reinforced by the glass cloth G2 outside the waveguide 2, and the signal transmission loss in the waveguide 2 can be reduced.

Note that the above embodiment is an example, and various changes are possible.
For example, although glass cloth G1 and G2 are illustrated as base materials for the first interlayer insulating layer 21 and the second interlayer insulating layer 22, the present invention is not limited thereto. As the base material of the first interlayer insulating layer 21 and the second interlayer insulating layer 22, various dielectric materials such as aramid cloth such as aramid nonwoven fabric and aramid fiber, and polyester fiber can be used, for example.

Further, in the above embodiment, the waveguide 2 that penetrates the entire printed wiring board 1 has been described as an example, but the invention is not limited to this. A tube 2 may also be provided. Further, a plurality of such waveguides 2 may be provided and the waveguides 2 may be electrically connected to each other by a coaxial line or the like.

Further, in addition to the vias 41 and 42 forming the waveguide 2, vias for the purpose of electrically connecting circuit layers may be further provided.

Further, the buildup layer B may be provided only on one side of the core layer C.

In addition, specific details such as the configuration, structure, positional relationship, and shape shown in the above embodiments can be changed as appropriate without departing from the spirit of the present disclosure. Furthermore, the configurations, structures, positional relationships, and shapes shown in the above embodiments can be combined as appropriate without departing from the spirit of the present disclosure.

1 Printed wiring board 2 Waveguide 20 Core insulating layer 21 First interlayer insulating layer 22 Second interlayer insulating layer 23, 24 Insulator 30 Core conductor layer 31, 32 Conductor layer 41 Via (first via)
42 Via (second via)
50-52 Through hole 60 Antenna conductor 70 Copper foil (metal foil)
81 First laminate 82 Second laminate B Buildup layer B1 First buildup layer B2 Second buildup layer C Core layer G1, G2 Glass cloth (base material)
21P First prepreg 21A First opening 22P Second prepreg 22A Second opening R1, R2 Resin S1 First surface S2 Second surface

Claims (10)

Comprising a core layer and one or more buildup layers laminated on the first surface of the core layer,
The core layer has a core insulating layer and a through hole,
The through hole has a tubular shape, penetrates the core insulating layer, and is provided to electrically connect conductors provided on both sides of the core insulating layer,
The buildup layer includes an interlayer insulating layer and a plurality of vias,
The interlayer insulating layer contains a base material made of a dielectric material,
The plurality of vias are electrically connected to the through hole, penetrate the interlayer insulating layer, and are provided at positions surrounding the through hole when viewed from a direction perpendicular to the first surface. ,
When a region of the interlayer insulating layer surrounded by the plurality of vias is defined as a first region, and a region excluding the first region is defined as a second region, the first region is larger than the second region. Also, the volume percentage of the base material is small ,
The plurality of vias are arranged such that a portion of the peripheral edge of each via is along an inner wall of the through hole when viewed from a direction perpendicular to the first surface.
Printed wiring board. The printed wiring board according to claim 1, wherein the first region does not contain the base material. 3. The printed wiring board according to claim 1, wherein the first region and the second region are made of the same material except for the base material. one of the buildup layers is laminated on the first surface of the core layer;
4. The printed wiring board according to claim 1, wherein the insulator filling the inside of the through hole and the interlayer insulating layer are made of different materials except for the base material. The printed wiring board according to any one of claims 1 to 3, wherein two or more of the build-up layers are laminated on the first surface of the core layer. The interlayer insulating layer of each of the buildup layers excluding the buildup layer of the uppermost layer and the insulator filling the inside of the through hole are made of the same material except for the base material,
6. The interlayer insulating layer of the uppermost buildup layer and the interlayer insulation layer of a buildup layer adjacent to the uppermost buildup layer are made of different materials except for the base material. Printed wiring board as described. The printed wiring board according to any one of claims 1 to 6, wherein the base material is glass cloth. The printed wiring board according to any one of claims 1 to 7, wherein the material of the interlayer insulating layer excluding the base material is continuous from the first region to the through hole. forming a first opening in a first prepreg containing a base material made of a dielectric;
For a core layer having a core insulating layer and a tubular through hole penetrating the core insulating layer, the through hole and the first opening overlap when viewed from a direction perpendicular to a first surface of the core layer. laminating the first prepreg at a position and laminating a metal foil on the first prepreg to form a first laminate;
Heating and pressurizing the first laminate to fill the inside of the first opening with the molten material of the first prepreg and solidifying the molten material to form a first interlayer insulating layer on the core layer. The process of
At positions surrounding the through hole when viewed from a direction perpendicular to the first surface, a plurality of holes extend from lands of the through hole, are electrically connected to the through hole, and penetrate the first interlayer insulating layer. a step of forming one via;
including;
In the step of forming the plurality of first vias, each first via is formed at a position where a portion of a peripheral edge of each first via is along an inner wall of the through hole when viewed from a direction perpendicular to the first surface. ,
A method for manufacturing printed wiring boards. forming a second opening in a second prepreg containing a base material made of a dielectric;
The second prepreg is laminated on the side of the first interlayer insulating layer opposite to the core layer at a position where the through hole and the second opening overlap when viewed from a direction perpendicular to the first surface, and a step of laminating metal foil on the second prepreg to form a second laminate;
The second laminate is heated and pressurized to fill the inside of the second opening with the molten material of the second prepreg and solidify the molten material, so that the core layer side of the first interlayer insulating layer and the molten material are solidified. forming a second interlayer insulating layer on the opposite side;
electrically connected to the through hole via the plurality of first vias and penetrating the second interlayer insulating layer at a position surrounding the through hole when viewed from a direction perpendicular to the first surface of the core layer. forming a plurality of second vias;
including ;
In the step of forming the plurality of second vias, each second via is formed at a position where a part of the peripheral edge of each second via is along an inner wall of the through hole when viewed from a direction perpendicular to the first surface. ,
The method for manufacturing a printed wiring board according to claim 9.

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