JP7484538B2 - Condition determination system and machine tool - Google Patents

Description

This technology relates to a state determination system that determines the on/off state of a switch, and to a machine tool.

Machine tools, industrial robots, etc. have safety circuits that supply power to motors and other power generators only when the environment in which they are used is safe. The safety circuit receives input signals from safety switches such as emergency stop switches and safety area sensors such as safety door switches. Based on the input signals, the safety circuit monitors the open/closed state of the switch contacts to determine the on/off state of the switch, and stops driving the motor etc. when a malfunction occurs, and will not restart the motor etc. if the cause of the malfunction is not removed.

The open/closed state of the switch contacts is detected by an open/close detection circuit. In the case of Patent Document 1, the signal input to the contacts is converted into a pulse, and the waveform sent out is compared with the waveform of the signal returning from the contacts to determine that the power supply is not short-circuited and that the signal has traveled through a specified path.

JP 2019-150864 A

When using the technology of Patent Document 1 to prevent erroneous detection of open/closed states due to wiring shorts between multiple contacts, the timing of the pulses is shifted. Depending on the size of a machine tool, there may be nearly 100 emergency stop switches and door switches alone. When adjusting the timing to prevent erroneous detection of each switch contact, the more the timing is shifted, the longer the pulse interval becomes, and the longer the non-detection time becomes. This results in a decrease in the accuracy of switch on/off detection.
This safety circuit is a type that adds a pulse test function to a B contact circuit. The B contact circuit is normally on, and an off pulse is sent for testing, so the on period is long. A minimum contact current is set for the switch contact, and there is a limit to how much the current can be reduced, so if the on period is long, the power consumption of the switch circuit increases.

This disclosure has been made in light of these circumstances, and aims to provide a state determination system and machine tool that can accurately detect the open/closed state of a contact and determine the on/off state of a switch.

A state determination system according to one aspect of the present invention includes a switch having a first contact, a first control unit that stores a first eigenvalue corresponding to the first contact, outputs a first output signal including the first eigenvalue, and has a first output terminal connected to the input side of the first contact, and a second control unit that stores a first expected value corresponding to the first contact, is connected to the output side of the first contact, and has a first input terminal that inputs a first input signal when the first contact is in a closed state, and the second control unit determines that the first contact is in a closed state when the first eigenvalue included in the first input signal matches the first expected value.

According to the above configuration, the open/close status of the contacts is judged at multiple stages, including whether communication is established and comparing the eigenvalue with the expected value, so that in addition to power supply short circuits and ground faults, abnormalities due to cross-connection with nearby electric wires can be detected and erroneous judgment of the on/off state of the switch can be prevented. The on/off state of the switch can be accurately judged, and the presence or absence of an abnormality can be accurately judged.
There is no need for the signal transmitted by the first control unit and the signal received by the second control unit to be synchronized, and there is no need to share a clock, etc., and the second control unit can determine the open/closed state of the contacts independently of the first control unit.
Since the determination is made based on the data of the signal including the eigenvalue, the ON period can be shortened, and the power consumption in the switch circuit can be reduced.

In the above-mentioned state determination system, the switch has a second contact, and the first control unit further stores the first expected value and a second expected value corresponding to the second contact, and is provided with a second input terminal connected to the output side of the first contact and inputting a first input signal when the first contact is in a closed state, and a third input terminal connected to the output side of the second contact and inputting a second input signal when the second contact is in a closed state, and determines that the first contact is in a closed state when a first eigenvalue contained in the first input signal input to the second input terminal matches the first expected value, and determines that the first contact is in a closed state when the first eigenvalue contained in the first input signal input to the third input terminal matches the first expected value. When a second eigenvalue included in the input signal matches the second expected value, the second contact is determined to be in a closed state, and the second control unit stores the second eigenvalue, the first expected value, and the second expected value corresponding to the second contact, outputs a second output signal including the second eigenvalue, and includes a second output terminal connected to the input side of the second contact and a fourth input terminal connected to the output side of the second contact and inputs a second input signal when the second contact is in a closed state, and may determine that the second contact is in a closed state when a second eigenvalue included in the second input signal input to the fourth input terminal matches the second expected value.

According to the above configuration, when the switch has two contacts and the safety system is duplicated, the open/closed state of the two contacts can be determined independently without synchronization between the control units. When the contacts are multiplexed as described above, the synchronization timing between the contacts is shifted, which lengthens the pulse interval and avoids the problem of long undetected time. Therefore, the open/closed state of the contacts can be detected well, and the on/off state of the switch can be determined.

In the above-mentioned state determination system, the first control unit and the second control unit may determine that the switch has been operated or is abnormal when at least one of the first contact and the second contact is in an open state, and may determine that the switch is normal when both the first contact and the second contact are in a closed state.

With the above configuration, the switch can be determined to be normal only when both the first contact and the second contact are closed, increasing safety.

In the above-mentioned condition determination system, the first control unit and the second control unit may transmit the determination results to the other control unit, and if the determination results of each control unit do not match, it may be determined that an abnormality has occurred.

With the above configuration, the system is deemed normal only when the judgment results of each control unit match, thus improving safety.

In the above-mentioned state determination system, the communication between the first control unit and the second control unit may be serial communication.

The above configuration requires fewer circuits, is low cost, and wiring is simple, allowing communication over long distances. Clock (timing) deviations are less likely to occur, and it is also resistant to noise.

The above-mentioned state determination system may be provided with multiple switches.

According to the above configuration, when there are multiple switches and the safety system is multiplexed, the open/closed state of the contacts of the multiple switches can be determined independently without synchronization between the control units. When the contacts are multiplexed as described above, the synchronization timing between the contacts is shifted, which lengthens the pulse interval and avoids the problem of long undetected time. Therefore, the open/closed state of the contacts can be detected well, and the on/off state of the switch can be determined.

In the above-mentioned state determination system, the switch may further include a contact and a control unit corresponding to the contact.

With the above configuration, when there are three or more contacts and the safety system is multiplexed, the open/closed states of the multiple contacts can be determined independently and accurately between the control units, allowing accurate determination of the on/off state of the switch.

In one embodiment of the present invention, the machine tool has a normally closed switch and is equipped with the above-mentioned state determination system in which the contacts are open when an emergency stop occurs, a door is open, or a member is in an abnormal position.

The above configuration accurately determines the on/off state of the switch, detects when an abnormality has occurred and the switch has been operated, stops the operation of the power generator such as a motor, and prevents the motor from being driven again if the cause of the malfunction is not eliminated, thereby ensuring safety at the manufacturing site.

The state determination system according to one aspect of the present invention can effectively detect the open/closed state of the contacts and determine the on/off state of the switch.

1 is a block diagram illustrating a simplified diagram of a machine tool equipped with a state determination system according to a first embodiment; 11 is a flowchart showing a procedure of a packet transmission process by the FPGA 1; FIG. 2 is a conceptual diagram showing an example of a packet configuration. 10 is a flowchart showing a procedure for a process of determining an open/closed state of a contact by the FPGA 2; 11 is a timing chart showing a transmission period, a transmission packet, noise, opening and closing of a contact, the number of judgments, a reception interval, a reception packet, and a judgment of opening and closing. FIG. 11 is a block diagram illustrating a machine tool equipped with a state determination system according to a second embodiment. 10 is a flowchart showing a procedure for a process of determining whether a switch is on or off by an FPGA. 11 is a timing chart showing the determination of opening and closing of two contacts by two FPGAs, and the determination of on/off of a switch by two determination units. FIG. 11 is a block diagram illustrating a machine tool equipped with a state determination system according to a third embodiment. FIG. 13 is a block diagram illustrating a machine tool equipped with a state determination system according to a fourth embodiment. 11 is a flowchart showing a procedure for a process of determining whether a switch is on or off by the FPGA 1.

(Embodiment 1)
Hereinafter, the present invention will be described with reference to the drawings showing a state determination system according to embodiment 1. Fig. 1 is a block diagram that shows a simplified view of a machine tool 100 equipped with a state determination system 5 according to embodiment 1.
Status determination system 5 includes a field programmable gate array (FPGA 1), an FPGA 2, and a switch 3 having contacts 31. A case will be described in which machine tool 100 includes status determination system 5 and switch 3 is a normally closed emergency stop switch. Machines to which status determination system 5 according to this embodiment is applied are not limited to machine tool 100. Switch 3 is not limited to being an emergency stop switch, and may be one whose contacts are opened when a door is open or when a member is in an abnormal position. In addition, the switch may be of a normally open type.

The control unit 6 controls the driving of a power generator such as a motor of the machine tool 100. A later-described judgment unit 21 of the FPGA 2 detects the open/closed state of the contact 31, judges the on/off state of the switch 3, and outputs the result to the control unit 6. When the switch 3 is operated and the state judgment system 5 judges that the contact 31 is in an open state, the control unit 6 stops the driving of the motor, etc. Instead of an FPGA, an ASIC (Application Specific Integrated Circuit) may be used as the integrated circuit. Any IC that can provide multiple serial ports will suffice.

The FPGA 1 comprises a packet generation unit 11, a transmission unit 12, a memory 13, a timing unit 14, and an output terminal 15. A unique value A, which is an identification code corresponding to the contact 31, is stored in the memory 13. The packet generation unit 11 reads out the unique value A from the memory 13 and generates a packet. The output terminal 15 is connected to the input side of the contact 31 and outputs the generated packet. The timing unit 14 performs timing. The packet communication protocol may be an existing protocol such as HTTP (Hypertext Transfer Protocol) or a unique protocol.

2 is a flow chart showing a procedure of packet transmission processing by the FPGA 1. The FPGA 1 performs the following transmission processing at regular intervals.
The packet generating unit 11 of the FPGA 1 reads out the unique value A from the memory 13 (S1).

The packet generator 11 of the FPGA 1 generates a packet including the unique value A and a CRC code (S2).
FIG. 3 is a conceptual diagram showing an example of a packet configuration. A packet is composed of, for example, a header, data, and a footer. The header is composed of a start bit. The header may include an address. The data includes a unique value A. The footer is composed of a data CRC (Cyclic Redundancy Code) code and an end bit. The CRC code is used to check whether the data has been transmitted correctly. Before transmission, a check CRC value is calculated and added to the data, and when received, the CRC value is calculated for the same part of the data using the same procedure. If the two match, it is determined that there is no error, and if they do not match, it is determined that part of the data is missing or has changed.

The FPGA 1 transmits a packet from the output terminal 15 at a predetermined timing measured by the timer 14 via the transmitter 12 (S3), and ends the process.

The FPGA 2 comprises a judgment unit 21, a comparison unit 22, a reception unit 23, a memory 24, a timer unit 25, and an input terminal 26. The memory 24 stores an expected value A that corresponds to the contact 31 and is identical to the unique value A. The input terminal 26 is connected to the output side of the contact 31, and inputs a packet when the contact 31 is in a closed state. The comparison unit 22 compares the unique value A of the packet data with the expected value A.

The receiving unit 23 operates at a constant cycle, but the cycle is not synchronized with the transmission cycle of the transmitting unit 12. The receiving unit 23 waits to receive a packet. Since it is not synchronized with the transmitting unit 12, it is not known when the packet will be received. When the contact 31 is closed, the receiving unit 23 receives a packet via the input terminal 26.

If the determination unit 21 has not received a packet for time a or more, or if the packet is corrupted, it determines that the contact 31 is open, and if the packet is normal (CRC code matches) but the unique value does not match the expected value A, crosstalk or the like has occurred, it determines that the contact 31 is open, and it determines that the switch 3 is off. If the determination unit 21 receives a packet normally and the unique value of the packet matches the expected value A, it determines that the contact 31 is closed and the switch 3 is on.

FIG. 4 is a flowchart showing a procedure for determining the open/closed state of the contact 31 by the FPGA 2.
The FPGA 2 starts measuring time in the timer section 25 (S11).
The receiving section 23 of the FPGA 2 determines whether or not a packet has been received from the input terminal 26 (S12).

When the FPGA 2 determines that the receiving unit 23 has not received a packet (S12: NO), the determining unit 21 determines whether or not the time a has elapsed (S13). When the FPGA 2 determines that the time a has not elapsed (S13: NO), the process returns to S12.
When the FPGA 2 determines that the time a has elapsed (S13: YES), it determines that the contact 31 is open, that is, the switch 3 is off, and thus determines that the switch 3 has been operated (S14).

When the FPGA 2 determines that the receiving unit 23 has received a packet (S12: YES), it determines whether the packet is normal or not (S15). The FPGA 2 calculates a CRC value using the receiving unit 23, and determines that the packet is normal if the CRC values match. When the FPGA 2 determines that the packet is not normal (S15: NO), it advances the process to S14.

If the receiving unit 23 of the FPGA 2 determines that the packet is normal (S15: YES), it performs a decoding process.

In the comparison unit 22, the FPGA 2 reads the expected value A from the memory 24, compares the unique value of the data extracted from the packet by decoding processing with the expected value A, and determines whether it matches the expected value A (S17), and outputs the determination result to the determination unit 21. Note that the decoding processing refers to removing the header and footer from the packet.

If the determination unit 21 of the FPGA 2 determines that the eigenvalue does not match the expected value A (S17: NO), the FPGA 2 determines that the contact 31 is open, that is, that the switch 3 is off (S14).
When the determination unit 21 of the FPGA 2 determines that the eigenvalue matches the expected value A (S17: YES), the FPGA 2 determines that the contact 31 is in a closed state, that is, that the switch 3 is on (S18).
The FPGA 2 causes the determination unit 21 to output the determination result to the control unit 6 (S19), and ends the process.
When the control unit 6 receives an input from the determination unit 21 indicating that the switch 3 is off, the control unit 6 stops driving the motor and the like.

Figure 5 is a timing chart showing the transmission period, transmitted packets, noise, opening and closing of contacts, number of judgments, reception interval, received packets, and opening and closing judgments. For the sake of explanation, a case is shown here where no packets are sent and abnormal data is sent, but normally, the transmitter 12 transmits packets containing the unique value A at regular intervals. The transmitter 12 and receiver 23 of the state judgment system 5 are not synchronized, and the receiver 23 performs an interrupt operation to process when a packet is received, but this is a safety system, and if no packet is received after the passage of time a, it is judged that the contacts are open.

Contact 31 is initialized as being open.
In the first transmission cycle, FPGA 1 transmits a packet including normal data from transmitting unit 12. At this time, contact 31 is open. Because contact 31 is open, FPGA 2 cannot input a packet through receiving unit 23 at point A (first judgment) after time a has elapsed. Judgment unit 21 maintains the previous state (contact open) up to point A, judges again that contact 31 is in the open state at point A, and clears the timer.

FPGA1 does not transmit a packet in the second transmission cycle. Contact 31 is in a closed state just before the second cycle. Because no packet has been transmitted, FPGA2 cannot input a packet via the receiver 23 at point B (second determination) after time a has elapsed. The determination unit 21 maintains the previous state (contact open) up to point B, at which point it is determined that contact 31 is again in an open state, and clears the timer.

In the third transmission cycle, FPGA1 transmits a packet containing normal data from transmitter 12, but noise is introduced at this time. Judgment unit 21 maintains the previous state from point B to point C (third judgment), and receives a corrupted packet at point C via receiver 23. Since judgment unit 21 received the corrupted packet at point C, it again judges that contact 31 is open and clears the timer.

In the fourth transmission cycle, FPGA1 transmits a packet containing abnormal data that contains an eigenvalue different from eigenvalue A via transmitter 12. Determination unit 21 maintains the previous state from point C to point D (fourth determination), and receives a packet containing abnormal data at point D via receiver 23. Since determination unit 21 received a packet containing abnormal data at point D, it again determines that contact 31 is open and clears the timer.

In the fifth transmission cycle, FPGA2 transmits a packet containing normal data via transmitter 12. Judgment unit 21 maintains the previous state from point D to point E (fifth judgment), and FPGA2 receives a packet containing normal data at point E via receiver 23. Since judgment unit 21 received a packet containing normal data at point E, it judges that contact 31 is closed, changes the output, and clears the timer.

According to this embodiment, the opening and closing of the contact 31 is determined at multiple stages, including whether communication has been established, whether the data is correct, and a comparison between the eigenvalue and the expected value. This makes it possible to detect abnormalities due to cross-connection with nearby electric wires in addition to power supply short circuits and ground faults, and prevents erroneous determination of the on/off state of the switch.
There is no need for the signal transmitted by FPGA1 and the signal received by FPGA2 to be synchronized, there is no need to share a clock unit or the like, and FPGA2 can determine the open/closed state of contact 31 independently of FPGA1.
Since the determination is made based on a unique value of the packet data, the ON period can be shortened to reduce power consumption in the switch circuit.

(Embodiment 2)
FIG. 6 is a block diagram illustrating a machine tool 100 equipped with a state determination system 5 according to the second embodiment.
The switch 3 of the state determination system 5 has a contact 31 and a contact 32, and the contacts 31 and 32 are opened in synchronization with the operation of the switch 3.

The FPGA 1 of the state determination system 5 includes a packet generation unit 11, a transmission unit 12, a memory 13, a timer unit 14, a determination unit 16, a determination unit 17, a comparison unit 18, a comparison unit 19, a reception unit 20, an output terminal 15, an input terminal 41, and an input terminal 42. The memory 13 stores a unique value A, which is an identification code corresponding to the contact 31, an expected value A corresponding to the contact 31 and which is the same as the unique value A, and an expected value B corresponding to the contact 32 and which is the same as the unique value B described later. The packet generation unit 11 reads the unique value A from the memory 13 and generates a packet. The output terminal 15 is connected to the input side of the contact 31 and outputs the generated packet. The input terminal 41 is connected to the output side of the contact 31 and inputs a packet when the contact 31 is in a closed state. The input terminal 42 is connected to the output side of the contact 32 via an insulating circuit 45 and inputs a packet when the contact 32 is in a closed state.

The receiving unit 20 operates at a constant cycle, but the cycle of operation is not synchronized with the cycle of transmission by the transmitting unit 12. The receiving unit 20 waits to receive a packet. When the contact 31 is closed, the receiving unit 20 receives a packet from the input terminal 41. When the packet received from the input terminal 41 is normal, the receiving unit 20 performs a decode process and outputs the packet to the comparing unit 18. The comparing unit 18 compares the unique value contained in the decoded data with the expected value A read from the memory 13, and outputs the result to the determining unit 17. When any one of the following is true, the determining unit 17 determines that the contact 31 is open if a packet has not been received from the input terminal 41 for a time a or more, if the packet is corrupted, or if the packet is normal but the unique value does not match the expected value A. When the determining unit 17 receives a packet normally and the unique value of the packet matches the expected value A, it determines that the contact 31 is closed.

When the contact 32 is closed, the receiving unit 20 receives a packet from the input terminal 42. When the packet received from the input terminal 42 is normal, the receiving unit 20 performs a decode process and outputs the packet to the comparison unit 19. The comparison unit 19 compares the unique value contained in the decoded data with the expected value B read from the memory 13, and outputs the result to the determination unit 17. The determination unit 17 determines that the contact 32 is open if any one of the following is true: a packet has not been received from the input terminal 42 for time b or more, the packet is corrupted, or the packet is normal but the unique value does not match the expected value B. The determination unit 17 determines that the contact 32 is closed if the unique value matches the expected value B.

When both contacts 31 and 32 are closed, the determination unit 17 determines that the switch 3 is on, and when at least one of the contacts 31 and 32 is open, the determination unit 17 determines that the switch 3 is off, and outputs the result to the determination unit 16. The determination unit 17 also outputs the result to the determination unit 29 connected via the insulation circuit 47. The communication at this time is coded serial communication.

The FPGA 2 includes a packet generating unit 27, a transmitting unit 30, a memory 24, a timer unit 25, a determining unit 21, a determining unit 29, a comparing unit 22, a comparing unit 28, a receiving unit 23, an output terminal 43, an input terminal 26, and an input terminal 44. The memory 24 stores a unique value B, which is an identification code corresponding to the contact 32, an expected value A which is the same as the unique value A, and an expected value B which is the same as the unique value B. The packet generating unit 27 reads the unique value B from the memory 24 and generates a packet. The output terminal 43 is connected to the input side of the contact 32 and outputs the generated packet. The input terminal 26 is connected to the output side of the contact 31 via an insulating circuit 46, and inputs a packet when the contact 31 is in a closed state. The input terminal 44 is connected to the output side of the contact 32 and inputs a packet when the contact 32 is in a closed state.

The receiving unit 23 operates at a predetermined timing, but the operation cycle is not synchronized with the transmission cycle of the transmitting unit 30. The receiving unit 23 waits to receive a packet. When the contact 31 is closed, the receiving unit 23 receives a packet from the input terminal 26. When the packet received from the input terminal 26 is normal, the receiving unit 23 performs a decode process and outputs the packet to the comparing unit 22. The comparing unit 22 compares the unique value contained in the decoded data with the expected value A read from the memory 24, and outputs the result to the determining unit 21. When the determining unit 21 has not received a packet from the input terminal 26 for a time a or more, when the packet is corrupted, or when the unique value does not match the expected value A even if the packet is normal, the determining unit 21 determines that the contact 31 is in an open state. When the determining unit 21 receives a packet normally and the unique value of the packet matches the expected value A, the determining unit 21 determines that the contact 31 is in a closed state.

When the contact 32 is closed, the receiving unit 23 receives a packet from the input terminal 44. When the packet received from the input terminal 44 is normal, the receiving unit 23 performs a decode process and outputs the packet to the comparing unit 28. The comparing unit 28 compares the unique value contained in the decoded data with the expected value B read from the memory 24, and outputs the result to the judging unit 21. When a packet has not been received from the input terminal 44 for time b or more, when the packet is corrupted, or when the packet is normal but the unique value does not match the expected value B, the judging unit 21 judges that the contact 32 is open. When the unique value matches the expected value B, the judging unit 29 judges that the contact 32 is closed.

When both contacts 31 and 32 are closed, the determination unit 21 determines that the switch 3 is on, and when at least one of the contacts 31 and 32 is open, the determination unit 21 determines that the switch 3 is off, and outputs the result to the determination unit 29. The determination unit 21 also outputs the result to the determination unit 16 connected via the insulation circuit 48.

The judgment unit 16 judges whether the results output by the judgment units 17 and 21 match. If the judgment results of the judgment units 17 and 21 do not match, the judgment unit 16 judges that the switch 3 is off and abnormal. If the judgment results of the judgment units 17 and 21 match, that is, if both judge that the switch 3 is on, the judgment unit 16 judges that the switch 3 is on and normal, and if both judge that the switch 3 is off, the judgment unit 16 judges that the switch 3 is off. The judgment unit 16 outputs the result to the control unit 6.

The judgment unit 29 judges whether the judgment results output by the judgment units 17 and 21 match. If the judgment results of the judgment units 17 and 21 do not match, the judgment unit 29 judges that the switch 3 is off and abnormal. If the judgment results of the judgment units 17 and 21 match, that is, if both judge that the switch 3 is on, the judgment unit 29 judges that the switch 3 is on and normal, and if both judge that the switch 3 is off, the judgment unit 29 judges that the switch 3 is off. The judgment unit 29 outputs the result to the control unit 6.

When the control unit 6 receives input from the judgment unit 16 and judgment unit 29 indicating that the switch 3 is off, i.e., the switch 3 has been operated, and an emergency stop is required, the control unit 6 stops driving the motor, etc.

FIG. 7 is a flow chart showing the procedure of the process of determining whether the switch 3 is on or off by the FPGA 1 and FPGA 2.
The packet generator 11 of the FPGA 1 reads the unique value A from the memory 13 and generates a packet including the unique value A and a CRC code (S21).
The FPGA 1 causes the transmission unit 12 to transmit the packet from the output terminal 15 at a predetermined timing clocked by the clock unit 14 (S22).

When a packet is input from the input terminal 41, the FPGA 1 determines the open/closed state of the contact 31 using the receiver 20, comparator 18, and determiner 17 (S23). The open/closed state of the contact 31 is determined in the same manner as in the process of the flowchart in FIG. 4.

When a packet is input from the input terminal 42, the FPGA 1 determines the open/closed state of the contact 32 by the receiver 20, comparator 19, and determiner 17 (S24). The open/closed state of the contact 32 is determined in the same manner as the process in the flowchart of FIG. 4. Note that the order of determination is not limited to S23, S24. When a packet is input from the input terminal 42 first, the open/closed state of the contact 32 is determined in S24 first.

The FPGA 1, in the judgment unit 17, judges that the switch 3 is in the on state when both the contacts 31 and 32 are in the closed state, and judges that the switch 3 is in the off state when at least one of the contacts 31 and 32 is in the open state (S25).

The packet generator 27 of the FPGA 2 reads the unique value B from the memory 24 and generates a packet including the unique value B and a CRC code (S31).
The FPGA 2 causes the transmission unit 30 to transmit the packet from the output terminal 43 at a predetermined timing clocked by the clock unit 25 (S32).

When a packet is input from the input terminal 26, the FPGA 2 determines the open/closed state of the contact 31 using the receiver 23, comparator 22, and determiner 21 (S33). The open/closed state of the contact 31 is determined in the same manner as in the process of the flowchart in FIG. 4.

When a packet is input from the input terminal 44, the FPGA 2 determines the open/closed state of the contact 32 by the receiver 23, comparator 28, and determiner 21 (S34). The open/closed state of the contact 32 is determined in the same manner as the process in the flowchart of FIG. 4. Note that the order of determination is not limited to S33, S34. When a packet is input from the input terminal 44 first, the open/closed state of the contact 32 is determined in S34 first.

The FPGA 2 determines in the judgment unit 21 that the switch 3 is in the on state when both the contacts 31 and 32 are in the closed state, and determines that the switch 3 is in the off state when at least one of the contacts 31 and 32 is in the open state (S35).

The FPGA 1 causes the determination unit 17 to output the determination result to the determination units 16 and 29 (S26).
The FPGA2 receives the determination result of the FPGA1 (S36).
The FPGA 2 causes the determination unit 21 to output the determination result to the determination units 29 and 16 (S37).
The FPGA1 receives the determination result of the FPGA2 (S27).
The order of the processes is not limited to S26 and S27, but is based on the order of the processes of determining the on/off state of the switch 3 by the FPGA1 and FPGA2. If the process of determining whether the switch 3 is correct or not by the FPGA2 is performed first, the input of the determination result by the FPGA2 (S27) is performed before S26.

In the FPGA 1, the judgment unit 16 judges whether the results output by the judgment units 17 and 21 match, and judges whether the switch 3 is on or off (S28). If the judgment results of the judgment units 17 and 21 do not match, the judgment unit 16 judges that the switch 3 is off. If the judgment results of the judgment units 17 and 21 match, that is, if both judge that the switch 3 is on, the judgment unit 16 judges that the switch 3 is on, and if both judge that the switch 3 is off, the judgment unit 16 judges that the switch 3 is off.
The FPGA 1 outputs the determination result by the determination unit 16 to the control unit 6 (S29), and ends the process.

The FPGA 2 determines in the determination unit 29 whether the results output by the determination units 17 and 21 match, and determines whether the switch 3 is on or off (S38). If the determination results of the determination units 17 and 21 do not match, the determination unit 29 determines that the switch 3 is off. If the determination results of the determination units 17 and 21 match, that is, if both determine that the switch 3 is on, the determination unit 29 determines that the switch 3 is on, and if both determine that the switch 3 is off, the determination unit 29 determines that the switch 3 is off.
The FPGA 2 outputs the result from the determination unit 29 to the control unit 6 (S39), and ends the process.

Figure 8 is a timing chart showing the determination of whether contact 31 is open or closed by FPGA1, the determination of whether contact 32 is open or closed, the determination of whether switch 3 is on or off by determination unit 17, the determination of whether switch 3 is on or off by determination unit 16, the determination of whether contact 31 is open or closed by FPGA2, the determination of whether contact 32 is open or closed, the determination of whether switch 3 is on or off by determination unit 21, and the determination of whether switch 3 is on or off by determination unit 29.

First, the FPGA 1 judges whether the contacts 31 and 32 are open or closed. If the received packet is normal and the unique value matches the expected value, the FPGA 1 judges that the contacts are in a closed state. At point A, it is judged that both the contacts 31 and 32 are in a closed state.
At point B, since both contacts 31 and 32 are in the closed state, the determination unit 17 determines that the switch 3 is on.

The FPGA 2 judges whether the contacts 31 and 32 are open or closed. If the received packet is normal and the inherent value matches the expected value, the FPGA 2 judges that the contacts are in a closed state. At point D, it is judged that both the contacts 31 and 32 are in a closed state.
At point E, since both contacts 31 and 32 are closed, the determination unit 21 determines that the switch 3 is on.

Since the determination unit 17 determines that the switch 3 is on, and the determination unit 21 determines that the switch 3 is on, at point C, the determination unit 29 determines that the switch 3 is on.

Since the determination unit 17 determines that the switch 3 is on, and the determination unit 21 determines that the switch 3 is on, at point F, the determination unit 16 determines that the switch 3 is on. Since the determination units 16 and 29 determine whether the switch 3 is on or off based on the determination results of the determination units 17 and 21, the determination results are the same.

In the above explanation, FPGA1 first determines whether contacts 31 and 32 are open or closed, but FPGA2 may first determine whether contacts 31 and 32 are open or closed.

In this embodiment, when the switch 3 has two contacts and the safety system is duplicated, the open/closed states of the two contacts can be determined asynchronously and satisfactorily. When the contacts are multiplexed as described above, the synchronization timing between the contacts is shifted, which lengthens the pulse interval and avoids the problem of a long non-detection time. Therefore, the open/closed states of the contacts can be detected satisfactorily, and the on/off state of the switch 3 can be determined.
In order to prevent FPGA1 and FPGA2 from affecting each other in the event of a failure, signals transmitted between them are sent via isolation circuits 47 and 48. Separate clocks are also used for each. With this configuration, it is difficult to synchronize FPGA1 and FPGA2, and if synchronization is required at the clock level, the cost of isolation circuits 47 and 48 will be high. By making the communication asynchronous, this problem does not occur.
When at least one of the contacts 31, 32 is open, the switch 3 is determined to be off, and when the determination results of the FPGA1 and the FPGA2 do not match, the switch 3 is determined to be off, thereby improving safety.

(Embodiment 3)
FIG. 9 is a block diagram that shows a simplified view of a machine tool 100 equipped with a state determination system 5 according to the third embodiment.
In addition to the switch 3, the state determination system 5 includes a switch 7 having contacts 71, 72. In Fig. 9, the same parts as in Fig. 6 are given the same reference numerals and detailed description will be omitted. In Fig. 9, the timer unit, packet generator, memory, and comparator are omitted. The process of determining whether the switch 3 is on/off is similar to that of embodiment 2. The FPGAs 1, 2 include communication units 53, 61, respectively, and the determination unit 17 outputs the determination result to the determination unit 29 via the communication units 53, 61, and the determination unit 21 outputs the determination result to the determination unit 16. The determination unit 52, described later, outputs the determination result to the determination unit 59 via the communication units 53, 61, and the determination unit 60 outputs the determination result to the determination unit 51.

The FPGA1 and FPGA2 of the state determination system 5 have two sets of blocks for transmitting and receiving packets and for determining, corresponding to the switch 3 and the switch 7, respectively. In addition to the block for the switch 3 described above, the FPGA1 has a block for the switch 7. The block for the switch 7 has a transmitting unit 49, a determining unit 51, a determining unit 52, a receiving unit 50, an output terminal 54, an input terminal 55, and an input terminal 56. The memory stores the unique value C, which is an identification code corresponding to the contact 71, the expected value C which is the same as the unique value C, and the expected value D which corresponds to the contact 72 and is the same as the unique value D described later. The output terminal 54 is connected to the input side of the contact 71, and the transmitting unit 49 outputs a packet generated by reading the unique value C from the memory from the output terminal 54. The input terminal 55 is connected to the output side of the contact 71, and inputs a packet when the contact 71 is in a closed state. The input terminal 56 is connected to the output side of the contact 72 via an insulating circuit (not shown), and inputs a packet when the contact 72 is in a closed state.

The receiving unit 50 operates at a constant cycle, but the cycle of operation is not synchronized with the cycle of transmission by the transmitting unit 49. If the packet received from the input terminal 55 is normal, the receiving unit 50 performs a decoding process. If a packet is not received from the input terminal 55 for time c or more, if the packet is corrupted, or if the packet is normal but the unique value does not match the expected value C, the determining unit 52 determines that the contact 71 is open. If the packet is received normally and the unique value of the packet matches the expected value C, the determining unit 52 determines that the contact 71 is closed.

The receiving unit 50 performs a decoding process if the packet received from the input terminal 56 is normal. The determining unit 52 determines that the contact 72 is open if a packet has not been received from the input terminal 56 for a time d or more, if the packet is corrupted, or if the packet is normal but the unique value does not match the expected value D. The determining unit 52 determines that the contact 72 is closed if the packet is received normally and the unique value of the packet matches the expected value D.

When both contacts 71 and 72 are closed, the determination unit 52 determines that the switch 7 is on, and when at least one of the contacts 71 and 72 is open, the determination unit 52 determines that the switch 7 is off, and outputs the result to the determination unit 51. The determination unit 52 also outputs the result to the determination unit 59, which is connected via the communication unit 53, an insulating circuit (not shown), and the communication unit 61, and which will be described later. The communication at this time is coded serial communication.

FPGA2 has a block for switch 7 in addition to the block for switch 3 described above. The block for switch 7 includes a transmission unit 57, a judgment unit 59, a judgment unit 60, a reception unit 58, an output terminal 62, an input terminal 63, and an input terminal 64. The memory stores unique value D, expected value C, and expected value D, which are identification codes corresponding to contact 72. The output terminal 62 is connected to the input side of contact 72, and the transmission unit 57 reads unique value D from the memory and generates a packet and outputs it from the output terminal 62. The input terminal 63 is connected to the output side of contact 71 via an insulating circuit (not shown), and inputs a packet when contact 71 is in a closed state. The input terminal 64 is connected to the output side of contact 72, and inputs a packet when contact 72 is in a closed state.

The receiving unit 58 operates at a constant cycle, but the cycle of operation is not synchronized with the cycle of transmission by the transmitting unit 57. If the packet received from the input terminal 63 is normal, the receiving unit 58 performs a decoding process. If a packet is not received from the input terminal 63 for time c or more, if the packet is corrupted, or if the packet is normal but the unique value does not match the expected value C, the determining unit 60 determines that the contact 71 is in an open state. If the determining unit 60 receives a packet normally and the unique value of the packet matches the expected value C, it determines that the contact 71 is in a closed state.

If the packet received from the input terminal 64 is normal, the receiving unit 58 performs a decoding process. If the packet has not been received from the input terminal 64 for a time d or more, if the packet is corrupted, or if the packet is normal but the unique value does not match the expected value D, the determining unit 60 determines that the contact 72 is open. If the packet is received normally and the unique value of the packet matches the expected value D, the determining unit 60 determines that the contact 72 is closed.

When both contacts 71 and 72 are closed, the determination unit 60 determines that the switch 7 is on, and when at least one of the contacts 71 and 72 is open, the determination unit 60 determines that the switch 7 is off, and outputs the result to the determination unit 59. The determination unit 60 also outputs the result to the determination unit 51 connected via the communication unit 61, an insulating circuit (not shown), and the communication unit 53. The communication at this time is coded serial communication.

The judgment unit 51 judges whether the results output by the judgment units 52 and 60 match. If the judgment results of the judgment units 52 and 60 do not match, the judgment unit 51 judges that the switch 7 is off. If the judgment results of the judgment units 52 and 60 match, that is, if both judge that the switch 7 is on, the judgment unit 51 judges that the switch 7 is on, and if both judge that the switch 7 is off, the judgment unit 51 judges that the switch 7 is off. The judgment unit 16 outputs the result to the control unit 6.

The determination unit 59 determines whether the results output by the determination units 52 and 60 match. If the determination results of the determination units 52 and 60 do not match, the determination unit 59 determines that the switch 7 is off. If the determination results of the determination units 52 and 60 match, that is, if both determine that the switch 7 is on, the determination unit 59 determines that the switch 7 is on, and if both determine that the switch 7 is off, the determination unit 59 determines that the switch 7 is off. The determination unit 59 outputs the result to the control unit 6.

When the control unit 6 receives input from the determination units 51 and 59 indicating that the switch 7 is off, i.e., the switch 7 has been operated, an abnormal situation occurs that requires an emergency stop, and the control unit 6 stops driving the motor, etc.

According to this embodiment, when there are multiple switches and the safety system is multiplexed, the open/closed state of multiple contacts can be determined independently and accurately. When the contacts are multiplexed as described above, the synchronization timing between the contacts is shifted, which lengthens the pulse interval and avoids the problem of long undetected times. Therefore, the on/off state of each switch can be determined accurately.

(Embodiment 4)
FIG. 10 is a block diagram that shows a simplified view of a machine tool 100 that includes a state determination system 5 according to the fourth embodiment.
The state determination system 5 further includes an FPGA 8, and the switch 3 has a contact 33 in addition to the contacts 31 and 32. In Fig. 10, the same parts as those in Fig. 6 and Fig. 9 are given the same reference numerals and detailed description will be omitted. In Fig. 10, the timer unit, packet generator, memory, and comparator are omitted. The process of determining the open/closed state of the contacts 31 and 32 is the same as that in the second embodiment. In the figure, the connection between the communication unit 73 and the communication units 53 and 61 is omitted.

The FPGA 8 includes a transmission unit 67, a judgment unit 69, a judgment unit 70, a reception unit 68, a communication unit 73, an output terminal 74, an input terminal 75, an input terminal 76, and an input terminal 77. The memory stores an expected value A, an expected value B, a unique value E that is an identification code corresponding to the contact 33, and an expected value E that is the same as the unique value E. The output terminal 74 is connected to the input side of the contact 33, and the transmission unit 67 outputs a packet generated by reading the unique value E from the memory from the output terminal 74. The input terminal 75 is connected to the output side of the contact 31 via an insulating circuit (not shown), and inputs a packet when the contact 31 is in a closed state. The input terminal 76 is connected to the output side of the contact 32 via an insulating circuit (not shown), and inputs a packet when the contact 32 is in a closed state. The input terminal 77 is connected to the output side of the contact 33, and inputs a packet when the contact 33 is in a closed state.

The receiving unit 68 operates at a constant cycle, but the cycle of operation is not synchronized with the cycle of transmission by the transmitting unit 67. If the packet received from the input terminal 75 is normal, the receiving unit 68 performs a decoding process. If a packet is not received from the input terminal 75 for time a or more, if the packet is corrupted, or if the packet is normal but the unique value does not match the expected value A, the determining unit 70 determines that the contact 31 is in an open state. If the determining unit 70 receives a packet normally and the unique value of the packet matches the expected value A, it determines that the contact 31 is in a closed state.

The receiving unit 68 performs a decoding process if the packet received from the input terminal 76 is normal. The determining unit 70 determines that the contact 32 is open if a packet has not been received from the input terminal 76 for time b or more, if the packet is corrupted, or if the packet is normal but the unique value does not match the expected value B. The determining unit 70 determines that the contact 32 is closed if the packet is received normally and the unique value of the packet matches the expected value B.

The receiving unit 68 performs a decoding process if the packet received from the input terminal 77 is normal. The determining unit 70 determines that the contact 33 is open if a packet has not been received from the input terminal 77 for a period of time e or more, if the packet is corrupted, or if the packet is normal but the unique value does not match the expected value E. The determining unit 70 determines that the contact 33 is closed if the packet is received normally and the unique value of the packet matches the expected value E.

When all of the contacts 31, 32, and 33 are closed, the determination unit 70 determines that the switch 3 is on, and when at least one of the contacts 31, 32, and 33 is open, the determination unit 70 determines that the switch 3 is off, and outputs the result to the determination unit 69. The determination unit 70 also outputs the result to the determination units 16 and 29 via the communication units 73, 53, and 61. An insulating circuit (not shown) is interposed between the communication units. The communication at this time is coded serial communication.

The FPGA 1 is connected to the output side of the contact 33 via an insulating circuit (not shown), and includes an input terminal 65 for inputting a packet when the contact 33 is in a closed state.
The receiving unit 20 performs a decoding process if the packet received from the input terminal 65 is normal. The determining unit 17 determines that the contact 33 is open if a packet has not been received from the input terminal 65 for time e or more, if the packet is corrupted, or if the packet is normal but the unique value does not match the expected value E. The determining unit 17 determines that the contact 33 is closed if the packet is received normally and the unique value of the packet matches the expected value E.
If all of the contacts 31, 32, and 33 are in the closed state, the judgment unit 17 judges that the switch 3 is on, and if at least one of the contacts 31, 32, and 33 is in the open state, it judges that the switch 3 is off, and outputs the result to the judgment units 16, 29, and 69.

The FPGA 2 is connected to the output side of the contact 33 via an insulating circuit (not shown), and includes an input terminal 66 for inputting a packet when the contact 33 is in a closed state.
The receiving unit 23 performs a decoding process if the packet received from the input terminal 66 is normal. The determining unit 21 determines that the contact 33 is open if the packet has not been received from the input terminal 66 for time e or more, if the packet is corrupted, or if the packet is normal but the unique value does not match the expected value E. The determining unit 21 determines that the contact 33 is closed if the packet is received normally and the unique value of the packet matches the expected value E.
If all of the contacts 31, 32, and 33 are in the closed state, the judgment unit 21 judges that the switch 3 is on, and if at least one of the contacts 31, 32, and 33 is in the open state, it judges that the switch 3 is off, and outputs the result to the judgment units 29, 16, and 69.

The determination unit 16 determines whether the results output by the determination units 17, 21, and 70 match. If the determination results of the determination units 17, 21, and 70 do not match, the determination unit 16 determines that the switch 3 is off. If the results of the determination units 17, 21, and 70 match, that is, if all of them determine that the switch 3 is on, the determination unit 16 determines that the switch 3 is on, and if all of them determine that the switch 3 is off, the determination unit 16 determines that the switch 3 is off. The determination unit 16 outputs the result to the control unit 6.
The determination units 29 and 69 also make a determination in the same manner as above, and output the result to the control unit 6 .

FIG. 11 is a flow chart showing the procedure of the process of determining whether the switch 3 is on or off by the FPGA 1.
The packet generator 11 of the FPGA 1 reads the unique value A from the memory and generates a packet including the unique value A and a CRC code (S41).
The FPGA 1 causes the transmission unit 12 to transmit the packet from the output terminal 15 at a predetermined timing measured by the timer unit (S42).

When a packet is input from the input terminal 41, the FPGA 1 determines the open/closed state of the contact 31 by the receiving unit 20 and the determining unit 17 (S43). The open/closed state of the contact 31 is determined in the same manner as the process in the flowchart of FIG. 4.

When a packet is input from the input terminal 42, the FPGA 1 determines the open/closed state of the contact 32 using the receiving unit 20 and the determining unit 17 (S44).

When a packet is input from the input terminal 65, the FPGA 1 determines the open/closed state of the contact 33 by the receiving unit 20 and the determining unit 17 (S45). Note that the order of determining whether the contacts 31, 32, and 33 are open/closed is not limited to the above case.

The FPGA 1 determines in the judgment unit 17 that the switch 3 is in the on state if all of the contacts 31, 32, and 33 are in the closed state, and determines that the switch 3 is in the off state if at least one of the contacts 31, 32, and 33 is in the open state (S46).

The FPGA 1 outputs the determination result to the determination units 16, 29, and 69 via the communication unit 53 (S47).
The FPGA 1 receives the judgment results from the judgment units 29 and 69 via the communication units 53, 61 and 73 (S48).
The FPGA 1 determines, via the determination unit 16, whether the switch 3 is on or off based on the results output by the determination units 17, 21, and 70 (S49).
The FPGA 1 outputs the determination result to the control unit 6 (S50), and ends the process.
Similarly to FPGA 1, FPGAs 2 and 8 determine whether switch 3 is on or off.

According to this embodiment, when there are three or more contacts and the safety system is multiplexed, the open/closed states of the multiple contacts can be determined independently and accurately, and the on/off state of switch 3 can be determined accurately.

1, 2, 8 FPGAs
Reference Signs List 3, 7 Switch 31, 32, 33, 71, 72 Contact 5 State determination system 6 Control unit 11 Packet generation unit 12, 30, 49, 57, 67 Transmission unit 20, 23, 50, 58, 68 Reception unit 14, 25 Timer unit 16, 17, 21, 29, 51, 52, 59, 60, 69, 70 Determination unit 15, 43, 54, 62, 74 Output terminal 26, 42, 44, 56, 63, 64, 65, 66, 75, 76, 77 Input terminal

Claims (8)

a switch having a first contact;
a first control unit that stores a first eigenvalue corresponding to the first contact, outputs a first output signal including the first eigenvalue, and has a first output terminal connected to an input side of the first contact;
a second control unit that stores a first expected value corresponding to the first contact, is connected to an output side of the first contact, and has a first input terminal that receives a first input signal when the first contact is in a closed state;
The second control unit determines that the first contact is in a closed state when a predetermined time has not elapsed since the start of a determination process for determining the open/closed state of the first contact, the first input signal is normal, and a first eigenvalue contained in the first input signal matches the first expected value. a switch having a first contact;
a first control unit that stores a first eigenvalue corresponding to the first contact, outputs a first output signal including the first eigenvalue, and has a first output terminal connected to an input side of the first contact;
a second control unit that stores a first expected value corresponding to the first contact, is connected to an output side of the first contact, and has a first input terminal to which a first input signal is input when the first contact is in a closed state;
Equipped with
the second control unit determines that the first contact is in a closed state when a first eigenvalue included in the first input signal matches the first expected value;
the switch has a second contact;
The first control unit is
further storing the first expected value and a second expected value corresponding to the second contact point;
a second input terminal connected to an output side of the first contact and for receiving a first input signal when the first contact is in a closed state;
a third input terminal connected to an output side of the second contact and for inputting a second input signal when the second contact is in a closed state;
determining that the first contact is in a closed state when a first eigenvalue included in the first input signal input to the second input terminal matches the first expected value;
determining that the second contact is in a closed state when a second eigenvalue included in the second input signal input to the third input terminal matches the second expected value;
The second control unit is
storing a second eigenvalue corresponding to the second tangent point, the first expected value, and the second expected value;
a second output terminal that outputs a second output signal including the second eigenvalue and is connected to an input side of the second contact;
a fourth input terminal connected to an output side of the second contact and receiving a second input signal when the second contact is in a closed state;
A state determination system that determines that the second contact is in a closed state when a second eigenvalue contained in the second input signal input to the fourth input terminal matches the second expected value. The state determination system according to claim 2, wherein the first control unit and the second control unit determine that the switch has been operated or is abnormal when at least one of the first contact and the second contact is in an open state, and determine that the switch is normal when both the first contact and the second contact are in a closed state. The first control unit and the second control unit transmit a determination result to the other control unit,
4. The condition determination system according to claim 3, wherein when the determination results of the respective control units do not match, it is determined that an abnormality has occurred. The state determination system according to any one of claims 2 to 4, wherein the communication between the first control unit and the second control unit is serial communication. A state determination system according to any one of claims 2 to 5, comprising a plurality of switches. The switch further comprises a contact;
The state determination system according to claim 2 , further comprising a control unit corresponding to the contact. A machine tool equipped with a state determination system according to any one of claims 1 to 7, wherein the switch is of a normally closed type, and the contacts are open when an emergency stop occurs, a door is open, or a member is in an abnormal position.

Images