JP7501062B2 - Electro-optical device and electronic device - Google Patents

Description

This disclosure relates to electro-optical devices and electronic devices.

An electro-optical device that displays an image using liquid crystal elements supplies a video voltage based on an image signal that specifies the gradation of each pixel to a pixel circuit corresponding to each pixel via a data line, thereby controlling the transmittance of the liquid crystal in each pixel circuit to a transmittance based on the video voltage. As a result, the gradation of each pixel is set to the gradation specified by the image signal. Patent Document 1 discloses an electro-optical device that uses a demultiplex drive method. Patent Document 2 discloses an electro-optical device that uses a phase expansion drive method.

JP 2018-185415 A JP 2008-242160 A

The demultiplex drive method requires a larger number of video output signals than the phase expansion drive method, and increasing the number of video signal outputs to accommodate higher definition increases the power consumption of the video output amplifier. Limiting the video output amplifier's capabilities to reduce its power consumption makes high-speed drive difficult. In the demultiplex drive method, one possible way to accommodate higher definition without increasing the number of video signal outputs is to increase the number of selection signals provided externally to select a series. However, increasing the number of selection signals poses the problem of needing to increase the panel size in accordance with the increase in input terminals for the selection signals, as well as the problem of needing to drive the selection signals at high speed.

In order to solve the above problem, one aspect of the electro-optical device disclosed herein is an electro-optical device having a first substrate including a pixel region in which pixel circuits are provided at each intersection of a scanning line and K data lines divided into K series, and a group of input terminals arranged along one side of the pixel region, including a video input terminal to which a video signal in which data voltages of each series are time-division multiplexed and an input terminal to which a control signal is input, the electro-optical device has a demultiplexer having K sample switches that selects the data line to which the video signal is supplied in response to a selection signal of the K series, and a data line driving circuit arranged between the pixel region and the group of input terminals, the data line driving circuit having a circuit block that generates the selection signal of the K series, and a video data line that is arranged between the circuit block and a circuit block adjacent to the circuit block and is connected to the video input terminal and the K sample switches. Note that K is an integer equal to or greater than 2, and J is an integer smaller than K.

1 is a block diagram showing a configuration of an electro-optical device according to a first embodiment of the present disclosure. FIG. 2 is a block diagram showing a configuration of a panel substrate. FIG. 4 is a diagram illustrating a configuration example of a selection circuit. 4 is an explanatory diagram of the configuration of a selection signal generating circuit and its operation in a test mode and a normal mode. FIG. FIG. 2 is an explanatory diagram of wiring in a flexible substrate. FIG. 11 is a block diagram showing a configuration of an electro-optical device according to a second embodiment of the present disclosure. FIG. 4 is a diagram illustrating a configuration example of a selection circuit. FIG. 2 is an explanatory diagram of a configuration of a selection signal generating circuit. FIG. 2 is an explanatory diagram of a code decoded by a decoder circuit. FIG. 4 is a diagram illustrating an example of the operation of a decoder circuit. FIG. 4 is an explanatory diagram of an example of the operation of a decoder circuit; FIG. 1 is an explanatory diagram illustrating an example of an electronic device. FIG. 11 is an explanatory diagram showing another example of an electronic device. FIG. 11 is an explanatory diagram showing another example of an electronic device.

Embodiments of the present disclosure will be described below with reference to the drawings. Various technically preferable limitations are imposed on the embodiments described below. However, the embodiments of the present disclosure are not limited to the forms described below.

First Embodiment
1 is an explanatory diagram of an electro-optical device 1 according to a first embodiment of the present disclosure. The electro-optical device 1 is an electro-optical device having a demultiplexer. The electro-optical device 1 has a panel substrate 100A, a drive substrate 200, and a flexible substrate 300. The flexible substrate 300 is connected to the panel substrate 100A and the drive substrate 200. The panel substrate 100A is connected to a host CPU (Central Processing Unit) device (not shown) via the flexible substrate 300 and the drive substrate 200.

The driving substrate 200 is provided with a video signal output circuit 210A and a video signal output circuit 210B such as a driver IC (Integrated Circuit). The video signal output circuit 210A and the video signal output circuit 210B are devices that receive image signals and various control signals for driving control from a host CPU device (not shown) and drive each circuit of the panel substrate 100A via the flexible substrate 300. The number of video signal outputs of each of the video signal output circuits 210A and 210B is equivalent to the number of video signal outputs of a video signal output circuit in a general electro-optical device using a phase expansion driving method. Specifically, each of the video signal output circuits 210A and 210B outputs 48 video signals. In the following, when it is not necessary to distinguish between the video signal output circuit 210A and the video signal output circuit 210B, they will be referred to as the video signal output circuit 210. The number of video signal outputs per video signal output circuit 210 is equivalent to that of a video signal output circuit in a typical electro-optical device using a phase expansion drive method, so a high-performance amplifier can be used to handle each video signal output. For example, the video signal output circuit 210 may be configured using an amplifier capable of writing in about 30 nsec to 40 sec. In this embodiment, two video signal output circuits 210 drive each circuit on the panel substrate 100A, but one video signal output circuit 210 may also drive each circuit on the panel substrate 100A.

1, the panel substrate 100A has a pixel region 110, a scanning line driving circuit 130, a data line driving circuit 140A, a precharge circuit 150, and an input terminal group 160. FIG. 2 is a block diagram showing an example of the configuration of the panel substrate 100A. Note that the input terminal group 160 is omitted in FIG. 2. As shown in FIG. 2, N scanning lines 120, M data lines 122, and N×M pixel circuits PX are arranged in the pixel region 110. Note that both N and M are integers of 2 or more, and in this embodiment, N is 1080 and M is 1920 (20×48×2). In other words, the resolution of the electro-optical device 1 is FHD. The M data lines 122 are classified into a data line group including, for example, K data lines 122. However, K is an integer of 2 or more. In the example shown in FIG. 2, K is 20. Note that K is not limited to 20 as long as it is an integer of 2 or more. Furthermore, the total number of data lines 122 is not limited to 1920. For example, the total number of data lines 122 may be K. In this case, the number of data line groups is one. The panel substrate 100A is an example of a first substrate in this disclosure, and the drive substrate 200 is an example of a second substrate in this disclosure.

The 1920 data lines 122 are classified into 96 data line groups each including 20 data lines 122. Of these 96 data line groups, the 48 data line groups on the left side are given a video signal output from the video signal output circuit 210A, and the 48 data line groups on the right side are given a video signal output from the video signal output circuit 210B. The region in which the pixel circuits PX corresponding to the data line groups to which the video signal is given from the video signal output circuit 210A are arranged is an example of a first pixel region in this disclosure. In addition, the region in which the pixel circuits PX corresponding to the data line groups to which the video signal is given from the video signal output circuit 210B are arranged is an example of a second pixel region that shares the scanning line 120 with the first pixel region. In addition, the video signal output circuit 210A is an example of a first video signal output circuit in this disclosure, and the video signal output circuit 210B is an example of a second video signal output circuit in this disclosure.

A scanning signal G is supplied to each of the N scanning lines 120, and an image signal S or a precharge signal is supplied to the data line 122. The number at the end of the code of the scanning signal G corresponds to the row number. The number at the end of the code of the image signal S and the sample switch SWv described later corresponds to the column number.

Each of the N×M pixel circuits PX is arranged corresponding to each intersection of the N scanning lines 120 and the M data lines 122. In the example shown in FIG. 2, the pixel circuits PX are arranged in a matrix of 1080 rows and 1920 columns. The number of pixel circuits PX is not limited to the example shown in FIG. 2. In FIG. 2, the row of the pixel circuit PX described at the top of the figure is the first row, and the column of the pixel circuit PX described at the leftmost side of the figure is the first column. In addition, hereinafter, the scanning line 120 connected to the pixel circuit PX in the nth row is also referred to as the scanning line 120 in the nth row, and the data line 122 connected to the pixel circuit PX in the mth column is also referred to as the data line 122 in the mth column. In addition, in the example shown in FIG. 2, n is an integer of 1 to 1080, and m is an integer of 1 to 1920.

As shown in FIG. 1, the input terminal group 160 is arranged along one side in the row direction of the pixel region 110, and the flexible substrate 300 is connected to the input terminal group 160. The input terminal group 160 includes video input terminals equal to the number of data line groups, and an input terminal for a control signal for selecting a series. A video signal in which the data voltages of each series included in the corresponding data line group are time-division multiplexed is input to the video input terminal. The video input terminal to which the video signal is provided from the video signal output circuit 210A is an example of a first video input terminal in this disclosure, and the video input terminal to which the video signal is provided from the video signal output circuit 210B is an example of a second video input terminal in this disclosure.

As shown in FIG. 1, the data line driving circuit 140A is disposed between the pixel region 110 and the input terminal group 160. During the horizontal scanning period, the data line driving circuit 140A sequentially supplies an image signal S to each of the 20 data lines 122 during 20 supply periods based on 20 selection signals SEL1 to SEL20 that sequentially select the 20 data lines 122 included in each data line group. In the following, when it is not necessary to distinguish between the selection signals SEL1 to SEL20, they will be referred to as the selection signal SEL. The horizontal scanning period is a period during which a video voltage based on the image signal S supplied to the data line 122 of each column is written to one row of pixel circuits PX.

The row to be written is selected by the scanning signal G supplied from the scanning line drive circuit 130 to the scanning line 120. The scanning line drive circuit 130 is not particularly different from the scanning line drive circuit in a conventional electro-optical device using a demultiplex drive method, so a detailed description will be omitted. The precharge circuit 150 supplies a precharge signal to all K data lines 122 during the horizontal scanning period prior to the supply of the image signal S. As a result, the data lines 122 before the image signal S is supplied are charged to a predetermined precharge voltage based on the precharge signal. The precharge circuit 150 is not particularly different from the precharge circuit in a conventional electro-optical device using a phase expansion drive method, so a detailed description will be omitted.

As shown in FIG. 1, the data line driving circuit 140A is disposed between the pixel region 110 and the input terminal group 160. As shown in FIG. 2, the data line driving circuit 140A has selection circuits A1 to A8, each of which is provided for each of the 12 video data lines VID. The configurations of the selection circuits A1 to A8 are the same. For this reason, FIG. 2 shows only the specific configuration of the selection circuit A1. When it is not necessary to distinguish between the selection circuits A1 to A8, they are referred to as selection circuit A. The selection circuit A includes 12 demultiplexers DM1 to DM12, each of which corresponds to each of the corresponding 12 data line groups, and a selection signal generation circuit 1410A. Each of the demultiplexers DM1 to DM12 included in the selection circuit A is connected to a video data line VID to which a video signal obtained by time-division multiplexing a video voltage to be supplied to the data line 122 included in the corresponding data line group is given. In Figure 2, the wiring of the video data line VID is shown in a simplified form only with respect to the demultiplexer DM1.

Each of the demultiplexers DM1 to DM12 includes K sample switches SWv that select the data line 122 to which the video signal is to be supplied in response to a K series of selection signals SEL. The sample switches SWv are, for example, N-channel transistors composed of thin film transistors (TFTs) or the like. The sample switches SWv are set to either a conductive state or a non-conductive state in response to the level of the selection signal SEL received at a control terminal such as a gate. The sample switches SWv may be P-channel transistors or switching elements other than TFTs. As shown in FIG. 2, the selection circuit A has a series selection signal line group 1420 consisting of 20 signal lines to which the selection signals SEL1 to SEL20 are respectively supplied. The series selection signal line group 1420 is wired in the selection circuit A along the row direction of the pixel region 110.

The selection signal generating circuit 1410A generates K series of selection signals SEL based on J control signals provided from the video signal output circuit 210 via the flexible substrate 300. J is an integer smaller than K, and in this embodiment, J is 9. The selection signal generating circuit 1410A is an example of a circuit block in this disclosure. In addition, the demultiplexer corresponding to the data line group to which the video signal output from the video signal output circuit 240A is provided is an example of the first demultiplexer in this disclosure, and the selection signal generating circuit 1410A corresponding to the first demultiplexer is an example of the first circuit block in this disclosure. In addition, the demultiplexer corresponding to the data line group to which the video signal output from the video signal output circuit 240B is provided is an example of the second demultiplexer in this disclosure, and the selection signal generating circuit 1410A corresponding to the second demultiplexer is an example of the second circuit block in this disclosure.

In this embodiment, the selection signal generating circuit 1410A generates the selection signals SEL1 to SEL20 based on the control signals ENBX2B, ENBX1B, ENBX2, ENBX1, TEST, CLKX, CLKXB, DIRX, and DX. For example, the control signal ENBX2 and the control signal ENBX1 are output enable signals. The control signal ENBX2B is an inverted signal obtained by logically inverting the control signal ENBX2, and the control signal ENBX1B is an inverted signal obtained by logically inverting the control signal ENBX1. The control signal TEST is a test signal that instructs the execution of an inspection of the data line driving circuit 140A. The control signal CLKX is a clock signal, and the control signal CLKXB is a signal obtained by logically inverting the control signal CLKX. The control signal DIRX is a scanning direction indication signal. The control signal DX is a start pulse signal. The control signal ENBX2 and the control signal ENBX1 are an example of a first signal in this disclosure, and the control signal ENBX2B and the control signal ENBX1B are an example of a second signal in this disclosure.

3 is an explanatory diagram of an example of wiring of the video data line VID for the selection circuit A, the control signal line group 1430 to which various control signals are input, and the power line that supplies the operating voltage to the selection signal generation circuit 1410A. As shown in FIG. 3, the video data line VID is arranged along the outer edge of the selection signal generation circuit 1410A of the selection circuit A, in other words, so as to pass between the selection signal generation circuit 1410A and the selection signal generation circuit 1410A adjacent to the selection signal generation circuit 1410A. The video data line VID is arranged so as to pass between the selection signal generation circuits 1410A of the adjacent selection circuits A in order to wire the video data line VID from the video input terminal included in the input terminal group 160 to the demultiplexer in the shortest possible distance without making an unnecessary detour. The high potential power line PVDDX and the low potential power line PVSSX that supply the operating voltage to the selection signal generation circuit 1410A are arranged along one side in the row direction of the pixel area 110. The low-potential power line PVSSX is supplied with a potential VSSX, which is a ground potential, from a power circuit not shown. The potential VSSX is a non-selection potential of the sample switch SWv. The high-potential power line PVDDX is supplied with a potential VDDX from a power circuit not shown. The potential VDDX is a higher potential than the potential VSSX and is a selection potential of the sample switch SWv. The high-potential power line PVDDX and the low-potential power line PVSSX are examples of high-potential and low-potential power lines in this disclosure.

When the high potential power line PVDDX and the low potential power line PVSSX are arranged along one side of the pixel region 110 in the row direction, the input terminal group 160 is also arranged along one side of the pixel region 110 in the row direction, and the data line driving circuit 140A is arranged between the pixel region 110 and the input terminal group 160, if the video data line VID is wired as short as possible, it will intersect with the video data line VID of the high potential power line PVDDX and the low potential power line PVSSX. As shown in FIG. 3, the intersection of the video data line VID of the high potential power line PVDDX and the low potential power line PVSSX is thinner than other points. Since the intersection of the video data line VID of the high potential power line PVDDX and the low potential power line PVSSX is thinner than other points, the superposition of power supply noise on the video signal when driving the selection signal generating circuit 1410A is suppressed, and a high quality display is realized. In other words, in this embodiment, a high-quality display can be achieved even if the video data line VID crosses the high-potential power line PVDDX and the low-potential power line PVSSX, so the video data line VID can be wired as short as possible. Therefore, the wiring resistance and driving load of the video data line VID are smaller than those of conventional electro-optical devices using a phase expansion driving method, making it suitable for high-speed driving.

As shown in FIG. 3, the video data line VID also crosses the group of control signal lines 1430. Although details will be described later, the control signals supplied to the group of control signal lines 1430 include the control signal ENBX2B and the control signal ENBX1B, which are not used to generate the selection signals SEL1 to SEL20. In this embodiment, by crossing the control signal line to which the control signals ENBX2B and ENBX1B, which are not originally required, with the video data line VID, noise superimposition on the video signal from the two signals of positive and negative phases is canceled, and a high-quality display is realized. In other words, in this embodiment, a high-quality display can be realized even if the video data line VID crosses the group of control signal lines 1430, so that the video data can be wired as short a distance as possible. Of the control signal lines included in the group of control signal lines 1430, the control signal line to which the control signal ENBX2 is input and the control signal line to which the control signal ENBX1 is input are examples of the first signal line in this disclosure. Furthermore, among the control signal lines included in the group of control signal lines 1430, the control signal line to which the control signal ENBX2B is input and the control signal line to which the control signal ENBX1B is input are examples of second signal lines in this disclosure. Note that this does not prohibit the use of the control signal ENBX2B and the control signal ENBX1B to generate the selection signals SEL1 to SEL20. In addition, a configuration may be adopted in which the intersection of the signal wiring included in the group of control signal lines 1430 and the video data line VID is thinner than other locations.

FIG. 4 is an explanatory diagram of the configuration of the selection signal generation circuit 1410A and the operation in the inspection mode and normal mode. The selection signal generation circuit 1410A includes a shift register and a buffer circuit that are sequentially selected and driven by the control signals DX, CLKX, and CLKXB. In FIG. 4, the shift register is written as S/R, and the buffer circuit is written as BUF. The data line driving circuit 140A includes eight selection signal generation circuits 1410A. The selection signal generation circuit 1410A includes one shift register. Therefore, the data line driving circuit 140A includes eight shift registers. In FIG. 4, only three of the eight shift registers are shown for explanation. In FIG. 4, the symbol I/O_R indicates the input node of the shift register, and the symbol I/O_L indicates the output node of the shift register. In addition, the selection signal generation circuit 1410A has 20 buffer circuits for one shift register, but in FIG. 4, only four of the 20 buffer circuits are shown for explanation. Specifically, only four buffer circuits corresponding to the selection signals SEL1, SEL2, SEL3, and SEL20 are shown. The buffer circuits are composed of a logical product circuit between the control signal ENBX2 or ENBX1 and the output signal of each stage of the shift register, and a multi-stage inverter group that inputs the output signal of the logical product circuit.

Each of the eight shift registers included in the data line driving circuit 140A has 20 stages of output. The shift direction of the shift register can be switched by the control signal DIRX. As shown in FIG. 3, the video data lines VID are wired so as to pass on both sides of the shift register of the selection signal generating circuit 1410A. In this way, the wiring resistance difference and parasitic capacitance difference of the 12 video data lines VID can be reduced, so that unevenness in the display is suppressed. The 12 video data lines VID can also be arranged together on one side of the shift register. However, if this is done, for example, the wiring resistance difference and parasitic capacitance difference between the video data line VID corresponding to the demultiplexer DM12 in the selection circuit A1 and the video data line VID corresponding to the demultiplexer DM1 in the selection circuit A2 will become large, which may cause display problems such as unevenness at the block boundary.

The buffer circuit receives the output signal of the corresponding shift register and the control signal ENBX1 or the control signal ENBX2. For example, the buffer circuit in the odd-numbered column receives the output signal of the corresponding shift register and the control signal ENBX1, and the buffer circuit outputs the logical product signal of both signals as the selection signal SEL of the odd-numbered series. The buffer circuit in the even-numbered column receives the output signal of the corresponding shift register and the control signal ENBX2, and the buffer circuit outputs the logical product signal of both signals as the selection signal SEL of the even-numbered series. The reason for using the two systems of the control signals ENBX1 and ENBX2 is to ensure reliable waveform shaping in consideration of signal blunting. Thus, in this embodiment, the control signal ENBX1 or the control signal ENBX2 is used to generate the selection signal SEL, but the control signal ENBX1B and the control signal ENBX2B are not used. The configuration of the selection signal generation circuit 1410A may be a configuration in which the number of stages of the shift register of the data line driving circuit in a conventional electro-optical device using a phase expansion driving method is reduced.

The shift registers of all the selection signal generating circuits 1410A included in the data line driving circuit 140A are connected in series via series connection switches. In FIG. 4, only the switches SW1A and SW2A of these series connection switches are shown. In addition, the input terminals of the above-mentioned shift registers are connected to the control signal line to which the control signal DX is supplied via a path switching switch. In FIG. 4, only the switches SW1B and SW2B of these path switching switches are shown. Note that the control signal DX is always input to the first-stage shift register connected in series via the series connection switches, so no path switching switch is provided for the first-stage shift register. In addition, the output terminal of the final-stage shift register is connected to a buffer circuit that stores an end pulse EP via a switch SW3A. The input terminal of this buffer circuit is connected to the low-potential power line PVSSX via a switch SW3B.

By exclusively turning on or off the series connection switch and switch SW3A and the path switching switch and switch SW3B in response to the control signal TEST, the data line driving circuit 140A operates in one of two operating modes, a test mode and a normal driving mode. The series connection switch and switch SW3A, the path switching switch and switch SW3B are examples of switches in this disclosure. Note that in FIG. 4, the connection between the control signal TEST and the series connection switch, switch SW3A, the path switching switch and switch SW3B is omitted, but in detail, for example, each switch is configured with a CMOS switch. The gate electrodes of the N-channel transistors of the series connection switch and switch SW3A are connected to a control signal line to which the control signal TEST is given, and the gate electrodes of the P-channel transistors are connected to a control signal line to which the inverted signal of the control signal TEST is given. On the other hand, the gate electrodes of the P-channel transistors of the path switching switch and switch SW3B are connected to a control signal line to which the control signal TEST is given, and the gate electrodes of the N-channel transistors are connected to a control signal line to which the inverted signal of the control signal TEST is given. The inverted signal of the control signal TEST can be easily generated from the control signal TEST using an inverter (not shown). In this way, when the control signal TEST is at H level, the series connection switch and switch SW3A are turned on, and the path switching switch and switch SW3B are turned off, resulting in the test mode. On the other hand, when the control signal TEST is at L level, the series connection switch and switch SW3A are turned off, and the path switching switch and switch SW3B are turned on, resulting in the normal drive mode. For this reason, the signal supply path in the data line drive circuit 140A differs between the test mode and the normal drive mode.

In the inspection mode, all the shift registers included in the data line driving circuit 140A are connected in series, so if each shift register is normal, when the control signal DX is input to the data line driving circuit 140A, an end pulse EP is output from the buffer circuit connected to the final stage shift register. In other words, it is easy to inspect all the shift registers included in the data line driving circuit 140A. The buffer circuit that outputs the end pulse EP is stationary in the normal driving mode, so power consumption is reduced.

The data line driving circuit 140A is divided into eight selection circuits A1 to A8, and a selection signal SEL is generated in each of the selection circuits A1 to A8. Since the group of series selection signal lines 1420 is provided in the selection circuit A, in this embodiment, the wiring length of the group of series selection signal lines 1420 in one selection circuit A is 1/8 compared to a conventional electro-optical device of 20 series using a demultiplex driving method in which the data line driving circuit is not divided. In addition, in one selection circuit A, there are 12 sample switches SWv connected to one series selection signal line, and in a conventional electro-optical device using a demultiplex driving method, there are 96 sample switches connected to one series selection signal line, so the number of sample switches connected to one series selection signal line is 1/8. According to this embodiment, the wiring resistance is reduced by the amount that the wiring length of the series selection signal line is shorter compared to a conventional electro-optical device using a demultiplex driving method. In addition, the number of switches connected to one series selection signal line is also reduced, so the drive load is reduced and the time constant is reduced. This allows the buffer circuit to drive the sample switch at high speed. The reduced time constant allows the channel width of the sample switch to be increased, improving the ability to write to the data line.

The generation of various control signals for driving the shift register can be realized by making small changes to a conventional phase expansion driving IC. This is because the shift register included in the selection circuit A according to the configuration of the present application is, so to speak, a reduced version of the shift register of an electro-optical device using a conventional phase expansion driving method. The transmission order of the video signals is different, but this can be accommodated by changing the sending order of the video signals built into the storage means. In other words, the video signal output circuit 210 can be configured by making small changes to a conventional phase expansion driving IC. As described above, according to this embodiment, since the same driving IC can be used to support the phase expansion driving method and the demultiplex driving method, it is possible to flexibly select the driving method according to the application, and it is possible to reduce the development cost and manufacturing cost of the electro-optical device. For example, for an electro-optical device with a resolution below FHD, the conventional phase expansion driving method can be selected because the flexible substrate can be manufactured at low cost, and for an electro-optical device with a resolution equal to or higher than FHD, the driving configuration of the present application, which is suitable for high-speed driving, can be selected. When the number of pixels increases, heat dissipation becomes an issue with the COF mounting used in conventional electro-optical devices that use the demultiplex drive method, but with the configuration of this disclosure, the video signal output circuit 210 is placed on a drive substrate 200 that is separate from the panel substrate 100A, making it easier to deal with heat.

Figure 5 is a diagram showing an example of wiring in the flexible substrate 300. As shown in Figure 5, in the flexible substrate 300, a power line group including a common power line, a plurality of video data lines VID for supplying video signals to the panel substrate 100A, and a control signal line group for supplying various control signals to the panel substrate 100A are arranged along the end edge 300a of the flexible substrate 300 on the panel substrate 100A side. In Figure 5, the panel substrate 100A side is extracted to show characteristic elements of the wiring arrangement. A group of external video data lines consisting of six external video data lines VID is wired to the selection circuit A, one group on each side, and a high potential power line PVDDX and a low potential power line PVSSX for supplying an operating voltage to the selection circuit A are arranged between the groups of external video data lines. The external video data line VID connecting the first video input terminal and the video signal output circuit 210A described above is an example of the first external video data line in this disclosure, and the external video data line VID connecting the second video input terminal and the video signal output circuit 210B described above is an example of the second external video data line in this disclosure. In this embodiment, the operating voltage is supplied to the data line driving circuit 140A by the high potential power line PVDDX and the low potential power line PVSSX, which are dedicated power lines, so that the power supply to the data line driving circuit 140A is strengthened. As a result, the voltage drop in the selection circuit A is suppressed, the on potential and the off potential of the sample switch SWv are maintained, and display unevenness is suppressed.

As shown in FIG. 5, in this embodiment, the power lines located next to the external video data lines VID are power lines of the same potential, specifically, the high potential power line PVDDX. If the power lines of the same potential are arranged next to the external video data lines, even if there is an influence of power noise due to the coupling capacitance between the external video data lines and the power lines, the influence of the power noise is unified in each of the selection circuits A1 to A8, and it becomes easier to correct unevenness by correcting the video signal. The reason why the power line located next to the external video data line VID is the high potential power line PVDDX is as follows. In terms of display quality, it is important to suppress the power noise at the end of writing the video signal to the data line 122. When an N-channel transistor is used as the sample switch SWv, when the sample switch SWv is turned off, the power consumption of the inverter in the final stage of the buffer circuit that controls the sample switch SWv becomes large. Since the power noise on the low potential side is large when the sample switch SWv is turned off, it is preferable that the power line located next to the external video data line VID is the selection potential of the sample switch SWv and is a high potential power line with relatively small power noise when the sample switch SWv is turned off. For this reason, in this embodiment, the power line located next to the external video data line VID is the high potential power line PVDDX. Note that when a P-channel transistor is used as the sample switch SWv, when the sample switch SWv is turned off, the power noise on the high potential side is large, so it is preferable that the power line located next to the video data line VID is the selection potential of the sample switch SWv and is a low potential power line with relatively small power noise when the sample switch SWv is turned off. In this case, the power line located next to the external video data line VID may be the low potential power line PVSSX.

As described above, according to this embodiment, selection of a series can be achieved with a smaller number of control signals than the number of series, so that in an electro-optical device using a demultiplex drive method, it is possible to accommodate higher definition without increasing the number of input terminals for control signals and the number of video signal outputs.

Second Embodiment
FIG. 6 is a block diagram showing the configuration of the electro-optical device 1 according to the second embodiment of the present disclosure. In FIG. 6, the same components as those in FIG. 1 are given the same reference numerals. As is clear from comparing FIG. 6 with FIG. 1, the electro-optical device 1 according to this embodiment differs from the electro-optical device 1 according to the first embodiment in that the panel substrate 100B is provided instead of the panel substrate 100A. The panel substrate 100B differs from the panel substrate 100A in that the precharge circuit 150 is omitted and that the data line drive circuit 140B is provided instead of the data line drive circuit 140A. Although detailed illustration is omitted in FIG. 6, the data line drive circuit 140B differs from the data line drive circuit 140A according to the first embodiment in that the selection circuits B1 to B8 are provided instead of the selection circuits A1 to A8. In the following, when it is not necessary to distinguish between the selection circuits B1 to B8, they will be referred to as the selection circuit B. The reason why the precharge circuit 150 can be omitted in this embodiment will be made clear later. Below, the selection circuit B, which is a difference from the first embodiment, will be mainly described.

Figure 7 is a block diagram showing the configuration of selection circuit B. Selection circuit B is addressed by address data lines D0 to D04. Note that address data lines D2 to D4 are not shown in Figure 7. Address data line D0B is an inverted signal line for address data line D0, and address data line D1B is an inverted signal line for address data line D1.

As is clear from comparing FIG. 7 with FIG. 3, the selection circuit B is different from the selection circuit A in that it has a selection signal generation circuit 1410B instead of the selection signal generation circuit 1410A. FIG. 8 is a block diagram showing an example of the configuration of the data line driving circuit 140B. The data line driving circuit 140B includes eight selection circuits B. Therefore, the data line driving circuit 140B includes eight decoder circuits. Each of these eight decoder circuits is, for example, a 5-bit decoder circuit and is connected to the address data lines D0 to D4. Note that in FIG. 8, the inverted signals of each address data line are omitted. For example, the inverted signal of the signal provided to the address data line D0 can be generated by a buffer circuit to which the signal of the address data line D0 is input. The buffer circuit may be configured by connecting an odd number of inverters in series.

The selection signal generating circuit 1410B also includes a total of 20 OR circuits, each corresponding to the first to Kth series, for one decoder circuit, and a total of 20 buffer circuits. Each of the 20 OR circuits performs an OR operation between the output signal of the decoder circuit and a control signal ALL, and outputs the operation result. The control signal ALL is a forced selection signal that instructs the selection of all data lines 122. Each of the address data lines D0 to D4 and the control signal ALL is connected to the low-potential power line PVSSX via a pull-down resistor R. The resistance value of this pull-down resistor R is, for example, 1 MΩ. This pull-down resistor R is provided to prevent the selection signal SEL from being erroneously generated at the selection potential when the power is turned on or off. Since the selection signal SEL does not unintentionally become the selection potential when the power is turned on or off, for example, line-like burn-in can be suppressed.

The buffer circuit performs a logical AND operation between the output signal of the OR circuit of the same series and the control signal ENBX1 or ENBX2, and outputs the result of the operation. The odd-numbered series buffer circuit performs a logical AND operation between the output signal of the OR circuit of the same series and the control signal ENBX1, and outputs the result of the operation. The even-numbered series buffer circuit performs a logical AND operation between the output signal of the OR circuit of the same series and the control signal ENBX2, and outputs the result of the operation. The control signals ENBX1 and ENBX2 may also be connected to the low-potential power line PVSSX via pull-down resistors. Figure 9 is a diagram showing an example of code for a 5-bit decoder circuit. It is configured so that the selection signal does not become the selection potential when the output signals of each of the address data lines D0 to D4 are all 0.

In this embodiment, the control signal ALL can be used to simultaneously turn on or off the selection signals SEL1 to SEL20, and precharging can be performed from the data line driving circuit 140B. For this reason, the precharge circuit 150 is omitted in this embodiment. Since the precharge circuit 150 can be omitted, this embodiment makes it possible to reduce the size of the electro-optical device. Note that the electro-optical device 1 of this embodiment may be provided with an inspection circuit that inspects the data line driving circuit 140B, allowing more detailed inspection to be performed.

This embodiment also achieves the same effect as the first embodiment. In addition, this embodiment makes it easy to set the selection signal to the selection potential in any order. Therefore, this embodiment makes it possible to select a series while rotating the selection order of the series for each frame or each row, which is effective in eliminating display unevenness. For example, as shown in FIG. 10, in the first horizontal scanning period, each series is selected in the order of the first series, the third series, ... the 19th series, the second series, the fourth series ... the 20th series, and in the second horizontal scanning period, each series is selected in the order of the third series, the fifth series, ... the 19th series, the first series, the fourth series ... the 20th series, and the second series. In the ninth horizontal scanning period, as shown in FIG. 11, each series is selected in the order of the 17th series, the 19th series, the first series ... the 18th series, the 20th series, the second series ... the 16th series, and in the 20th horizontal scanning period, each series is selected in the order of the 19th series, the first series, ... the 17th series, the 20th series, the second series ... the 18th series. The drive signal for the decoder circuit included in the selection circuit B is different from the drive signal for the shift register, but if the address data signal is configured to receive a designated signal from a higher-level circuit and output it, for example, the video signal output circuit 210 can be configured by making minor changes to a drive IC that uses a conventional phase expansion drive method.

<Modification>
The above-mentioned embodiments may be modified in various ways. Specific modified embodiments are illustrated below. Two or more embodiments selected from the following examples may be combined as long as they are not mutually contradictory.
<Modification 1>
In the first embodiment, the selection signal generating circuit 1410A may be configured using a shift register with ten output stages. Furthermore, although the video data line VID is wired to pass on both sides of the shift register of the selection signal generating circuit 1410A, this is not limiting. For example, the selection signal generating circuit may be divided into a plurality of subcircuit blocks, and the video data line VID may be arranged to pass between the subcircuit blocks. In this case, the subcircuit block may be configured, for example, of one or more latch circuits that constitute a shift register. In this case, the number of latch circuits included in the subcircuit block may not be equal. In the second embodiment, the subcircuit block may be configured, for example, of one or more unit circuits that perform series selection output of the decoder circuit. In this case, the number of unit circuits that perform series selection output included in the subcircuit block may not be equal. Furthermore, in the arrangement of the video data line VID, it is not mandatory to completely avoid the transistors that constitute the selection signal generating circuit. Specifically, the video data line VID may be arranged in a wiring layer above the transistors that constitute the selection signal generating circuit, and a part of the video data line VID may overlap the transistor. In the second embodiment, the selection signal generating circuit 1410B may be configured using a decoder circuit corresponding to 10 different outputs, specifically, a 4-bit decoder circuit. Furthermore, in the second embodiment, the power supply of the connection destination via the resistor R of the address data line may be set to select a code that does not erroneously generate the selection signal SEL of the selection potential. Therefore, for example, based on FIG. 9, a code that is "NO SEL" with no selection series, that is, the connection destinations via the resistor R of the address data lines D0 to D4 may all be set to VDDX. Alternatively, the connection destination via the resistor R of the address data line D0 may be set to VSSX, and the connection destinations via the resistor R of the other D1 to D4 may be set to VDDX.

<Modification 2>
In the above-described embodiments, a device using liquid crystal is exemplified as an electro-optical device, but the present disclosure is not limited thereto. That is, any electro-optical device may be used as long as it uses an electro-optical material whose optical characteristics change with electrical energy. Note that the electro-optical material is a material whose optical characteristics, such as transmittance and brightness, change with the supply of an electrical signal, such as a current signal or a voltage signal. For example, the present disclosure may be applied to a display panel using light-emitting elements, such as organic electroluminescent (EL), inorganic electroluminescent, or light-emitting polymer, in the same manner as in the first and second embodiments described above.

The present disclosure may also be applied to an electrophoretic display panel that uses, as an electro-optical material, microcapsules containing a colored liquid and white particles dispersed in the liquid, in the same manner as in the first and second embodiments described above. Furthermore, the present disclosure may also be applied to a twist ball display panel that uses, as an electro-optical material, twist balls that are painted in different colors for areas with different polarities, in the same manner as in the first and second embodiments described above. The present disclosure may also be applied to various electro-optical devices, such as a toner display panel that uses black toner as an electro-optical material, in the same manner as in the first and second embodiments described above.

<Application Examples>
The present invention can be applied to various electronic devices. Figures 12 to 14 show examples of specific forms of electronic devices to which the present invention can be applied.
Fig. 12 is an explanatory diagram showing an example of an electronic device. Fig. 12 is a perspective view of a portable personal computer 2000 that employs the electro-optical device 1. The personal computer 2000 has the electro-optical device 1 that displays various images, and a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed.

Fig. 13 is an explanatory diagram showing another example of an electronic device. Fig. 13 is a perspective view of a mobile phone 3000. The mobile phone 3000 has a number of operation buttons 3001 and a scroll button 3002, and an electro-optical device 1 that displays various images. By operating the scroll button 3002, the screen displayed on the electro-optical device 1 is scrolled.

Figure 14 is an explanatory diagram showing another example of an electronic device. Note that Figure 14 is a schematic diagram showing the configuration of a projection display device 4000 that employs an electro-optical device 1. The projection display device 4000 is, for example, a three-panel projector. The electro-optical device 1R shown in Figure 14 is an electro-optical device 1 that corresponds to the red display color, the electro-optical device 1G is an electro-optical device 1 that corresponds to the green display color, and the electro-optical device 1B is an electro-optical device 1 that corresponds to the blue display color.

That is, the projection display device 4000 has three electro-optical devices 1R, 1G, and 1B corresponding to the display colors of red, green, and blue, respectively. The illumination optical system 4001 supplies the red component r of the light emitted from the illumination device 4002, which is a light source, to the electro-optical device 1R, supplies the green component g to the electro-optical device 1G, and supplies the blue component b to the electro-optical device 1B. Each of the electro-optical devices 1R, 1G, and 1B functions as an optical modulator such as a light valve that modulates each monochromatic light supplied from the illumination optical system 4001 according to the display image. The projection optical system 4003 combines the light emitted from each of the electro-optical devices 1R, 1G, and 1B and projects it onto the projection surface 4004. That is, the present disclosure is also applicable to a liquid crystal projector.

Note that examples of electronic devices to which the present disclosure can be applied include the devices illustrated in FIG. 1 and FIG. 12 to FIG. 14 as well as personal digital assistants (PDAs). Other examples include digital still cameras, televisions, video cameras, car navigation devices, in-vehicle displays such as instrument panels, electronic organizers, electronic paper, calculators, word processors, workstations, videophones, and POS terminals. Further examples include printers, scanners, copiers, video players, and devices equipped with touch panels.

<Aspects grasped from at least one of the embodiment and each modified example>
The present disclosure is not limited to the above-mentioned embodiments and modifications, and can be realized in various aspects without departing from the spirit of the present disclosure. For example, the present disclosure can also be realized in the following aspects. The technical features in the above-mentioned embodiments corresponding to the technical features in each aspect described below can be appropriately replaced or combined in order to solve some or all of the problems of the present disclosure or to achieve some or all of the effects of the present disclosure. Furthermore, if the technical feature is not described as essential in this specification, it can be appropriately deleted.

One aspect of the electro-optical device disclosed herein includes a pixel region in which pixel circuits are provided at each intersection of a scanning line and K data lines divided into K series, a video input terminal to which a video signal in which data voltages of each series are time-division multiplexed is input, and an input terminal to which a control signal is input, and a first substrate having an input terminal group arranged along one side of the pixel region, and a data line driving circuit. The data line driving circuit has a demultiplexer having K switches that selects a data line to which the video signal is supplied in response to a K series selection signal, and is arranged between the pixel region and the input terminal group. The data line driving circuit also has a circuit block that generates the K series selection signal, and a video data line that is arranged between the circuit block and a circuit block adjacent to the circuit block and is connected to the video input terminal and the K switches. K is an integer of 2 or more. According to this aspect, the data line driving circuit is divided into a plurality of circuit blocks, and a selection signal is generated in each circuit block. Also, a video data line is wired between the circuit blocks. The wiring resistance and driving load of the video data line are equivalent to those of the conventional circuit block. In addition, the wiring resistance and driving load of the selection signal line are reduced, allowing high-speed driving and reducing the number of video data lines. This allows the output amplifier's capabilities to be increased to the same level as phase expansion driving.

In a more preferred embodiment of the electro-optical device, the circuit block may include a shift register, and may generate the K-series selection signal based on an output signal of the shift register. According to this embodiment, a video signal output circuit can be configured by making small changes to a conventional phase expansion driving IC, and it becomes possible to flexibly select a driving method according to the application. In a further preferred embodiment of the electro-optical device, the circuit block may have two operation modes: a normal mode in which the K-series selection signal is generated based on the output signal of the shift register, and an inspection mode in which the output signal of the shift register is output, and may have a switch for switching between the two operation modes. According to this embodiment, it becomes possible to easily inspect the data line driving circuit.

In another preferred embodiment of the electro-optical device, the circuit block may include a decoder circuit, and generate the K-series selection signal based on an output signal from the decoder circuit. According to this embodiment, it is possible to select a series while rotating the series selection order for each frame or each row, which is effective in eliminating display unevenness.

In another preferred embodiment of the electro-optical device, high and low potential power lines that supply operating power to the circuit blocks may intersect with the video data lines, and each of the power lines may be thinner at the points where they intersect with the video data lines than at other points. According to this embodiment, the area of each power line where it intersects with the video data lines is thinner than at other points, so that superimposition of power supply noise on the video signal when driving the circuit blocks is suppressed, and a high-quality display is achieved.

In another preferred embodiment of the electro-optical device, the video data lines may intersect with a first signal line to which a first signal is supplied and a second signal line to which a second signal that is an inverted signal of the first signal is supplied. According to this embodiment, noise superimposed on the video data lines is cancelled out by the first signal and the second signal, thereby realizing a high-quality display.
In another preferred embodiment of the electro-optical device, the circuit block generates the K series of selection signals based on J number of the control signals, and the first signal and the second signal may be included in the J number of the control signals, where J is an integer smaller than K. According to this embodiment, it becomes possible to generate the K series of selection signals with J number of control signals, which is smaller than the number of series of the selection signals.

In another preferred embodiment of the electro-optical device, a second substrate may be provided on which a video signal output circuit that outputs the video signal to the video input terminal is disposed. According to this embodiment, the video signal output circuit is provided on a second substrate that is different from the first substrate, making it easier to deal with heat in the video signal output circuit.

In another preferred embodiment of the electro-optical device, the first substrate may have the first pixel region and the second pixel region that share the scanning line. In this embodiment, the input terminal group may include a first video input terminal to which the first video signal supplied to the data line of the first pixel region is input, and a second video input terminal to which the second video signal supplied to the data line of the second pixel region is input. The data line driving circuit may have a first demultiplexer and a first circuit block corresponding to the first pixel region, and a second demultiplexer and a second circuit block corresponding to the second pixel region. Furthermore, the electro-optical device may have a flexible substrate that connects the first substrate and the second substrate, and a first external video data line, a second external video data line, and a power supply line group may be arranged on the flexible substrate. The first external video data line connects the first video input terminal and the video signal output circuit. The second external video data line connects the second video input terminal and the video signal output circuit. The power supply line group is arranged between the first external video data line and the second external video data line, and includes high and low potential power supply lines that supply operating power to the first circuit block, and high and low potential power supply lines that supply operating power to the second circuit block. According to this aspect, power is supplied to each of the first circuit block and the second circuit block via a dedicated power supply line, so that voltage drops in each of the first circuit block and the second circuit block are suppressed.

In another preferred embodiment of the electro-optical device, the potential of the power line arranged next to the first external video data line in the power line group may be the same as the potential of the power line arranged next to the second external video data line. According to this embodiment, since the potential of the power line arranged next to the first external video data line is the same as the potential of the power line arranged next to the second external video data line, even if there is an effect of power supply noise, the effect of the power supply noise is the same in each of the first circuit block and the second circuit block, making it easier to correct unevenness by correcting the video signal.

In another preferred embodiment of the electro-optical device, the power supply line arranged next to the first external video data line and the power supply line arranged next to the second external video data line may be power supply lines for the selection potential of the sample switch. According to this embodiment, the occurrence of display unevenness caused by the switch turning off is suppressed.

The electronic device of the present disclosure includes an electro-optical device according to any one of the above aspects. According to this aspect, it is possible to drive an electronic device including an electro-optical device using a demultiplex drive method at high speed, and it is possible to reduce the number of video data lines. Therefore, the performance of the output amplifier for the video signal in an electronic device including an electro-optical device using a demultiplex drive method can be increased to the same level as in phase expansion drive.

1, 1B, 1G, 1R... electro-optical device, 100A, 100B... panel substrate, 200... drive substrate, 300... flexible substrate, 110... pixel area, 120... scanning line, 122... data line, 130... scanning line drive circuit, 140A, 140B... data line drive circuit, 150... precharge circuit, 160... input terminal group, 210A, 210B... video signal output circuit, A1 to A8, B1 to B8... selection circuit, 1410A, 1410B... selection signal generation circuit, 1420... series selection signal Group of lines, 1430...group of control signal lines, PVDDX...high potential power line, PVSSX...low potential power line, 2000...personal computer, 2001...power switch, 2002...keyboard, 2010...main body, 3000...mobile phone, 3001...operation button, 3002...scroll button, 4000...projection display device, 4001...illumination optical system, 4002...illumination device, 4003...projection optical system, 4004...projection surface, PX...pixel circuit, SWv...sample switch.

Claims (10)

An electro-optical device comprising a first substrate having a pixel area in which pixel circuits are provided at each intersection of scanning lines and K data lines divided into K series (K is an integer of 2 or more), and a group of input terminals arranged along the pixel area, including a video input terminal to which a video signal obtained by time-division multiplexing data voltages of each series is input, and an input terminal to which a control signal is input,
a data line driving circuit disposed between the pixel region and the input terminal group, the data line driving circuit having a demultiplexer having K sample switches for selecting a data line to which the video signal is to be supplied in response to a K series selection signal;
The data line driving circuit includes:
A circuit block for generating the K-series selection signal;
a video data line disposed between the circuit block and a circuit block adjacent to the circuit block, the video data line being connected to the video input terminal and the K sample switches;
The circuit block includes a shift register, and has two operating modes: a normal mode in which the K series selection signal is generated based on an output signal of the shift register, and an inspection mode in which the output signal of the shift register is output, and the electro-optical device has a switch for switching between the two operating modes. The electro-optical device according to claim 1, wherein the circuit block includes a decoder circuit and generates the K-series selection signal based on an output signal from the decoder circuit. An electro-optical device comprising a first substrate having a pixel area in which pixel circuits are provided at each intersection of scanning lines and K data lines divided into K series (K is an integer of 2 or more), and a group of input terminals arranged along the pixel area, including a video input terminal to which a video signal obtained by time-division multiplexing data voltages of each series is input, and an input terminal to which a control signal is input,
a data line driving circuit disposed between the pixel region and the input terminal group, the data line driving circuit having a demultiplexer having K sample switches for selecting a data line to which the video signal is to be supplied in response to a K series selection signal;
The data line driving circuit includes:
A circuit block for generating the K-series selection signal;
a video data line disposed between the circuit block and a circuit block adjacent to the circuit block, the video data line being connected to the video input terminal and the K sample switches;
An electro-optical device, wherein high and low potential power lines that supply operating power to the circuit block intersect with the video data lines, and each of the power lines is thinner at the points where it intersects with the video data lines than at other points. An electro-optical device comprising a first substrate having a pixel area in which pixel circuits are provided at each intersection of scanning lines and K data lines divided into K series (K is an integer of 2 or more), and a group of input terminals arranged along the pixel area, including a video input terminal to which a video signal obtained by time-division multiplexing data voltages of each series is input, and an input terminal to which a control signal is input,
a data line driving circuit disposed between the pixel region and the input terminal group, the data line driving circuit having a demultiplexer having K sample switches for selecting a data line to which the video signal is to be supplied in response to a K series selection signal;
The data line driving circuit includes:
A circuit block for generating the K-series selection signal;
a video data line disposed between the circuit block and a circuit block adjacent to the circuit block, the video data line being connected to the video input terminal and the K sample switches;
The electro-optical device, wherein the video data lines intersect with a first signal line to which a first signal is supplied and a second signal line to which a second signal that is an inverted signal of the first signal is supplied. the circuit block generates the K series of selection signals based on J (J is an integer smaller than K) number of the control signals;
The electro-optical device according to claim 4 , wherein the first signal and the second signal are included in J of the control signals. a second substrate on which a video signal output circuit for outputting the video signal to the video input terminal is disposed;
6. The electro-optical device according to claim 1 . An electro-optical device comprising a first substrate having a pixel area in which pixel circuits are provided at each intersection of scanning lines and K data lines divided into K series (K is an integer of 2 or more), and a group of input terminals arranged along the pixel area, including a video input terminal to which a video signal obtained by time-division multiplexing data voltages of each series is input, and an input terminal to which a control signal is input,
a data line driving circuit disposed between the pixel region and the input terminal group, the data line driving circuit having a demultiplexer having K sample switches for selecting a data line to which the video signal is to be supplied in response to a K series selection signal;
The data line driving circuit includes:
A circuit block for generating the K-series selection signal;
a video data line disposed between the circuit block and a circuit block adjacent to the circuit block, the video data line being connected to the video input terminal and the K sample switches;
The first substrate is
a first pixel region and a second pixel region that share the scanning line;
The input terminal group includes:
a first video input terminal to which the first video signal to be supplied to a data line of the first pixel region is input;
a second image input terminal to which the second image signal to be supplied to a data line of the second pixel region is input;
The data line driving circuit includes:
a first demultiplexer and a first circuit block corresponding to a first pixel region;
a second demultiplexer and a second circuit block corresponding to a second pixel region;
a flexible substrate that connects the first substrate and a second substrate on which a video signal output circuit that outputs the video signal to the video input terminal is disposed ;
The flexible substrate includes:
a first external video data line connecting the first video input terminal and the video signal output circuit;
a second external video data line connecting the second video input terminal and the video signal output circuit;
an electro-optical device, comprising: a power supply line group arranged between the first external video data line and the second external video data line, the power supply line group including high and low potential power supply lines for supplying operating power to the first circuit block, and high and low potential power supply lines for supplying operating power to the second circuit block; The electro-optical device according to claim 7, wherein the potential of the power line arranged next to the first external video data line and the potential of the power line arranged next to the second external video data line in the power line group are the same potential. The electro-optical device according to claim 8, wherein the power supply line arranged next to the first external video data line and the power supply line arranged next to the second external video data line are power supply lines for the selection potential of the sample switch. 10. An electronic device comprising the electro-optical device according to claim 1.

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