JP7501196B2 - NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - Patent application - Google Patents

Description

The present invention relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device.

2. Description of the Related Art Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) using gallium nitride (GaN) have been known (see, for example, Japanese Patent Application Laid-Open No. 2003-233663).
Also, when forming a region doped with a first conductivity type impurity in an n-type GaN-based semiconductor epitaxial layer (hereinafter, n-type GaN layer), a method is known in which an insulator layer is formed on the n-type GaN layer, an ion implantation mask made of photoresist is formed on the insulator layer, and ions of the first conductivity type impurity such as magnesium (Mg) are implanted into the n-type GaN layer through openings formed in the ion implantation mask and the insulator layer (see, for example, Patent Document 2).
Also, a method is known in which ions are implanted into a semiconductor substrate using an oxide film as a mask (see, for example, Japanese Patent Application Laid-Open No. 2003-233664).

JP 2017-188687 A JP 2012-104801 A JP 2017-92361 A

In the process of ion-implanting a first conductivity type impurity (acceptor) into a GaN layer using a photoresist, carbon elements (C) and oxygen elements (O) are released into the atmosphere in the chamber due to degassing from the photoresist, and the released C and O may be implanted into the GaN layer together with the first conductivity type impurity. In the GaN layer, C acts as an acceptor and O acts as a donor. Therefore, when C and O are implanted into the GaN layer together with the first conductivity type impurity (acceptor), the effective acceptor concentration in the GaN layer may fluctuate, and the characteristics of the element having the GaN layer may deteriorate.

In addition, the method of using an oxide film instead of a photoresist as an ion implantation mask prevents the release of C and O due to degassing. However, with this method, when the oxide film is etched away from the GaN layer after ion implantation, the surface of the region located under the opening of the ion implantation mask (i.e., the ion implantation region) may be over-etched and damaged. If the GaN layer is damaged, the characteristics of the device having the GaN layer may be degraded.

The present invention has been made with a focus on the above-mentioned problems, and aims to provide a nitride semiconductor device and a method for manufacturing a nitride semiconductor device that can suppress deterioration of characteristics.

In order to solve the above problems, a nitride semiconductor device according to one aspect of the present invention includes a gallium nitride layer having an implanted region into which an impurity element of a first conductivity type is implanted, and a non-implanted region adjacent to the implanted region into which the impurity element is not implanted. In the implanted region, an average concentration of carbon element (C) in a range from a surface of the implanted region to a peak position where the amount of implantation of the impurity element is maximum in a depth direction is 1E+16/ ^cm3 or less. A step at a boundary between the implanted region and the non-implanted region is 1 nm or less.

As a result, the concentration of carbon element (C) acting as an acceptor in the implanted region is kept low, so that fluctuations in the effective acceptor concentration (or effective donor concentration) in the implanted region can be suppressed. This makes it possible to suppress deterioration in the characteristics of the element including the implanted region. In addition, the step at the boundary between the implanted region and the non-implanted region is 1 nm or less. This makes it possible to suppress electric field concentration at the step at the boundary when a voltage is applied in the reverse direction to an element including this boundary, and suppress deterioration in the breakdown voltage.

The above "surface" may not be the surface strictly, but may be near the surface. Near the surface may be "a position closest to the surface where the measured concentration is reliable". Near the surface may be "a position 0.2 μm away from the surface in the depth direction". Alternatively, near the surface may be "a position closest to the surface where the concentration of the impurity element is 1E+16/cm ³ or more and 1E+18/cm ³ or less". The effective acceptor concentration is the concentration obtained by offsetting the donor concentration from the acceptor concentration. The effective donor concentration is the concentration obtained by offsetting the acceptor concentration from the donor concentration. E+ is an exponential notation. For example, 1E+16 means 1×10 ¹⁶ .

A nitride semiconductor device according to another aspect of the present invention includes a gallium nitride layer having an implanted region into which an impurity element of a first conductivity type is implanted, and a non-implanted region adjacent to the implanted region into which the impurity element is not implanted. In the implanted region, an average concentration of oxygen (O) in a range from a surface of the implanted region to a peak position where the amount of implantation of the impurity element is maximum in a depth direction is 1E+16/cm3 or ^less . A step at a boundary between the implanted region and the non-implanted region is 1 nm or less.

As a result, the concentration of oxygen (O), which acts as a donor, is kept low in the implanted region, so that fluctuations in the effective acceptor concentration (or effective donor concentration) in the implanted region can be suppressed. This makes it possible to suppress deterioration in the characteristics of the element including the implanted region. In addition, because the step at the boundary between the implanted region and the non-implanted region is 1 nm or less, electric field concentration at this step at the boundary can be suppressed, and deterioration in the breakdown voltage can be suppressed.

A method for manufacturing a nitride semiconductor device according to one aspect of the present invention includes the steps of: forming a first inorganic material film on a gallium nitride layer; forming a second inorganic material film on the first inorganic material film, the second inorganic material film having a higher etching rate in a dry etching process using a fluorine-containing gas than the first inorganic material film; patterning the second inorganic material film by the dry etching process to form a first opening penetrating the second inorganic material film in the thickness direction in the second inorganic material film; performing a first wet etching process on the first inorganic material film using the second inorganic material film in which the first opening is formed as a mask to form a second opening in the first inorganic material film that communicates with the first opening; ion-implanting a first conductive type impurity element into the gallium nitride layer through the first opening and the second opening; performing a second wet etching process on the second inorganic material film to remove the second inorganic material film from above the first inorganic material film; and performing a third wet etching process on the first inorganic material film to remove the first inorganic material film from above the gallium nitride layer.

According to this, the manufacturing apparatus can suppress overdry etching of the surface of the implantation region into which the first conductive type impurity element is ion-implanted, and can suppress damage such as the generation of defects and interface states on the surface of the implantation region. In addition, when ion-implanting the first conductive type impurity element, a laminated film composed of a first inorganic material film and a second inorganic material film is used as a mask instead of a resist pattern. As a result, there is no outgassing from the resist pattern during the above ion implantation, and carbon element (C) and oxygen element (O) contained in the outgas are not implanted into the implantation region. In the gallium nitride layer, C acts as an acceptor and O acts as a donor, but C and O from the outgas are not implanted during the above ion implantation, so that it is possible to suppress fluctuations in the effective acceptor concentration (or effective donor concentration) in the implantation region. This makes it possible to suppress deterioration in the characteristics of the element including the implantation region.

The present invention provides a nitride semiconductor device and a method for manufacturing a nitride semiconductor device that can suppress deterioration of characteristics.

FIG. 1 is a cross-sectional view showing an example of the configuration of a nitride semiconductor device according to a first embodiment of the present invention. FIG. 2 is a plan view showing a configuration example of the nitride semiconductor device according to the first embodiment of the present invention. 3A to 3C are cross-sectional views showing the steps of a method for manufacturing the pn diode according to the first embodiment of the present invention. 3A to 3B are cross-sectional views showing the process steps of a method for manufacturing the pn diode according to the first embodiment of the present invention. 3A to 3C are cross-sectional views showing the process steps of a method for manufacturing the pn diode according to the first embodiment of the present invention. 3A to 3D are cross-sectional views showing the process steps of a method for manufacturing the pn diode according to the first embodiment of the present invention. 3A to 3E are cross-sectional views showing the process steps of a method for manufacturing the pn diode according to the first embodiment of the present invention. 3F is a cross-sectional view showing a method for manufacturing the pn diode according to the first embodiment of the present invention in the order of steps. FIG. 4 is a graph showing the results (experimental results) of actual measurements of the relationship between the depth from the surface and the carbon (C) concentration in the p-type region of the pn diode according to the first embodiment of the present invention. FIG. 5 is a graph showing the results of a simulation of the relationship between the depth from the surface and the oxygen element (O) concentration in the p-type region of the pn diode according to the first embodiment of the present invention. FIG. 6 is a graph showing the results of a simulation of the relationship between the depth from the surface and the carbon (C) concentration in the p-type region of the pn diode according to Comparative Example 1 of the present invention. FIG. 7 is a graph showing the results of a simulation of the relationship between the depth from the surface and the oxygen element (O) concentration for the p-type region of the pn diode according to Comparative Example 1 of the present invention. FIG. 8 is a graph showing the results of a simulation of the relationship between the depth from the surface of the p-type region and the carbon (C) concentration for the p-type region of a pn diode according to Comparative Example 2 of the present invention. FIG. 9 is a graph showing the results of a simulation of the relationship between the depth from the surface and the oxygen element (O) concentration for the p-type region of the pn diode according to Comparative Example 2 of the present invention. FIG. 10 is a diagram showing the results of a simulation of the relationship between the reverse voltage and the leakage current density for the pn diode according to the first embodiment of the present invention. FIG. 11 is a diagram showing the results of a simulation of the relationship between the reverse voltage and the leakage current density for the pn diode according to Comparative Example 1 of the present invention. FIG. 12 is a cross-sectional view showing a configuration example of a nitride semiconductor device according to the second embodiment of the present invention. FIG. 13A is a cross-sectional view showing a method for manufacturing a vertical MOSFET according to the second embodiment of the present invention in the order of steps. 13A to 13B are cross-sectional views showing the process steps of a method for manufacturing the vertical MOSFET according to the second embodiment of the present invention. 13A to 13C are cross-sectional views showing the process steps of a method for manufacturing a vertical MOSFET according to the second embodiment of the present invention. 13A to 13D are cross-sectional views showing the process steps of a method for manufacturing a vertical MOSFET according to the second embodiment of the present invention. 13A to 13E are cross-sectional views showing the process steps of a method for manufacturing a vertical MOSFET according to the second embodiment of the present invention. 13A to 13F are cross-sectional views showing the process steps of a method for manufacturing a vertical MOSFET according to the second embodiment of the present invention. FIG. 14 is a cross-sectional view showing a configuration example of a nitride semiconductor device according to the third embodiment of the present invention.

The following describes an embodiment of the present invention. In the following description of the drawings, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each component, etc., differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

In the following description, the positive direction of the Z axis may be referred to as "up" and the negative direction of the Z axis may be referred to as "down". "Up" and "down" do not necessarily mean the vertical direction relative to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationships in regions, layers, films, substrates, etc., and do not limit the technical concept of the present invention. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up".

In the following explanation, an example will be given in which the first conductivity type is p-type and the second conductivity type is n-type. The + or - attached to p or n means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without a + or - attached. However, even if the same p and p (or n and n) are attached to semiconductor regions, this does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

<Embodiment 1>
(composition)
FIG. 1 is a cross-sectional view showing a configuration example of a nitride semiconductor device according to the first embodiment of the present invention. FIG. 2 is a plan view showing a configuration example of a nitride semiconductor device according to the first embodiment of the present invention. FIG. 1 shows a cross section taken along line X2-X'2 of the plan view shown in FIG. 2. In addition, in FIG. 2, in order to show a surface 12a of a GaN layer 12, a surface 14a of a p-type region 14, and a boundary 13 between the surfaces 12a and 14a, which will be described later, an insulating film 16 and an anode electrode 18 are omitted. In addition, in FIG. 1, FIG. 2, and FIG. 12 and FIG. 14, which will be described later, the X-axis direction and the Y-axis direction are parallel to the surface 12a of the GaN layer 12, and the Z-axis direction is the depth direction of the GaN layer 12. The X-axis, the Y-axis, and the Z-axis are orthogonal to each other.

As shown in FIGS. 1 and 2, the nitride semiconductor device according to the first embodiment includes a pn diode 1 (one example of the "diode" of the present invention). The pn diode 1 includes an n ⁺ type gallium nitride substrate (GaN substrate) 10, an n type gallium nitride layer (GaN layer) 12 provided on the surface 10a side of the GaN substrate 10, a p type region 14 provided in the GaN layer 12, an insulating film 16 provided on the surface 12a of the GaN layer 12, an anode electrode 18 connected to the p type region 14, and a cathode electrode 20 connected to the n ⁺ type GaN substrate 10. The p type region 14 is one example of the "implanted region" of the present invention. In the n type GaN layer 12, a region adjacent to the p type region 14 is one example of the "non-implanted region" of the present invention.

The GaN substrate 10 is, for example, an n ⁺ type c-plane GaN single crystal substrate. The n-type impurities contained in the GaN substrate 10 are one or more elements selected from the group consisting of Si (silicon), O (oxygen), and Ge (germanium). As an example, the n-type impurities contained in the GaN substrate 10 are Si or O, and the impurity concentration of Si in the GaN substrate 10 is 5E+17/ ^cm3 or more.

The GaN substrate 10 may be n-type or n ^-type . The GaN substrate 10 may be a low-dislocation freestanding substrate with a dislocation density of less than 1E+7 cm ^-2 . When the GaN substrate 10 is a low-dislocation freestanding substrate, the dislocation density of the GaN layer 12 formed on the GaN substrate 10 is also low. Furthermore, by using a low-dislocation substrate for the GaN substrate 10, even when a large-area power device is formed on the GaN substrate 10, the leakage current in the power device can be reduced. This allows the manufacturing apparatus to manufacture power devices with a high yield rate. Furthermore, the ion-implanted impurities can be prevented from diffusing deeply along the dislocations during heat treatment.

The GaN layer 12 is provided on the surface 10a of the GaN substrate 10. The GaN layer 12 is, for example, an n-type GaN single crystal layer, and is a layer epitaxially grown on the surface 10a of the GaN substrate 10. The GaN layer 12 is formed by doping with an n-type impurity during the epitaxial growth process. The n-type impurity is, for example, Si. For example, the concentration of Si in the GaN layer 12 is 2E+16/ ^cm3 . The thickness of the GaN layer 12 is 4 μm.

The p-type region 14 is formed by ion-implanting a p-type impurity element (p-type impurity) into the n-type GaN layer 12 and performing a heat treatment. The p-type impurity is, for example, magnesium (Mg). As illustrated in Figs. 4 and 5 described later, in the p-type region 14, the average concentration of carbon element (C) and the average concentration of oxygen element (O) in the range from the surface (or near the surface) to the Mg peak position where the amount of Mg implanted in the depth direction is maximum are each 1E+16/cm ³ or less. In addition, the step of the boundary 13 between the surface 12a of the GaN layer 12 and the surface 14a of the p-type region 14 is, for example, 1 nm or less.

The insulating film 16 is, for example, a silicon oxide (SiO ₂ ) film. An opening H1 is provided in the insulating film 16. The anode electrode 18 is provided on the insulating film 16 and is connected to the p-type region 14 through the opening H1. The cathode electrode 20 is provided on the rear surface 10b side of the n ⁺ -type GaN substrate 10 and is connected to the GaN substrate 10. The anode electrode 18 and the cathode electrode 20 are made of, for example, Al, an Al alloy (for example, a Ti-Al alloy), Ni, or a Ni alloy (for example, a Ni-Au alloy).

(Production method)
Next, a method for manufacturing the pn diode 1 shown in Figures 1 and 2 will be described. Figures 3A to 3F are cross-sectional views showing the process steps of the method for manufacturing the pn diode 1 according to the first embodiment of the present invention. The pn diode 1 is manufactured using various types of equipment, such as a film formation device (including an epitaxial growth device, a CVD device, a sputtering device, and a resist coating device), an exposure device, an ion implantation device, an annealing device, and an etching device. Hereinafter, these devices will be collectively referred to as manufacturing devices.

As shown in FIG. 3A, the manufacturing equipment forms a GaN layer 12 on the surface 10a of the GaN substrate 10. For example, the manufacturing equipment epitaxially grows the GaN layer 12 on the GaN substrate 10 by metal organic chemical vapor deposition (MOCVD). In the process of epitaxially growing the GaN layer 12, the manufacturing equipment dopes the GaN layer 12 with Si as an n-type impurity.

Next, the manufacturing equipment forms an aluminum oxide ( _Al2O3 ) film 22 (an example of _a "first inorganic material film" of the present invention) on the GaN layer 12 by a CVD method. The manufacturing equipment forms _{the Al2O3} film 22 to a thickness of, for example, 150 nm. Next, as shown in Fig. 3B, the manufacturing equipment forms _{a SiO2 film} 24 (an example of a "second inorganic material film" of the present invention) on the _Al2O3 film 22 by a CVD method. The manufacturing equipment forms the _SiO2 film 24 to a thickness of, for example, 2 µm.

3C, the manufacturing equipment forms a pattern (resist pattern) RP1 made of photoresist on the SiO ₂ film 24. Then, the manufacturing equipment uses the resist pattern RP1 as a mask to perform a dry etching process on the SiO ₂ film 22 with a fluorine-containing gas (e.g., methane trifluoride (CHF ₃ )). As a result, the manufacturing equipment forms a first opening H11 in the SiO ₂ film 24 that penetrates the SiO ₂ film 24 in the thickness direction.

The etching rate of the Al ₂ O ₃ film 22 in dry etching processing using a fluorine-containing gas (e.g., CHF ₃ ) is smaller than that of the SiO ₂ film. In other words, the etching rate of the SiO ₂ film 24 in dry etching processing using a fluorine-containing gas (e.g., CHF ₃ ) is larger than that of the Al ₂ O ₃ film 22. The etching rate is the amount of etching per unit time. Since the etching rate of the Al ₂ O ₃ film 22 in dry etching processing is smaller than that of the SiO ₂ film 24, the Al ₂ O ₃ film 22 functions as an etching stopper. This allows the manufacturing device to control the progress of dry etching so that the surface 12a of the GaN layer 12 is not over-dry-etched.

Next, the manufacturing equipment removes the resist pattern RP1 using acetone (C ₃ H ₆ O). The SiO ₂ film 24 and the Al ₂ O ₃ film 22 are not etched by acetone and remain as they are on the GaN layer 12. Next, the manufacturing equipment performs a first wet etching process on the Al ₂ O ₃ film 22 using the SiO ₂ film 24 in which the first opening H11 is formed as a mask. As a result, as shown in FIG. 3D, the manufacturing equipment forms a second opening H12 in the Al ₂ O ₃ film 22 that communicates with the first opening H11. The second opening H12 penetrates the Al ₂ O ₃ film 22 in the thickness direction.

In the first wet etching _process , a chemical (e.g., TMAH) is used that has a higher etching rate for the _Al2O3 film 22 than for the _SiO2 film 24 and the GaN layer 12. The etching rate of the GaN layer 12 by TMAH is zero or close to zero. This allows the manufacturing device to form the ion implantation mask 25 having a layered structure composed of _{the Al2O3} film 22 and the _SiO2 film 24 while suppressing over-etching of the surface 12a of the GaN layer 12.

Because overetching is suppressed, it is possible to suppress the occurrence of a step at the boundary 13' between the area covered by the ion implantation mask 25 and the area exposed from the ion implantation mask 25 (i.e., the area exposed at the bottom surface of the first opening H11) on the surface 12a of the GaN layer 12. In addition, because overetching is suppressed, it is possible to suppress the occurrence of damage such as defects and interface states on the surface 12a of the GaN layer 12.

Next, as shown in FIG. 3E, the manufacturing device ions-implants Mg into the GaN layer 12 through the first opening H11 and the second opening H12 of the ion implantation mask 25. As a result, an Mg-implanted region 14' is formed in the GaN layer 12. The ion implantation of Mg is performed using an ion implantation mask 25 composed of an Al ₂ O ₃ film 22 and a SiO ₂ film 24, rather than a resist pattern. Therefore, there is no degassing from the resist pattern in the ion implantation process of FIG. 3E, and the carbon element (C) and oxygen element (O) contained in the degassing from the resist pattern are not implanted into the GaN layer 12 together with Mg. As a result, the carbon element (C) concentration and the oxygen element (O) concentration in the Mg-implanted region 14' can be kept low. For example, the average concentration of the carbon element (C) and the average concentration of the oxygen element (O) in the range from the surface (or near the surface) of the Mg-implanted region 14' to the Mg peak position where the amount of Mg implanted in the depth direction is maximum can be set to 1E+16/cm ³ or less.

Next, the manufacturing equipment performs a second wet etching process on the SiO ₂ film 24 to remove the SiO ₂ film 24 from above the Al ₂ O ₃ film 22. In the second wet etching process, a chemical (e.g., a hydrofluoric acid (HF) aqueous solution) having a higher etching rate for the SiO ₂ film 24 than for the GaN layer 12 is used. The etching rate of the GaN layer 12 by the HF aqueous solution is sufficiently smaller than the etching rate of the SiO ₂ film 24 by the HF aqueous solution, and is, for example, zero or a value close to zero. This allows the manufacturing equipment to remove the SiO ₂ film 24 from above the Al ₂ O ₃ film 22 while suppressing over-etching of the surface 12a of the GaN layer 12.

Next, the manufacturing equipment performs a third wet etching process on the Al ₂ O ₃ film 22 to remove the Al ₂ O ₃ film 22 from above the GaN layer 12. In the third wet etching process, a chemical (e.g., TMAH) having a higher etching rate for the Al ₂ O ₃ film 22 than for the GaN layer 12 is used. The etching rate of the GaN layer 12 by TMAH depends on the crystal direction. In this example, the surface (device surface) on which the element structure is formed is the C-plane ((0001) plane). The etching rate of the C-plane of the GaN layer 12 by TMAH is sufficiently smaller than the etching rate of the Al ₂ O ₃ film 22 by TMAH, and is, for example, zero or a value close to zero. This allows the manufacturing equipment to remove the Al ₂ O ₃ film 22 from above the GaN layer 12 while suppressing over-etching of the surface 12a of the GaN layer 12.

Next, the manufacturing equipment performs an annealing process on the entire substrate including the Mg-implanted regions 14' to activate the Mg contained in the Mg-implanted regions 14', thereby forming p-type regions 14 in the GaN layer 12, as shown in FIG.
Thereafter, the manufacturing equipment forms an insulating film 16 (see FIG. 1) on the front surface 12a of the GaN layer 12, and forms an opening H1 (see FIG. 1) in the insulating film 16. Next, the manufacturing equipment forms an anode electrode 18 (see FIG. 1) on the front surface 12a side of the GaN layer 12. Also, before or after the step of forming the anode electrode 18, the manufacturing equipment forms a cathode electrode 20 (see FIG. 1) on the back surface 10b side of the GaN substrate 10. Through the above steps, the pn diode 1 shown in FIG. 1 is completed.

(simulation result)
Fig. 4 is a graph showing the results of an actual measurement (experimental results) of the relationship between the depth from the surface 14a and the carbon element (C) concentration for the p-type region 14 of the pn diode 1 according to the first embodiment of the present invention. The horizontal axis of Fig. 4 indicates the depth [μm] from the surface 14a, and the vertical axis indicates the carbon element (C) concentration [/cm ³ ]. Fig. 5 is a graph showing the results of a simulation of the relationship between the depth from the surface 14a and the oxygen element (O) concentration for the p-type region 14 of the pn diode 1 according to the first embodiment of the present invention. The horizontal axis of Fig. 5 indicates the depth [μm] from the surface 14a, and the vertical axis indicates the oxygen element (O) concentration [/cm ³ ].

4 and 5 show the results of a simulation in which Mg is implanted in multiple stages such that the average Mg concentration in the range from near the surface of the p-type region 14 to the Mg peak position where the amount of Mg implanted in the depth direction is maximum is 1E+18/ ^cm3 . In this simulation, the near the surface of the p-type region 14 is a position 0.2 μm away from the surface 14a in the depth direction. As shown in FIGS. 4 and 5, the range from the surface 14a of the p-type region 14 (i.e., the position at a depth of 0 μm in FIGS. 4 and 5) to 0.2 μm in the depth direction is a region in which the Mg concentration changes significantly depending on the state of the surface 14a, and the value of the Mg concentration is unreliable, so this range was excluded from the calculation of the average concentration.

As shown in Fig. 4, the average concentration of carbon element (C) in the range from the surface vicinity of p-type region 14 (e.g., a position at a depth of 0.2 µm) to the Mg peak position (e.g., 620 nm) was 1E+16/cm3 or less in p-type region ^14. Also, as shown in Fig. 5, the average concentration of oxygen element (O) in the range from the surface vicinity of p-type region 14 (e.g., a position at a depth of 0.2 µm) to the Mg peak position (e.g., 620 nm) was also 1E+16/cm3 or less in p-type region ¹⁴ .
Since the p-type region 14 is formed by Mg ion implantation, it has a concentration profile (Mg profile) in which the Mg concentration changes with depth from the surface 14a, as shown in FIGS.

6 is a graph showing the results of simulating the relationship between the depth from the surface and the carbon element (C) concentration for the p-type region of the pn diode according to Comparative Example 1 of the present invention. The vertical axis of FIG. 6 indicates the depth from the surface [μm], and the vertical axis indicates the carbon element (C) concentration [/cm ³ ]. FIG. 7 is a graph showing the results of simulating the relationship between the depth from the surface and the oxygen element (O) concentration for the p-type region of the pn diode according to Comparative Example 1 of the present invention. The vertical axis of FIG. 7 indicates the depth from the surface [μm], and the vertical axis indicates the oxygen element (O) concentration [/cm ³ ]. The p-type region of Comparative Example 1 is formed by ion implanting Mg using a resist pattern as a mask, not a laminated ion implantation mask.

6 and 7 show the results of a simulation in which Mg is ion-implanted in one step such that the average concentration of Mg in the range from the surface vicinity of the p-type region to the Mg peak position is 1E+19/cm ^3. In this simulation, the surface vicinity of the p-type region is a position 0.2 μm away from the surface in the depth direction. As shown in FIGS. 6 and 7, the average concentrations of carbon element (C) and oxygen element (O) in the range from the surface vicinity of the p-type region to the Mg peak position were each greater than the simulation values in the first embodiment. This is believed to be due to the fact that carbon element (C) and oxygen element (O) contained in the degassing from the resist pattern are implanted into the GaN layer together with Mg ions when Mg is ion-implanted.

8 is a graph showing the results of simulating the relationship between the depth from the surface of the p-type region and the carbon element (C) concentration for the p-type region of the pn diode according to Comparative Example 2 of the present invention. The horizontal axis of FIG. 8 indicates the depth from the surface [μm], and the vertical axis indicates the carbon element (C) concentration [/cm ³ ]. FIG. 9 is a graph showing the results of simulating the relationship between the depth from the surface and the oxygen element (O) concentration for the p-type region of the pn diode according to Comparative Example 2 of the present invention. The horizontal axis of FIG. 9 indicates the depth from the surface [μm], and the vertical axis indicates the oxygen element (O) concentration [/cm ³ ]. As with Comparative Example 1, the p-type region of Comparative Example 2 was also formed by ion implantation of Mg using a resist pattern as a mask.

8 and 9 show the results of a simulation in which Mg is ion-implanted in one step such that the average concentration of Mg in the range from the surface vicinity of the p-type region to the Mg peak position is 3E+18/cm ^3. In this simulation, the surface vicinity of the p-type region is a position 0.2 μm away from the surface in the depth direction. As shown in FIGS. 8 and 9, the average concentration of carbon element (C) and the average concentration of oxygen element (O) in the range from the surface vicinity of the p-type region to the Mg peak position were each greater than the simulation values of the first embodiment. This is believed to be due to the carbon element (C) and oxygen element (O) contained in the degassing from the resist pattern, as in Comparative Example 1.

The numerical values of the simulation results for Figures 4 to 9 are shown in Table 1.

Figure 10 is a diagram showing the results of a simulation of the relationship between reverse voltage and leakage current density for the pn diode 1 according to embodiment 1 of the present invention. Figure 11 is a diagram showing the results of a simulation of the relationship between reverse voltage and leakage current density for the pn diode according to comparative example 1 of the present invention. In each of Figures 10 and 11, the horizontal axis indicates the reverse voltage [V], and the vertical axis indicates the leakage current density [A/cm2]. As can be seen by comparing Figures 10 and 11, the pn diode 1 according to embodiment 1 has a smaller leakage current with respect to the reverse voltage than the pn diode according to comparative example 1.

This is believed to be due to the low average concentration of oxygen element (O) in the p-type region 14, as shown in Table 1. Since oxygen element (O) acts as a donor, the lower the average concentration of oxygen element (O) in the p-type region 14, the higher the effective acceptor concentration. This allows the depletion layer between the p-type region 14 and the n-type GaN layer 12 to expand toward the n-type GaN layer 12. This allows the pn diode 1 to suppress leakage current against reverse voltage and suppress a decrease in the pn junction breakdown voltage.

Another reason is thought to be that overdry etching of the region where Mg is ion-implanted is suppressed in the process shown in FIG. 3C. The p-type region 14 is formed by ion-implanting Mg, but by suppressing overdry etching, damage such as defects and interface states on the surface 14a of the p-type region 14 is suppressed, and charge accumulation due to defects, interface states, etc. is suppressed. This allows the pn diode 1 to suppress leakage current against reverse voltage and suppress a decrease in the pn junction breakdown voltage.

Another reason is thought to be that the step at the boundary 13 between the surface 14a of the p-type region 14, which is an Mg-implanted region, and the surface 12a of the GaN layer 12, which is an Mg-unimplanted region, is suppressed to, for example, 1 nm or less. Because the step is suppressed to 1 nm or less, concentration of the electric field at this step is suppressed when a reverse voltage is applied. This allows the pn diode 1 to suppress leakage current against reverse voltage and suppress a decrease in the pn junction breakdown voltage.

(Effects of the First Embodiment)
As described above, the nitride semiconductor device according to the first embodiment of the present invention includes a pn diode 1. The pn diode 1 includes a GaN layer 12 having a p-type region 14 implanted with a p-type impurity element (e.g., Mg) and a non-implanted region adjacent to the p-type region 14 and into which Mg is not implanted. In the p-type region 14, the average concentration of carbon elements (C) in the range from a surface 14a of the p-type region 14 to an Mg peak position where the amount of Mg implanted is maximum in the depth direction is 1E+16/cm3 or ^less . The step at the boundary 13 between the p-type region 14 implanted with Mg and the non-implanted region is 1 nm or less.

As a result, the concentration of carbon (C), which acts as an acceptor, is kept low in the p-type region 14, suppressing fluctuations in the effective acceptor concentration in the p-type region 14. As a result, the pn diode 1 including the p-type region 14 can suppress fluctuations in the pn junction breakdown voltage. In addition, the step of the boundary 13 is 1 nm or less. Therefore, the pn diode 1 including the boundary 13 can suppress electric field concentration at the step of the boundary 13 when a voltage is applied in the reverse direction, and suppress deterioration of the breakdown voltage.

Furthermore, in the p-type region 14, the average concentration of oxygen (O) in the range from the surface 14a to the Mg peak position may be 1E+16/ ^cm3 or less. Since the concentration of oxygen (O) acting as a donor in the p-type region 14 is kept low, fluctuations in the effective acceptor concentration in the p-type region 14 are further suppressed. This makes it possible to further suppress fluctuations in the pn junction breakdown voltage in the pn diode 1 including the p-type region 14.

The Mg concentration at the Mg peak position may be 1E+16/cm3 ^or more and 1E+21/ ^cm3 or less, or 1E+17/cm3 ^or more and 1E+19/cm3 or ^less . In addition to the above-mentioned Mg concentration range at the Mg peak position, the depth from the surface 12a of the GaN layer 12 to the Mg peak position is preferably 500 nm or more. This makes it easy to ensure the breakdown voltage.

The method for manufacturing the nitride semiconductor device according to the first embodiment of the present invention includes the steps of: forming an Al ₂ O ₃ film 22 on a GaN layer 12; forming a SiO 2 film 24 on the Al ₂ O ₃ film 22, the SiO ₂ film 24 having an etching rate in a dry etching process using a fluorine-containing gas higher than that of the Al ₂ O ₃ film 22; patterning the SiO ₂ film 24 by a dry etching process to form a first opening H11 in the SiO ₂ film 24 penetrating the SiO ₂ film 24 in a thickness direction; performing a first wet etching process on the Al ₂ O ₃ film 22 using the SiO ₂ film 24 in which the first opening H11 is formed as a mask to form a second opening H12 in the Al ₂ O ₃ film 22 communicating with the first opening H11; ion implanting Mg into the GaN layer 12 through the first opening H11 and the second opening H12; The method includes a step of performing a second wet etching process on _{the SiO2} film 24 to remove _{the SiO2 film} 24 from above the _Al2O3 film 22, and a step of performing a third wet etching process on the _Al2O3 film 22 to remove _{the Al2O3 film} 22 from above the gallium nitride layer.

As a result, the manufacturing equipment can suppress overdry etching of the surface of the Mg-implanted region 14' into which Mg ions are implanted, and can suppress damage to the surface of the Mg-implanted region 14', such as the generation of defects and interface states. As a result, the pn diode 1 can suppress an increase in interface state density at the contact interface between the insulating film 16 for element isolation and the p-type region 14, and can suppress the accumulation of charges due to the interface states. As a result, the pn diode 1 can suppress deterioration of the breakdown voltage.

Furthermore, when Mg ions are implanted, a laminated ion implantation mask 25 made up of _{an Al2O3} film 22 and a _SiO2 film 24 is used instead of a resist pattern. This prevents outgassing from the resist pattern during Mg ion implantation, and prevents carbon (C) and oxygen (O) elements contained in the outgas from being implanted into the Mg implanted region 14'. In the GaN layer, C acts as an acceptor and O acts as a donor, but since C and O from the outgas are not implanted during Mg ion implantation, the fluctuation of the effective acceptor concentration in the p-type region 14 can be suppressed.

The etching rate of the _Al2O3 film 22 in the first wet etching process may be greater than that of the _SiO2 film 24 and the gallium nitride layer. The etching rate of the _SiO2 film 24 in the second wet etching process may be greater than that of the GaN layer 12. The etching rate of the _Al2O3 film 22 in the _{third wet} etching process may be greater than that of the GaN layer 12.
This makes it possible to prevent over-etching of surface 14a of p-type region 14. It is possible to reduce the step at boundary 13 between p-type region 14, which is an Mg-implanted region, and a non-Mg-implanted region adjacent to p-type region 14, and for example, the step at boundary 13 can be set to 1 nm or less.

<Embodiment 2>
In the above embodiment 1, the case where the present invention is applied to a pn diode has been described. However, the application of the present invention is not limited to a pn diode. The present invention may also be applied to a vertical MOSFET.

(composition)
12 is a cross-sectional view showing a configuration example of a nitride semiconductor device according to the second embodiment of the present invention. As shown in FIG. 12, the nitride semiconductor device according to the second embodiment includes a planar gate structure vertical MOSFET 2 (one example of the "vertical MOSFET" of the present invention). The vertical MOSFET 2 includes a GaN substrate 10, an n-type GaN layer 12 provided on the front surface 10a of the GaN substrate 10, a p-type region 14 provided in the GaN layer 12, an n+ type source region 30 provided in the p-type region 14, an insulating film 32 for element isolation provided on the front surface 12a of the GaN layer 12, a gate insulating film 34 provided on the front surface 12a of the GaN layer 12, a gate electrode 36 provided on the gate insulating film 34, a source electrode 38 provided on the front surface 12a of the GaN layer 12 and connected to the n+ type source region 30 and the p-type region 14, and a drain electrode 40 provided on the rear surface 10b of the GaN substrate 10. In this example, the n-type GaN layer 12 functions as a drift region, and the p-type region 14 functions as a well region.

The source region 30 is provided on the surface 14a side of the p-type region 14. The source region 30 is formed by ion-implanting an n-type impurity such as Si (silicon) to a predetermined depth from the surface 14a of the p-type region 14, and then performing a heat treatment.
The insulating film 32 is made of, for example, a _SiO2 film. An opening H2 is provided in the insulating film 32. The p-type region 14 and the source region 30 are exposed at the bottom surface of the opening H2. The source electrode 38 is connected to the p-type region 14 and the source region 30 through the opening H2. As a result, the potential of the p-type region 14 is fixed to the potential of the source electrode 38.

The gate insulating film 34 is made of, for example, a _SiO2 film or an _aluminum oxide film ( _Al2O3 film). The gate electrode 36, the source electrode 38, and the drain electrode 40 are made of, for example, Al, an Al alloy (for example, a Ti-Al alloy), Ni, or a Ni alloy (for example, a Ni-Au alloy). The gate electrode 36 may be made of polysilicon doped with impurities (pOly-Si), or the like.

The channel region of the vertical MOSFET 2 with a planar gate structure is located between the n-type GaN layer 12, which is a region where Mg is not injected, and the n ⁺ -type source region 30, and is formed in a region facing the gate electrode 36 via the gate insulating film 34. The on-current of the vertical MOSFET 2 flows from the drain electrode 40 through the GaN substrate 10, the GaN layer 12, the channel region, and the source region 30 to the source electrode 38.

(Production method)
Next, a method for manufacturing the vertical MOSFET 2 shown in Fig. 12 will be described. Fig. 13A to Fig. 13F are cross-sectional views showing the process steps of a method for manufacturing the vertical MOSFET 2 according to the second embodiment of the present invention. The vertical MOSFET 2 is manufactured using various manufacturing equipment such as a film formation equipment (including an epitaxial growth equipment, a CVD equipment, a sputtering equipment, and a resist coating equipment), an exposure equipment, an ion implantation equipment, an annealing equipment, and an etching equipment.

In Fig. 13A, the process up to the step of forming the SiO ₂ film is the same as the manufacturing method of the pn diode 1 described in the first embodiment (see Figs. 3A and 3B). After the SiO ₂ film 24 is formed, the manufacturing equipment forms a resist pattern RP2 on the SiO ₂ film 24. Then, the manufacturing equipment performs a dry etching process on the SiO ₂ film 22 using a fluorine-containing gas (e.g., methane trifluoride (CHF ₃ )) using the resist pattern RP2 as a mask. As a result, the manufacturing equipment forms a first opening H11 in the SiO ₂ film 24 that penetrates the SiO ₂ film 24 in the thickness direction.

As described in the first embodiment, the etching rate of the dry etching process is smaller for the Al ₂ O ₃ film 22 than for the SiO ₂ film 24, and the Al ₂ O ₃ film 22 functions as an etching stopper. Therefore, in the step of forming the first opening H11, the manufacturing equipment can control the progress of the dry etching so that the surface 12 a of the GaN layer 12 is not over-dry-etched.

Next, the manufacturing equipment removes the resist pattern RP2 using acetone (C ₃ H ₆ O). Next, the manufacturing equipment performs a first wet etching process on the Al ₂ O ₃ film 22 using the SiO ₂ film 24 in which the first opening H11 is formed as a mask. As a result, as shown in FIG. 13B, the manufacturing equipment forms a second opening H12 in the Al ₂ O ₃ film 22 that communicates with the first opening H11. As in the first embodiment, the first wet etching process uses a chemical (e.g., TMAH) in which the etching rate of the Al ₂ O ₃ film 22 is greater than that of the SiO ₂ film 24 and the GaN layer 12. As a result, the manufacturing equipment can form an ion implantation mask 25 having a stacked structure composed of the Al ₂ O ₃ film 22 and the SiO ₂ film 24 while suppressing over-etching of the surface 12a of the GaN layer 12.

Next, as shown in Fig. 13C, the manufacturing equipment ions-implants Mg into the GaN layer 12 through the first opening H11 and the second opening H12 of the ion implantation mask 25. As a result, an Mg-implanted region 14' is formed in the GaN layer 12. Since the ion implantation of Mg is performed using the _ion implantation mask 25 composed of the _Al2O3 film 22 and the _SiO2 film 24, rather than the resist pattern, there is no outgassing from the resist pattern. Since it is possible to prevent the carbon element (C) and the oxygen element (O) contained in the outgassing from the resist pattern from being implanted into the GaN layer 12 together with Mg, it is possible to suppress the carbon element (C) concentration and the oxygen element (O) concentration in the Mg-implanted region 14' to be low.

Next, the manufacturing equipment performs a second wet etching process on the SiO ₂ film 24 to remove the SiO ₂ film 24 from above the Al ₂ O ₃ film 22. As in the first embodiment, the second wet etching process uses a chemical solution (e.g., a hydrofluoric acid (HF) aqueous solution) that has a higher etching rate for the SiO ₂ film 24 than for the GaN layer 12. This allows the manufacturing equipment to remove the SiO ₂ film 24 from above the Al ₂ O ₃ film 22 while suppressing over-etching of the surface 12a of the GaN layer 12.

Next, the manufacturing equipment performs a third wet etching process on the Al ₂ O ₃ film 22 to remove the Al ₂ O ₃ film 22 from above the GaN layer 12. As in the first embodiment, the third wet etching process uses a chemical (e.g., TMAH) that has a higher etching rate for the Al ₂ O ₃ film 22 than for the GaN layer 12. This allows the manufacturing equipment to remove the Al ₂ O ₃ film 22 from above the GaN layer 12 while suppressing over-etching of the surface 12a of the GaN layer 12.
Next, the manufacturing equipment performs an annealing process on the entire substrate including the Mg-implanted regions 14' to activate the Mg contained in the Mg-implanted regions 14', thereby forming p-type regions 14 in the GaN layer 12, as shown in FIG.

Next, as shown in FIG. 13E, the manufacturing equipment forms a resist pattern RP3 on the GaN layer 12. Then, the manufacturing equipment uses the resist pattern RP3 as a mask to ion-implant n-type impurities such as Si into the p-type region 14. This forms a Si-implanted region 30' in the p-type region 14. Next, the manufacturing equipment removes the resist pattern RP3 using acetone (C ₃ H ₆ O). Next, the manufacturing equipment performs an annealing process on the entire substrate including the Si-implanted region 30' to activate the Si contained in the Si-implanted region 30'. This forms a source region 30 as shown in FIG. 13F.

Then, the manufacturing equipment forms an insulating film 32 for element isolation and a gate insulating film 34 on the surface 12a of the GaN layer 12. Next, the manufacturing equipment forms a gate electrode 36 (see FIG. 12) on the gate insulating film 34. Next, the manufacturing equipment forms a source electrode 38 (see FIG. 12) on the surface 12a side of the GaN layer 12. Also, before or after the process of forming the source electrode 38, the manufacturing equipment forms a drain electrode 40 (see FIG. 12) on the back surface 10b side of the GaN substrate 10. Through the above processes, the planar gate structure vertical MOSFET 2 shown in FIG. 12 is completed.

(Effects of the Second Embodiment)
As described above, the nitride semiconductor device according to the second embodiment of the present invention includes a vertical MOSFET 2 having a planar gate structure. The vertical MOSFET 2 includes a GaN layer 12 having a p-type region 14 implanted with a p-type impurity element (e.g., Mg) and a non-implanted region adjacent to the p-type region 14 and not implanted with Mg. In the p-type region 14, the average concentration of carbon elements (C) in the range from the surface 14a to the Mg peak position is 1E+16/ ^cm3 or less. The step at the boundary 13 between the p-type region 14 implanted with Mg and the n-type GaN layer 12, which is the non-implanted region of Mg, is 1 nm or less.

According to this, the concentration of carbon (C) acting as an acceptor in the p-type region 14 is kept low, so that the fluctuation of the effective acceptor concentration in the p-type region 14 is suppressed. A channel is formed in the p-type region 14. Therefore, the vertical MOSFET 2 can suppress the fluctuation of the effective acceptor concentration in the channel region, and can suppress the fluctuation of the threshold voltage Vth. Furthermore, since the fluctuation of the effective acceptor concentration in the p-type region 14 is suppressed, the vertical MOSFET 2 can suppress the fluctuation of the pn junction breakdown voltage between the p-type region 14 and the n-type GaN layer 12, which is a region not implanted with Mg.
In addition, the step of the boundary 13 is 1 nm or less. Therefore, the vertical MOSFET 2 including the boundary 13 can suppress electric field concentration at the step of the boundary 13 when a voltage is applied in the reverse direction, and can suppress deterioration of the breakdown voltage.

Also in the method for manufacturing a nitride semiconductor device according to the second embodiment of the present invention, similarly to the first embodiment, the manufacturing apparatus can suppress over-dry etching of the surface of the Mg-implanted region 14' into which Mg is ion-implanted, and can suppress damage to the surface of the Mg-implanted region 14', such as the generation of defects (e.g., donor-type defects) and interface states. This allows the vertical MOSFET 2 to suppress an increase in the interface state density of the p-type region 14 in which a channel is formed. For example, by suppressing the above-mentioned over-dry etching, the interface state density of the contact interface between the p-type region 14 and the gate insulating film 34 can be suppressed to the order of 1E+10 cm ^-2 /eV. This allows the vertical MOSFET 2 to suppress a decrease in mobility.

In addition, by suppressing overdry etching and the occurrence of donor defects as described above, it is possible to suppress the decrease in the effective acceptor concentration in the p-type region 14. As a result, the vertical MOSFET 2 can suppress the decrease in the threshold voltage Vth.

<Embodiment 3>
In the above-described second embodiment, the case has been described in which the nitride semiconductor device according to the embodiment of the present invention includes the vertical MOSFET 2 having a planar gate structure. However, in the embodiments of the present invention, the vertical MOSFET included in the nitride semiconductor device is not limited to the planar gate structure. The vertical MOSFET may have a trench gate structure.

Figure 14 is a cross-sectional view showing an example of the configuration of a nitride semiconductor device according to embodiment 3 of the present invention. As shown in Figure 14, the nitride semiconductor device according to embodiment 3 includes a vertical MOSFET 3 with a trench gate structure (one example of the "vertical MOSFET" of the present invention). The vertical MOSFET 3 with a trench gate structure has a trench H3 provided in the GaN layer 12. The trench H3 opens on the surface 12a side of the GaN layer 12. The depth of the trench H3 is greater than the thickness of the GaN layer 12. The side surface of the trench H3 faces the source region 30 and the p-type region 14, and the bottom surface of the trench H3 faces the n-type GaN layer 12.

Arranged inside the trench H3 are a gate insulating film 34 and a gate electrode 60. The side and bottom surfaces of the trench H3 are covered with the gate insulating film 34, and the gate electrode 36 is buried in the trench H3 with the gate insulating film 34 interposed therebetween.
In the vertical MOSFET 3 with a trench gate structure, a channel is formed in the p-type region 14, which is located between the n-type GaN layer 12, which is a non-implanted region, and the n ⁺ -type source region 30, and which faces the gate electrode 36 via the gate insulating film 34. The on-current of the vertical MOSFET 3 flows from the drain electrode 40 through the GaN substrate 10, the GaN layer 12, the channel region, and the source region 30 to the source electrode 38. The source electrode 38 is connected not only to the source region 30 but also to the p-type region 14. As a result, the potential of the p-type region 14 is fixed to the potential of the source electrode 38.

The nitride semiconductor device according to the third embodiment of the present invention has the same effects as the nitride semiconductor device according to the second embodiment.

<Other embodiments>
As described above, the present invention has been described by the embodiments and modifications, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure.
For example, a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, or a silicon nitride (SiN) film can be used for the gate insulating film 34. A composite film in which several single-layer insulating films are stacked can also be used for the gate insulating film 34. A MOSFET using an insulating film other than a _SiO2 film as the gate insulating film 34 may be called a MISFET. MISFET refers to a more comprehensive insulated gate transistor that includes a MOSFET.

In the above embodiment, the first conductivity type is p-type and the second conductivity type is n-type. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being n-type and the second conductivity type being p-type.
In the above embodiment, magnesium (Mg) is used as the "impurity element of first conductivity type" of the present invention. However, instead of Mg, beryllium (Be), silicon (Si) or germanium (Ge) may be used, or oxygen element (O) may be used.
In the above embodiment, aluminum oxide (Al ₂ O ₃ ) is used as the “first inorganic material film” of the present invention, but hafnium oxide (HfO ₂ ), aluminum nitride (AlN) or silicon nitride (SiN) may be used instead of Al ₂ O ₃ .

As such, the present invention naturally includes various embodiments not described here. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of the above-mentioned embodiments and each modified example. Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present. The technical scope of the present invention is determined only by the invention-specific matters related to the scope of the claims that are appropriate from the above explanation.

1 pn diode 2, 3 vertical MOSFET
10 GaN substrate 10a, 12a, 14a Surface 10b Back surface 12 GaN layer 13 Boundary 14 p-type region 14' Mg-implanted region 16, 32 Insulating film 18 Anode electrode 20 Cathode electrode 22 _Al2O3 film 24 _SiO2 film 25 Ion implantation mask 30 Source region 30 _' Si-implanted region 34 Gate insulating film 36 Gate electrode 38 Source electrode 40 Drain electrode 60 Gate electrode H1, H2 Opening H2 Opening H3 Trench H11 First opening H12 Second opening RP1, RP2, RP3 Resist pattern

Claims (15)

an implantation region into which an impurity element of a first conductivity type is implanted;
a non-implanted region adjacent to the implanted region and into which the impurity element is not implanted;
a gallium nitride layer having
In the implantation region, the average concentration of carbon element (C) in the range from the surface of the implantation region to a peak position where the implantation amount of the impurity element is maximum in the depth direction is 1E+16/ ^cm3 or less;
The nitride semiconductor device has a step of 1 nm or less at a boundary between the implanted region and the non-implanted region. 2 . The nitride semiconductor device according to claim 1 , wherein an average concentration of oxygen elements (O) in the range from said surface to said peak position in said implanted region is 1E+16/cm ³ or less. an implantation region into which an impurity element of a first conductivity type is implanted;
a non-implanted region adjacent to the implanted region and into which the impurity element is not implanted;
a gallium nitride layer having
In the implantation region, the average concentration of oxygen (O) in the range from the surface of the implantation region to a peak position where the implantation amount of the impurity element is maximum in the depth direction is 1E+16/ ^cm3 or less;
The nitride semiconductor device has a step of 1 nm or less at a boundary between the implanted region and the non-implanted region. The nitride semiconductor device according to any one of claims 1 to 3, wherein the depth from the surface of the gallium nitride layer to the peak position is 500 nm or more. The nitride semiconductor device according to claim 1 , wherein a concentration of said impurity element at said peak position is not less than 1E+16/cm ³ and not more than 1E+21/cm ³ . The nitride semiconductor device according to claim 1 , wherein a concentration of said impurity element at said peak position is not less than 1E+17/cm ³ and not more than 1E+19/cm ³ . The nitride semiconductor device according to claim 1 , wherein a concentration of said impurity element in said surface is not less than 1E+16/cm ³ and not more than 1E+18/cm ³ . The nitride semiconductor device according to any one of claims 1 to 7, wherein the impurity element is magnesium (Mg), beryllium (Be), silicon (Si) or germanium (Ge). The nitride semiconductor device according to any one of claims 1, 4 to 8, wherein the impurity element is oxygen (O). the conductivity type of the implantation region is a first conductivity type;
the non-implanted region has a second conductivity type;
The nitride semiconductor device according to claim 1 , further comprising a diode formed by the implanted region and the non-implanted region. the conductivity type of the implantation region is a first conductivity type;
the non-implanted region has a second conductivity type;
The nitride semiconductor device according to claim 1 , comprising a vertical MOSFET of a planar gate structure, in which a channel is formed in the implantation region. the conductivity type of the implantation region is a first conductivity type;
the non-implanted region has a second conductivity type;
The nitride semiconductor device according to claim 1 , comprising a vertical MOSFET having a trench gate structure, in which a channel is formed in the implantation region. forming a first inorganic material film on the gallium nitride layer;
forming a second inorganic material film on the first inorganic material film, the second inorganic material film having an etching rate in a dry etching process using a fluorine-containing gas higher than that of the first inorganic material film;
patterning the second inorganic material film by the dry etching process to form a first opening in the second inorganic material film, the first opening penetrating the second inorganic material film in a thickness direction;
a step of performing a first wet etching process on the first inorganic material film using the second inorganic material film in which the first opening is formed as a mask to form a second opening in the first inorganic material film, the second opening communicating with the first opening;
ion-implanting an impurity element of a first conductivity type into the gallium nitride layer through the first opening and the second opening;
a step of performing a second wet etching process on the second inorganic material film to remove the second inorganic material film from above the first inorganic material film;
and performing a third wet etching process on the first inorganic material film to remove the first inorganic material film from above the gallium nitride layer. an etching rate of the first wet etching process is greater for the first inorganic material film than for the second inorganic material film and than for the gallium nitride layer;
an etching rate of the second wet etching process is greater for the second inorganic material film than for the gallium nitride layer;
The method for manufacturing a nitride semiconductor device according to claim 13 , wherein an etching rate in said third wet etching process is higher for said first inorganic material film than for said gallium nitride layer. the first inorganic material film is aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), aluminum nitride (AlN) or silicon nitride (SiN);
The method for manufacturing a nitride semiconductor device according to claim 13 or 14, wherein the second inorganic material film is silicon oxide (SiO ₂ ).

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