JP7515766B2 - Digital Transmitter - Google Patents

Description

The present disclosure relates to a digital transmitter.

The digital transmitter described in Non-Patent Document 1 directly converts a baseband frequency band modulated signal generated by a modem or the like into a high frequency band and transmits the signal by delta-sigma modulation using a delta-sigma modulation circuit. This allows the digital transmitter to realize the transmission using an inexpensive, general-purpose IC, for example, an FPGA (Field-Programmable Gate Array). As a clock generation circuit that drives the delta-sigma modulation circuit, for example, the PLL (Phase Lock Loop) circuit inside the FPGA is used.

Takashi Maehata, Kazuyuki Totani, Taku Kameda, and Noriharu Suematsu, "Development of Elemental Technologies for 1-bit Digital RF Transmitter," IEICE Technical Report, vol.113, no.57, SR2013-2, pp.9-15, May 2013.

However, if the phase noise of the above-mentioned PLL circuit is large, the phase noise of the digital modulated signal delta-sigma modulated by the above-mentioned delta-sigma modulation circuit also becomes large, resulting in a degradation of the signal-to-noise ratio of the signal transmitted from the above-mentioned digital transmitter, i.e., a degradation of communication quality.

The object of the present disclosure is to provide a digital transmitter that can suppress degradation of the signal-to-noise ratio of a signal transmitted from the digital transmitter.

In order to solve the above-mentioned problems, the digital transmitter of the present disclosure includes a clock generation circuit that generates a clock, a delta-sigma modulation circuit that generates a first delta-sigma modulated signal by performing delta-sigma modulation on a digitally modulated signal based on the clock, a distribution circuit that distributes the first delta-sigma modulated signal into a plurality of second delta-sigma modulated signals, a plurality of reproduction circuits that retime the plurality of second delta-sigma modulated signals, and a synthesis circuit that synthesizes the retimed plurality of second delta-sigma modulated signals output from the plurality of reproduction circuits, wherein the loop bandwidth of the plurality of reproduction circuits is equal to or less than the loop bandwidth of the clock generation circuit, and the distribution circuit performs the distribution so that the plurality of second delta-sigma modulated signals are in phase at the carrier frequency, or the synthesis circuit performs the synthesis so that the plurality of retimed second delta-sigma modulated signals are in phase at the carrier frequency.

The digital transmitter of the present disclosure can suppress degradation of the signal-to-noise ratio of the signal transmitted from the digital transmitter.

2 shows the configuration of a digital transmitter DS according to the first embodiment. 2A shows an example of a characteristic between the detuning frequency and the phase noise of the first embodiment (before in-phase synthesis), and FIG 2B shows an example of a characteristic between the detuning frequency and the phase noise of the first embodiment (after in-phase synthesis). 3A shows an example of a characteristic between the detuning frequency and the phase noise of the first modification (before in-phase synthesis), and FIG 3B shows an example of a characteristic between the detuning frequency and the phase noise of the first modification (after in-phase synthesis). 1 shows a configuration of a cascade-connected series resonant circuit 101 that constitutes the in-phase distribution circuit 2 and the in-phase combining circuit 4 of the second modified example. 1 shows a configuration of an in-phase distribution circuit 2 according to a second modified example. 1 shows a configuration of an in-phase combining circuit 4 according to a second modified example. 1 shows the configuration of a digital transmitter DS according to a second embodiment. 13 shows the configuration of a modified digital transmitter DS. 13 shows the configuration of a digital transmitter DS according to a third embodiment.

An embodiment of a digital transmitter according to the present disclosure is described below.

Embodiment 1.
First Embodiment
The digital transmitter DS of the first embodiment will be described.

Configuration and Operation of First Embodiment
FIG. 1 shows the configuration of a digital transmitter DS according to the first embodiment.

As shown in FIG. 1, the digital transmitter DS of embodiment 1 includes a modulated signal output circuit 1, an in-phase distribution circuit 2, a CDR circuit unit 3, an in-phase combining circuit 4, an amplifier 5, a filter 6, and an antenna 7.

The clock generation circuit 1A corresponds to a "clock generation circuit", the ΔΣ modulation circuit 1C corresponds to a "delta sigma modulation circuit", the in-phase distribution circuit 2 corresponds to a "distribution circuit", the CDR circuit unit 3 corresponds to a "regeneration circuit", and the in-phase synthesis circuit 4 corresponds to a "synthesis circuit".

As shown in Fig. 1, the modulated signal output circuit 1 has a clock generation circuit 1A, a modem 1B, and a ΔΣ modulation circuit 1C. The clock generation circuit 1A has a conventionally known PLL circuit PK (not shown) and generates a clock CL. The modem 1B generates a digitally modulated signal DG (e.g., multi-bit) by digitally modulating the communication data TD to be transmitted based on the clock CL. The ΔΣ modulation circuit 1C generates a ΔΣ modulation signal DL (e.g., 1 bit) by delta-sigma modulating the digitally modulated signal DG based on the clock CL.

The in-phase distribution circuit 2 is, for example, a Wilkinson-type in-phase distribution circuit. The in-phase distribution circuit 2 distributes the ΔΣ modulated signal DL output from the ΔΣ modulation circuit 1C to the CDR circuits 3(1) to 3(n) (n is an integer equal to or greater than 2) in the CDR circuit unit 3 so that the multiple ΔΣ modulated signals DL after distribution are in phase at one (same) carrier frequency (RF frequency).

CDR circuits 3(1) to 3(n) are each composed of a PLL circuit (not shown). The PLL circuit includes, for example, a phase comparison circuit, a phase synchronization loop filter, and a voltage-controlled oscillator. CDR circuits 3(1) to 3(n) perform so-called retiming of the ΔΣ modulated signal DL distributed by the in-phase distribution circuit 2, and more specifically, generate a reproduced clock signal by extracting a clock component from the multiple ΔΣ modulated signals DL using the above-mentioned PLL circuit, and retime the multiple ΔΣ modulated signals DL using the reproduced clock signal. Here, CDR circuits 3(1) to 3(n) perform the same operations as each other.

The in-phase synthesis circuit 4 is, for example, a Wilkinson-type in-phase synthesis circuit. The in-phase synthesis circuit 4 synthesizes the multiple ΔΣ modulated signals DL output from the CDR circuits 3(1) to 3(n) so that the multiple ΔΣ modulated signals DL retimed by the CDR circuits 3(1) to 3(n) are in-phase at one (same) carrier frequency (RF frequency).

The amplifier 5 amplifies the ΔΣ modulated signal DL combined by the in-phase combining circuit 4. The filter 6 filters the ΔΣ modulated signal DL amplified by the amplifier 5, i.e., suppresses quantization noise and unwanted waves. The antenna 7 transmits the ΔΣ modulated signal DL filtered by the filter 6, i.e., radiates it into space.

Figure 2 shows an example of the characteristics between detuning frequency and phase noise in embodiment 1.

The phase noise of the ΔΣ modulation circuit 1C is dominated by the phase noise of the clock generation circuit 1A, more specifically, by the phase noise of the above-mentioned PLL circuit PK of the clock generation circuit 1A, and therefore the noise level is high, as shown by the dotted line in Figure 2A.

As described above, the ΔΣ modulated signal DL output from the ΔΣ modulation circuit 1C is retimed by the CDR circuits 3(1) to 3(n). If the loop bandwidth of the CDR circuits 3(1) to 3(n) is the same as the loop bandwidth of the PLL circuit PK inside the clock generation circuit 1A, the phase noise of the CDR circuits 3(1) to 3(n) will be equivalent to the phase noise of the ΔΣ modulation circuit 1C, as shown by the solid line in FIG. 2A.

As described above, the multiple ΔΣ modulated signals DL output from the CDR circuits 3(1) to 3(n) are in-phase combined by the in-phase combining circuit 4. The ΔΣ modulated signals DL within the loop band output from the CDR circuits 3(1) to 3(n) are in-phase with each other, so are voltage-added. In contrast, the noise outside the loop band of the CDR circuits 3(1) to 3(n) is uncorrelated with each other, so is power-added instead of voltage-added as described above. As a result, the phase noise of the CDR circuits 3(1) to 3(n) is reduced compared to the phase noise of the ΔΣ modulated circuit 1C (shown by the solid lines in FIG. 2A and FIG. 2B), as shown by the solid lines in FIG. 2B. Specifically, the power of the noise is reduced by 3 dB in 2-combination (when combining two signals) and by 6 dB in 4-combination (when combining four signals) compared to the power of the signal.

Effects of the First Embodiment
As described above, in the digital transmitter DS of embodiment 1, the in-phase combining circuit 4 performs voltage addition on multiple ΔΣ modulated signals DL that are output from CDR circuits 3(1) to 3(n) and are within the loop band and are in-phase with each other, and in contrast, performs power addition on multiple noise signals that are output from CDR circuits 3(1) to 3(n) and are outside the loop band and are uncorrelated with each other.

This results in a smaller increase in noise power compared to an increase in carrier power (signal power). As a result, the phase noise of the ΔΣ modulated signal DL after in-phase synthesis can be improved compared to the phase noise of the ΔΣ modulated signal DL output without voltage addition and power addition under the in-phase synthesis described above.

It is sufficient if either the in-phase distribution circuit 2 or the in-phase combination circuit 4 has a configuration for ensuring the in-phase function (shown in Figures 4 to 6); in other words, it is not necessary for both the in-phase distribution circuit 2 and the in-phase combination circuit 4 to have a configuration for ensuring the above-mentioned in-phase function.

<Variation 1>
FIG. 3 shows an example of the characteristics between the detuning frequency and the phase noise in the first modification.

In embodiment 1, as shown in FIG. 2A, the loop bandwidth of CDR circuit 3(1) to CDR circuit 3(n) is the same as the loop bandwidth of the ΔΣ modulation circuit 1C.

In the first modification, unlike the above, as shown in FIG. 3A, the loop band of the CDR circuits 3(1) to 3(n) is narrower than the loop band of the ΔΣ modulation circuit 1C. Here, generally, the phase noise outside the loop band of the CDR circuits 3(1) to 3(n) is better than the phase noise outside the loop band of the clock generation circuit 1A. Therefore, in the first modification, the phase noise within the loop band of the CDR circuits 3(1) to 3(n) is the same as the phase noise within the loop band of the clock generation circuit 1A, but the phase noise outside the loop band of the CDR circuits 3(1) to 3(n) is improved compared to the phase noise outside the loop band of the clock generation circuit 1A.

Furthermore, by the in-phase combining circuit 4 in-phase combining the multiple ΔΣ modulated signals DL output from the CDR circuits 3(1) to 3(n), as shown in FIG. 3B, the phase noise outside the loop band of the in-phase combining circuit 4 is improved in the same manner as the phase noise outside the loop band of the in-phase combining circuit 4 shown in FIG. 2B.

From the above, it can be said that it is desirable for the loop bandwidth of CDR circuit 3(1) to CDR circuit 3(n) to be less than the loop bandwidth of clock generation circuit 1A.

<Modification 2>
FIG. 4 shows a configuration of a cascade-connected series resonant circuit 101 that constitutes the in-phase distribution circuit 2 and the in-phase combining circuit 4 of the second modification.

Figure 5 shows the configuration of the in-phase distribution circuit 2 of variant example 2.

Figure 6 shows the configuration of the in-phase synthesis circuit 4 of variant example 2.

Configuration of the cascaded series resonant circuit 101
The in-phase distribution circuit 2 and the in-phase combination circuit 4 (both circuits are shown in FIG. 1) may be configured by a cascaded series resonant circuit 101 as shown in FIG. 4. The cascaded series resonant circuit 101 is, for example, made up of series resonant circuits 102(1) to 102(4) connected in cascade with each other, and each series resonant circuit 102 includes a capacitor and an inductor.

<Configuration of in-phase distribution circuit 2>
In the in-phase distribution circuit 2 shown in FIG. 5 and composed of a cascaded series resonant circuit 101, the values of the capacitors and the inductors are set so that the resonant frequencies of the series resonant circuits 102(1) to 102(4) are identical to the carrier frequency of the ΔΣ modulated signal DL.

In addition to the above, as shown in FIG. 5, the output terminal of the ΔΣ modulation circuit 1C (shown in FIG. 1) is connected to the terminal TA of the cascaded series resonant circuit 101, and the input terminals of the CDR circuits 3(1) to 3(5) (assuming n=5) are connected to the terminals TB1 to TB5 of the cascaded series resonant circuit 101.

With the above-mentioned configuration, the ΔΣ modulated signals DL at both ends of the series resonant circuits 102(1) to 102(4) are in phase, and therefore multiple in-phase ΔΣ modulated signals DL are output to CDR circuits 3(1) to 3(5).

<Configuration of in-phase synthesis circuit 4>
In the in-phase synthesis circuit 4 shown in FIG. 6 and composed of a cascaded series resonant circuit 101, the values of the capacitors and the inductors are set so that the resonant frequencies of the series resonant circuits 102(1) to 102(4) are identical to the carrier frequency of the ΔΣ modulated signal DL.

In addition to the above, as shown in FIG. 6, CDR circuits 3(1) to 3(5) (assuming n=5) are connected to terminals TB1 to TB5 of the cascaded series resonant circuit 101, and the input terminal of amplifier 5 (shown in FIG. 1) is connected to terminal TA of the cascaded series resonant circuit 101.

With the above-mentioned configuration, the ΔΣ modulated signals DL at both ends of the series resonant circuits 102(1) to 102(4) are in phase, so that the multiple ΔΣ modulated signals DL from the CDR circuits 3(1) to 3(5) are combined in phase, and the combined ΔΣ modulated signals DL in phase are output to the amplifier 5.

Embodiment 2.
Second Embodiment
The digital transmitter DS of the second embodiment will be described.

Configuration of Second Embodiment
FIG. 7 shows the configuration of a digital transmitter DS according to the second embodiment.

The digital transmitter DS of the second embodiment, like the digital transmitter DS of the first embodiment (shown in FIG. 1), includes a modulated signal output circuit 1, an in-phase distribution circuit 2, and a CDR circuit unit 3. On the other hand, the digital transmitter DS of the second embodiment differs from the digital transmitter DS of the first embodiment in that it includes an amplifier unit 11, a filter unit 12, and an antenna unit 13 instead of the in-phase synthesis circuit 4, amplifier 5, and filter 6 of the first embodiment.

As shown in FIG. 7, the amplifier unit 11 has amplifiers 11(1) to 11(n), the filter unit 12 has filters 12(1) to 12(n), and the antenna unit 13 has antennas 13(1) to 13(n).

<Operation of the Second Embodiment>
The operation of the digital transmitter DS of the second embodiment will be described.

In the digital transmitter DS of embodiment 2, the modulated signal output circuit 1 to the CDR circuit unit 3 operate in the same manner as the modulated signal output circuit 1 to the CDR circuit unit 3 of embodiment 1. As a result, a plurality of distributed and retimed ΔΣ modulated signals DL are output from the CDR circuit 3(1) to CDR circuit 3(n) in the CDR circuit unit 3 to the amplifiers 11(1) to 11(n) in the amplifier unit 11.

Amplifiers 11(1) to 11(n) amplify the multiple ΔΣ modulated signals DL, filters 12(1) to 12(n) filter the amplified multiple ΔΣ modulated signals DL, and antennas 13(1) to 13(n) radiate the filtered multiple ΔΣ modulated signals DL into space.

The multiple ΔΣ modulated signals DL radiated from the multiple antennas 13(1) to 13(n) are combined in space. The multiple ΔΣ modulated signals DL radiated from the multiple antennas 13(1) to 13(n) within the loop band of the CDR circuits 3(1) to 3(n) are voltage-added because their carrier powers (signal powers) are in phase with each other. On the other hand, the phase noise outside the loop band of the CDR circuits 3(1) to 3(n) is uncorrelated with each other, so it is power-added rather than voltage-added. This makes it possible to improve the phase noise of the ΔΣ modulated signal DL output from the digital transmitter DS, as in the first embodiment.

Effects of the Second Embodiment
As described above, in the digital transmitter DS of embodiment 2, multiple ΔΣ modulated signals DL radiated into space from antennas 13(1) to 13(n) are combined in space, and the phase noise outside the loop band of CDR circuits 3(1) to 3(n) is voltage-added, making it possible to improve the phase noise of the combined ΔΣ modulated signal DL.

In addition to the above effects, in embodiment 2, multiple ΔΣ modulated signals DL radiated from antennas 13(1) to 13(n) are combined in space, making it possible to eliminate the need for the in-phase combining circuit 4 (shown in Figure 1) required in the digital transmitter DS of embodiment 1.

<Modification>
FIG. 8 shows the configuration of a modified digital transmitter DS.

As shown in Fig. 8, the digital transmitter DS of the modified example includes, similarly to embodiment 2, a modulated signal output circuit 1, an in-phase distribution circuit 2, an amplifier unit 11, a filter unit 12, and an antenna unit 13. On the other hand, as shown in Fig. 8, the digital transmitter DS of the modified example differs from embodiment 2 in that it further includes a variable delay circuit unit 21.

The variable delay circuit unit 21 has variable delay circuits 21(1) to 21(n) as shown in FIG. 8.

The variable delay circuits 21(1) to 21(n) adjust the delay amount of the ΔΣ modulated signal DL output from the CDR circuit 3(1) to CDR circuit 3(n). For example, the variable delay circuit 21(1) adjusts the delay amount of the ΔΣ modulated signal DL output from the CDR circuit 3(1), the variable delay circuit unit 21(2) adjusts the delay amount of the ΔΣ modulated signal DL output from the CDR circuit 3(2), and the variable delay circuit unit 21(n) adjusts the delay amount of the ΔΣ modulated signal DL output from the CDR circuit 3(n). As a result, the digital transmitter DS of the modified example can combine multiple ΔΣ modulated signals DL radiated from the antennas 13(1) to 13(n) in the desired direction in phase as a phased array antenna.

In a modified digital transmitter DS, instead of using variable delay circuits 21(1) to 21(n), multiple phase shifters (not shown) may be used to control the passing phase of multiple ΔΣ modulated signals DL output from CDR circuits 3(1) to 3(n).

Embodiment 3.
Third Embodiment
The digital transmitter DS of the third embodiment will be described.

Configuration and Operation of Third Embodiment
FIG. 9 shows the configuration of a digital transmitter DS according to the third embodiment.

As shown in FIG. 9, the digital transmitter DS of embodiment 3 includes a modulated signal output circuit 1, a CDR circuit unit 3, an amplifier 5, a filter 6, and an antenna 7, similar to the digital transmitter DS of embodiment 1 (shown in FIG. 1), and also includes a variable delay circuit unit 21, similar to embodiment 2.

On the other hand, as shown in FIG. 9, the digital transmitter DS of embodiment 3 differs from the digital transmitter DS of embodiments 1 and 2 in that it further includes a distribution circuit 31 and a synthesis circuit 32.

The distribution circuit 31 distributes the ΔΣ modulated signal DL output from the ΔΣ modulation circuit 1C to the CDR circuits 3(1) to 3(n). The CDR circuits 3(1) to 3(n) retime the multiple ΔΣ modulated signals DL after distribution and output them to the variable delay circuits 21(1) to 21(n).

The variable delay circuits 21 (1) to 21 (n) adjust the delay amount of the multiple ΔΣ modulated signals DL so that the multiple ΔΣ modulated signals DL are combined in phase at the carrier frequency by the combination circuit 32, and output the adjusted multiple ΔΣ modulated signals DL to the combination circuit 32.

The combining circuit 32 combines the multiple ΔΣ modulated signals DL with the adjusted delay amounts. The combined ΔΣ modulated signal DL, i.e., the in-phase combined ΔΣ modulated signal DL, passes through amplifiers 5 and 6 and is then radiated into space from antenna 7.

Effects of the Third Embodiment
As described above, in the third embodiment, the variable delay circuits 21(1) to 21(n) adjust the delay amounts of the multiple ΔΣ modulated signals DL in accordance with the phase variation of the multiple ΔΣ modulated signals DL output from the CDR circuits 3(1) to 3(n) after the distribution circuit 31 distributes the ΔΣ modulated signal DL, and the synthesis circuit 32 synthesizes the multiple ΔΣ modulated signals DL with the adjusted delay amounts, that is, performs in-phase synthesis. This in-phase synthesis causes the phase noise outside the loop band of the CDR circuits 3(1) to 3(n) to be voltage-added in the same manner as in the first and second embodiments, and therefore, in the same manner as in the first and second embodiments, it is possible to improve the phase noise of the ΔΣ modulated signal DL after the synthesis.

In addition to the effects described above, in embodiment 3, the in-phase distribution circuit 2 and the in-phase synthesis circuit 4 (both circuits shown in Figure 1) can be eliminated.

<Modification>
In the digital transmitter DS of embodiment 3, instead of controlling the delay amount of multiple ΔΣ modulated signals DL using variable delay circuits 21(1) to 21(n), for example, multiple phase shifters (not shown) may be used to control the passing phase of multiple ΔΣ modulated signals DL output from CDR circuit 3(1) to CDR circuit 3(n).

The above-described embodiments may be combined together without departing from the spirit and scope of the present disclosure, and components in each embodiment may be deleted or modified, or other components may be added, as appropriate.

The digital transmitter of the present disclosure can be used to suppress degradation of the signal-to-noise ratio of a signal transmitted from the digital transmitter.

1 Modulated signal output circuit, 1A Clock generation circuit, 1B Modem, 1C ΔΣ modulation circuit, 2 In-phase distribution circuit, 3 CDR circuit unit, 4 In-phase synthesis circuit, 5 Amplifier, 6 Filter, 7 Antenna, CL Clock, DG Digital modulated signal, DL ΔΣ modulated signal, DS Digital transmitter, TD Communication data.

Claims (6)

a clock generation circuit for generating a clock;
a delta-sigma modulation circuit that generates a first delta-sigma modulated signal by performing delta-sigma modulation on a digitally modulated signal based on the clock;
a distribution circuit that distributes the first delta-sigma modulated signal into a plurality of second delta-sigma modulated signals;
a plurality of recovery circuits for retiming the plurality of second delta-sigma modulated signals;
a synthesis circuit that synthesizes a plurality of retimed second delta-sigma modulated signals output from the plurality of reproduction circuits;
Including,
the loop bandwidth of the plurality of recovery circuits is equal to or smaller than the loop bandwidth of the clock generation circuit,
the distribution circuit performs the distribution such that the plurality of second delta-sigma modulated signals are in phase at a carrier frequency, or the combination circuit performs the combination such that the retimed plurality of second delta-sigma modulated signals are in phase at the carrier frequency;
Digital transmitter. a clock generation circuit for generating a clock;
a delta-sigma modulation circuit that generates a first delta-sigma modulated signal by performing delta-sigma modulation on a digitally modulated signal based on the clock;
a distribution circuit that distributes the first delta-sigma modulated signal into a plurality of second delta-sigma modulated signals;
a plurality of recovery circuits for retiming the plurality of second delta-sigma modulated signals;
a plurality of antennas that radiate the plurality of second delta-sigma modulated signals into space;
Including,
the loop bandwidth of the plurality of recovery circuits is equal to or smaller than the loop bandwidth of the clock generation circuit,
the distribution circuit performs the distribution so that the plurality of second delta-sigma modulated signals are in phase at a carrier frequency;
Digital transmitter. a plurality of variable delay circuits for controlling delay amounts of the retimed second delta-sigma modulated signals output from the plurality of reproduction circuits;
3. The digital transmitter of claim 2. a clock generation circuit for generating a clock;
a delta-sigma modulation circuit that generates a first delta-sigma modulated signal by performing delta-sigma modulation on a digitally modulated signal based on the clock;
a distribution circuit that distributes the first delta-sigma modulated signal into a plurality of second delta-sigma modulated signals;
a plurality of recovery circuits for retiming the plurality of second delta-sigma modulated signals;
a plurality of variable delay circuits that control delay amounts of the retimed second delta-sigma modulated signals output from the plurality of reproduction circuits;
a synthesizing circuit that synthesizes a plurality of second delta-sigma modulated signals, the delay amounts of which are controlled and output from the plurality of variable delay circuits;
Including,
a loop bandwidth of the plurality of recovery circuits is equal to or smaller than a loop bandwidth of the clock generation circuit;
Digital transmitter. 5. The digital transmitter according to claim 1, wherein the distribution circuit has a cascaded series resonant circuit in which a plurality of series resonant circuits are cascaded, and the carrier frequency of the first delta-sigma modulated signal is a resonant frequency. 5. The digital transmitter according to claim 1, wherein the combining circuit has a cascaded series resonant circuit in which a plurality of series resonant circuits are cascaded, the resonant frequency of which is the carrier frequency of the plurality of second delta-sigma modulated signals.

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