JP7516984B2 - Method for manufacturing wide band gap semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing wide band gap semiconductor devices such as silicon carbide (hereinafter referred to as SiC).

Conventionally, in the trench etching process, a resist is placed on the semiconductor surface, and then the resist is exposed and developed using an exposure device to pattern an exposure mask, and etching is performed using the exposure mask to form a trench. At this time, the exposure device is precisely focused so that the exposure mask is exposed to light in accordance with the unevenness of the semiconductor surface (see, for example, Patent Document 1).

For example, in an exposure device called a stepper, exposure is performed as follows. First, a resist is applied to the semiconductor surface, and then LED (Light Emitting Diode) light is incident from above the resist toward the semiconductor surface, and the reflected light is received to detect the unevenness of the semiconductor surface. More specifically, for each shot, the unevenness height of the semiconductor surface is measured at five points at the position of the focus sensor within the focus measurement range, and the surface reference plane for each shot is calculated based on the height data of the five points based on the least squares method. Next, the stage on which the semiconductor wafer is mounted is driven, and height adjustment and tilt correction are performed for the target shot based on scanning in the X and Y directions and adjustment in the Z direction. As a result, the height and tilt are corrected so that the surface reference plane of the target shot becomes a plane perpendicular to the exposure light at the focus position. Next, LED light is incident and received again to calculate the surface reference plane of the semiconductor surface of the target shot, and it is confirmed whether the height and tilt correction have been performed appropriately. If the correction has been performed appropriately, the resist of the target shot is exposed. This operation is repeated for each shot to expose the resist over the entire surface of the semiconductor wafer.

JP 2004-71851 A

However, when the semiconductor is SiC, it was found that the unevenness of the SiC surface cannot be measured accurately, which can result in variations in the line width of the formed trenches.

The inventors conducted extensive research into the reason for this phenomenon and found that if there is a defect on the SiC surface where the trench is formed, the unevenness of the SiC surface may not be measured accurately. Specifically, it was found that if there is a defect on the SiC surface, the defect causes a shift in the reflection direction of the LED light, and therefore the unevenness of the SiC surface cannot be measured accurately.

Note that, although the semiconductor described here is SiC, similar problems can occur with wide band gap semiconductors in which defects affect surface roughness measurement. Also, a trench formation mask has been used as an example of an exposure mask, but the problems described here can occur when forming the exposure mask. In other words, similar problems can occur with other exposure masks, such as ion implantation masks and etching masks for forming contact holes in interlayer insulating films.

In view of the above, the present invention aims to provide a method for manufacturing a wide band gap semiconductor device that can accurately form an exposure mask even if defects are present.

In order to achieve the above object, the invention described in claim 1 is a method for manufacturing a wide band gap semiconductor device, which includes arranging a resist (11) on a semiconductor wafer (10) made of a wide band gap semiconductor and exposing the resist to form an opening of a predetermined line width, and includes the steps of preparing a semiconductor wafer, identifying the position of a defect (12) present on the surface of the semiconductor wafer, arranging a resist on the surface side of the semiconductor wafer, measuring the height of the unevenness of the surface of the semiconductor wafer at multiple positions within the focus measurement range by irradiating a scanning light from above the resist toward the semiconductor wafer for each shot, with a predetermined focus measurement range being one shot, and receiving the reflected light of the scanning light, calculating a surface reference plane that is an approximate plane for each shot based on the least squares method from height data indicating the heights at each of the multiple positions measured in measuring the unevenness height, and adjusting the height and inclination of the surface reference plane to match the ideal surface, with a surface perpendicular to the exposure light and focused on the exposure, as the ideal surface, and then irradiating the resist with the exposure light to form an opening in the resist. Then, when measuring the unevenness height, each of the multiple positions in the focus measurement range is treated as a channel (CH1 to CH5), and the unevenness height is measured in more than three channels; when calculating the surface reference plane, if the position of the defect identified by identifying the position of the defect matches any of the channels, the height data of the matching channel is excluded and the surface reference plane is calculated using the least squares method.

In this way, when calculating the surface reference plane for each shot, if the position of a defect coincides with the position of any of the channels performing height measurement, the surface reference plane is calculated excluding that channel. This allows an approximate plane to be calculated while ignoring erroneous height data, that is, height data from a channel that was unable to accurately measure the unevenness of the semiconductor wafer surface due to the influence of a defect, so the surface reference plane can be calculated with high accuracy. Therefore, when forming an exposure mask from resist, an exposure mask can be formed accurately even if a defect is present.

The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below.

FIG. 1 is a diagram showing a schematic configuration of a stepper described in a first embodiment. 1 is a diagram showing the relationship between a focus measurement range by a stepper and an exposure area for one shot. 13A and 13B are diagrams illustrating calculation of a surface reference plane and tilt correction by focus measurement. FIG. 1 shows five channels in which focus measurement ranges and unevenness height measurements are performed. 11 is a diagram showing changes in reflected light in a normal state where no defect is formed and in an abnormal state where a defect is formed. FIG. 1A and 1B are diagrams showing images of five arbitrary shots of a semiconductor wafer used in an experiment. FIG. 11 is a contrast diagram of a shot in which a defect was present among five shots for which height measurements were performed in an experiment. FIG. 11 is a contrast diagram of a shot in which a defect was present among five shots for which height measurements were performed in an experiment. 13 is a diagram showing the relationship between the amount of deviation from an ideal surface when a surface reference plane is calculated and the line width of an opening in a resist. 13 is a diagram showing the relationship between the amount of deviation from an ideal surface when a surface reference plane is calculated and the line width of an opening in a resist. FIG. 1 is a diagram illustrating the amount of deviation from an ideal surface. FIG. 1 shows an image of an opening in the resist of a shot that contained a defect. FIG. 1 shows an image of a resist opening for a shot that does not contain any defects. 1 is a diagram showing the relationship when the absolute value of the tolerance of the deviation from an ideal surface is x and the height of the irregularities of a defect that makes it impossible to obtain a required line width is y. 1 is a cross-sectional view of a vertical MOSFET showing an example of a SiC semiconductor device subjected to an exposure process.

The following describes embodiments of the present invention with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are denoted by the same reference numerals.

First Embodiment
A first embodiment will be described. Here, a method for manufacturing a SiC semiconductor device using a stepper will be described. As one step in manufacturing a SiC semiconductor device, an exposure mask is patterned using a stepper, and the exposure mask is further used as a trench formation mask to form trenches.

First, the configuration of the stepper will be described with reference to FIG. 1. In the following description, the left-right direction on the paper in FIG. 1 is the X direction, the direction perpendicular to the paper is the Y direction, and the top-bottom direction on the paper is the Z direction.

The stepper 1 is used to pattern a resist 11 placed on the front side of a semiconductor wafer 10, which has a front side and a back side on the opposite side. The patterned resist 11 is used as an exposure mask, such as a trench formation mask. As shown in FIG. 1, the stepper 1 is configured to include a wafer stage 2, a reticle stage 3, an exposure light source 4, an illumination optical system 5, a projection optical system 6, a light projecting unit 7, a light receiving unit 8, and a control unit 9.

The wafer stage 2 is used to mount a semiconductor wafer 10 to be processed on which a resist 11 of, for example, 1 μm thickness has been formed, and to perform position and tilt correction so that the resist 11 can be well exposed. Here, as an example of a semiconductor wafer 10, a SiC wafer 10a on which a SiC epitaxial layer (hereinafter simply referred to as an epilayer) 10b has been formed is shown. Based on a control signal from the control unit 9, the wafer stage 2 is capable of scanning on an XY plane parallel to the X and Y directions and correcting the tilt of the semiconductor wafer 10. For this reason, the wafer stage 2 can be controlled to correct the height and tilt of the semiconductor wafer 10 for each shot by the stepper 1, that is, for each rectangular area (hereinafter referred to as an exposure area) exposed by one exposure process.

Here, the semiconductor wafer 10 can be measured for crystal defects in advance to identify the defect positions in the semiconductor wafer 10. As will be described later, in this embodiment, the defect positions in the semiconductor wafer 10 are identified as a preliminary step, and the XY position coordinates of each defect are stored based on a landmark such as an alignment mark (not shown).

The reticle stage 3 is a support for the reticle 3a, and is configured to be movable in the XY plane. The reticle 3a is a photomask that serves as an original for transferring a pattern to the resist 11 to be transferred by exposure, and is formed with a desired pattern that corresponds to the shape of the pattern to be transferred to the semiconductor wafer 10. An opening 3b is formed in the reticle stage 3, and the reticle 3a on which the desired pattern is formed is placed on the reticle stage 3 so as to straddle the opening 3b. The exposure light irradiated onto the reticle 3a from the illumination optical system 5 passes through the opening 3b and enters the projection optical system 6.

The exposure light source 4 generates exposure light for exposing the resist 11. For example, an i-line with a wavelength of 365 nm is used as the exposure light. The exposure light generated by the exposure light source 4 is transmitted to the illumination optical system 5.

The illumination optical system 5 collects the exposure light transmitted from the exposure light source 4 and irradiates it toward the reticle 3a.

The projection optical system 6 includes a projection lens and receives the light that has passed through the reticle 3a on which the desired pattern is formed, reduces it to a specified ratio using the projection lens, and projects it onto the resist 11.

The light projecting unit 7 outputs LED light that serves as the scanning light for focus measurement, and irradiates the scanning light within the focus measurement range on the surface of the semiconductor wafer 10. In the stepper 1, the focus measurement range is determined as a fixed area due to its specifications. The light projecting unit 7 irradiates the scanning light for height measurement at multiple points within the focus measurement range, for example, at the center position and the four corners, for a total of five points.

In the stepper 1, the "focus measurement range" may be the same as the "exposure area" of one shot, or may be a different range. For example, as shown in FIG. 2, the "focus measurement range" has the same center position as the "exposure area" and is a different size from the "exposure area". The "focus measurement range" is set for each "exposure area", and the step pitch of both is the same. In the example of FIG. 2, the "focus measurement range" is set to a size that surrounds the "exposure area", where the "focus measurement range" is 2.2 cm□ and the "exposure area" is 1 cm□. Conversely, the "exposure area" may be set to a size that surrounds the "focus measurement range". The focus measurement is performed within the effective area of the semiconductor wafer 10 that is used as a chip, the same number of times as the number of shots. Here, the effective area is the area excluding a certain width from the edge of the semiconductor wafer 10, and the outside part is set to an invalid area that is not extracted as a chip. Note that in the above, one exposure in an exposure process is called one shot, but one focus measurement is also called one shot.

The light receiving unit 8 receives the reflected light of the LED light, which is the scanning light irradiated from the light projecting unit 7 onto the semiconductor wafer 10, and transmits a detection signal indicating the light reception result to the control unit 9.

The control unit 9 performs various calculations related to focus measurement, such as calculation of the surface reference plane in the focus measurement range, based on the light reception results transmitted from the light receiving unit 8. The surface reference plane is calculated, for example, by performing a least squares calculation based on the heights at multiple points scanned within the focus measurement range. The control unit 9 also controls the reticle stage 3, the wafer stage 2, and the irradiation of exposure light from the exposure light source 4. This allows the reticle 3a to move on the XY plane, the semiconductor wafer 10 to be processed to move on the XY plane, and tilt correction based on the focus measurement to be performed.

Next, we will explain the exposure process of the resist 11 using the stepper 1. First, we will explain the normal exposure process performed by the stepper 1.

First, resist is applied to the surface of the semiconductor wafer 10, and then, as shown in state (a) of FIG. 3, LED light, which serves as scanning light, is projected from the light projector 7 onto the surface of the semiconductor wafer 10 from above the resist 11, and the reflected light is received by the light receiver 8. Then, in the control unit 9, calculations of the surface reference plane in the focus measurement range are performed based on the light reception results transmitted from the light receiver 8.

More specifically, for each shot, the height of the unevenness on the semiconductor surface is measured at multiple positions corresponding to the position of the focus sensor within the focus measurement range, here five channels. That is, as shown in FIG. 4, height measurements are performed at the center position and five points at the four corners of the focus measurement range. Hereinafter, the five channels will be referred to as CH1 at the top left of FIG. 3, CH2 at the top right, CH3 at the center position, CH4 at the bottom left, and CH5 at the bottom right. The positional relationship of each channel is arbitrary, but in this embodiment, CH1, CH2, CH4, and CH5 are positioned to form a square, and the distance between the channels that make up each side of the square is 1.4 cm.

Then, as shown in state (b) of Figure 3, once height measurements have been completed at five points CH1 to CH5, a surface reference plane that is an approximate plane for each shot is calculated based on the height data at those five points using the least squares method.

Next, as shown in state (c) of FIG. 3, the wafer stage 2 on which the semiconductor wafer 10 is mounted is driven, and height adjustment and tilt correction for the target shot are performed based on scanning in the X and Y directions and adjustment in the Z direction. As a result, the height and tilt are corrected so that the surface reference plane of the target shot at the focus position becomes a plane perpendicular to the exposure light. Next, the LED light is again incident and received to calculate the surface reference plane of the surface of the semiconductor wafer 10 of the target shot, and it is confirmed whether the height and tilt correction have been performed properly. Then, if the correction has been performed properly, the exposure light source 4 outputs i-lines that become the exposure light, and the i-lines are irradiated onto the resist 11 of the target shot through the illumination optical system 5, the reticle 3a, and the projection optical system 6, thereby performing exposure. This operation is repeated for each shot, and the resist 11 is exposed in all shots of the effective area of the semiconductor wafer 10.

If a defect exists in any of channels CH1 to CH5, depending on the size of the irregularities of the defect, a deviation occurs in the reflection direction of the LED light, making it impossible to accurately measure the height in that channel. Specifically, as shown in FIG. 5, in an abnormal state in which a large defect 12 exists on the surface of the semiconductor wafer 10, a deviation occurs in the reflection direction of the LED light compared to a normal state in which no large defect 12 exists. As a result, it becomes impossible to accurately measure the irregularities on the surface of the semiconductor wafer 10. In that case, when a surface reference plane that is an approximation surface for each shot is calculated based on the least squares method from the height data of the five points as described above, the height data of the channel in which accurate height measurement could not be performed will affect the calculation of the surface reference plane with high precision.

For this reason, in this embodiment, as a preliminary step, the position of the defect 12 present on the surface of the semiconductor wafer 10 is identified, and if it is confirmed that the defect 12 exists at any of the positions CH1 to CH5, the surface reference plane is calculated excluding that point.

Advance preparation is performed before the application of the resist 11. Specifically, a surface defect inspection device is used to measure the positions of defects present on the surface of the semiconductor wafer 10, i.e., the XY position coordinates on the semiconductor wafer 10. For example, the surface defect inspection device measures the defect positions based on the contrast of the surface image of the semiconductor wafer 10.

There is a correlation between contrast and the size of the irregularities in the defect. For this reason, the contrast value of the area containing the defect 12 for which the height measurement could not be performed accurately is determined through experiments, and, for example, the minimum value is set as the judgment threshold. The position where the contrast value is equal to or greater than the judgment threshold is then identified as the position of the defect 12 for which the height measurement may not be performed accurately, and is stored as the position of the defect 12 present in the semiconductor wafer 10. Furthermore, when the semiconductor wafer 10 after being coated with the resist 11 is mounted on the wafer stage 2, the semiconductor wafer 10 is aligned using a landmark such as an alignment mark as a reference, and the XY position coordinates of the stored defect position are identified.

After such preparations are made, the exposure process described above is carried out. At this time, when calculating the surface reference plane for each shot, if the position of the defect 12 stored in the preparations matches the position of any one of the five channels, that channel is excluded and an approximate plane is calculated based on the least squares method, which is used as the surface reference plane.

Calculation of the approximate plane based on the least squares method can be performed more accurately the more channels of height data are used in the calculation, but accuracy deteriorates if erroneous height data is included. For this reason, the surface reference plane can be calculated with high accuracy by ignoring erroneous height data, that is, height data from channels in which the unevenness of the surface of the semiconductor wafer 10 could not be accurately measured due to the influence of defects 12.

In other words, if it is confirmed that a defect 12 exists in one of the five channels in a shot, the surface reference plane is calculated based on the height data of the remaining four channels. Also, if it is confirmed that a defect 12 exists in two of the five channels in a shot, the surface reference plane is calculated based on the height data of the remaining three channels.

However, to calculate the surface reference plane based on the least squares method, height data for three or more points is required. For this reason, if it is confirmed that defects 12 exist in three or more of the five channels in a shot, the surface reference plane cannot be calculated based on the least squares method. In this case, the inclination is assumed to be a plane perpendicular to the exposure light, and only the height is calculated based on the height data for the remaining two points to obtain the surface reference plane. In this case, if one of the remaining two points is CH3, the surface reference plane is calculated based on the height data of the height data channel for CH3, and since it is assumed to be close to the median of the height range in the shot, it is possible to calculate the height with relatively high accuracy.

For reference, we will explain the results of an experiment to determine the size of the irregularity defect 12 required for accurate height measurement.

In the experiment, five arbitrary shots on the semiconductor wafer 10 were selected, for example the five shots shown in Figure 6. One of the five shots was selected to contain a defect 12 that overlaps with CH1 to CH5. The exposure process was then carried out as described above, and the resist 11 was patterned. However, at this time, the channel containing the defect 12 was not ignored when calculating the approximate plane based on the least squares method, and the surface reference plane was calculated including the height data of that channel.

Then, for the resist 11 patterned in this way, the line width of the openings that were removed by exposure, for example the dimensions that correspond to the trench width when the resist 11 is used as a mask for forming trenches, was confirmed using an electron microscope or the like. Such experiments were performed on multiple semiconductor wafers 10.

Figure 7A is an image of an analysis taken by a surface defect inspection device of a shot containing defect 12 among any five shots of a first semiconductor wafer 10. Also, Figure 7B is an image of an analysis taken by a surface defect inspection device of a shot containing defect 12 among any five shots of a second semiconductor wafer 10. The surface defect inspection device used was a SICA manufactured by Lasertec Corporation for SiC wafer defect inspection. With this device, the unevenness of the SiC surface is expressed by a contrast value with 256 gradations.

In the case of Figure 7A, a defect 12 was formed in the CH1 channel, and the contrast value was 214. In the case of Figure 7B, a defect 12 was formed in the CH5 channel, and the contrast value was 185.

When the surface reference plane was calculated for each of the cases shown in FIG. 7A and FIG. 7B, the relationship between the deviation from the ideal surface plane and the line width of the opening in the resist 11 was examined, and the results shown in FIG. 8A and FIG. 8B were obtained. Note that the ideal surface plane here is a plane perpendicular to the exposure light and at a height where the exposure is focused. Also, the deviation from the ideal surface plane represents the distance between both surfaces at the end of the shot when the ideal surface plane and the surface reference plane are overlapped at the center of the shot, as shown in FIG. 9. When the tilt is corrected before exposure, the tilt is corrected by the amount of deviation. Also, the ideal value for the line width of the opening in the resist 11 was set to 0.3 μm.

As shown in Figures 8A and 8B, there are points where the line width is far from the ideal value even though the deviation from the ideal surface is small. For example, at the circled point in Figures 8A and 8B, the deviation from the ideal surface is the lowest at about -0.02 μm, but the obtained line width is 0.25 μm or less, which is the farthest from the ideal line width. This circled point was confirmed to be a shot in which a defect 12 was formed at a position overlapping with the channel, as shown in Figures 7A and 7B. When images of the openings in the resist 11 were checked for the shots that contained the defect 12 shown in Figures 7A and 7B and the other shots, they were as shown in Figures 10A and 10B, and the line width of the former was narrower than the line width of the latter.

This phenomenon occurred because the surface reference plane was calculated incorrectly due to the effect of defect 12. In other words, during tilt correction before exposure, tilt correction is performed for the amount of deviation from the ideal surface, but because there is an error in the calculated surface reference plane, tilt correction is not performed sufficiently. This causes the focus tolerance (hereinafter referred to as DOF (Depth of Focus)) to fall outside the range, causing defocusing in which the exposure focal position is shifted from the optimal position, resulting in a shift in the line width of the opening in resist 11.

Then, the relationship between the deviation from the ideal surface and the line width of the opening in the resist 11 was examined for shots containing defects 12 with various contrast values. As a result, it was confirmed that, for example, when performing exposure to achieve a line width of 1 μm or less, if defects 12 with a contrast value of 180 or more are included, the required line width will be outside the tolerance range of, for example, the ideal value ±10%.

A contrast value of 180 or more means that the height of the defect 12 is 85 nm or more relative to the surrounding SiC surface. If the surface reference plane is calculated while even one of the five channels contains a defect 12 with this level of height, it will be outside the range of the DOF and the desired line width will not be obtained. This value varies depending on the required DOF, but for example, when the DOF is ±0.2 μm away from the ideal surface, it was necessary to calculate the surface reference plane while ignoring channels that overlap with defects 12 with a contrast value of 180 or more. In addition, when the DOF is ±0.4 μm away from the ideal surface, it was found that it was necessary to calculate the surface reference plane while ignoring channels that overlap with defects 12 with a contrast value of 256 or more, that is, with a height of 170 nm or more.

If these are graphed, with x being the absolute value of the DOF value, i.e., the allowable deviation from the ideal surface, and y being the height of the irregularities of defect 12 at which the required line width cannot be obtained, the result will be as shown in Figure 11. Therefore, if the surface reference surface is calculated ignoring channels in which there exists a defect 12 with an irregularity height y that satisfies the following equation, the deviation of the surface reference surface from the ideal surface can be kept within the range of the DOF, making it possible to obtain the desired line width in the exposure process.

以上説明したように、ショット毎の表面基準面を算出する際に、高さ測定を行う５つのチャンネルのうちのいずれかの位置に所定の凹凸高さを有する欠陥１２の位置が一致している場合、そのチャンネルを除いて表面基準面を算出している。これにより、誤った高さデータ、つまり欠陥１２の影響によって半導体ウェハ１０の表面の凹凸を正確に測定できなかったチャンネルの高さデータを無視して近似平面が算出されるため、精度良く表面基準面を算出できる。よって、レジスト１１によって露光マスクを形成する際に、欠陥１２が存在していても的確に露光マスクを形成できる。

As described above, when calculating the surface reference plane for each shot, if the position of defect 12 having a predetermined unevenness height coincides with any of the positions of the five channels performing height measurement, the surface reference plane is calculated excluding that channel. This allows the approximate plane to be calculated while ignoring erroneous height data, that is, height data of a channel in which the unevenness of the surface of semiconductor wafer 10 could not be accurately measured due to the influence of defect 12, so that the surface reference plane can be calculated with high accuracy. Therefore, when forming an exposure mask using resist 11, the exposure mask can be formed accurately even if defect 12 is present.

And it is possible to manufacture very fine semiconductor elements with minimum processing dimensions of 1 μm or less, for example 0.3 to 0.8 μm, with high precision.

For example, it is preferable to perform the above-mentioned exposure process as one step in the manufacturing method of a SiC semiconductor device having a vertical MOSFET as shown in FIG. 12.

The SiC semiconductor device uses an n ⁺ type substrate 21 made of SiC, and an n ^{- type low concentration layer 22 made of SiC having a lower impurity concentration than the n + type substrate 21 is epitaxially grown on the main surface of the n + type substrate 21. In this manner, the n - type low concentration} layer 22 corresponding to the epitaxial layer 10b formed on the n ⁺ type substrate 21 corresponding to the SiC wafer 10a corresponds to the semiconductor wafer 10.

The n ^- type low concentration layer 22 is connected to a narrowed JFET portion 22a at a position away from the n ⁺ type substrate 21, and a p-type deep layer 23 made of SiC is formed on both sides of the JFET portion 22a. The p-type deep layer 23 is configured to have the same thickness as the JFET portion 22a. Furthermore, a p-type base region 24 made of SiC is formed on the JFET portion 22a and the p-type deep layer 23, and an n ⁺ type source region 25 and a p ⁺ type contact region 26 made of SiC are formed on the p-type base region 24. The n ⁺ type source region 25 is formed on a portion of the p-type base region 24 corresponding to the JFET portion 22a, and the p ⁺ type contact region 26 is formed on a portion of the p-type base region 24 corresponding to the p-type deep layer 23.

A gate trench 27 is formed, which penetrates the p-type base region 24 and the n ⁺ -type source region 25 and reaches the JFET portion 22a. The above-mentioned p-type base region 24 and n ⁺ -type source region 25 are arranged so as to contact the side surface of the gate trench 27. The gate trench 27 is formed in a line-shaped layout with the left-right direction of the paper surface of FIG. 12 as the width direction, one direction normal to the paper surface as the length direction, and the up-down direction of the paper surface as the depth direction. Although only one gate trench 27 is shown in FIG. 12, multiple gate trenches 27 are arranged at equal intervals in the left-right direction of the paper surface, and are arranged so as to be sandwiched between the p-type deep layers 23, forming a stripe shape.

In addition, a gate insulating film 28 is formed on the inner wall surface of the gate trench 27 including the channel region, which is a portion of the p-type base region 24 located on the side surface of the gate trench 27 and serves as a channel region connecting the n ⁺ -type source region 25 and the JFET portion 22a when the vertical MOSFET is in operation. A gate electrode 29 made of doped Poly-Si is formed on the surface of the gate insulating film 28, and the inside of the gate trench 27 is filled with the gate insulating film 28 and the gate electrode 29. This forms a trench gate structure.

An interlayer insulating film 30 is formed on the surfaces of the n ⁺ type source region 25, the p ⁺ type contact region 26, and the trench gate structure. A source electrode 31 and a gate wiring layer (not shown) are formed as conductor patterns on the interlayer insulating film 30. A contact hole 30a is formed in the interlayer insulating film 30, and the source electrode 31 is electrically contacted with the n ⁺ type source region 25 and the p ⁺ type contact region 26. In a cross section different from that of FIG. 12, a contact hole is further formed in the interlayer insulating film 30, and the gate electrode 29 and the gate wiring layer are electrically connected through this contact hole.

Furthermore, a drain electrode 32 electrically connected to the n ⁺ type substrate 21 is formed on the back side of the n ⁺ type substrate 21. With this structure, an n-channel type inversion type trench gate structure vertical MOSFET is formed. A cell region is formed by arranging a plurality of such vertical MOSFETs. Then, a peripheral breakdown voltage structure using a guard ring (not shown) or the like is formed so as to surround the cell region in which such a vertical MOSFET is formed, thereby forming a SiC semiconductor device.

In such a SiC semiconductor device, the minimum processing dimension of each impurity layer and gate trench 27, for example the width of the gate trench 27, is set to 0.3 to 0.8 μm. When using an exposed resist 11 as an exposure mask for forming such a gate trench 27, the exposure mask can be accurately formed by performing the exposure process described above, and the gate trench 27 can be formed with the desired line width. Therefore, it is possible to accurately manufacture a SiC semiconductor device with the desired characteristics.

Other Embodiments
Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

For example, in the above embodiment, a case has been described in which a resist 11 is placed on a semiconductor wafer 10 having an epitaxial layer 10b formed on a SiC wafer 10a, and the resist 11 is exposed to light. However, this is merely one example of the shape of the semiconductor wafer 10, and other structures may be used. Also, a trench formation mask has been used as an example of the exposure mask with which the resist 11 is exposed, but it may be used as a mask other than a trench formation mask, such as an ion implantation mask or an etching mask for forming contact holes in an interlayer insulating film.

In the above embodiment, for simplicity, a configuration in which resist 11 is applied to the surface of the semiconductor wafer 10 to be processed has been described as an example, but a configuration in which an insulating film such as an oxide film is placed on the semiconductor wafer 10 and resist 11 is applied on the insulating film may also be used. Even in such a case, the same can be said as above, since defects 12 have an effect when the scanning light passes through the insulating film and is reflected on the surface of the semiconductor wafer 10, affecting the calculation of the surface reference plane.

In addition, a vertical MOSFET has been given as an example of a semiconductor element formed using a semiconductor wafer 10 having an epitaxial layer 10b formed on a SiC wafer 10a, but other devices, such as a Schottky diode, may also be used.

The numerical values mentioned in the above embodiments, such as the focus measurement range and the distance between channels, are merely examples. Although 1 μm has been given as an example of the film thickness of the resist 11, this is not limiting. However, the thicker the film thickness of the resist 11, the greater the impact of the line width becoming narrower than the desired line width when forming an opening with a narrow line width, and this impact is particularly likely to occur when the aspect ratio, which is the ratio of the line width to the thickness of the resist 11, is 1 or more. For this reason, it is preferable to perform the above-mentioned exposure process when the aspect ratio, which is such that the line width is 1 μm or less when the film thickness of the resist 11 is 1 μm or more, is 1 or more.

Furthermore, in the above embodiment, an example was described in which an epitaxial layer 10b is formed on a SiC wafer 10a as a semiconductor wafer 10 to manufacture a SiC semiconductor device, but the present invention can also be applied to the manufacture of wide band gap semiconductor devices.

REFERENCE SIGNS LIST 1 Stepper 2 Wafer stage 4 Exposure light source 7 Light projecting section 8 Light receiving section 9 Control section 10 Semiconductor wafer 10a SiC wafer 10b Epi layer 11 Resist

Claims (6)

A method for manufacturing a wide band gap semiconductor device, comprising the steps of: placing a resist (11) on a semiconductor wafer (10) made of a wide band gap semiconductor; and exposing the resist to form an opening having a predetermined line width,
providing the semiconductor wafer;
Identifying a location of a defect (12) present on a surface of the semiconductor wafer;
placing the resist on a front side of the semiconductor wafer;
a predetermined focus measurement range is defined as one shot, and for each shot, a scanning light is irradiated from above the resist toward the semiconductor wafer while receiving reflected light of the scanning light, thereby measuring heights of irregularities on the surface of the semiconductor wafer at a plurality of positions within the focus measurement range;
calculating a surface reference plane that is an approximate plane for each shot based on a least squares method from height data indicating heights at each of the multiple positions measured in measuring the irregularity heights;
a surface that is perpendicular to the exposure light and on which the exposure light is focused is defined as an ideal surface, the height and inclination of the surface reference surface are adjusted to match the ideal surface, and then the exposure light is irradiated onto the resist to form the opening in the resist;
In the measuring of the unevenness height, a plurality of positions in the focus measurement range are defined as channels (CH1 to CH5), and the unevenness height is measured in more than three channels;
In the calculation of the surface reference plane, when the position of the defect identified by identifying the position of the defect coincides with any one of the channels, the height data of the channel that coincides is excluded, and the surface reference plane is calculated by the least squares method ;
In identifying the position of the defect, the value of the focus tolerance in the exposure is x, the height of the irregularities of the defect is y, and

and determining a position of the defect having the irregularity height y that satisfies the above formula (1) . In the step of measuring the unevenness height, the unevenness height is measured in five channels as the number of channels greater than three;
2. The method for manufacturing a wide bandgap semiconductor device according to claim 1, wherein, in calculating the surface reference plane, if the position of the defect identified by identifying the position of the defect coincides with any one of the channels, the surface reference plane is calculated using the least squares method based on the height data of four channels excluding the height data of the one channel that coincides. A method for manufacturing a wide band gap semiconductor device, comprising the steps of: placing a resist (11) on a semiconductor wafer (10) made of a wide band gap semiconductor; and exposing the resist to form an opening having a predetermined line width,
providing the semiconductor wafer;
Identifying a location of a defect (12) present on a surface of the semiconductor wafer;
placing the resist on a front side of the semiconductor wafer;
a predetermined focus measurement range is defined as one shot, and for each shot, a scanning light is irradiated from above the resist toward the semiconductor wafer while receiving reflected light of the scanning light, thereby measuring heights of irregularities on the surface of the semiconductor wafer at a plurality of positions within the focus measurement range;
calculating a surface reference plane that is an approximate plane for each shot based on a least squares method from height data indicating heights at each of the multiple positions measured in measuring the irregularity heights;
a surface that is perpendicular to the exposure light and on which the exposure light is focused is defined as an ideal surface, the height and inclination of the surface reference surface are adjusted to match the ideal surface, and then the exposure light is irradiated onto the resist to form the opening in the resist;
In the measuring of the unevenness height, a plurality of positions in the focus measurement range are defined as channels (CH1 to CH5), and the unevenness height is measured in more than three channels;
In the calculation of the surface reference plane, when the position of the defect identified by identifying the position of the defect coincides with any one of the channels, the height data of the channel that coincides is excluded, and the surface reference plane is calculated by the least squares method;
In the step of measuring the unevenness height, the unevenness height is measured in five channels as the number of channels greater than three;
A method for manufacturing a wide band gap semiconductor device, in which, when the position of the defect identified by identifying the position of the defect coincides with any two of the channels, the surface reference plane is calculated using the least squares method based on the height data of three channels excluding the height data of the two channels that coincide. A method for manufacturing a wide band gap semiconductor device, comprising the steps of: placing a resist (11) on a semiconductor wafer (10) made of a wide band gap semiconductor; and exposing the resist to form an opening having a predetermined line width,
providing the semiconductor wafer;
Identifying a location of a defect (12) present on a surface of the semiconductor wafer;
placing the resist on a front side of the semiconductor wafer;
a predetermined focus measurement range is defined as one shot, and for each shot, a scanning light is irradiated from above the resist toward the semiconductor wafer while receiving reflected light of the scanning light, thereby measuring heights of irregularities on the surface of the semiconductor wafer at a plurality of positions within the focus measurement range;
calculating a surface reference plane that is an approximate plane for each shot based on a least squares method from height data indicating heights at each of the multiple positions measured in measuring the irregularity heights;
a surface that is perpendicular to the exposure light and on which the exposure light is focused is defined as an ideal surface, the height and inclination of the surface reference surface are adjusted to match the ideal surface, and then the exposure light is irradiated onto the resist to form the opening in the resist;
In the measuring of the unevenness height, a plurality of positions in the focus measurement range are defined as channels (CH1 to CH5), and the unevenness height is measured in more than three channels;
In the calculation of the surface reference plane, when the position of the defect identified by identifying the position of the defect coincides with any one of the channels, the height data of the channel that coincides is excluded, and the surface reference plane is calculated by the least squares method;
In the step of measuring the unevenness height, the unevenness height is measured in five channels as the number of channels greater than three;
In the calculation of the surface reference plane, when the position of the defect identified by identifying the position of the defect coincides with any one of the channels, the surface reference plane is calculated by the least squares method based on the height data of the four channels excluding the height data of the one channel that coincides;
Furthermore, in the measurement of the unevenness height, the unevenness height is measured in four channels located in a square shape and in a channel located at the center of the square shape as the five channels;
A method for manufacturing a wide band gap semiconductor device, in which, when the position of the defect identified by identifying the position of the defect matches any three of the channels, the surface reference plane is calculated based on the height data of at least one of the two channels excluding the height data of the three channels that match. In the measurement of the unevenness height, the unevenness height is measured in four channels located in a square shape and in a channel located at the center of the square shape as the five channels;
4. The method for manufacturing a wide band gap semiconductor device according to claim 2 or 3, wherein, in calculating the surface reference plane, if the position of the defect identified by identifying the position of the defect coincides with any three of the channels, the surface reference plane is calculated based on the height data of at least one of two channels excluding the height data of the three channels that coincide. 6. The method for manufacturing a wide band gap semiconductor device according to claim 4 or 5, wherein, in calculating the surface reference plane, if the position of the defect identified by identifying the position of the defect coincides with any three of the channels, and at least one of the two channels excluding the height data of the three matching channels is the channel at the center of the square shape, the surface reference plane is calculated based on the height data of the channel at the center of the square shape.

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