JP7523738B2 - Image display device manufacturing method and image display device - Google Patents

Description

Embodiments of the present invention relate to a method for manufacturing an image display device and an image display device.

There is a demand for thin image display devices that have high brightness, a wide viewing angle, high contrast, and low power consumption. In order to meet such market demands, development of display devices that use self-luminous elements is underway.

The emergence of display devices using micro LEDs, which are minute light-emitting elements, is expected as a self-emitting element. As a manufacturing method for display devices using micro LEDs, a method of sequentially transferring individually formed micro LEDs to a drive circuit has been introduced. However, as the number of micro LED elements increases with the trend toward higher image quality such as full high definition, 4K, 8K, etc., the transfer process requires an enormous amount of time if a large number of micro LEDs are individually formed and sequentially transferred to a substrate on which a drive circuit, etc. is formed. Furthermore, there is a risk of poor connection between the micro LEDs and the drive circuit, etc., resulting in a decrease in yield.

A technique is known in which a semiconductor layer including a light-emitting layer is grown on a silicon substrate, electrodes are formed on the semiconductor layer, and then the semiconductor layer is bonded to a circuit board on which a driving circuit is formed (see, for example, Patent Document 1).

JP 2002-141492 A

One embodiment of the present invention provides a manufacturing method for an image display device and an image display device that shortens the transfer process of light-emitting elements and improves yield.

A method for manufacturing an image display device according to one embodiment of the present invention includes the steps of: preparing a first substrate including a circuit element formed on a first surface of a translucent substrate, a first wiring layer connected to the circuit element, and a first insulating film covering the circuit element and the first wiring layer; preparing a semiconductor layer including a light-emitting layer; bonding the semiconductor layer to the first substrate; etching the semiconductor layer to form a light-emitting element including a light-emitting surface on the first insulating film and an upper surface facing the light-emitting surface; forming a second insulating film covering the first insulating film and the light-emitting element; forming a first via penetrating the first insulating film and the second insulating film; and forming a second wiring layer on the second insulating film. The first via is provided between the first wiring layer and the second wiring layer, and electrically connects the first wiring layer and the second wiring layer.

An image display device according to one embodiment of the present invention includes a light-transmitting member having a first surface, a circuit element provided on the first surface, a first wiring layer electrically connected to the circuit element, a first insulating film covering the first surface, the circuit element, and the first wiring layer, a light-emitting element on the first insulating film, the light-emitting element including a light-emitting surface and an upper surface facing the light-emitting surface, a second insulating film covering the first insulating film and the light-emitting element, a first via provided through the first insulating film and the second insulating film, and a second wiring layer provided on the second insulating film. The first via is provided between the first wiring layer and the second wiring layer, and electrically connects the first wiring layer and the second wiring layer.

An image display device according to one embodiment of the present invention includes a light-transmitting member having a first surface, a plurality of transistors provided on the first surface, a first wiring layer electrically connected to the plurality of transistors, a first insulating film covering the first surface, the plurality of transistors, and the first wiring layer, a first semiconductor layer including a light-emitting surface capable of forming a plurality of light-emitting regions on the first insulating film, a plurality of light-emitting layers provided on the first semiconductor layer, a plurality of second semiconductor layers provided on the plurality of light-emitting layers, each having a different conductivity type from the first semiconductor layer, a second insulating film covering the first insulating film, the first semiconductor layer, the plurality of light-emitting layers, and the plurality of second semiconductor layers, a plurality of first vias provided through the first insulating film and the second insulating film, and a second wiring layer provided on the second insulating film. The plurality of second semiconductor layers and the plurality of light-emitting layers are separated by the second insulating film. The plurality of first vias are provided between the first wiring layer and the second wiring layer, and electrically connect the first wiring layer and the second wiring layer.

An image display device according to one embodiment of the present invention includes a light-transmitting member having a first surface, a circuit element provided on the first surface, a first wiring layer electrically connected to the circuit element, a first insulating film covering the first surface, the circuit element, and the first wiring layer, a plurality of light-emitting elements on the first insulating film, the light-emitting surface being an upper surface facing the light-emitting surface, a second insulating film covering the first insulating film and the plurality of light-emitting elements, a first via provided through the first insulating film and the second insulating film, and a second wiring layer provided on the second insulating film. The first via is provided between the first wiring layer and the second wiring layer, and electrically connects the first wiring layer and the second wiring layer.

According to one embodiment of the present invention, a method for manufacturing an image display device is realized that shortens the transfer process of light-emitting elements and improves yield.

According to one embodiment of the present invention, an image display device is realized that shortens the transfer process of light-emitting elements and improves yield.

1 is a schematic cross-sectional view illustrating a portion of an image display device according to a first embodiment. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a modified example of the first embodiment. FIG. 1 is a schematic block diagram illustrating an image display device according to a first embodiment. 1 is a schematic plan view illustrating a portion of an image display device according to a first embodiment. 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. 3A to 3C are schematic perspective views illustrating a part of a manufacturing method of the image display device according to the first embodiment. 1 is a schematic cross-sectional view illustrating a portion of an image display device according to a first embodiment. 1 is a schematic cross-sectional view illustrating a portion of an image display device according to a first embodiment. 1 is a schematic perspective view illustrating an image display device according to a first embodiment. FIG. 11 is a schematic cross-sectional view illustrating a portion of an image display device according to a second embodiment. FIG. 11 is a schematic block diagram illustrating an image display device according to a second embodiment. 10A to 10C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a second embodiment. 10A to 10C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a second embodiment. 10A to 10C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a second embodiment. 10A to 10C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a second embodiment. 10A to 10C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a second embodiment. 10A to 10C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a second embodiment. 10A to 10C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a second embodiment. 10A to 10C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a second embodiment. 10A to 10C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a second embodiment. FIG. 13 is a schematic cross-sectional view illustrating a portion of an image display device according to a third embodiment. FIG. 13 is a schematic block diagram illustrating an image display device according to a third embodiment. 11A to 11C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a third embodiment. 11A to 11C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a third embodiment. 11A to 11C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a third embodiment. 11A to 11C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a third embodiment. 11A to 11C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a third embodiment. 11A to 11C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a third embodiment. 11A to 11C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a third embodiment. 11A to 11C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a third embodiment. 11A to 11C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a third embodiment. 11A to 11C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a third embodiment. 11A to 11C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a third embodiment. 11A to 11C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a third embodiment. FIG. 13 is a schematic perspective view illustrating an image display device according to a third embodiment. FIG. 13 is a schematic cross-sectional view illustrating a portion of an image display device according to a fourth embodiment. 13A to 13C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a fourth embodiment. 13A to 13C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a fourth embodiment. 13A to 13C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a fourth embodiment. 13A to 13C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a fourth embodiment. 13A to 13C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a fourth embodiment. 13A to 13C are schematic cross-sectional views illustrating a part of a manufacturing method of an image display device according to a fourth embodiment. FIG. 13 is a schematic cross-sectional view illustrating a portion of an image display device according to a fifth embodiment. 13A to 13C are schematic cross-sectional views illustrating a part of a manufacturing method for an image display device according to a fifth embodiment. 13A to 13C are schematic cross-sectional views illustrating a part of a manufacturing method for an image display device according to a fifth embodiment. 13A to 13C are schematic cross-sectional views illustrating a part of a manufacturing method for an image display device according to a fifth embodiment. 13 is a schematic cross-sectional view illustrating a portion of an image display device according to a sixth embodiment. FIG. 13 is a schematic cross-sectional view illustrating a portion of an image display device according to a sixth embodiment. FIG. 13 is a schematic cross-sectional view illustrating a portion of an image display device according to a seventh embodiment. 13 is a schematic cross-sectional view illustrating a portion of an image display device according to a seventh embodiment. FIG. 13 is a block diagram illustrating an image display device according to an eighth embodiment. FIG. 23 is a block diagram illustrating an image display device according to a modified example of the eighth embodiment.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing.
In this specification and each drawing, elements similar to those described above with reference to the previous drawings are given the same reference numerals and detailed description thereof will be omitted as appropriate.

First Embodiment
FIG. 1 is a schematic cross-sectional view illustrating a part of an image display device according to this embodiment.
1 shows a schematic configuration of a subpixel 20 of an image display device according to this embodiment. In this embodiment and the other embodiments described later, a second embodiment and a sixth embodiment show examples in which a color filter is not attached, and therefore, when these are used as a monochrome image display device, for example, a subpixel becomes one pixel. In this specification, a light-emitting element including one light-emitting element is called a subpixel, whether one pixel is formed by one subpixel or one pixel is formed by multiple subpixels.

In the following, the three-dimensional coordinate system of XYZ may be used for explanation. The light-emitting elements 150 are arranged in a two-dimensional plane as shown in FIG. 11 described later. The light-emitting elements 150 are provided for each subpixel 20. The two-dimensional plane on which the subpixels 20 are arranged is the XY plane. The subpixels 20 are arranged along the X-axis direction and the Y-axis direction. FIG. 1 shows a cross section taken along line AA' in FIG. 4 described later, and is a cross section in which multiple cross sections perpendicular to the XY plane are connected on one plane. In other figures, as in FIG. 1, the X-axis and Y-axis are not shown in the cross sections of multiple cross sections perpendicular to the XY plane, and the Z-axis perpendicular to the XY plane is shown. In other words, in these figures, the plane perpendicular to the Z-axis is the XY plane.

In what follows, the positive direction of the Z axis will be referred to as "up" or "above" and the negative direction of the Z axis will be referred to as "down" or "below", but the direction along the Z axis is not necessarily limited to the direction in which gravity is applied. The length along the Z axis will be referred to as the height.

The subpixel 20 has a light-emitting surface 151S that is approximately parallel to the XY plane. The light-emitting surface 151S is a surface that mainly emits light in the negative direction of the Z axis that is perpendicular to the XY plane. In this embodiment, the modified examples described below, and all embodiments, the light-emitting surface emits light in the negative direction of the Z axis.

As shown in FIG. 1, the subpixel 20 of the image display device includes a substrate (light-transmitting member) 102, a transistor (circuit element) 103, a first wiring layer 110, a first interlayer insulating film (first insulating film) 112, a light-emitting element 150, a second interlayer insulating film (second insulating film) 156, a via (first via) 161d, and a second wiring layer 160.

In this embodiment, the substrate 102 has two surfaces, and a TFT lower layer film 106 is provided on one surface 102a. Circuit elements such as transistors 103 are formed on the TFT lower layer film 106. The first surface 102a is a flat surface that is approximately parallel to the XY plane. When a color filter is provided in the image display device of this embodiment, the color filter is formed on the second surface 102b, which is the other surface of the substrate 102. The second surface 102b is a surface facing the first surface 102a. In other embodiments described later, when a color filter is not provided, a color filter may be provided on the surface of the substrate that faces the surface on which the light-emitting elements are formed, as described above. The substrate 102 is a light-transmitting substrate, for example a glass substrate.

A circuit 101 is formed on a substrate 102 via a TFT underlayer film 106, and the circuit 101 is covered with a first interlayer insulating film 112 having optical transparency. A light-emitting element 150 is provided on the first interlayer insulating film 112. The light-emitting element 150 is driven by a transistor 103 provided via the first interlayer insulating film 112. The transistor 103 is a thin film transistor (TFT). The process of forming circuit elements including TFTs on a large glass substrate has been established for the manufacture of liquid crystal panels, organic EL panels, etc., and has the advantage of being able to utilize existing plants.

The configuration of the sub-pixel 20 will be described in detail below.
The transistor 103 is formed on a TFT lower layer film 106. The TFT lower layer film 106 is provided to ensure flatness when the transistor 103 is formed, and to protect the TFT channel of the transistor 103 from contamination during heat treatment. The TFT lower layer film 106 is an insulating film made of _SiO2 or the like, and has optical transparency.

In addition to the transistor 103, other transistors, capacitors, and other circuit elements are formed on the TFT lower layer film 106, and the circuit 101 is formed by wiring and the like. For example, in FIG. 3 described later, the transistor 103 corresponds to the drive transistor 26. In FIG. 3, the selection transistor 24 and capacitor 28 are other circuit elements. The circuit 101 includes the TFT channel 104, the insulating layer 105, the insulating film 108, vias 111s, 111d, and the first wiring layer 110.

In this example, the transistor 103 is a p-channel TFT. The transistor 103 includes a TFT channel 104 and a gate 107. The TFT channel 104 is preferably formed by a low temperature polysilicon (LTPS) process. In the LTPS process, the TFT channel 104 is formed by polycrystallizing and activating an amorphous Si region formed on the TFT underlayer film 106. For example, laser annealing using an excimer laser is used to polycrystallize and activate the amorphous Si region. The TFT formed by the LTPS process has a sufficiently high mobility.

The TFT channel 104 includes regions 104s, 104i, and 104d. The regions 104s, 104i, and 104d are all provided on the TFT underlayer film 106. The region 104i is provided between the region 104s and the region 104d. The regions 104s and 104d are doped with p-type impurities such as boron ions (B ⁺ ) or boron fluoride ions (BF ²⁺ ), and are ohmic-connected to the vias 111s and 111d.

The insulating layer 105 is disposed on the TFT underlayer film 106 and the TFT channel 104. The insulating layer 105 is, for example, _SiO2 . The insulating layer 105 may be a multi-layer insulating layer including _SiO2 , _{Si3N4 ,} etc. depending on the area it covers. The insulating layer 105 is formed thin enough to be optically transparent.

The gate 107 is provided on the TFT channel 104 via an insulating layer 105. The insulating layer 105 is provided to insulate the TFT channel 104 from the gate 107 and to insulate it from other adjacent circuit elements. When a potential lower than that of the region 104s is applied to the gate 107, a channel is formed in the region 104i, making it possible to control the current flowing between the regions 104s and 104d.

The gate 107 may be formed, for example, from polycrystalline Si, or may be formed from a high melting point metal such as W or Mo. When the gate 107 is formed from a polycrystalline Si film, it is formed, for example, by CVD or the like.

The insulating film 108 is provided on the insulating layer 105 and the gate 107. The insulating film 108 is made of an insulating material having optical transparency, and is, for example, an inorganic film such as _SiO2 or _Si3N4 . Preferably, the insulating film ₁₀₈ is _a laminated film of _SiO2 and _Si3N4 . The insulating film 108 is provided to separate adjacent circuit elements such as the transistors 103 from each other. The insulating film 108 provides a surface having a flatness sufficient to allow the formation of the first wiring layer 110.

The first wiring layer 110 is provided on the insulating film 108. The first wiring layer 110 can include multiple wirings that can have different potentials. The first wiring layer 110 includes wirings 110s and 110d. The wirings 110s and 110d are formed separately and can be connected to different potentials.

In the cross-sectional views from Figure 1 onwards, unless otherwise specified, the symbols representing the wiring layers are shown next to the wires that make up that wiring layer.

The wiring 110s is provided above the region 104s. The wiring 110s is connected to the power supply line 3 shown in FIG. 3, which will be described later, for example. The wiring 110d is provided above the region 104d. One end of the via 161d is connected to the wiring 110d. The other end of the via 161d is connected to the second wiring layer 160.

The vias 111s and 111d are provided through the insulating film 108 and the insulating layer 105. The via 111s is provided between the wiring 110s and the region 104s, and electrically connects the wiring 110s and the region 104s. The via 111d is provided between the wiring 110d and the region 104d, and electrically connects the wiring 110d and the region 104d.

The wiring 110s is connected to the region 104s through the via 111s. The region 104s is the source region of the transistor 103. Therefore, the source region of the transistor 103 is electrically connected to, for example, the power line 3 of the circuit of FIG. 3 through the via 111s and the wiring 110s.

Wiring 110d is connected to region 104d through via 111d. Region 104d is the drain region of transistor 103. Therefore, the drain region of transistor 103 is electrically connected to second wiring layer 160 through via 111d, wiring 110d, and via 161d.

The first interlayer insulating film 112 is provided to cover the insulating film 108 and the first wiring layer 110. The first interlayer insulating film 112 is formed of a material having optical transparency. The first interlayer insulating film 112 is formed of, for example, an organic resin, and is an organic transparent resin. The first interlayer insulating film 112 provides a planarized surface 112F for bonding a semiconductor layer having a light-emitting layer, as described in the manufacturing method.

The substrate 102, the TFT lower layer 106, the circuit 101 and the first interlayer insulating film 112 constitute the driving circuit section 100. The light-emitting element 150 is provided on the driving circuit section 100.

The light-emitting element 150 includes a light-emitting surface 151S provided on the planarized surface 112F. The light-emitting element 150 includes an upper surface 153U provided opposite the light-emitting surface 151S. In this example, the outer peripheral shape of the light-emitting surface 151S and the upper surface 153U in the XY plane view is square or rectangular, and the light-emitting element 150 is a prismatic element having the light-emitting surface 151S on the planarized surface 112F. The cross section of the prismatic element may be a polygon having five or more sides. The light-emitting element 150 is not limited to a prismatic element, and may be a cylindrical element.

The light-emitting element 150 includes an n-type semiconductor layer 151, a light-emitting layer 152, and a p-type semiconductor layer 153. The n-type semiconductor layer 151, the light-emitting layer 152, and the p-type semiconductor layer 153 are stacked in this order from the light-emitting surface 151S toward the upper surface 153U. The light-emitting surface 151S, which is the n-type semiconductor layer 151, is provided in contact with the planarized surface 112F. Therefore, the light-emitting element 150 emits light in the negative direction of the Z axis through the first interlayer insulating film 112, the insulating film 108, the insulating layer 105, the TFT lower film 106, and the substrate 102.

The n-type semiconductor layer 151 includes a connection portion 151a. The connection portion 151a is provided so as to protrude in one direction from the n-type semiconductor layer 151 on the planarized surface 112F. The height of the connection portion 151a from the planarized surface 112F is the same as the height of the n-type semiconductor layer 151 from the planarized surface 112F or is lower than the height of the n-type semiconductor layer 151 from the planarized surface 112F. The connection portion 151a is a part of the n-type semiconductor layer 151. The connection portion 151a is connected to one end of a via (second via) 161k, and the n-type semiconductor layer 151 is electrically connected to the via 161k via the connection portion 151a.

When the light emitting element 150 has a prismatic shape, the shape of the light emitting element 150 in the XY plane view is, for example, approximately square or rectangular. When the shape of the light emitting element 150 in the XY plane view is a polygon including a square, the corners of the light emitting element 150 may be rounded. When the shape of the light emitting element 150 in the XY plane view is cylindrical, the shape of the light emitting element 150 in the XY plane view is not limited to a circle, and may be, for example, an ellipse. By appropriately selecting the shape and arrangement of the light emitting element in the planar view, the degree of freedom of the wiring layout, etc. is improved.

For the light emitting element 150, for example, a gallium nitride compound semiconductor including a light emitting layer such as In _x Al _y Ga _1-X-Y N (0≦X, 0≦Y, X+Y<1) is preferably used. Hereinafter, the above-mentioned gallium nitride compound semiconductor may be simply referred to as gallium nitride (GaN). The light emitting element 150 in one embodiment of the present invention is a so-called light emitting diode. The wavelength of light emitted by the light emitting element 150 may be in the range from the near ultraviolet region to the visible light region, for example, about 467 nm±20 nm. The wavelength of light emitted by the light emitting element 150 may be blue-violet light of about 410 nm±20 nm. The wavelength of light emitted by the light emitting element 150 is not limited to the above-mentioned value, and may be any appropriate value.

The second interlayer insulating film 156 covers the planarized surface 112F and the light-emitting element 150. The second interlayer insulating film 156 separates adjacently arranged light-emitting elements 150. By covering the light-emitting element 150, the second interlayer insulating film 156 protects the light-emitting element 150 from the surrounding environment. The surface of the second interlayer insulating film 156 only needs to be flat enough to allow the second wiring layer 160 to be formed on the interlayer insulating film 156.

The second interlayer insulating film 156 is formed of an organic insulating material. The organic insulating material used for the second interlayer insulating film 156 is an insulating material having light reflectivity, and is preferably a white resin. By making the second interlayer insulating film 156 a white resin, it is possible to reflect the upward and lateral emitted light of the light emitting element 150 and the return light caused by the interface between the light emitting surface 151S and the planarized surface 112F, etc. Therefore, the light emitting efficiency of the light emitting element 150 is substantially improved.

The white resin is formed by dispersing scattering particles having a Mie scattering effect in a transparent resin such as a silicon-based resin such as SOG (Spin On Glass) or a novolac-type phenol-based resin. The scattering particles are colorless or white, and have a diameter of about 1/10 to several times the wavelength of the light emitted by the light-emitting element 150. The scattering particles preferably have a diameter of about 1/2 the wavelength of the light. For example, such scattering particles include TiO ₂ , Al ₂ O ₃ , and ZnO.

The white resin can also be formed by utilizing a large number of fine voids dispersed in a transparent resin. When the first interlayer insulating film 112 is whitened, a SiO ₂ film formed by ALD (Atomic-Layer-Deposition) or CVD may be used in combination with SOG or the like.

The second interlayer insulating film 156 may be a black resin. By making the second interlayer insulating film 156 a black resin, scattering of light within the subpixel 20 is suppressed, and stray light is more effectively suppressed. An image display device in which stray light is suppressed is capable of displaying sharper images.

The second wiring layer 160 is provided on the second interlayer insulating film 156. The second wiring layer 160 can include multiple wirings that can have different potentials. The second wiring layer 160 includes wirings 160k and 160a. The wirings 160k and 160a are formed separately and can be connected to different potentials.

A part of the wiring 160k is provided above the connection portion 151a. Another part of the wiring 160k is connected to, for example, the ground line 4 of the circuit in FIG. 3. A part of the wiring 160a is provided above the upper surface 153U. The upper surface 153U is connected to the wiring 160a by a connection member 161a. Another part of the wiring 160a is provided above the wiring 110d.

The via (first via) 161d is provided so as to penetrate the second interlayer insulating film 156 and the first interlayer insulating film 112 and reach the wiring 110d. The via 161d is provided between the wiring (first wiring) 160a and the wiring 110d, and electrically connects the wiring 160a and the wiring 110d. Therefore, the p-type semiconductor layer 153 is electrically connected to the drain region of the transistor 103 via the connection member 161a, the wiring 160a, the via 161d, the wiring 110d, and the via 111d.

The via (second via) 161k is provided so as to penetrate the second interlayer insulating film 156 and reach the connection portion 151a. The via 161k is provided between the wiring (second wiring) 160k and the connection portion 151a, and connects the wiring 160k and the connection portion 151a. Therefore, the n-type semiconductor layer 151 is electrically connected to, for example, the ground line 4 of the circuit in FIG. 3 via the connection portion 151a, the via 161k, and the wiring 160k.

The wiring layer 110 and the vias 111s, 111d, and 161k are formed, for example, from Al, an alloy of Al, or a laminated film of Al and Ti. For example, in a laminated film of Al and Ti, Al is laminated on a thin film of Ti, and Ti is further laminated on the Al.

In order to protect them from the external environment, a protective layer that covers them may be provided over the second interlayer insulating film 156 and the second wiring layer 160. In this case, it is preferable that the protective layer is a layer that has light reflectivity, and for example, this protective layer is formed of a white resin.

FIG. 2 is a schematic cross-sectional view illustrating a part of an image display device according to a modified example of this embodiment.
2, the shapes of the wirings 110s1 and 110d1 constituting the first wiring layer 110 are different from those in the first embodiment. The other components are the same as those in the first embodiment. The same components are denoted by the same reference numerals and detailed descriptions thereof will be omitted as appropriate.
As shown in Fig. 2, the image display device of the modified example includes a subpixel 20a. The subpixel 20a includes a first wiring layer 110. The first wiring layer 110 includes wirings 110s1 and 110d1. The wiring 110s1 is connected to a source region of a transistor 103 through a via 111s, and is connected to, for example, a power supply line 3 of the circuit in Fig. 3 described below. The wiring 110d1 is connected to a drain region of the transistor through a via 111d, and is also connected to a wiring 160a through a via 161d.

In addition to the circuit connection function, the wiring 110s1 and 110d1 have a light-shielding function to prevent the transistor 103 from malfunctioning. That is, the wiring 110s1 and the wiring 110d1 are provided to cover the TFT channel 104 of the transistor 103, and block light from the light-emitting element 150. The wiring 110s1 and 110d1 cover most of the TFT channel 104, thereby preventing the light emitted from the light-emitting element 150 from reaching the TFT channel 104 by the wiring 110s1 and 110d1. Therefore, it is possible to prevent the transistor 103 from malfunctioning due to light irradiation. The wiring 110s1 and 110d1 are not limited to the case where the wiring 110s1 and 110d1 shields the TFT channel 104 by these two wiring shapes as in this example, but may also shield the TFT channel 104 by the shape of either the wiring 110s1 or 110d1.

FIG. 3 is a schematic block diagram illustrating the image display device according to the present embodiment.
3, the image display device 1 of this embodiment includes a display area 2. Sub-pixels 20 are arranged in the display area 2. The sub-pixels 20 are arranged, for example, in a lattice pattern. For example, n sub-pixels 20 are arranged along the X axis, and m sub-pixels 20 are arranged along the Y axis.

The image display device 1 further includes a power supply line 3 and a ground line 4. The power supply line 3 and the ground line 4 are laid out in a grid pattern along the arrangement of the subpixels 20. The power supply line 3 and the ground line 4 are electrically connected to each subpixel 20, and supply power to each subpixel 20 from a DC power supply connected between the power supply terminal 3a and the GND terminal 4a. The power supply terminal 3a and the GND terminal 4a are provided at the ends of the power supply line 3 and the ground line 4, respectively, and are connected to a DC power supply circuit provided outside the display area 2. A positive voltage is supplied to the power supply terminal 3a with respect to the GND terminal 4a.

The image display device 1 further includes scanning lines 6 and signal lines 8. The scanning lines 6 are arranged in a direction parallel to the X-axis. In other words, the scanning lines 6 are arranged along the row direction of the subpixels 20. The signal lines 8 are arranged in a direction parallel to the Y-axis. In other words, the signal lines 8 are arranged along the column direction of the subpixels 20.

The image display device 1 further includes a row selection circuit 5 and a signal voltage output circuit 7. The row selection circuit 5 and the signal voltage output circuit 7 are provided along the outer edge of the display area 2. The row selection circuit 5 is provided along the Y-axis direction of the outer edge of the display area 2. The row selection circuit 5 is electrically connected to the sub-pixels 20 of each column via the scanning lines 6, and supplies a selection signal to each sub-pixel 20.

The signal voltage output circuit 7 is provided along the X-axis direction on the outer edge of the display area 2. The signal voltage output circuit 7 is electrically connected to the subpixels 20 in each row via signal lines 8, and supplies a signal voltage to each subpixel 20.

The subpixel 20 includes a light-emitting element 22, a selection transistor 24, a drive transistor 26, and a capacitor 28. In FIG. 3 and FIG. 4 described below, the selection transistor 24 may be labeled T1, the drive transistor 26 may be labeled T2, and the capacitor 28 may be labeled Cm.

The light-emitting element 22 is connected in series with the driving transistor 26. In this embodiment, the driving transistor 26 is a p-channel TFT, and the anode electrode of the light-emitting element 22 is connected to the drain electrode of the driving transistor 26. The main electrodes of the driving transistor 26 and the selection transistor 24 are the drain electrode and the source electrode. The anode electrode of the light-emitting element 22 is connected to the p-type semiconductor layer. The cathode electrode of the light-emitting element 22 is connected to the n-type semiconductor layer. The series circuit of the light-emitting element 22 and the driving transistor 26 is connected between the power supply line 3 and the ground line 4. The driving transistor 26 corresponds to the transistor 103 in FIG. 1, and the light-emitting element 22 corresponds to the light-emitting element 150 in FIG. 1. The current flowing through the light-emitting element 22 is determined by the voltage applied between the gate and source of the driving transistor 26, and the light-emitting element 22 emits light with a brightness according to the current flowing through it.

The selection transistor 24 is connected between the gate electrode of the drive transistor 26 and the signal line 8 via a main electrode. The gate electrode of the selection transistor 24 is connected to the scanning line 6. A capacitor 28 is connected between the gate electrode of the drive transistor 26 and the power line 3.

The row selection circuit 5 selects one row from an array of m rows of subpixels 20 and supplies a selection signal to the scanning line 6. The signal voltage output circuit 7 supplies a signal voltage having a required analog voltage value to each subpixel 20 in the selected row. A signal voltage is applied between the gate and source of the drive transistor 26 of the subpixel 20 in the selected row. The signal voltage is held by a capacitor 28. The drive transistor 26 passes a current according to the signal voltage to the light-emitting element 22. The light-emitting element 22 emits light with a brightness according to the current that has passed through it.

The row selection circuit 5 sequentially switches the selected row and supplies a selection signal. That is, the row selection circuit 5 scans the rows in which the subpixels 20 are arranged. A current corresponding to the signal voltage flows through the light-emitting elements 22 of the sequentially scanned subpixels 20, causing them to emit light. The luminance of the subpixels 20 is determined by the current flowing through the light-emitting elements 22. The subpixels 20 emit light at a gradation based on the determined luminance, and an image is displayed in the display area 2.

FIG. 4 is a schematic plan view illustrating a part of the image display device of this embodiment.
In Fig. 4, line AA' represents a cutting line in the cross-sectional view of Fig. 1 etc. In this embodiment, the light-emitting element 150 and the driving transistor 103 are stacked in the Z-axis direction via a first interlayer insulating film 112 and a second interlayer insulating film 156. The light-emitting element 150 corresponds to the light-emitting element 22 in Fig. 3. The driving transistor 103 corresponds to the driving transistor 26 in Fig. 3 and is also denoted as T2.

As shown in FIG. 4, the anode electrode of the light-emitting element 150 is provided by the p-type semiconductor layer 153 shown in FIG. 1. A connection member 161a is provided on the upper surface 153U of the p-type semiconductor layer 153. The p-type semiconductor layer 153 is connected to the wiring 160a via the connection member 161a. The wiring 160a is connected to the via 161d by the contact hole 161d1, and the wiring 160a is connected to the wiring 110d provided in the lower layer via the via 161d.

The wiring 110d is connected to the drain electrode of the transistor 103 through the via 111d shown in FIG. 1. The drain electrode of the transistor 103 is part of the TFT channel 104, and is the region 104d shown in FIG. 1. The source electrode of the transistor 103 is connected to the wiring 110s through the via 111s shown in FIG. 1. The source electrode of the transistor 103 is the region 104s shown in FIG. 1. In this example, the first wiring layer 110 includes the power line 3, and the wiring 110s is connected to the power line 3.

The cathode electrode of the light-emitting element 150 is provided by the connection portion 151a. The connection portion 151a is provided in a layer above the transistor 103 and the wiring layer 110. The connection portion 151a is electrically connected to the wiring 160k through the via 161k. More specifically, one end of the via 161k is connected to the connection portion 151a. The other end of the via 161k is connected to the wiring 160k through the contact hole 161k1. The wiring 160k is connected to the ground line 4.

In this way, the light emitting element 150 can electrically connect the first wiring layer 110, which is provided below the light emitting element 150, to the second wiring layer 160 by using the via 161d. The light emitting element 150 can electrically connect the connection portion 151a, which is provided below the second wiring layer 160, to the second wiring layer 160 by using the via 161k.

A method for manufacturing the image display device 1 of this embodiment will be described.
5A to 8B are schematic cross-sectional views illustrating a part of the method for manufacturing the image display device of this embodiment.
As shown in Fig. 5A, in the manufacturing method of the image display device 1 of this embodiment, a substrate 102 is prepared. A TFT lower layer film 106 is formed on the first surface 102a. The TFT lower layer film 106 is formed, for example, by a CVD method. A Si layer 1104 is formed on the formed TFT lower layer film 106. The Si layer 1104 is an amorphous Si layer when formed, and after formation, the Si layer 1104 is polycrystallized by, for example, scanning an excimer laser pulse multiple times to form the Si layer 1104.

As shown in FIG. 5B, the transistor 103 is formed at a predetermined position on the TFT underlayer film 106. For example, in the LTPS process, the transistor 103 is formed as follows.

The polycrystallized Si layer 1104 shown in FIG. 5A is processed into an island shape at a predetermined position and in a predetermined shape to form the TFT channel 104. For example, the predetermined position and the predetermined shape are the position and shape of the TFT channel 104 shown in FIG. 4. An insulating layer 105 is formed so as to cover the TFT underlayer film 106 and the TFT channel 104. The insulating layer 105 functions as a gate insulating film. A gate 107 is formed on the TFT channel 104 through the insulating layer 105. The transistor 103 is formed by selectively doping the gate 107 with impurities such as B ⁺ and thermally activating it. The regions 104s and 104d are p-type active regions and function as the source region and drain region of the transistor 103, respectively. The region 104i is an n-type active region and functions as a channel.

6, the insulating film 108 is formed to cover the insulating layer 105 and the gate 107. The insulating film 108 is formed by a suitable manufacturing method depending on the material of the insulating film 108. For example, when the insulating film 108 is made of _SiO2 , a technique such as ALD or CVD is used.

The flatness of the insulating film 108 needs to be sufficient to form the first wiring layer 110, and a flattening process does not necessarily have to be performed. If a flattening process is not performed on the insulating film 108, the number of steps required for the flattening process can be reduced.

Vias 111s and 111d are formed through insulating film 108 and insulating layer 105. Via 111s is formed to reach region 104s. Via 111d is formed to reach region 104d. RIE, for example, is used to form via holes for forming vias 111s and 111d.

The first wiring layer 110 including the wirings 110s and 110d is formed on the insulating film 108. The wiring 110s is connected to one end of the via 111s. The wiring 110d is connected to one end of the via 111d. The first wiring layer 110 may be formed simultaneously with the formation of the vias 111s and 111d.

The first interlayer insulating film (first insulating film) 112 is formed to cover the insulating film 108 and the first wiring layer 110. The surface of the first interlayer insulating film 112 is planarized by chemical mechanical polishing (CMP) or the like to form a planarized surface 112F.

In this manner, the drive circuit section (first substrate) 100 is formed. In this example, the drive circuit section 100 includes a substrate 102. The manufacturing process for the drive circuit section 100 may be performed in a plant separate from the wafer bonding process described below, or may be performed in the same plant as the wafer bonding process.

As shown in FIG. 7A, a semiconductor growth substrate 1194 is prepared. The semiconductor growth substrate 1194 includes a crystal growth substrate 1001 and a semiconductor layer 1150. The crystal growth substrate 1001 is, for example, a Si substrate or a sapphire substrate. Preferably, a Si substrate is used as the crystal growth substrate 1001. In addition, when a low-temperature crystal growth process such as a low-temperature sputtering method is used, it is also possible to use a less expensive glass substrate or the like.

The semiconductor layer 1150 is formed on the crystal growth substrate 1001. The semiconductor layer 1150 includes an n-type semiconductor layer 1151, an emission layer 1152, and a p-type semiconductor layer 1153. The n-type semiconductor layer 1151, the emission layer 1152, and the p-type semiconductor layer 1153 are stacked in this order from the crystal growth substrate 1001 side.

The semiconductor layer 1150 is formed, for example, by a CVD method, preferably a metal organic chemical vapor deposition (MOCVD) method. Alternatively, epitaxial crystal growth of the semiconductor layer 1150 is possible even at a process temperature of 700°C or less by using a low-temperature sputtering method. By using such a low-temperature sputtering method, it becomes possible to use a glass substrate or device with low heat resistance, thereby reducing manufacturing costs.

The semiconductor layer 1150 includes, for example, GaN, and more specifically, includes _{InxAlyGa1 -XYN (} 0≦X, 0≦Y, X+Y<1), or the like.

In the early stages of crystal growth, crystal defects may occur due to mismatches in the crystal lattice constants, and crystals with crystal defects exhibit n-type. Therefore, as in this example, when the semiconductor layer 1150 is formed from an n-type semiconductor layer 1151 on the crystal growth substrate 1001, a large margin can be taken in the production process, which has the advantage of making it easier to improve yields.

When forming the semiconductor layer 1150 on the crystal growth substrate 1001, the semiconductor layer 1150 may be formed via a buffer layer (not shown in FIG. 7A). The buffer layer may be made of a nitride such as AlN. By growing the semiconductor layer 1150 on the crystal growth substrate 1001 via a buffer layer, the mismatch at the interface between the GaN crystal and the crystal growth substrate 1001 can be alleviated. Therefore, it is expected that the quality of the semiconductor crystal of the semiconductor layer 1150 will be improved. On the other hand, in this embodiment, as shown in FIG. 8A described later, the n-type semiconductor layer 1151 is bonded to the planarized surface 112F, so a process of removing the buffer layer before bonding is added. This is the same for the other embodiments described later.

As shown in FIG. 7B, a support substrate (second substrate) 1190 is prepared. The support substrate 1190 is formed of, for example, quartz glass or Si. The semiconductor growth substrate 1194 is disposed so that the semiconductor layer 1150 formed on the semiconductor growth substrate 1194 faces the support substrate 1190. The exposed surface 1153E of the p-type semiconductor layer 1153 of the semiconductor layer 1150 is bonded to one surface 1190E of the support substrate 1190.

As shown in FIG. 8A, after the support substrate 1190 is bonded to the semiconductor layer 1150, the crystal growth substrate 1001 shown in FIG. 7B is removed to form the substrate 1195. The crystal growth substrate 1001 is removed by, for example, wet etching or laser lift-off.

The semiconductor layer 1150 of the substrate 1195 is bonded to the planarized surface 112F of the drive circuit section (first substrate) 100. The surface bonded to the planarized surface 112F is the exposed surface 1151E of the n-type semiconductor layer 1151. Thereafter, as shown in FIG. 8B, the support substrate 1190 is removed. The support substrate 1190 is also removed by wet etching or laser lift-off.

In the process of bonding the substrates, for example, the substrates are bonded together by heating and thermocompression bonding the substrates. In addition to the above, the bonding surfaces of the substrates may be further planarized using CMP or the like, and then the bonding surfaces may be cleaned by plasma treatment in a vacuum to adhere to each other.

When bonding the semiconductor layer 1150 to the drive circuit section 100, one semiconductor layer 1150 may be bonded to one drive circuit section 100, or multiple semiconductor layers 1150 may be bonded to one drive circuit section 100. When bonding one semiconductor layer 1150 to one drive circuit section 100, the size of the substrate 102 constituting the drive circuit section 100 may be, for example, a rectangular or square shape of about several tens of mm square to about 150 mm square. In this case, the semiconductor layer 1150 formed on the substrate 1195 may be sized according to the size of the substrate 102.

When multiple semiconductor layers 1150 are bonded to one drive circuit section 100, the substrate 102 constituting the drive circuit section 100 can be, for example, a roughly rectangular glass substrate of about 1500 mm x 1800 mm. The semiconductor layer 1150 formed on the substrate 1195 can be rectangular or square with a size of about 10 mm square to 150 mm square, and can be, for example, about 4 inches to 6 inches in wafer size. The size of the substrate 102 is appropriately selected depending on the size of the image display device, etc.

FIG. 9 is a perspective view illustrating a part of the method for manufacturing the image display device of this embodiment.
FIG. 9 is a schematic diagram showing an example in which a plurality of semiconductor layers 1150 are attached to one driver circuit portion 100 .
The diagram above the arrow in Fig. 9 shows that a plurality of substrates 1195 are arranged in a lattice pattern. The diagram below the arrow in Fig. 9 shows that a drive circuit section 100 having a planarized surface 112F formed thereon is arranged. Fig. 9 shows by the arrow that a plurality of substrates 1195 arranged in a lattice pattern are bonded together at the position of the two-dot chain line.

Since the quality of the semiconductor crystal deteriorates at and near the ends of the semiconductor layer 1150, care must be taken to avoid forming the light emitting element 150 at and near the ends of the semiconductor layer 1150.
As shown in Fig. 9, the ends of the semiconductor layer 1150 are formed so as to substantially coincide with the ends of the support substrate 1190. Therefore, the multiple substrates 1195 are arranged facing the drive circuit section 100 in a lattice pattern, for example, as shown by the solid line in Fig. 9, so as to minimize gaps between adjacent substrates 1195. The semiconductor layer 1150 is bonded onto the planarized surface 112F of the drive circuit section 100, as shown by the two-dot chain line in Fig. 9.

When multiple semiconductor layers 1150 are bonded to one driving circuit section 100, in a subsequent process, the driving circuit section 100 to which the multiple semiconductor layers 1150 are bonded can be divided together with the substrate 102 to produce image display devices of a quantity and size according to the number of divisions. Since it is preferable that the end of the semiconductor layer 1150 where the quality of the semiconductor crystal has deteriorated becomes the end of the display area, the unit of division is preferably set to match the shape of the substrate 1195.

In the manufacturing process of wafer bonding, the process leading up to the formation of semiconductor growth substrate 1194 and the process of processing after substrate 1195 is formed may be performed in the same plant or in different plants. For example, substrate 1195 may be manufactured in a first plant, and substrate 1195 may be transported to a second plant different from the first plant to perform the bonding process.

The method of bonding the semiconductor layer 1150 to the substrate 102 is not limited to the above, and the following method can also be used. That is, after the semiconductor layer 1150 is formed on the crystal growth substrate 1001, it is stored in a container, and for example, a support substrate 1190 is attached to it in the container and stored. After storage, the semiconductor layer 1150 is taken out of the container and bonded to the drive circuit section 100. Alternatively, the semiconductor layer 1150 is stored in the container without being attached to the support substrate 1190. After storage, the semiconductor layer 1150 is taken out of the container and bonded to the drive circuit section 100 as is.

10A and 10B are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device of this embodiment.
As shown in Fig. 10A, the semiconductor layer 1150 shown in Fig. 8B is processed into a predetermined shape by etching to form the light emitting element 150. In the process of forming the light emitting element 150, the connection portion 151a is formed, and then other portions are formed by further etching. This makes it possible to form the light emitting element 150 having the connection portion 151a that protrudes in one direction from the n-type semiconductor layer 151 on the planarized surface 112F. The light emitting element 150 is formed, for example, by a dry etching process, and preferably by anisotropic plasma etching (Reactive Ion Etching, RIE).

The second interlayer insulating film (second insulating film) 156 is formed to cover the planarized surface 112F and the light-emitting element 150.

As shown in FIG. 10B, via (first via) 161d is formed by filling a via hole that penetrates second interlayer insulating film 156 and first interlayer insulating film 112 and reaches wiring 110d with a conductive material. Via (second via) 161k is formed by filling a via hole that penetrates second interlayer insulating film 156 and reaches connection portion 151a with a conductive material. Connection member 161a is formed by filling a contact hole that is formed to reach upper surface 153U with a conductive material. For example, RIE or the like is used to form the via holes and contact holes.

The second wiring layer 160 including the wirings 160a and 160k is formed on the second interlayer insulating film 156. The wiring 160a is connected to the connection member 161a and one end of the via 161d. The wiring 160k is connected to one end of the via 161k. The second wiring layer 160 may be formed simultaneously with the formation of the vias 161k and 161d and the connection member 161a.

In the case of the subpixel 20a of the modified embodiment of this invention, in the process of forming the first wiring layer 110, the wirings 110s1 and 110d1 are shaped to cover the TFT channel 104. After the first wiring layer 110 is formed, the subpixel 20a shown in FIG. 2 is formed by the same manufacturing process as in the first embodiment described above.

In this way, subpixels 20 and 20a are formed, and an image display device is formed.

FIG. 11 is a schematic perspective view illustrating an image display device according to this embodiment.
11, in the image display device of this embodiment, a light-emitting circuit section 172 having a large number of light-emitting elements 150 is provided on a planarized surface 112F of a drive circuit section 100. The light-emitting circuit section 172 is a structure including the light-emitting elements 150, a second interlayer insulating film 156 covering the light-emitting elements 150, and a second wiring layer 160. As described above, the light-emitting circuit section 172 and the drive circuit section 100 are electrically connected by the vias 161d shown in FIG. 1 and the like.

The configuration shown in FIG. 11 is an example in which a color filter is not provided, and is applied to other embodiments described later in which a color filter is not provided. In addition, a color filter can be provided in this embodiment by applying the third embodiment shown in FIG. 19 and the fifth embodiment shown in FIG. 31 described later.

The effects of the image display device 1 of this embodiment will be described.
In the manufacturing method of the image display device 1 of this embodiment, after the semiconductor layer 1150 is bonded onto the planarized surface 112F of the drive circuit section 100, the semiconductor layer 1150 is etched to form the light emitting element 150. Thereafter, the light emitting element 150 is covered with a second interlayer insulating film 156, and a second wiring layer 160 that provides electrical connection with the first wiring layer 110 and an external circuit is formed. Therefore, the manufacturing process is significantly shortened compared to the case where the individual light emitting elements are individually transferred onto the planarized surface 112F.

For example, in an image display device with 4K image quality, the number of subpixels exceeds 24 million, and in the case of an image display device with 8K image quality, the number of subpixels exceeds 99 million. Forming such a large number of light-emitting elements individually and mounting them on a circuit board would require an enormous amount of time. For this reason, it is difficult to realize an image display device using micro LEDs at a realistic cost. Furthermore, if a large number of light-emitting elements are mounted individually, the yield will decrease due to poor connections during mounting, and further increases in costs will be unavoidable. However, the manufacturing method for the image display device of this embodiment provides the following effects.

As described above, in the manufacturing method of the image display device 1 of this embodiment, the entire semiconductor layer 1150 is bonded to the planarized surface 112F, and then the light-emitting element is formed by etching, so the transfer process of the light-emitting element is completed in one step. Therefore, in the manufacturing method of the image display device 1 of this embodiment, the time for the transfer process can be shortened and the number of steps can be reduced compared to conventional manufacturing methods.

Furthermore, the semiconductor layer 1150 is bonded to the planarized surface 112F at the wafer level without dividing the semiconductor layer 1150 in advance or forming electrodes at positions corresponding to the circuit elements. This eliminates the need for alignment during the bonding stage. This makes it possible to easily perform the bonding process in a short time. Since alignment is not required during bonding, the light-emitting element 150 can be easily miniaturized, making it suitable for high-definition displays.

In this embodiment, the drive circuit unit 100 can include a drive circuit including TFTs and a scanning circuit. By using an LTPS process or the like, the circuit 101 that constitutes the drive circuit unit 100 can be fabricated on a light-transmitting substrate such as a glass substrate, which has the advantage of being able to utilize existing manufacturing processes and plants for flat panel displays.

In this embodiment, the light emitting element 150 is formed in a layer above the transistor 103, etc. The light emitting element 150 formed in different layers and the circuit 101 including the transistor 103, etc. can be connected to each other by forming a via 161d that penetrates the second interlayer insulating film 156 and the first interlayer insulating film 112. By using this technically established multilayer wiring technology, a uniform connection structure can be easily realized and the yield can be improved. Therefore, a decrease in yield due to poor connection of the light emitting element, etc. is suppressed.

In the image display device 1 of this embodiment, the light output from the light-emitting surface 151S is radiated to the outside of the image display device 1 via an optical path including the first interlayer insulating film 112, the insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the substrate 102. The total thickness of the first interlayer insulating film 112, the insulating film 108, the insulating layer 105, and the TFT lower layer film 106 may range, for example, from about 1 μm to several μm. In other words, the light output from the light-emitting surface 151S is radiated to the outside via an optical path of about 1 μm to several μm. Therefore, the light output from the light-emitting surface 151S is attenuated according to the length of the optical path more than when it is directly radiated to the outside.

In this embodiment, the light-emitting element 150 is covered by the second interlayer insulating film 156 except for the light-emitting surface 151S. By forming the second interlayer insulating film 156 from a highly light-reflective material such as white resin, it is possible to reflect scattered light toward the upper surface 153U and sides of the light-emitting element 150, thereby preventing light from leaking above or to the sides of the light-emitting element 150.

In this way, in the image display device of this embodiment, the light emitting element 150 is covered with the second interlayer insulating film 156, and light traveling in a direction other than the light emitting surface 151S can be confined within the light emitting element 150. The light confined within the light emitting element 150 is reflected at the interface between the light emitting element 150 and the second interlayer insulating film 156, and a portion of the light is guided toward the light emitting surface 151S. Therefore, the light emitting element 150 has an improved effective light emission efficiency, has a long optical path from the light emitting surface 151S to the outside, and can radiate light of sufficient intensity to the outside even if the light intensity is attenuated.

In this embodiment, as described above, light of sufficient intensity is output from the light-emitting surface 151S, so that if the output light is irradiated onto the TFT channel 104, the transistor 103 may malfunction. In the image display device of this modified example, the wiring 110s1, 110d1 is arranged to cover the TFT channel 104. Therefore, most of the light output from the light-emitting surface 151S is blocked by the wiring 110s1, 110d1, and the light output from the light-emitting surface 151S is unlikely to reach the TFT channel 104. Therefore, malfunction of the transistor 103 due to irradiation with light is suppressed.

Second Embodiment
FIG. 12 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment.
12, the image display device of this embodiment includes a subpixel 220, which differs from the other embodiments described above in that the p-type semiconductor layer 253 provides a light-emitting surface 253S. In this embodiment, the configuration of the transistor 203 that drives the light-emitting element 250 is also different. The same components as those in the other embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

The subpixel 220 of the image display device of this embodiment includes a substrate 102, a transistor 203, a first wiring layer 110, a first interlayer insulating film 112, a light-emitting element 250, a second interlayer insulating film 156, a via 161d, and a second wiring layer 160.

The transistor 203 is provided on the TFT lower layer film 106. The transistor 203 is an n-channel TFT. The transistor 203 includes a TFT channel 204 and a gate 107. Preferably, the transistor 203 is formed by an LTPS process or the like, as in the other embodiments described above. In this embodiment, the circuit 101 includes the TFT channel 204, the insulating layer 105, the insulating film 108, the vias 111s, 111d, and the first wiring layer 110.

The TFT channel 204 includes regions 204s, 204i, and 204d. The regions 204s, 204i, and 204d are provided on the TFT lower layer film 106. The regions 204s and 204d are doped with n-type impurities such as phosphorus ions (P ⁻ ). The region 204s is in ohmic contact with the via 111s. The region 204d is in ohmic contact with the via 111d.

The gate 107 is provided on the TFT channel 204 via an insulating layer 105. The insulating layer 105 insulates the TFT channel 204 from the gate 107.

In the transistor 203, when a voltage higher than that of the region 204s is applied to the gate 107, a channel is formed in the region 204i. The current flowing between the regions 204s and 204d is controlled by the voltage of the gate 107 to the region 204s. The TFT channel 204 and the gate 107 are formed of the same material and by the same manufacturing method as the TFT channel 104 and the gate 107 in the other embodiments described above. The insulating layer 105 and the gate 107 are covered with the insulating film 108 as in the other embodiments described above, and the first wiring layer 110 is provided on the insulating film 108.

The first wiring layer 110 includes wirings 110s and 110d. Wiring 110s is provided above region 204s. Wiring 110s is connected to a ground line 4 shown in FIG. 13, which will be described later, for example. Wiring 110d is provided above region 204d. As in the other embodiments described above, wiring 110d is connected to via 161d, and is electrically connected to the second wiring layer 160 through via 161d.

The via 111s is provided between the wiring 110s and the region 204s, and electrically connects the wiring 110s and the region 204s. The via 111d is provided between the wiring 110d and the region 204d, and electrically connects the wiring 110d and the region 204d. The vias 111s and 111d are formed of the same material and by the same manufacturing method as in the other embodiments described above.

The first interlayer insulating film 112 is provided to cover the insulating film 108 and the first wiring layer 110, as in the other embodiments described above, and includes a planarized surface 112F.

The light-emitting element 250 is provided on the planarized surface 112F. The light-emitting element 250 includes a light-emitting surface 253S provided on the planarized surface 112F. The light-emitting surface 253S is in contact with the planarized surface 112F. The light-emitting element 250 includes an upper surface 251U provided opposite the light-emitting surface 253S. The light-emitting element 250 is a prismatic or cylindrical element, as in the other embodiments described above.

The light-emitting element 250 includes a p-type semiconductor layer 253, a light-emitting layer 252, and an n-type semiconductor layer 251. The p-type semiconductor layer 253, the light-emitting layer 252, and the n-type semiconductor layer 251 are stacked in this order from the light-emitting surface 253S toward the upper surface 251U. In this embodiment, the light-emitting surface 253S is provided by the p-type semiconductor layer 253.

The light-emitting element 250 includes a connection portion 253a. The connection portion 253a is provided so as to protrude in one direction from the p-type semiconductor layer 253 on the planarized surface 112F. The height of the connection portion 253a from the planarized surface 112F is the same as or lower than the height of the p-type semiconductor layer 253 from the planarized surface 112F. The connection portion 253a is a part of the p-type semiconductor layer 253. The connection portion 253a is connected to one end of the via 261a, and the p-type semiconductor layer 253 is electrically connected to the second wiring layer 160 via the via 261a.

The light-emitting element 250 has a shape in the XY plane view similar to that of the other embodiments described above. An appropriate shape is selected depending on the layout of the circuit elements, etc.

The light-emitting element 250 is a light-emitting diode similar to the other embodiments described above. That is, the wavelength of the light emitted by the light-emitting element 250 is, for example, blue light of about 467 nm±20 nm, or blue-violet light of about 410 nm±20 nm. The wavelength of the light emitted by the light-emitting element 250 is not limited to the above values and can be any appropriate value.

As in the other embodiments described above, the second interlayer insulating film 156 is provided to cover the planarized surface 112F and the light emitting element 250. A second wiring layer 160 is provided on the second interlayer insulating film 156.

The second wiring layer 160 includes wirings 260a and 260k. The wirings 260a and 260k are formed separately and can be connected to different potentials. A part of the wiring 260a is provided above the connection portion 253a. The other part of the wiring 260a is connected to the power supply line 3 of the circuit in FIG. 13, which will be described later, for example. A part of the wiring 260k is provided above the upper surface 251U. A connection member 261k is provided between the wiring 260k and the upper surface 251U, and the upper surface 251U is connected to the wiring 260k by the connection member 261k. The other part of the wiring 260k is provided above the wiring 110d.

The via 161d is provided between the wiring 260k and the wiring 110d, and electrically connects the wiring 260k and the wiring 110d. Therefore, the n-type semiconductor layer 251 is electrically connected to the drain region of the transistor 203 via the connection member 261k, the wiring 260k, the via 161d, the wiring 110d, and the via 111d.

The via 261a is provided so as to penetrate the second interlayer insulating film 156 and reach the connection portion 253a. The via 261a is provided between the wiring 260a and the connection portion 253a, and electrically connects the wiring 260a and the connection portion 253a. Therefore, the p-type semiconductor layer 253 is electrically connected to, for example, the power supply line 3 of the circuit in FIG. 13 via the connection portion 253a, the via 261a, and the wiring 260a.

FIG. 13 is a schematic block diagram illustrating an image display device according to this embodiment.
13, an image display device 201 of this embodiment includes a display area 2, a row selection circuit 205, and a signal voltage output circuit 207. In the display area 2, as in the other embodiments described above, for example, sub-pixels 220 are arranged in a lattice pattern on the XY plane.

The subpixel 220 includes a light emitting element 222, a selection transistor 224, a drive transistor 226, and a capacitor 228. In FIG. 13, the selection transistor 224 may be labeled T1, the drive transistor 226 may be labeled T2, and the capacitor 228 may be labeled Cm.

In this embodiment, the light-emitting element 222 is provided on the power supply line 3 side, and the drive transistor 226 connected in series to the light-emitting element 222 is provided on the ground line 4 side. In other words, the drive transistor 226 is connected to a lower potential side than the light-emitting element 222. The drive transistor 226 is an n-channel transistor.

The selection transistor 224 is connected between the gate electrode of the driving transistor 226 and the signal line 208. The capacitor 228 is connected between the gate electrode of the driving transistor 226 and the ground line 4.

The row selection circuit 205 and the signal voltage output circuit 207 supply a signal voltage of a different polarity to the signal line 208 in order to drive the drive transistor 226, which is an n-channel transistor.

In this embodiment, the polarity of the drive transistor 226 is n-channel, and therefore the polarity of the signal voltage, etc., differs from the other embodiments described above. That is, the row selection circuit 205 supplies a selection signal to the scanning line 206 to sequentially select one row from the array of m rows of subpixels 220. The signal voltage output circuit 207 supplies a signal voltage having a required analog voltage value to each subpixel 220 of the selected row. The drive transistor 226 of the subpixel 220 of the selected row passes a current corresponding to the signal voltage to the light-emitting element 222. The light-emitting element 222 emits light with a brightness corresponding to the current that has passed through it.

The manufacturing method of the image display device of this embodiment will be described.

14A to 15 are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device of this embodiment.
As shown in Figure 14A, a semiconductor growth substrate 1194 is provided. The semiconductor growth substrate 1194 has the configuration described in connection with Figure 7A.

As shown in FIG. 14B, the semiconductor layer 1150 of the semiconductor growth substrate 1194 is bonded to the drive circuit section 100. In this bonding process, the exposed surface 1153E of the p-type semiconductor layer 1153 is bonded to the planarized surface 112F.

As shown in FIG. 15, after the semiconductor layer 1150 is bonded to the planarized surface 112F, the crystal growth substrate 1001 is removed. The crystal growth substrate 1001 is removed by wet etching or laser lift-off.

16A to 17B are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device of this embodiment.
The steps shown in Figures 16A to 17B are applied in place of the steps shown in Figures 14A to 15. In the steps shown in Figures 16A to 17B, the semiconductor layer 1150 is transferred to a support substrate 1190, and then the support substrate 1190 is bonded to the drive circuit section 100.

As shown in FIG. 16A, a semiconductor growth substrate 1294 is prepared. The semiconductor growth substrate 1294 has a different configuration from the semiconductor growth substrate 1194 shown in FIG. 7A and FIG. 14A. In the semiconductor growth substrate 1294, the semiconductor layer 1150 is stacked in the order of p-type semiconductor layer 1153, light-emitting layer 1152, and n-type semiconductor layer 1151 from the crystal growth substrate 1001 side.

As shown in FIG. 16B, a support substrate 1190 is prepared. The exposed surface 1151E of the n-type semiconductor layer 1151 of the semiconductor layer 1150 is bonded to one surface 1190E of the support substrate 1190.

As shown in FIG. 17A, the substrate 1295 is bonded to the drive circuit section 100. The substrate 1295 is a substrate in which the semiconductor layer 1150 is bonded onto the support substrate 1190. The bonding surface with the planarized surface 112F is the exposed surface 1153E of the p-type semiconductor layer 1153.

As shown in FIG. 17B, the support substrate 1190 is removed. As in the other embodiments described above, wet etching or laser lift-off is used to remove the support substrate 1190. In this manner, the semiconductor layer 1150 can be bonded to the drive circuit section 100.

18A and 18B are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device of this embodiment.
As shown in Fig. 18A, the semiconductor layer 1150 shown in Fig. 15 or 17B is processed into a predetermined shape to form the light emitting element 250. In forming the light emitting element 250, a connection portion 253a is formed, and other portions are formed, similarly to the other embodiments described above.

The second interlayer insulating film 156 is formed to cover the planarized surface 112F and the light-emitting element 250.

As shown in FIG. 18B, a via 161d is formed so as to penetrate the second interlayer insulating film 156 and the first interlayer insulating film 112 and reach the wiring 110d. A via 261a is formed so as to penetrate the second interlayer insulating film 156 and reach the connection portion 253a. A connection member 261k is formed so as to reach the upper surface 251U. A second wiring layer 160 including wirings 260a and 260k is formed, the wiring 260a and the via 261a are connected, and the wiring 260k and the via 161d are connected. The wiring 260k is also connected to the connection member 261k. The second wiring layer 160 may be formed simultaneously with the formation of the vias 261a, 161d and the connection member 261k.

In this manner, subpixel 220 is formed.

The effects of the image display device of this embodiment will be described.
In the image display device of this embodiment, similarly to the other embodiments described above, it is possible to shorten the time of the transfer step for forming the light emitting element 250 and reduce the number of steps. In addition, in the crystal growth step of the semiconductor layer 1150, when crystal growth is performed from the n-type semiconductor layer 1151, it is possible to eliminate the need for transfer to the support substrate 1190, thereby reducing the number of steps.

In the image display device 201 of this embodiment, the p-type semiconductor layer 253 can be used as the light-emitting surface 253S, which increases the degree of freedom in circuit configuration and improves the efficiency of product design.

Third Embodiment
FIG. 19 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment.
This embodiment differs from the other embodiments described above in that the light emitting element 150 has an n-type semiconductor layer 151 as a light emitting surface 151S1. This embodiment includes a light blocking layer 330. This embodiment has a color filter 180 attached to the light emitting surface 151S1 side. The same components as those in the other embodiments described above are given the same reference numerals and detailed description will be omitted as appropriate.

As shown in FIG. 19, the subpixel 320 of the image display device of this embodiment includes a color filter 180, a transistor 103, a first wiring layer 110, a first interlayer insulating film 112, a light-shielding layer 330, a first interlayer insulating film 112, a light-emitting element 150, a second interlayer insulating film 156, a via 161d, and a second wiring layer 160. The transistor 103 is a p-channel TFT, and is the same as in the first embodiment. The light-emitting element 150 provides a light-emitting surface 151S1 by an n-type semiconductor layer 151. In this embodiment, the light-emitting surface 151S1 is roughened.

The color filter 180 includes a light-shielding portion 181 and a color conversion portion 182. In this way, the color filter (wavelength conversion member) 180 is a light-transmitting member because it includes the color conversion portion 182 that is light-transmitting. The color conversion portion 182 is provided directly below the light-emitting surface 151S1 of the light-emitting element 150 in accordance with the shape of the light-emitting surface 151S1. In the color filter 180, the portion other than the color conversion portion 182 is a light-shielding portion 181. The light-shielding portion 181 is a so-called black matrix, and reduces bleeding due to color mixing of light emitted from adjacent color conversion portions 182, making it possible to display a sharp image.

The color conversion section 182 may have one layer or two or more layers. FIG. 19 shows a case where the color conversion section 182 has two layers. Whether the color conversion section 182 has one layer or two layers is determined by the color, i.e., the wavelength, of the light emitted by the subpixel 320. When the emission color of the subpixel 320 is red, the color conversion section 182 is preferably made up of two layers, a color conversion layer 183 and a filter layer 184 that transmits red light. When the emission color of the subpixel 320 is green, the color conversion section 182 is preferably made up of two layers, a color conversion layer 183 and a filter layer 184 that transmits green light. When the emission color of the subpixel 320 is blue, the color conversion section 182 is preferably made up of one layer.

When the color conversion section 182 has two layers, the first layer is the color conversion layer 183 and the second layer is the filter layer 184. The first color conversion layer 183 is provided in a position closer to the light emitting element 150. The filter layer 184 is laminated on the color conversion layer 183.

The color conversion layer 183 converts the wavelength of the light emitted by the light emitting element 150 to a desired wavelength. In the case of a subpixel 320 that emits red light, the light having a wavelength of 467 nm ± 20 nm, which is the wavelength of the light emitting element 150, is converted to light having a wavelength of, for example, approximately 630 nm ± 20 nm. In the case of a subpixel 320 that emits green light, the light having a wavelength of 467 nm ± 20 nm, which is the wavelength of the light emitting element 150, is converted to light having a wavelength of, for example, approximately 532 nm ± 20 nm.

The filter layer 184 blocks the wavelength components of the blue light emission that remain unconverted in the color conversion layer 183. The filter layer 184 also prevents the color conversion layer 183 from erroneously emitting light due to blue ambient light entering from the outside.

When the color of the light emitted by the subpixel 320 is blue, the light may be outputted through the color conversion layer 183, or directly without passing through the color conversion layer 183. When the wavelength of the light emitted by the light-emitting element 150 is about 467 nm ± 20 nm, the light may be outputted without passing through the color conversion layer 183. When the wavelength of the light emitted by the light-emitting element 150 is 410 nm ± 20 nm, it is preferable to provide one color conversion layer 183 in order to convert the wavelength of the output light to about 467 nm ± 20 nm.

Even in the case of a blue subpixel 320, the subpixel 320 may have a filter layer 184. By providing the blue subpixel 320 with a filter layer 184 that transmits blue light, minute reflections of external light other than blue light that occur on the surface of the light-emitting element 150 are suppressed.

The color filter 180 has a first surface 180a. A transparent thin-film adhesive layer 188 is provided on the first surface 180a. The driving circuit section 100 is provided on the first surface 180a via the transparent thin-film adhesive layer 188. In this embodiment, the driving circuit section 100 includes a TFT lower layer 106, a circuit 101, and a first interlayer insulating film 112.

In this embodiment, a p-channel transistor 103 is formed on the TFT underlayer film 106. The transistor 103 is a TFT, and its configuration is the same as that of the first and second embodiments described above, so detailed description will be omitted.

In this embodiment, the first interlayer insulating film 112 includes two insulating films 112a and 112b. The insulating films 112a and 112b are made of the same material to form the first interlayer insulating film 112. The insulating film (first insulating film) 112a is provided on the insulating film 108 and the first wiring layer 110. A light-shielding layer 330 is provided on the insulating film 112a. An insulating film (third insulating film) 112b is provided on the light-shielding layer 330, and the light-shielding layer 330 is provided between the insulating films 112a and 112b. The light-shielding layer 330 is provided over the entire surface except for a portion between the first interlayer insulating film 112 and the second interlayer insulating film 156.

The light-shielding layer 330 may be made of any material that has light-shielding properties, whether conductive or not, and is made of, for example, a metal material that has light reflectivity. The light-shielding layer 330 may be made of black resin. When the light-shielding layer 330 is made of black resin, the via can be formed together with the first interlayer insulating film 112 and the like without having to form a through hole larger than the diameter of the via in advance.

The light emitting element 150 allows the light emitted through the first interlayer insulating film 112, the insulating film 108, the insulating layer 105, and the TFT lower layer film 106 to reach the color filter 180. Therefore, the light shielding layer 330 has a through hole 331L to ensure a path for the light emitted by the light emitting element 150. Since the via 161d is provided by penetrating the second interlayer insulating film 156 and the first interlayer insulating film 112, when the light shielding layer 330 is formed of a conductive material, the through hole 331d has a diameter larger than the diameter of the via 161d in order to pass the via 161d through.

Light emitted from the light-emitting element 150 is emitted from the area where the light-emitting surface 151S1 and the through-hole 331L overlap. Therefore, if the positions of the two are misaligned due to manufacturing variations, etc., there is a risk that the size of the area from which light is emitted will vary for each light-emitting element 150. Therefore, assuming that manufacturing variations, etc. will occur, it is desirable to set the inner diameter of the through-hole 331L so that it includes the outer periphery of the light-emitting surface 151S1. For example, the inner diameter of the through-hole 331L is formed slightly larger than the outer periphery of the light-emitting surface 151S1.

The light-shielding layer 330 includes a light-shielding portion 330a, which is provided so as to cover most of the TFT channel 104. Preferably, the outer periphery of the light-shielding portion 330a is set so as to include the outer periphery of the TFT channel 104 when the TFT channel 104 is projected onto the light-shielding portion 330a in an XY plane view. In this case, the light-shielding portion 330a can cover the entire TFT channel 104.

By setting the light-shielding portion 330a in this manner, even if light is emitted below the light-emitting element 150, the scattered light, etc. is blocked by the light-shielding portion 330a and hardly reaches the TFT channel 104, thereby suppressing malfunction of the transistor 103.

The light-shielding layer 330 may be provided in a limited region including the portion directly above the TFT channel 104, separated from other portions. In this example, the light-shielding layer 330 is not connected to any potential, but may be connected to a specific potential such as ground potential or power supply potential. When the light-shielding layer 330 has multiple separated portions, all of them may be at a common potential, or each portion may be connected to a different potential.

The light-emitting element 150 is provided on the planarized surface 112F. The light-emitting surface 151S1 of the light-emitting element 150 is roughened. A transparent planarized film 155 is provided between the light-emitting surface 151S1 and the planarized surface 112F. The transparent planarized film 155 provides a planarized surface so that the roughened light-emitting surface 151S1 is in close contact with the planarized surface 112F.

The light-emitting element 150 is a prismatic or cylindrical element including a light-emitting surface 151S1 and an upper surface 153U. The light-emitting surface 151S1 is in contact with the planarized surface 112F via a transparent planarizing film 155. The upper surface 153U is a surface provided opposite the light-emitting surface 151S1.

The light-emitting element 150 includes an n-type semiconductor layer 151, a light-emitting layer 152, and a p-type semiconductor layer 153. The n-type semiconductor layer 151, the light-emitting layer 152, and the p-type semiconductor layer 153 are stacked in this order from the light-emitting surface 151S1 toward the upper surface 153U.

The light-emitting element 150 includes a connection portion 151a. The connection portion 151a is formed so as to protrude in one direction from the n-type semiconductor layer 151 on the planarized surface 112F via the transparent planarized film 155. The transparent planarized film 155 is also provided between the connection portion 151a and the planarized surface 112F. The connection portion 151a is a part of the n-type semiconductor layer 151. The connection portion 151a is connected to one end of the via 161k, and connects the n-type semiconductor layer 151 to the wiring 160k via the via 161k. The configuration of the light-emitting element 150 is the same as that of the first embodiment described above, except that the light-emitting surface 151S1 is roughened, so further detailed description will be omitted.

The second interlayer insulating film 156 is provided to cover the planarized surface 112F, the light emitting element 150, and the transparent planarization film 155. The configurations of the via 161d, the connection member 161a, and the second wiring layer 160 are the same as those in the first embodiment described above, and detailed description will be omitted.

FIG. 20 is a schematic block diagram illustrating an image display device according to this embodiment.
20 , in an image display device 301 of this embodiment, sub-pixels 320 are arranged in a display region 2. The sub-pixels 320 are arranged, for example, in a lattice pattern. For example, n sub-pixels 320 are arranged along the X axis, and m sub-pixels 320 are arranged along the Y axis.

A pixel 10 includes a number of subpixels 320 that emit light of different colors. Subpixel 320R emits red light. Subpixel 320G emits green light. Subpixel 320B emits blue light. The emission color and brightness of one pixel 10 are determined by the three types of subpixels 320R, 320G, and 320B emitting light at the desired brightness.

One pixel 10 includes three subpixels 320R, 320G, and 320B, which are arranged, for example, in a line on the X-axis. Each pixel 10 may have subpixels of the same color arranged in the same column, or, as in this example, subpixels of different colors arranged in each column.

In the image display device 301 of this embodiment, the configuration of the power supply line 3, ground line 4, scanning line 6, and signal line 8 is the same as in the first embodiment described above. The image display device 301 differs from the first embodiment in that the three types of subpixels are caused to emit light at a set brightness to determine the emission color and brightness of one pixel 10. A detailed description of the circuit configuration is omitted because it is the same as the example in FIG. 3 for the first embodiment, except that the signal configuration for this purpose may be different. A full-color image display device can be created by adding a color filter 180 using the color scheme of this embodiment to the circuit shown in FIG. 3 or FIG. 13.

A method for manufacturing the image display device of this embodiment will be described.
21A to 23B are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device of this embodiment.
In the manufacturing method of the image display device of this embodiment, the same manufacturing steps are applied up to the formation of the first wiring layer 110 among the steps of preparing the driving circuit unit 100 on the substrate 102 shown in Fig. 6. The manufacturing method of this embodiment will be described starting from the steps after the formation of the first wiring layer 110.
21A , an insulating film 112a is formed on the insulating film 108 and the first wiring layer 110. A light-shielding layer 330 is formed on the insulating film 112a. The light-shielding layer 330 including the through-holes 331L and 331d is formed, for example, by forming a metal layer on the insulating film 112a and then processing it by etching. The light-shielding portion 330a is formed on the TFT channel 104 when the light-shielding layer 330 is formed.

As shown in FIG. 21B, an insulating film 112b is formed on the insulating film 112a and the light-shielding layer 330. The through holes 331L and 331d are filled with the insulating film 112b, and the surface of the insulating film 112b is planarized to form a planarized surface 112F.

As shown in FIG. 22A, the substrate 1195 shown in FIG. 8A is prepared, and the n-type semiconductor layer 1151 of the substrate 1195 is roughened to form a roughened exposed surface 1151E1. The substrate 1195 is formed by applying the process described in FIG. 7A to FIG. 8A. A transparent planarizing film 1155 is formed over the exposed surface 1151E1, and the exposed surface 1155E of the transparent planarizing film 1155 is planarized. For example, CMP is used to planarize the exposed surface 1155E.

As shown in FIG. 22B, the semiconductor layer 1150 is bonded to the substrate 102 and the drive circuit section 100 formed on the substrate 102. The bonding surfaces are the exposed surface 1155E of the transparent planarizing film 1155 of the semiconductor layer 1150 and the planarized surface 112F of the drive circuit section 100.

As shown in FIG. 23A, the semiconductor layer 1150 shown in FIG. 22B is etched into a predetermined shape to form the light-emitting element 150. The process of forming the light-emitting element 150 is the same as in the other embodiments described above. The transparent planarization film 155 is formed at the same time as the light-emitting element 150 is formed. In this example, the substrate 102 is removed later, so the drive circuit section 100 includes the TFT lower layer film 106, the circuit 101, and the first interlayer insulating film 112.

The second interlayer insulating film 156 is formed to cover the planarized surface 112F and the light-emitting element 150. When the transparent planarizing film 155 is exposed on the side surface of the light-emitting element 150, the second interlayer insulating film 156 is provided to cover the transparent planarizing film 155 as well.

As shown in FIG. 23B, vias 161d, 161k, connection member 161a, and second wiring layer 160 are formed on the second interlayer insulating film 156 in the same manner as in the other embodiments described above.

As shown in FIG. 24A, an adhesive layer 1170 is formed on the second interlayer insulating film 156 and the second wiring layer 160, and a reinforcing substrate 1180 is adhered via the adhesive layer 1170. The adhesive layer 1170 and the reinforcing substrate 1180 may contain a material having optical reflectivity, for example, a white resin. The substrate 102 is then removed to expose the formation surface 1192A of the color filter 180. The substrate 102 is removed by wet etching or laser lift-off.

As shown in FIG. 24B, the color filter (wavelength conversion member) 180 is adhered to the forming surface 1192A by a transparent thin-film adhesive layer 188.

The purpose of removing the substrate 102 when adhering the color filter 180 is to reduce the transmission loss of the light emitted from the light emitting surface 151S1. Therefore, the removal of the substrate 102 is not limited to removing the entire substrate 102, and for example, a part of the substrate 102 may be removed to form the color filter 180. Removing a part of the substrate 102 means thinning the substrate 102 by etching or the like. Alternatively, the substrate 102 may be previously constructed in a multi-layer structure using a transparent resin or the like, and the substrate 102 may be substantially thinned by peeling off a part of the layer.

25A to 25D are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device of this embodiment.
25A to 25D show a method for forming a color filter by an inkjet method. This manufacturing process is applied instead of the process shown in FIG. 24B.

As shown in FIG. 25A, the substrate 102 is removed, and a structure 1192 is prepared with the formation surface 1192A exposed. The structure 1192 includes the drive circuit section 100, the light-emitting element 150, the vias 161d and 161k, the second wiring layer 160, the adhesive layer 1170, and the reinforcing substrate 1180.

As shown in FIG. 25B, a light shielding portion 181 is formed on the color filter formation surface 1192A. The light shielding portion 181 is formed, for example, by using a screen printing or photolithography technique.

As shown in FIG. 25C, phosphors corresponding to the emitted color are ejected from an inkjet nozzle to form a color conversion layer 183. The phosphors color the areas where the light-shielding portion 181 is not formed. For example, fluorescent paints using general phosphor materials, perovskite phosphor materials, or quantum dot phosphor materials are used as the phosphors. When using perovskite phosphor materials or quantum dot phosphor materials, each emitted color can be realized, and monochromaticity and color reproducibility are high, which is preferable. After drawing with the inkjet nozzle, a drying process is performed at an appropriate temperature and time. The thickness of the coating film during coloring is set to be thinner than the thickness of the light-shielding portion 181.

As already explained, for blue-emitting subpixels, if no color conversion section is formed, the color conversion layer 183 is not formed. Also, when forming a blue color conversion layer for a blue-emitting subpixel, if a single layer of color conversion section is sufficient, the thickness of the coating of the blue phosphor is preferably approximately the same as the thickness of the light-shielding section 181.

As shown in FIG. 25D, the paint for the filter layer 184 is sprayed from an inkjet nozzle. The paint is applied over the phosphor coating. The total thickness of the phosphor and paint coating is approximately the same as the thickness of the light blocking portion 181.

Whether it is a film-type color filter or an inkjet-type color filter, it is desirable for the color conversion layer 183 to be as thick as possible in order to improve color conversion efficiency. On the other hand, if the color conversion layer 183 is too thick, the emitted light of the color-converted light is approximated to Lambertian, while the emission angle of the blue light that is not color-converted is limited by the light shielding portion 181. This causes a problem in that the display color of the displayed image becomes visual angle dependent. In order to match the light distribution of the subpixel in which the color conversion layer 183 is provided to the light distribution of the blue light that is not color-converted, it is desirable for the thickness of the color conversion layer 183 to be about half the opening size of the light shielding portion 181.

For example, in the case of a high-definition image display device of about 250 ppi, the pitch of the subpixels 20 is about 30 μm, so the thickness of the color conversion layer 183 is preferably about 15 μm. Here, when the color conversion material is made of spherical phosphor particles, it is preferable that they are stacked in a close-packed structure to suppress light leakage from the light emitting element 150. For this purpose, at least three layers of particles are required. Therefore, the particle size of the phosphor material constituting the color conversion layer 183 is preferably, for example, about 5 μm or less, and more preferably about 3 μm or less. Since perovskite phosphor materials, quantum dot phosphor materials, and the like are easily deteriorated by oxygen and moisture, it is preferable that the color conversion layer 183 is sealed with an inorganic film such as SiO ₂ .

FIG. 26 is a schematic perspective view illustrating an image display device of this embodiment.
26, in the image display device of this embodiment, a drive circuit unit 100 is provided on a color filter 180. A light-emitting circuit unit 172 having a large number of light-emitting elements 150 is provided on the drive circuit unit 100. The light-emitting circuit unit 172 and the drive circuit unit 100 are electrically connected by vias 161d shown in FIG.

In this embodiment, a color filter 180 is provided to configure a full-color image display device 301, but as in the other embodiments described above, an image display device may be configured without providing a color filter. In that case, for example, the substrate 102 may be left as it is without being removed.

The effects of the image display device 301 of this embodiment will be described.
In the manufacturing method of the image display device 301 of this embodiment, as in the other embodiments described above, in addition to the effect of shortening the time of the transfer process for forming the light-emitting element 150 and reducing the number of processes, since the light-emitting surface 151S1 is made of the n-type semiconductor layer 151 which has a lower resistance than the p-type, the n-type semiconductor layer 151 can be formed thick and the light-emitting surface 151S1 can be sufficiently roughened.

In the image display device 301 of this embodiment, the light-emitting surface 151S1 is roughened to diffuse the emitted light, so that even a small light-emitting element 150 can be used as a light source with a sufficient light-emitting area.

In the image display device 301 of this embodiment, the light-shielding layer 330 is provided between the insulating films 112a and 112b. The light-shielding layer 330 is provided between the light-emitting element 150 and the transistor 103. Therefore, even if the light-emitting element 150 emits light, the emitted light is unlikely to reach the TFT channel 104, and malfunction of the transistor 103 can be prevented.

The light-shielding layer 330 can be formed of a conductive material such as metal, and can be connected to any potential. For example, a part of the light-shielding layer 330 can be placed directly under a switching element such as the transistor 103 and connected to a ground potential or a power supply potential, which can be useful for noise suppression.

The light-shielding layer 330 is not limited to application in this embodiment, but can be commonly applied to the subpixels of the other embodiments described above and other embodiments described below. Even when applied to other embodiments, the same effects as described above can be obtained.

In the above example, the configuration and manufacturing method of the light-emitting element having a roughened light-emitting surface were described. In the light-emitting element having a connection portion, a roughened light-emitting surface can be applied as in the present embodiment. Specific applications are the light-emitting element 150 in the first embodiment and its modified examples, the light-emitting element 250 in the second embodiment, and the semiconductor layer 750 in the seventh embodiment described below. By roughening the light-emitting surface of the components of these light-emitting elements, the above-mentioned effects can be achieved. Note that in the other embodiments, the roughening of the light-emitting surface can be applied by applying a light-emitting element provided with a connection portion.

Fourth Embodiment
FIG. 27 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment.
This embodiment differs from the other embodiments described above in that a third wiring layer 440 is included between the light emitting element 150 and the planarized surface 112F. This embodiment also differs from the other embodiments described above in that a fourth wiring layer 470 is included on the light emitting element 150. In other respects, this embodiment is the same as the other embodiments described above, and the same components are denoted by the same reference numerals and detailed descriptions thereof are omitted as appropriate.

As shown in FIG. 27, the subpixel 420 of the image display device of this embodiment includes a substrate 102, a transistor 103, a first wiring layer 110, a first interlayer insulating film 112, a third wiring layer 440, a light-emitting element 150, a fourth wiring layer 470, a second interlayer insulating film 156, a via 161d, and a second wiring layer 160.

In this embodiment, the drive circuit section 100 includes a substrate 102, a TFT lower layer film 106, a circuit 101, and a first interlayer insulating film 112. The configuration of the drive circuit section 100 is the same as that of the first embodiment, and detailed description will be omitted.

The third wiring layer 440 is provided on the planarized surface 112F. The third wiring layer 440 includes wiring 440a. The wiring 440a is provided between the light-emitting element 150 and the planarized surface 112F. The third wiring layer 440 includes a plurality of wirings 440a corresponding to the plurality of light-emitting elements 150, and in this example, each of the wirings 440a is separated.

The third wiring layer 440 is formed of a conductive film having optical transparency. The conductive film is, for example, a transparent conductive film such as ITO or ZnO. The wiring 440a is also formed of the same material.

The third wiring layer 440 and the wiring 440a are in contact with the planarized surface 112F. The light-emitting element 150 is in contact with the wiring 440a at the light-emitting surface 151S and is electrically connected to the wiring 440a. The outer periphery of the wiring 440a is set to include the outer periphery of the light-emitting element 150 when the light-emitting element 150 is projected onto the wiring 440a in an XY plane view. The wiring 440a is provided so as to protrude in one direction above the planarized surface 112F from directly below the light-emitting surface 151S. One end of the via (second via) 161k is connected to the protruding region of the wiring 440a. The via 161k electrically connects the wiring 160k and the wiring 440a between the wiring (second wiring) 160k and the wiring 440a. Therefore, the n-type semiconductor layer 151 is electrically connected to the ground line 4 of the circuit of FIG. 20 described above, for example, through the wiring 440a, the via 161k, and the wiring 160k. Note that the via (first via) 161d is provided to penetrate the second interlayer insulating film 156 and the first interlayer insulating film 112 and reach the wiring 110d, as in the other embodiments described above, and electrically connects the wiring (first wiring) 160a and the wiring 110d.

A resin layer 457 is provided on the planarized surface 112F, the light emitting element 150, and the third wiring layer 440. The resin layer 457 is, for example, a transparent resin. The fourth wiring layer 470 is provided on the resin layer 457. The fourth wiring layer 470 can include multiple wirings. For example, some of the multiple wirings can be physically separated and electrically at different potentials. In this example, the fourth wiring layer 470 includes wirings 470a and 470b that are formed separately.

The wiring 470a (first portion) is provided above and to the sides of the light-emitting element 150, covering the upper surface 153U and the side surface of the light-emitting element 150. The wiring 470a covers most of the light-emitting element except for the light-emitting surface 151S, so that scattered light and reflected light to the sides and above the light-emitting element 150 are reflected toward the light-emitting surface 151S. The wiring 470a functions as a member for reflecting light. The connection electrode 461a is provided between the upper surface 153U and the wiring 470a, and electrically connects the upper surface 153U and the wiring 470a.

When the resin layer 457 is made of a transparent resin, the scattered light emitted from above or the sides of the light-emitting element 150 is reflected by the wiring 470a toward the light-emitting surface 151S. This improves the actual light-emitting efficiency of the light-emitting element 150. When the resin layer 457 is made of a material with high light reflectivity, such as a white resin, the wiring 470a is further provided on the resin layer 457, so that the scattered light leaking from the resin layer 457 can be reflected toward the light-emitting surface 151S, thereby achieving higher light reflectivity.

The second interlayer insulating film 156 is provided to cover the resin layer 457 and the fourth wiring layer 470. The second wiring layer 160 including wirings 160a and 160k is provided on the second interlayer insulating film 156.

The via 161d is provided so as to penetrate the second interlayer insulating film 156, the resin layer 457, and the first interlayer insulating film 112 and reach the wiring 110d. The via 161d is provided between the wiring 160a and the wiring 110d, and electrically connects the wiring 160a and the wiring 110d. The wiring 160a is connected to the wiring 470a via the connection member 471a. Therefore, the p-type semiconductor layer 153 is electrically connected to the drain region of the transistor 103 via the connection electrode 461a, the wiring 470a, the connection member 471a, the wiring 160a, the via 161d, the wiring 110d, and the via 111d.

The via 161k is provided so as to penetrate the second interlayer insulating film 156 and the resin layer 457 and reach the wiring 440a. The via 161k is provided between the wiring 160k and the wiring 440a, and electrically connects the wiring 160k and the wiring 440a. Therefore, the n-type semiconductor layer 151 is electrically connected to, for example, the ground line 4 of the circuit in FIG. 3 via the wiring 440a, the via 161k, and the wiring 160k.

A method for manufacturing the image display device of this embodiment will be described.
28A to 30B are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device of this embodiment.
As shown in Fig. 28A, a substrate 1195 is prepared. The substrate 1195 is formed by applying the process shown in Fig. 7A and Fig. 7B. A light-transmitting conductive layer 1440 is formed on an n-type semiconductor layer 1151 of the substrate 1195. The conductive layer 1440 is formed on an exposed surface 1151E of the n-type semiconductor layer 1151.

As shown in FIG. 28B, the drive circuit section 100 formed on the substrate 102 is prepared. The semiconductor layer 1150 is bonded to the planarized surface 112F of the drive circuit section 100 via the conductive layer 1440. The support substrate 1190 is then removed by wet etching or laser lift-off.

As shown in FIG. 29A, the conductive layer 1440 shown in FIG. 28B is processed by etching to form a third wiring layer 440 including wiring 440a. The semiconductor layer 1150 shown in FIG. 28B is processed by etching to form a light emitting element 150.

The resin layer 457 is formed to cover the planarized surface 112F, the light-emitting element 150, and the third wiring layer 440. An opening 462a is formed in the resin layer 457 to expose a portion of the upper surface 153U of the light-emitting element 150.

Then, as shown in FIG. 29B, metal layer 1470 is formed to cover resin layer 457. When forming metal layer 1470, opening 462a shown in FIG. 29A may be filled at the same time to form connection electrode 461a, or opening 462a may be filled to form connection electrode 461a, and then metal layer 1470 may be formed.

As shown in FIG. 30A, the metal layer 1470 shown in FIG. 29B is etched to form the fourth wiring layer 470. When the fourth wiring layer 470 is formed, a wiring (first portion) 470a and a wiring 470b are formed separately. The wiring 470a is formed so as to cover the upper surface 153U and the side surface of the light-emitting element. A second interlayer insulating film 156 is formed to cover the resin layer 457 and the fourth wiring layer 470.

As shown in FIG. 30B, a second wiring layer 160 including wirings 160a and 160k is formed on the second interlayer insulating film 156. A via 161k is formed to penetrate the second interlayer insulating film 156 and reach the wiring 440a. The via (second via) 161k is between the wiring 160k and the wiring 440a and electrically connects the wiring 160k and the wiring 440a. As in the other embodiments described above, a via 161d and a connection member 471a are formed and connected to the second wiring layer 160.

In this manner, subpixel 420 is formed.

The effects of the image display device of this embodiment will be described.
In the image display device of this embodiment, similarly to the other embodiments described above, it is possible to shorten the time of the transfer process for forming the light emitting element 150 and reduce the number of processes. In addition, it has the following effects.

The third wiring layer 440 and the wiring 440a are formed from a light-transmitting conductive film such as ITO, making them easy to process, and may shorten the series of manufacturing steps for the light-emitting element 150 and the third wiring layer 440.

In this embodiment, the third wiring layer 440 and the wiring 440a are used to lead out the electrodes on the light emitting surface 151S side, so that the light emitting element 150 can be a vertical type. In the vertical type light emitting element 150, the current flowing through the semiconductor layer can be directed substantially along the Z axis by reducing the component along the XY plane, which has the advantage of reducing losses in the semiconductor layer.

In the image display device of this embodiment, the subpixel 420 includes a fourth wiring layer 470. The fourth wiring layer 470 is electrically isolated from the light-emitting element 150 by the resin layer 457. The fourth wiring layer 470 includes wiring 470a, which covers the upper surface 153U and side surface of the light-emitting element 150 via the resin layer 457. Therefore, scattered light, etc., above or to the side of the light-emitting element 150 can be reflected to the light-emitting surface 151S side. Therefore, the substantial light-emitting efficiency of the light-emitting element 150 can be improved.

Fifth Embodiment
FIG. 31 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment.
This embodiment differs from the other embodiments described above in that an electrode 565a is provided to cover the upper surface 153U of the light emitting element 150, and the electrode 565a is connected to a wiring 560a formed on the wall surface of the contact hole 561a. In this example, a color filter 180 is provided on a thinned substrate 502. In other respects, this embodiment is the same as the other embodiments, and the same components are denoted by the same reference numerals and detailed description thereof will be omitted as appropriate.

As shown in FIG. 31, the subpixel 520 of the image display device of this embodiment includes a color filter 180, a substrate (light-transmitting member) 502, a transistor 103, a first wiring layer 110, a first interlayer insulating film 112, a third wiring layer 440, a light-emitting element 150, a second interlayer insulating film 156, a via 161d, and a second wiring layer 160. In this embodiment, the light-emitting element 150 is provided on the wiring 540a of the third wiring layer 440, and is electrically connected to the wiring 540a at the light-emitting surface 151S.

The substrate 502 is a substrate having optical transparency, for example, a resin substrate having optical transparency. Instead of a resin substrate, a thinned glass substrate may be used. A TFT lower layer film 106 is formed on the first surface 502a, which is one surface of the substrate 502, and a driving circuit section 100 including the substrate 502 is formed. In this embodiment, the driving circuit section 100 is configured to include the substrate 502, the TFT lower layer film 106, the circuit 101, and the first interlayer insulating film 112. A color filter (wavelength conversion member) 180 is provided on the second surface 502b, which is the other surface of the substrate 502. The color filter 180 is the same as that described in the third embodiment. The color filter 180 may be in the form of a pasted film, or may be formed by an inkjet method. The configurations of the color filter 180 and the driving circuit section 100 are the same as those of the other embodiments described above, except for the substrate 502, and detailed description will be omitted.

The third wiring layer 440 is provided on the planarized surface 112F. The third wiring layer 440 includes wiring 540a. The wiring 540a is provided between the light-emitting element 150 and the planarized surface 112F. The third wiring layer 440 includes a plurality of wirings 540a corresponding to the plurality of light-emitting elements 150, and in this example, each of the wirings 540a is separated.

The third wiring layer 440 and the wiring 540a are in contact with the planarized surface 112F. The light-emitting element 150 is in contact with the wiring 540a at the light-emitting surface 151S and is electrically connected to the wiring 540a. The outer periphery of the wiring 540a is set to include the outer periphery of the light-emitting element 150 when the light-emitting element 150 is projected onto the wiring 540a in an XY plane view. The wiring 540a is provided so as to protrude in one direction above the planarized surface 112F from directly below the light-emitting surface 151S. One end of the via 161k is connected to the protruding region of the wiring 540a. The via 161k electrically connects the wiring 160k and the wiring 540a between the wiring 160k and the wiring 540a. Therefore, the n-type semiconductor layer 151 is electrically connected to, for example, the ground line 4 of the circuit in FIG. 3 described above via the wiring 540a, the via 161k, and the wiring 160k.

The second interlayer insulating film 156 is provided to cover the planarized surface 112F, the light-emitting element 150, and the third wiring layer 440.

A contact hole 561a is provided above the light-emitting element 150. The contact hole 561a is formed by removing a portion of the second interlayer insulating film 156. The opening diameter of the contact hole 561a is set to be sufficiently large, and the inner circumference of the contact hole 561a is set to be the same as the outer circumference of the upper surface 153U or slightly inside the outer circumference of the upper surface 153U.

An electrode 565a is provided over the upper surface 153U. The electrode 565a is provided at the bottom of the contact hole 561a. Therefore, the outer circumference of the electrode 565a almost coincides with the inner circumference of the contact hole 561a. Therefore, the electrode 565a is provided so as to cover all or most of the upper surface 153U. The electrode 565a is light reflective, so it reflects scattered light, etc., upward from the light emitting element 150 to the light emitting surface 151S side. Therefore, the substantial light emitting efficiency of the light emitting element 150 is improved. The electrode 565a can be formed integrally with the wiring 560a formed on the wall surface of the contact hole 561a.

The second wiring layer 160 includes a wiring 560a. The wiring 560a is provided on the second interlayer insulating film 156, and is provided on the wall surface of the contact hole 561a and connected to the electrode 565a. The wiring 560a is connected to the wiring 110d through the via 161d, so that the p-type semiconductor layer 153 is electrically connected to the drain region of the transistor 103 through the electrode 565a, the wiring 560a, the via 161d, the wiring 110d, and the via 111d.

A method for manufacturing the image display device of this embodiment will be described.
32A to 33 are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment.
28B in that the substrate 502 is formed on the substrate 102, but the method can be easily applied by replacing the substrate 102 shown in Fig. 28B with the substrate 102 and the substrate 502 formed on the substrate 102. The steps described in the fourth embodiment using Fig. 28A and Fig. 28B are applied, and the following description will be given assuming that they are applied to the steps from Fig. 28B onwards.

As shown in FIG. 32A, the light-transmitting conductive layer 1440 shown in FIG. 28B is processed by etching to form the third wiring layer 440 and wiring 540a. The semiconductor layer 1150 shown in FIG. 28B is processed by etching to form the light-emitting element 150. The second interlayer insulating film 156 is formed to cover the planarized surface 112F, the light-emitting element 150, and the second wiring layer 440.

A via hole 162d is formed so as to penetrate the second interlayer insulating film 156 and the first interlayer insulating film 112 and reach the wiring 110d. A via hole 162k is formed so as to penetrate the second interlayer insulating film 156 and reach the wiring 540a. A portion of the second interlayer insulating film 156 on the light-emitting element 150 is removed, and the upper surface 153U is exposed from the opening 561.

The upper surface 153U exposed by the opening 561 of the contact hole 561a is preferably exposed entirely, but is appropriately set according to the accuracy of forming the contact hole 561a. For example, the inner circumference of the contact hole 561a is set to be slightly smaller than the outer circumference of the upper surface 153U.

The via holes 162d and 162k are formed, for example, at the same time. The contact hole 561a may be formed at the same time as the via holes 162d and 162k, or may be formed separately.

As shown in FIG. 32B, the via holes 162d and 162k shown in FIG. 32A are filled with a conductive material to form vias 161d and 161k. When forming the vias 161d and 161k, the bottom of the contact hole 561a, i.e., the upper surface 153U, may be covered with a conductive material.

The second wiring layer 160 is formed on the second interlayer insulating film 156. When forming the second wiring layer 160, a conductive layer that forms the second wiring layer 160 is formed on the second interlayer insulating film 156, and then processed by etching to form the second wiring layer 160 including the wirings 560a and 160k. The conductive layer is formed on the second interlayer insulating film 156, as well as on the exposed upper surface 153U and the wall surface of the contact hole 561a.

In this way, wiring 560a is formed, which is connected to via 161d, and wiring 160k is formed, which is connected to via 161k. Since wiring 560a is provided over the wall surface of contact hole 561a, it is also connected to upper surface 153U.

An adhesive layer 1170 is provided on the second interlayer insulating film 156 and the second wiring layer 160, and the reinforcing substrate 1180 is adhered to the adhesive layer 1170. The substrate 102 is then removed by wet etching or the like, and processed so that the thin substrate 502 remains.

As shown in FIG. 33, a color filter 180 is provided on the second surface 502b of the substrate 502. In this example, the color filter 180 is adhered to the surface 502b via a transparent thin-film adhesive layer 188. Instead of a film-type color filter, a color filter may be formed on the second surface 502b by an inkjet method.

If the substrate 502 is a thin glass plate, a thick glass substrate can be thinned by wet etching or the like.

The effects of the image display device of this embodiment will be described.
The image display device of this embodiment, like the image display devices of the other embodiments described above, has the effect of shortening the time of the transfer process for forming the light-emitting element 150 and reducing the number of processes. In addition, since the electrode 565a is provided over the upper surface 153U, the scattered light emitted upward by the light-emitting element 150 can be reflected toward the light-emitting surface 151S. Therefore, the substantial light-emitting efficiency of the light-emitting element 150 is improved.

In this embodiment, the electrode 565a can be formed at the same time as the via formation and the first wiring layer 110, so there is no need to add a process for forming the electrode 565a. This shortens the manufacturing process and the time from input of materials to completion of the product.

In this embodiment, the substrate 502 is made of a thin plate of organic transparent resin or glass, and is therefore flexible. This allows the image display device 501 to be bent, making it possible to attach it to curved surfaces and use it in wearable devices and the like without any sense of incongruity.

In this embodiment, the image display device includes a color filter 180, but may be configured without a color filter as in the other embodiments described above.

Sixth Embodiment
FIG. 34 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment.
In this embodiment, the configuration of the light emitting element 650 is different from that of the other embodiments. The other components are the same as those of the other embodiments described above. The same components are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.
As shown in FIG. 34, the third wiring layer 440 includes a wiring 640a. The third wiring layer 440 and the wiring 640a are in contact with the planarized surface 112F. The light emitting element 650 is in contact with the wiring 640a at the light emitting surface 651S and is electrically connected to the wiring 640a. The outer periphery of the wiring 640a is set to include the outer periphery of the light emitting element 650 when the light emitting element 650 is projected onto the wiring 640a in the XY plane view. The wiring 640a is provided so as to protrude in one direction on the planarized surface 112F from directly below the light emitting surface 651S. One end of the via 161k is connected to the protruding region of the wiring 640a. Therefore, the n-type semiconductor layer 151 is electrically connected to, for example, the ground line 4 of the circuit of FIG. 3 described above through the wiring 640a, the via 161k, and the wiring 110k.

In this embodiment, a light-shielding layer 330 is provided. The light-shielding layer 330 has the same configuration as that described in the third embodiment with reference to FIG. 19. The light-shielding layer 330 includes a light-shielding portion 330a. Preferably, the outer periphery of the light-shielding portion 330a is set to include the outer periphery of the TFT channel 104 when the TFT channel 104 is projected onto the light-shielding portion 330a in an XY plane view. The light-shielding layer 330 is provided with through holes 331L and 331d. The through hole 331L is provided for an optical path, and the through hole 331d is provided for insulation from the via 161d.

The light-emitting element 650 is provided on the wiring 640a. The light-emitting element 650 is a truncated pyramid or truncated cone-shaped element formed so that its area in the XY plane decreases in the positive direction of the Z axis.

FIG. 35 shows a detailed positional relationship between the planarized surface 112F and the light emitting element 650.
As shown in Fig. 35, the planarized surface 112F is a plane substantially parallel to the XY plane. The light emitting element 650 is provided on the planarized surface 112F, and the light emitting surface 651S is a surface substantially parallel to the planarized surface 112F. A wiring 640a is provided on the planarized surface 112F, and the light emitting surface 651S is provided on the planarized surface 112F via the wiring 640a. The thickness of the wiring 640a is sufficiently thin, and the reflection and absorption of light are sufficiently small.

The light-emitting element 650 has a side surface 655a. The side surface 655a is a surface between the upper surface 653U and the planarized surface 112F, and is a surface adjacent to the light-emitting surface 651S. The interior angle θ between the side surface 655a and the planarized surface 112F is smaller than 90°. Preferably, the interior angle θ is about 70°. More preferably, the interior angle θ is smaller than the critical angle at the side surface 655a, which is determined based on the refractive index of the light-emitting element 650 and the refractive index of the second interlayer insulating film 156. The light-emitting element 650 is covered with the second interlayer insulating film 156, and the side surface 655a is in contact with the second interlayer insulating film 156.

The critical angle θc of the interior angle θ between the side surface 655a of the light emitting element 650 and the planarized surface 112F is determined, for example, as follows.
When the refractive index of the light emitting element 650 is n0 and the refractive index of the second interlayer insulating film 156 is n1, the critical angle θc of light emitted from the light emitting element 650 to the second interlayer insulating film 156 can be calculated using the following equation (1).

θc=90°-sin ^-1 (n1/n0) (1)

For example, it is known that the refractive index of typical transparent organic insulating materials such as acrylic resin is around 1.4 to 1.5. Therefore, if the light emitting element 650 is made of GaN and the second interlayer insulating film 156 is made of a typical transparent organic insulating material, the refractive index of the light emitting element 650 can be set to n0 = 2.5, and the refractive index of the second interlayer insulating film 156 can be set to n = 1.4. By substituting these values into equation (1), the critical angle θc = 56° is obtained.

This shows that when the interior angle θ between the planarized surface 112F and the side surface 655a is θc = 56°, the light emitted from the light-emitting layer 652 that is parallel to the first surface 103a is totally reflected by the side surface 655a. It also shows that the light emitted from the light-emitting layer 652 that has a component in the positive direction of the Z axis is totally reflected by the side surface 655a. In the above, for simplicity, the second interlayer insulating film 156 is made of a transparent resin. However, even if the transparent resin is made of a white resin, the effect on the refractive index of the scattering particles for the white resin is small, so it is ignored in the above calculation.

On the other hand, light emitted from the light-emitting layer 652 that has a component in the negative direction of the Z axis is emitted from the side surface 655a at an emission angle that depends on the refractive index at the side surface 655a. Light that is incident on the second interlayer insulating film 156 is emitted from the second interlayer insulating film 156 at an angle determined by the refractive index of the second interlayer insulating film 156.

The light totally reflected by the side surface 655a is reflected again by other element interfaces and the top surface 653U, and the light that has a component in the negative direction of the Z axis among the reflected light is emitted from the light emitting surface 651S and the side surface 655a. The light parallel to the planarized surface 112F and the light that has a component in the positive direction of the Z axis are totally reflected by the side surface 655a.

In this way, the light emitted from the light-emitting layer 652, which is parallel to the planarized surface 112F and has a component in the positive direction of the Z axis, is converted by the side surface 655a and the top surface 653U into light having a component in the negative direction of the Z axis. Therefore, the proportion of the light emitted from the light-emitting element 650 that is directed toward the light-emitting surface 651S increases, and the actual light-emitting efficiency of the light-emitting element 650 improves.

By making θ<θc, most of the light having a component parallel to the planarized surface 112F can be totally reflected inside the light emitting element 650. If the refractive index of the second interlayer insulating film 156 is n=1.4, the critical angle θc is about 56°, so it is more preferable to set the interior angle θ to 45°, 30°, or the like. Also, the critical angle θc becomes smaller for materials with a larger refractive index n. However, even if the interior angle θ is set to about 70°, most of the light having a component in the negative direction of the Z axis can be converted into light having a component in the positive direction of the Z axis, so the interior angle θ may be set to, for example, 80° or less, taking into account manufacturing variations, etc.

A method for manufacturing the image display device of this embodiment will be described.
In this embodiment, the manufacturing process of the light emitting device 650 is different from that of the other embodiments, and the other manufacturing processes can be applied to the other embodiments described above. The different parts of the manufacturing process will be described below.
In this embodiment, the following steps are carried out to obtain the shape of the light emitting device 650 shown in FIG.
The semiconductor layer 1150 shown in Fig. 28B is attached to the planarized surface 112F, and then etched into the shape of the light emitting element 650 shown in Fig. 34. In forming the light emitting element 650, an etching rate is selected so that the side surface 655a shown in Fig. 35 forms an interior angle θ with the planarized surface 112F. For example, a higher etching rate is selected closer to the upper surface 653U. Preferably, the etching rate is set to increase linearly from the light emitting surface 651S side toward the upper surface 653U side.

Specifically, for example, the resist mask pattern for dry etching is designed to become gradually thinner toward its end during exposure. This allows the resist to gradually recede from the thin portion during dry etching, increasing the amount of etching from the light-emitting surface 651S toward the top surface 653U. As a result, the side surface 655a of the light-emitting element 650 is formed to form a certain angle with respect to the planarized surface 112F. Therefore, in the light-emitting element 650, the areas of the layers in the XY plane view from the top surface 653U are formed to increase in the order of p-type semiconductor layer 653, light-emitting layer 652, and n-type semiconductor layer 651.

Subpixel 620 is then formed by applying the same process as in the other embodiments.

The effects of the image display device of this embodiment will be described.
The image display device of this embodiment, like the image display devices of the other embodiments described above, has the effect of shortening the time for the transfer process for forming the light-emitting element 650 and reducing the number of processes, as well as the following effects.
In the image display device of this embodiment, the light emitting element 650 is formed to have a side surface 655a that forms an interior angle θ with respect to the planarized surface 112F on which the light emitting element 650 is provided. The interior angle θ is set based on a critical angle θc that is smaller than 90° and is determined by the refractive index of the materials of the light emitting element 650 and the second interlayer insulating film 156. The interior angle θ can convert light that is emitted from the light emitting layer 652 and that is directed to the side or upper side of the light emitting element 650 into light that is directed to the light emitting surface 651S and is then emitted. By making the interior angle θ sufficiently small, the substantial light emitting efficiency of the light emitting element 650 is improved.

In this embodiment, the light-emitting element 650 is a vertical element and is connected to the via 161k using the third wiring layer 440. Alternatively, the light-emitting element may be provided with a connection portion formed on the planarized surface 112F and connected to the via 161k via the connection portion.

Seventh Embodiment
FIG. 36 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment.
In this embodiment, the image display device is different from the other embodiments in that it includes a sub-pixel group 720 including a plurality of light-emitting regions on one light-emitting surface. The same components are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.
36, the image display device of this embodiment includes a subpixel group 720. The subpixel group 720 includes a substrate 102, a plurality of transistors 103-1 and 103-2, a first wiring layer 110, a first interlayer insulating film 112, a semiconductor layer 750, a second interlayer insulating film 156, vias 761d1 and 761d2, and a second wiring layer 160. The semiconductor layer 750 is provided on the planarized surface 112F.

In this embodiment, by turning on the p-channel transistors 103-1 and 103-2, holes are injected from one side of the semiconductor layer 750 through the first wiring layer 110 and the vias 761d1 and 761d2. By turning on the p-channel transistors 103-1 and 103-2, electrons are injected from the other side of the semiconductor layer 750 through the second wiring layer 160. Holes and electrons are injected into the semiconductor layer 750, and the separated light-emitting layers 752a1 and 752a2 emit light due to the combination of the holes and electrons. The driving circuit for driving the light-emitting layers 752a1 and 752a2 may have the circuit configuration shown in FIG. 3, for example. Using the example of the second embodiment, the n-type semiconductor layer and the p-type semiconductor layer of the semiconductor layer may be interchanged, and the semiconductor layer may be driven by an n-channel transistor. In that case, the driving circuit may have the circuit configuration shown in FIG. 13.

The configuration of subpixel group 720 is explained in detail below.

The TFT lower layer film 106 is formed on the first surface 102a. The TFT lower layer film 106 is planarized, and the TFT channels 104-1, 104-2, etc. are formed on the TFT lower layer film 106.

The insulating layer 105 covers the TFT lower layer film 106 and the TFT channels 104-1 and 104-2. The gate 107-1 is provided on the TFT channel 104-1 via the insulating layer 105. The gate 107-2 is provided on the TFT channel 104-2 via the insulating layer 105. The transistor 103-1 includes the TFT channel 104-1 and the gate 107-1. The transistor 103-2 includes the TFT channel 104-2 and the gate 107-2.

TFT channel 104-1 includes p-doped regions 104s1 and 104d1, which are the source and drain regions of transistor 103-1. Region 104i1 is n-doped and forms the channel of transistor 103-1. TFT channel 104-2 similarly includes p-doped regions 104s2 and 104d2, which are the source and drain regions of transistor 103-2. Region 104i2 is n-doped and forms the channel of transistor 103-2.

The insulating film 108 covers the insulating layer 105 and the gates 107-1 and 107-2. In this embodiment, the circuit 101 includes the TFT channels 104-1 and 104-2, the insulating layer 105, the insulating film 108, the vias 111s1, 111d1, 111s2, and 111d2, and the first wiring layer 110.

The first wiring layer 110 is provided on the insulating film 108. The first wiring layer 110 includes wirings 710f, 710s1, 710s2, 710d1, and 710d2.

Wiring (second portion) 710f is provided between light-emitting regions 751R1 and 751R2. In this example, wiring 710f is not electrically connected to any of the circuit elements shown in FIG. 36, but can be connected to any potential or circuit element. By being disposed between light-emitting regions 751R1 and 751R2, wiring 710f blocks the light emitted from each of light-emitting regions 751R1 and 751R2.

The wiring 710s1 is provided above the region 104s1. The via 111s1 is provided between the wiring 710s1 and the region 104s1, and electrically connects the wiring 710s1 and the region 104s1. The wiring 710s2 is provided above the region 104s2. The via 111s2 is provided between the wiring 710s2 and the region 104s2, and electrically connects the wiring 710s2 and the region 104s2. The wirings 710s1 and 710s2 are connected to the power supply line 3 of the circuit shown in FIG. 3, for example.

The wiring 710d1 is provided above the region 104d1. The via 111d1 is provided between the wiring 710d1 and the region 104d1, and electrically connects the wiring 710d1 and the region 104d1. The wiring 710d1 is connected to one end of the via 761d1. The wiring 710d2 is provided above the region 104d2. The via 111d2 is provided between the wiring 710d2 and the region 104d2, and electrically connects the wiring 710d2 and the region 104d2. The wiring 710d2 is connected to one end of the via 761d2.

The first interlayer insulating film 112 is provided to cover the insulating film 108 and the first wiring layer 110. The first interlayer insulating film 112 has a planarized surface 112F.

The semiconductor layer 750 has a light emitting surface 751S that contacts the planarized surface 112F. The light emitting surface 751S is a surface of the n-type semiconductor layer 751. The light emitting surface 751S includes a plurality of light emitting regions 751R1 and 751R2.

The semiconductor layer 750 includes an n-type semiconductor layer 751, light-emitting layers 752a1 and 752a2, and p-type semiconductor layers 753a1 and 753a2. The light-emitting layer 752a1 is provided on the n-type semiconductor layer 751. The light-emitting layer 752a2 is provided on the n-type semiconductor layer 751, separated and spaced apart from the light-emitting layer 752a1. The p-type semiconductor layer 753a1 is provided on the light-emitting layer 752a1. The p-type semiconductor layer 753a2 is provided on the light-emitting layer 752a2, separated and spaced apart from the p-type semiconductor layer 753a1.

The p-type semiconductor layer 753a1 has an upper surface 753U1 that faces the surface on which the light-emitting layer 752a1 is provided. The p-type semiconductor layer 753a2 has an upper surface 753U2 that faces the surface on which the light-emitting layer 752a2 is provided.

Light-emitting region 751R1 is a region of light-emitting surface 751S that approximately corresponds to the region facing upper surface 753U1. Light-emitting region 751R2 is a region of light-emitting surface 751S that approximately corresponds to the region facing upper surface 753U2.

FIG. 37 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment.
FIG. 37 is a schematic diagram for explaining light emitting regions 751R1 and 751R2.
As shown in Fig. 37, the light emitting regions 751R1 and 751R2 are surfaces on the light emitting surface 751S. In Fig. 37, the portions of the semiconductor layer 750 including the light emitting regions 751R1 and 751R2 are called light emitting portions R1 and R2, respectively. The light emitting portion R1 includes a portion of the n-type semiconductor layer 751, the light emitting layer 752a1, and the p-type semiconductor layer 753a1. The light emitting portion R2 includes a portion of the n-type semiconductor layer 751, the light emitting layer 752a2, and the p-type semiconductor layer 753a2.

The semiconductor layer 750 includes a connection portion R0. The connection portion R0 is provided between the light emitting portions R1 and R2, and is a part of the n-type semiconductor layer 751. One end of the via 761k shown in FIG. 36 is connected to the connection portion R0, and provides a current path between the light emitting portions R1 and R2.

In the light-emitting portion R1, electrons supplied through the connection portion R0 are supplied to the light-emitting layer 752a1. In the light-emitting portion R1, holes supplied through the p-type semiconductor layer 753a1 are supplied to the light-emitting layer 752a1. The electrons and holes supplied to the light-emitting layer 752a1 are combined to emit light. The light emitted by the light-emitting layer 752a1 reaches the light-emitting surface 751S through the n-type semiconductor layer 751 of the light-emitting portion R1. Since the light travels almost straight along the Z-axis direction in the light-emitting portion R1, it is the light-emitting region 751R1 that emits light on the light-emitting surface 751S. Therefore, in this example, the light-emitting region 751R1 approximately coincides with the area surrounded by the outer periphery of the light-emitting layer 752a1 projected onto the light-emitting surface 751S in the XY plane view.

The light-emitting portion R2 is similar to the light-emitting portion R1. That is, in the light-emitting portion R2, electrons supplied through the connection portion R0 are supplied to the light-emitting layer 752a2. In the light-emitting portion R2, holes supplied through the p-type semiconductor layer 753a2 are supplied to the light-emitting layer 752a2. The electrons and holes supplied to the light-emitting layer 752a2 are combined to emit light. The light emitted from the light-emitting layer 752a2 reaches the light-emitting surface 751S through the n-type semiconductor layer 751 of the light-emitting portion R2. Since the light travels almost straight along the Z-axis direction in the light-emitting portion R2, it is the light-emitting region 751R2 that emits light on the light-emitting surface 751S. Therefore, in this example, the light-emitting region 751R2 almost coincides with the region surrounded by the outer periphery of the light-emitting layer 752a2 projected onto the light-emitting surface 751S in the XY plane view.

In this way, in the semiconductor layer 750, the n-type semiconductor layer 751 can be shared to form multiple light-emitting regions 751R1, 751R2 on the light-emitting surface 751S.

In this embodiment, the semiconductor layer 750 can be formed by forming a part of the n-type semiconductor layer 751 as the connection portion R0 in the multiple light-emitting layers 752a1, 752a2 and multiple p-type semiconductor layers 753a1, 753a2 of the semiconductor layer 750. Therefore, the semiconductor layer 750 can be formed in the same manner as the method for forming the light-emitting elements 150, 250 in the first embodiment, the second embodiment, etc. described above.

Returning to FIG. 36, the explanation will be continued.
The second interlayer insulating film 156 is provided on the planarized surface 112F and the semiconductor layer 750.

The second wiring layer 160 is provided on the second interlayer insulating film 156. The second wiring layer 160 includes wirings 760d1, 760d2, and 760k. The wiring 760d1 is connected to the upper surface 753U1 via a connection member 761a1. The wiring 760d2 is connected to the upper surface 753U2 via a connection member 761a2. The wiring 760k is connected to, for example, the ground line 4 of the circuit in FIG. 3.

Via 761d1 is provided so as to penetrate the second interlayer insulating film 156 and the first interlayer insulating film 112 and reach the wiring 710d1. Via 761d1 is provided between wiring 760d1 and wiring 710d1, and electrically connects wiring 760d1 and wiring 710d1. Via 761d2 is provided so as to penetrate the second interlayer insulating film 156 and the first interlayer insulating film 112 and reach the wiring 710d2. Via 761d2 is provided between wiring 760d2 and wiring 710d2, and electrically connects wiring 760d2 and wiring 710d2.

The via 761k is provided so as to penetrate the second interlayer insulating film 156 and reach the n-type semiconductor layer 751. The via 761k is between the wiring 760k and the n-type semiconductor layer 751 and electrically connects the wiring 760k and the n-type semiconductor layer 751.

For example, transistors 103-1 and 103-2 are driving transistors for adjacent subpixels, and are driven sequentially. When holes supplied from transistor 103-1 are injected into light-emitting layer 752a1 and electrons supplied from wiring 760k are injected into light-emitting layer 752a1, light-emitting layer 752a1 emits light and light is emitted from light-emitting region 751R1. When holes supplied from transistor 103-2 are injected into light-emitting layer 752a2 and electrons supplied from wiring 760k are injected into light-emitting layer 752a2, light-emitting layer 752a2 emits light and light is emitted from light-emitting region 751R2.

The effects of the image display device of this embodiment will be described.
The image display device of this embodiment, like the image display devices of the other embodiments described above, has the effect of shortening the time of the transfer process for forming the semiconductor layer 750 and reducing the number of processes. In addition, since the connection portion R0 can be shared by a plurality of light-emitting portions R1 and R2, it is possible to reduce the number of vias 761k provided in the connection portion R0. By reducing the number of vias, it is possible to reduce the pitch of the light-emitting portions R1 and R2 that constitute the sub-pixel group 720, and it is possible to provide a small-sized, high-definition image display device.

In this embodiment, the emitted light from the light-emitting regions 751R1 and 751R2 must pass through the first interlayer insulating film 112, the insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the substrate 102 before being emitted to the outside. For this reason, it is considered that the light spreads on the path until it is emitted to the outside. In this embodiment, the wiring 710f is provided in the middle of the path until the light is emitted to the outside, so that the spreading light is blocked and the light emitted from adjacent pixels is prevented from being mixed. Therefore, it is possible to realize a high-quality image display device by narrowing the pixel pitch. In the above example, the case where two light-emitting regions are provided has been described, but the number of light-emitting regions is not limited to two, and can be any number of three or more.

Seventh Embodiment
The above-mentioned image display device can be an image display module having an appropriate number of pixels, and can be, for example, a computer display, a television, a portable terminal such as a smartphone, or a car navigation system.

FIG. 38 is a block diagram illustrating an image display device according to this embodiment.
FIG. 38 shows the main components of a computer display.
38 , an image display device 801 includes an image display module 802. The image display module 802 is an image display device having the configuration of, for example, the first embodiment described above. The image display module 802 includes a display area 2 in which a plurality of subpixels including the subpixel 20 are arranged, a row selection circuit 5, and a signal voltage output circuit 7.

The image display device 801 further includes a controller 870. The controller 870 inputs a control signal that is separated and generated by an interface circuit (not shown), and controls the row selection circuit 5 and the signal voltage output circuit 7 to drive each subpixel and control the drive order.

(Modification)
The above-mentioned image display device can be an image display module having an appropriate number of pixels, and can be, for example, a computer display, a television, a portable terminal such as a smartphone, or a car navigation system.

FIG. 39 is a block diagram illustrating an image display device according to a modified example of this embodiment.
FIG. 39 shows the configuration of a high-definition thin television.
As shown in Fig. 39, an image display device 901 includes an image display module 902. The image display module 902 is, for example, the image display device 1 having the configuration of the first embodiment described above. The image display device 901 includes a controller 970 and a frame memory 980. The controller 970 controls the driving order of each sub-pixel in the display area 2 based on a control signal supplied by a bus 940. The frame memory 980 stores one frame's worth of display data and is used for processing such as smooth video playback.

The image display device 901 has an I/O circuit 910. In FIG. 39, the I/O circuit 910 is simply written as "I/O". The I/O circuit 910 provides an interface circuit for connecting to an external terminal or device. The I/O circuit 910 includes, for example, a USB interface for connecting an external hard disk device, an audio interface, etc.

The image display device 901 has a receiving unit 920 and a signal processing unit 930. An antenna 922 is connected to the receiving unit 920, which separates and generates necessary signals from the radio waves received by the antenna 922. The signal processing unit 930 includes a DSP (Digital Signal Processor) and a CPU (Central Processing Unit), and the signals separated and generated by the receiving unit 920 are separated and generated by the signal processing unit 930 into image data, audio data, etc.

By configuring the receiver 920 and the signal processor 930 as high-frequency communication modules for transmitting and receiving signals in a mobile phone, for Wi-Fi, a GPS receiver, or the like, the device can be used as another image display device. For example, an image display device equipped with an image display module with an appropriate screen size and resolution can be used as a mobile information terminal such as a smartphone or a car navigation system.

The image display module in this embodiment is not limited to the configuration of the image display device in the first embodiment, but may be a modified version thereof or a different embodiment. The image display module in this embodiment and the modified version includes a large number of sub-pixels, as shown in Figures 11 and 26.

The embodiment described above makes it possible to realize a manufacturing method for an image display device and an image display device that shortens the transfer process of light-emitting elements and improves yield.

Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their variations are included within the scope and gist of the invention, as well as within the scope of the invention and its equivalents described in the claims. In addition, the above-mentioned embodiments can be implemented in combination with each other.

1,201,301,801,901 Image display device, 2 Display area, 3 Power supply line, 4 Ground line, 5,205 Row selection circuit, 6,206 Scanning line, 7,207 Signal voltage output circuit, 8,208 Signal line, 10 Pixel, 20,220,320,420,520,620 Subpixel, 22,222 Light-emitting element, 24,224 Selection transistor, 26,226 Driving transistor, 28,228 Capacitor, 100 Driving circuit section, 101 Circuit, 102,502 Substrate, 102a,180a,502a First surface, 103,103-1,103-2,203 Transistor, 104,104-1,104-2,204 TFT channel, 105 Insulating layer, 107, 107-1, 107-2 Gate, 108 Insulating film, 110 First wiring layer, 112 First interlayer insulating film, 150, 250, 650 Light emitting element, 151S, 151S1, 253S, 651S, 751S Light emitting surface, 156 Second interlayer insulating film, 160a, 160k, 260a, 260k, 560a, 760d1, 760d2, 760k Wiring, 161a, 261k, 471a, 761a1, 761a2 Connection member, 161d, 161k, 761d1, 761d2, 761k Via, 172 Light emitting circuit section, 180 Color filter, 720 Subpixel group, 1001 Crystal growth substrate, 1150 Semiconductor layer, 1161, 1162, 1163, 1164 Metal layer, 1180 Reinforcing substrate, 1190 Support substrate, 1192 Structure, 1194, 1294 Semiconductor growth substrate

Claims (22)

A step of preparing a first substrate including a circuit element formed on a first surface of a light-transmitting substrate, a first wiring layer connected to the circuit element, and a first insulating film covering the circuit element and the first wiring layer;
providing a semiconductor layer including a light emitting layer;
bonding the semiconductor layer to the first substrate;
forming a light emitting element including a light emitting surface on the first insulating film and an upper surface opposite to the light emitting surface by etching the semiconductor layer;
forming a second insulating film covering the first insulating film and the light emitting element;
forming a first via penetrating the first insulating film and the second insulating film;
forming a second wiring layer on the second insulating film;
Equipped with
A method for manufacturing an image display device, wherein the first via is provided between the first wiring layer and the second wiring layer, and electrically connects the first wiring layer and the second wiring layer. The method for manufacturing an image display device according to claim 1 further comprises a step of roughening the exposed surface of the semiconductor layer before the step of bonding the semiconductor layer, and forming a planarizing film having optical transparency over the roughened surface. forming a second via penetrating the second insulating film;
the light emitting element includes a connection portion formed on the first insulating film,
The method for manufacturing an image display device according to claim 1 , wherein the second via is provided between the second wiring layer and the connection portion, and electrically connects the second wiring layer and the connection portion. forming a conductive layer having optical transparency on an exposed surface of the semiconductor layer before the step of bonding the semiconductor layer;
forming a third wiring layer by etching the conductive layer after the step of bonding the semiconductor layer;
The method for manufacturing an image display device according to claim 1 , further comprising: forming a second via penetrating the second insulating film;
The method for manufacturing an image display device according to claim 4 , wherein the second via is provided between the second wiring layer and the third wiring layer, and electrically connects the second wiring layer and the third wiring layer. The method for manufacturing an image display device according to any one of claims 1 to 5, wherein the step of preparing the first substrate includes a step of forming a light-shielding layer that covers the circuit elements. The method further includes a step of forming a fourth wiring layer before the step of forming the second insulating film,
7. The method for manufacturing an image display device according to claim 1, wherein the fourth wiring layer includes a first portion that covers the light emitting element. The method for manufacturing an image display device according to any one of claims 1 to 7, wherein the semiconductor layer includes a gallium nitride compound semiconductor. The method for manufacturing an image display device according to any one of claims 1 to 8, further comprising the step of forming a wavelength conversion member on a second surface opposite to the first surface. The method for manufacturing an image display device according to any one of claims 1 to 8, further comprising the step of removing the translucent substrate and forming a wavelength conversion member in place of the translucent substrate. a light-transmitting member having a first surface;
A circuit element provided on the first surface;
a first wiring layer electrically connected to the circuit element;
a first insulating film covering the first surface, the circuit element, and the first wiring layer;
a light emitting element including a light emitting surface and an upper surface facing the light emitting surface on the first insulating film;
a second insulating film covering the first insulating film and the light emitting element;
a first via provided through the first insulating film and the second insulating film;
a second wiring layer provided on the second insulating film;
a second via provided through the second insulating film;
Equipped with
the first via is provided between the first wiring layer and the second wiring layer and electrically connects the first wiring layer and the second wiring layer;
the light emitting element includes a connection portion formed on the first insulating film,
the second wiring layer includes a first wiring and a second wiring separated from the first wiring,
the first via is provided between the first wiring and the first wiring layer and electrically connects the first wiring and the first wiring layer;
The second via is provided between the second wiring and the connection portion, and electrically connects the second wiring and the connection portion . The image display device according to claim 11 , wherein the light emitting surface is roughened. a light-transmitting member having a first surface;
A circuit element provided on the first surface;
a first wiring layer electrically connected to the circuit element;
a first insulating film covering the first surface, the circuit element, and the first wiring layer;
a light emitting element including a light emitting surface and an upper surface facing the light emitting surface on the first insulating film;
a second insulating film covering the first insulating film and the light emitting element;
a first via provided through the first insulating film and the second insulating film;
a second wiring layer provided on the second insulating film;
a third wiring layer having optical transparency and provided between the first insulating film and the light emitting surface;
a second via provided through the second insulating film;
Equipped with
the first via is provided between the first wiring layer and the second wiring layer and electrically connects the first wiring layer and the second wiring layer;
the second wiring layer includes a first wiring and a second wiring separated from the first wiring,
the first via is provided between the first wiring and the first wiring layer and electrically connects the first wiring and the first wiring layer;
The second via is provided between the second wiring and the third wiring layer, and electrically connects the second wiring and the third wiring layer . a fourth wiring layer covering the upper surface and a side surface of the light emitting element and including a first portion having light reflectivity;
The image display device according to claim 13 , wherein the first portion is electrically connected to the upper surface. the second wiring layer includes an electrode covering the upper surface and electrically connected to the upper surface;
The image display device according to claim 13 , wherein the first via is connected to the electrode. 16. The image display device according to claim 13, wherein an internal angle between the light emitting surface and a side surface of the light emitting element is smaller than 90°. a light-shielding layer provided on the first insulating film;
a third insulating film provided between the light-shielding layer and the second insulating film;
The image display device according to any one of claims 11 to 16 , further comprising: 18. The image display device according to claim 11, wherein the second insulating film has light reflectivity. 19. The image display device according to claim 11 , wherein the light emitting element includes a gallium nitride compound semiconductor. 20. The image display device according to claim 11, further comprising a wavelength conversion member provided on a second surface opposite to the first surface. a light-transmitting member having a first surface;
A plurality of transistors disposed on the first surface;
a first wiring layer electrically connected to the plurality of transistors;
a first insulating film covering the first surface, the plurality of transistors, and the first wiring layer;
a first semiconductor layer including a light emitting surface on the first insulating film on which a plurality of light emitting regions can be formed;
A plurality of light emitting layers provided on the first semiconductor layer;
a plurality of second semiconductor layers provided on the plurality of light emitting layers, the second semiconductor layers having a different conductivity type from the first semiconductor layers;
a second insulating film covering the first insulating film, the first semiconductor layer, the plurality of light emitting layers, and the plurality of second semiconductor layers;
a plurality of first vias provided through the first insulating film and the second insulating film;
a second wiring layer provided on the second insulating film;
Equipped with
the second semiconductor layers and the light emitting layers are separated by the second insulating film;
The image display device, wherein the plurality of first vias are provided between the first wiring layer and the second wiring layer, and electrically connect the first wiring layer and the second wiring layer. the plurality of light emitting regions are formed according to positions of the plurality of light emitting layers in a plan view,
22. The image display device according to claim 21 , wherein the first wiring layer includes a second portion provided between adjacent light emitting regions among the plurality of light emitting regions.

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