JP7524977B2 - Wideband transmission line wiring board - Google Patents

Description

The present invention relates to a wideband transmission line wiring board in which a transmission line is formed through which a wideband high-frequency signal propagates and a bias circuit is mounted to supply power to the transmission line.

Conventionally, an example of this type of wiring board is the inductor wiring board disclosed in Patent Document 1. In this inductor wiring board, a transmission line through which a high-frequency signal of 40 Gb/s class propagates and a transmission line pattern connected to the transmission line are mounted on a flexible board. The transmission line pattern is wired so that one end is connected between the input end and the output end of the transmission line and spreads radially as it moves away from the one end, creating an inductor with a conical structure. This inductor is configured by continuously connecting inductors L1, L2, ... Ln (L1 < L2 < ... < Ln) whose inductance is smaller the closer to the transmission line and larger the farther away from the transmission line, and serves as a bias circuit that supplies power to the transmission line. The ground surface of the board on the back side of the mounting surface of this inductor is removed to reduce parasitic capacitance.

As another conventional bias circuit of this type, for example, there is a wideband bias circuit disclosed in Patent Document 2. This wideband bias circuit is composed of three stages of inductors L1, L2, and L3 connected in series, one end of which is connected to a power supply, and the other end of which is connected to a transmission line that is connected to the output of an amplifier circuit. High-frequency signals in the 1 MHz to 3 GHz band are transmitted through this transmission line. The first stage inductor L1 connected to the transmission line has the smallest inductance, and the inductors L2 and L3 connected to the second and third stages have increasing inductances (L1<L2<L3).

JP 2008-47711 A JP 2010-232988 A

In both of the bias circuits disclosed in the above-mentioned conventional patent documents 1 and 2, inductors with smaller inductances are arranged closer to the connection point with the transmission line in order to maintain the transmission line's high transmission characteristics over a wide frequency band. The transmission characteristics of the transmission line are represented by the S-parameter S21. However, inductors with small inductance generate losses in the low frequency band of the propagating signal, so the transmission line cannot maintain high transmission characteristics over an ultra-wide band ranging from several MHz to several tens of GHz.

In addition, the bias circuit disclosed in Patent Document 1 has a conical inductor structure formed by wiring the transmission line pattern so that it spreads out radially, and a large area of the ground surface on the back side is removed to reduce parasitic capacitance. This increases the impedance of the ground surface, causing noise problems such as potential oscillations on the ground surface.

The present invention has been made to solve such problems,
a transmission line formed on the component mounting surface through which a high frequency signal propagates;
a bias circuit including a first chip inductor having one end connected to the transmission line at a location on the component mounting surface closest to the connection point with the transmission line and mounted on the component mounting surface, and multiple subsequent chip inductors connected in series to the first chip inductor from a location second closest to the connection point and mounted on the component mounting surface, with the last one connected in series being connected to a DC power source, the self-resonant frequency of the subsequent first chip inductor among the subsequent chip inductors connected next to the first chip inductor at the location second closest to the connection point being the largest, the first chip inductor being the second largest after the subsequent first chip inductor, and the subsequent chip inductors following the subsequent first chip inductor being set to the same frequency as the first chip inductor or successively smaller frequency than the first chip inductor;
A wideband transmission line wiring board is configured, which is provided with a ground surface formed on the rear side of the component mounting surface and in which the conductive portion in the region located on the rear side of the component mounting surface on which the bias circuit is mounted is removed.

According to this configuration, a low-frequency band signal that has been propagating through the transmission line and causing loss in the inductor located closest to the connection point with the transmission line is reflected by the impedance of the leading chip inductor that has the second highest self-resonant frequency after the trailing leading chip inductor, and is prevented from entering the bias circuit. Therefore, the low-frequency band signal that has been causing loss no longer causes loss in the leading inductor located closest to the connection point with the transmission line.

In addition, a propagation signal in the high frequency band of the largest self-resonant frequency of the subsequent leading chip inductor passes through the leading chip inductor and penetrates into the subsequent leading chip inductor, and in the path from the leading chip inductor to the subsequent leading chip inductor, the signal tends to leak from the transmission line to the ground plane via the parasitic capacitance that occurs between the leading chip inductor and the ground plane on the back side of the component mounting surface. However, the conductive portion of the ground plane in the area located on the back side of the component mounting surface on which the bias circuit is mounted is removed, so the occurrence of such parasitic capacitance is reduced, and the propagation signal in the high frequency band is prevented from leaking from the transmission line to the ground plane. This makes it possible to maintain high transmission characteristics of the transmission line over a wide band.

In addition, each inductor constituting the bias circuit is composed of a surface-mount type chip inductor. Therefore, each inductor constituting the bias circuit can be mounted on the board without occupying a large area, like the inductor formed in a conical structure with a transmission line pattern disclosed in Patent Document 1. Therefore, the area of the conductive portion removed region located on the ground surface on the back side of the component mounting surface portion on which the bias circuit is mounted can be reduced, preventing the impedance of the ground surface from increasing. As a result, noise problems due to potential vibrations generated on the ground surface do not occur.

As a result, the present invention makes it possible to maintain high transmission characteristics of the transmission line over a wide bandwidth, and also makes it possible to implement a bias circuit on a wiring board that does not cause noise problems due to potential oscillations on the ground surface.

1A and 1B are diagrams illustrating the concept of a wideband transmission line wiring board according to the present invention. 1 is a diagram illustrating an outline of a wideband transmission line wiring board according to a first embodiment of the present invention; 5 is a graph showing frequency characteristics of impedance of each chip inductor constituting a bias circuit in the wideband transmission line wiring board according to the first embodiment. 1 is a diagram illustrating a bias circuit in a conventional wideband transmission line wiring board, modeled on each chip inductor constituting the bias circuit in the wideband transmission line wiring board according to the first embodiment. FIG. 5 is a graph showing the transmission characteristic of the bias circuit shown in FIG. 4 . 5 is a cross-sectional view of the wideband transmission line wiring board shown in FIG. 4, taken along the arrow direction. 5A and 5B are diagrams illustrating a measurement board used for measuring transmission characteristics of a transmission line in the wideband transmission line wiring board according to the first embodiment. 8 is a cross-sectional view of the measurement substrate shown in FIG. 7, taken along the arrow direction. FIG. 9 is a perspective view showing a measurement system used to measure the transmission characteristics of the transmission line in the measurement board shown in FIGS. 7 and 8 . 10 is a graph showing the results of measuring the transmission characteristics of a transmission line using the measurement system shown in FIG. 9 together with comparative examples, and a diagram illustrating the configuration of each comparative example. FIG. 13 is a diagram illustrating an outline of a wideband transmission line wiring board according to a second embodiment of the present invention. FIG. 13 is a diagram illustrating an outline of a wideband transmission line wiring board according to a third embodiment of the present invention. 13A to 13C are diagrams illustrating wiring patterns on a front surface and a back surface of a wideband transmission line wiring board according to a third embodiment.

Next, we will explain the embodiment of the wideband transmission line wiring board according to the present invention. In the following explanation, the same or corresponding parts are denoted by the same reference numerals.

Figure 1 is a diagram explaining the concept of the wideband transmission line wiring board 1 of the present invention, where (a) is a plan view of the wiring board 1 and (b) is a cross-sectional view of the wiring board 1 taken along line Ib-Ib and viewed from the direction of the arrow.

An IC (highly integrated circuit) 2 and a bias circuit 3 are mounted on the component mounting surface 1a of the wiring board 1, and a transmission line 4 is formed. An ultra-wideband high-frequency signal s that is transmitted and received by the IC 2 to and from a circuit not shown propagates through the transmission line 4. The bias circuit 3 is composed of a leading chip inductor L2, one end of which is connected to the transmission line 4 and mounted on the component mounting surface 1a, and a number of trailing chip inductors L1, ..., Ln, which are connected in series to the leading chip inductor L2 and mounted on the component mounting surface 1a.

In general, the bias circuit 3 is called a bias T circuit, and the leading chip inductor L2 and the trailing chip inductors L1, ..., Ln that constitute the bias circuit 3 are called bias T inductors. The leading chip inductor L2 and the trailing chip inductors L1, ..., Ln are surface-mount type inductors that are configured with electrodes provided at both ends of a rectangular parallelepiped body, and are connected in series with wiring patterns 5a, 5b, ..., 5n-1 and connected in shunt to the transmission line 4. The trailing chip inductor Ln, which is the last to be connected in series to the leading chip inductor L2, is connected to a DC power source (not shown) via wiring pattern 5n.

A DC bias current i is supplied from the DC power supply to the transmission line 4 via the bias circuit 3, and a DC bias power supply is supplied by the bias circuit 3 to IC2 and a circuit (not shown) that communicates with IC2 via the transmission line 4.

For communication using the transmission line 4, PoC (Power Over Coax) transmission technology is used, which superimposes a signal and a DC bias power supply on a single transmission line 4. In PoC transmission technology, the high-frequency signal propagating through the transmission line 4 and the DC bias power supply supplied to the transmission line 4 are separated by the bias circuit 3. The bias circuit 3 must supply a DC current i from the DC power supply to the transmission line 4 while not preventing the high-frequency propagation signal s propagating through the transmission line 4 from transmitting from the signal input end of the transmission line 4 to the signal output end of the transmission line 4. Possible factors that hinder this transmission include leakage of the propagation signal s to the bias circuit 3, loss of the propagation signal s in the bias circuit 3 (conversion to heat), and reflection of the propagation signal s due to disturbance in the characteristic impedance of the connection between the bias circuit 3 and the transmission line 4.

The leading chip inductor L2 and the trailing chip inductors L1, ..., Ln constituting the bias circuit 3 have a self-resonant frequency set to the highest for the trailing leading chip inductor L1 among the trailing chip inductors L1, ..., Ln connected next to the leading chip inductor L2. The leading chip inductor L2 has a self-resonant frequency set to the second highest after the trailing leading chip inductor L1. The trailing chip inductors ..., Ln following the trailing leading chip inductor L1 have a self-resonant frequency set to be the same as the leading chip inductor L2 or successively smaller than the leading chip inductor L1. In addition, the inductance value of the trailing leading chip inductor L1 is the smallest, the leading chip inductor L2 is the next smallest, and the trailing chip inductors ..., Ln are set to be the same as the leading chip inductor L2 or successively larger than the leading chip inductor L1.

These chip inductors L2, L1, ..., Ln have high impedance near the self-resonant frequency, and can prevent the propagation signal s in the band near each self-resonant frequency from leaking to the bias circuit 3. The number of these chip inductors L2, L1, ..., Ln may be four or more.

The ground plane 1b formed on the back side of the component mounting surface 1a is drawn in light ink in the plan view of FIG. 1(a), and the conductive portion 1b2 of the area 1b1 located on the back side of the component mounting surface portion on which the bias circuit 3 is mounted is removed. A surface ground 6, described below, a portion of which is shown in FIG. 1(b), may be formed on the component mounting surface 1a. The wiring board 1 is formed in multiple layers, and in addition to the layer on which the ground plane 1b is formed, it also has a layer on which the ground plane 1c is formed, and the ground plane 1d is formed on the back side of the board. The surface ground 6 and each of the ground planes 1b, 1c, and 1d are electrically connected by through holes 7.

Figure 2 is a diagram illustrating an outline of a wideband transmission line wiring board 1A on which a bias circuit 3 according to a first embodiment of the present invention is implemented, where (a) is a plan view of the wiring board 1A and (b) is a cross-sectional view of the wiring board 1A taken along line IIb-IIb and viewed from the direction of the arrow.

The wiring board 1A according to the first embodiment differs from the wiring board 1 shown in Fig. 1 only in that the bias circuit 3 is composed of a leading chip inductor L2 and two trailing chip inductors L1, L3, and the other configurations are the same as those of the wiring board 1 shown in Fig. 1. The wiring board 1A avoids the above-mentioned factors that hinder the transmission of the propagating signal s through the transmission line 4, and the bias circuit 3 is configured to be wideband so that the transmission characteristic S21 of the transmission line 4 is -0.5 dB or more for propagating signals s up to 45 GHz and -2.5 dB or more for propagating signals s from 45 GHz to 60 GHz.

The transmission line 4 is a line such as a microstrip line or a coplanar line designed to have a characteristic impedance of 50 Ω. In the wiring board 1A, a surface ground 6 that surrounds the transmission line 4 is formed on the component mounting surface 1a, and the transmission line 4 is used as a coplanar line. In addition, a battery, a voltage regulator, or the like is used as the DC power source connected to the bias circuit 3.

Figure 3 is a graph showing the frequency characteristics of the impedance of each chip inductor L1, L2, and L3. The horizontal axis of the graph represents frequency [Hz], and the vertical axis represents impedance [Ω]. The thick solid characteristic line 21 represents the characteristics of the trailing leading chip inductor L1, the thin solid characteristic line 22 represents the characteristics of the leading chip inductor L2, and the dashed characteristic line 23 represents the characteristics of the trailing chip inductor L3.

The leading chip inductor L1 is 0603 (mm) size, has a self-resonant frequency of about 15 GHz, and an inductance value of 0.04 μH for high frequencies, while the leading chip inductor L2 is 0603 (mm) size, has a self-resonant frequency of about 1 GHz, and an inductance value of 3 μH for medium frequencies. The leading chip inductor L3 is 1608 (mm) size, has a self-resonant frequency of about 20 GHz, and an inductance value of 47 μH for low frequencies.

To prevent leakage of the propagation signal s to the bias circuit 3 over a wide band, it is desirable that the self-resonant frequency of the trailing leading chip inductor L1 be in the band of 10 to 30 GHz, the self-resonant frequency of the leading chip inductor L2 be in the band of 10 MHz to 10 GHz, and the self-resonant frequency of the trailing chip inductor L3 be in the band of 1 to 500 MHz. Each of the chip inductors L1, L2, and L3 has a high impedance near the self-resonant frequency, preventing the propagation signal s in the band near each of these self-resonant frequencies from leaking to the bias circuit 3.

In the graph showing the impedance frequency characteristics, if the impedance curves of the chip inductors L1, L2, and L3 are steep and a valley occurs in the composite impedance when connected in series, the bias circuit 3 may connect a resistor in parallel to at least one of the chip inductors L1, L2, and L3 so as to fill in the valley. In that case, the resistance value of the resistor connected in parallel is preferably 500 to 1000 Ω.

In this way, by connecting resistor R in parallel to any one of the chip inductors L1, L2, L3, the bandwidth of the self-resonant frequency of that chip inductor is appropriately set to an optimal bandwidth in relation to the bandwidth of the self-resonant frequency of an adjacent chip inductor, such that no band is generated between the self-resonant frequencies that would cause degradation of the transmission characteristic S21.

Figure 4 shows a bias circuit 8 that mimics a conventional wiring board 1Z with chip inductors L1, L2, and L3. This bias circuit 8, like the bias circuits shown in Patent Documents 1 and 2, is configured such that the trailing leading chip inductor L1, which has the highest self-resonant frequency, is placed closest to the connection point with the transmission line 4, followed by the leading chip inductor L2, which has the next highest self-resonant frequency after the trailing leading chip inductor L1, and finally the trailing chip inductor L3, which has the lowest self-resonant frequency.

Figure 5 is a graph showing the transmission characteristic S21 of the transmission line 4 supplied with power by the bias circuit 8 described above. The horizontal axis of the graph represents frequency, and the vertical axis represents the transmission characteristic S21 [dB]. Furthermore, characteristic line 24 represents the transmission characteristic S21 of the transmission line 4, and the dashed line represents an example of a target line 25 for the transmission characteristic S21. It is desirable that characteristic line 24 be located above target line 25 on the graph.

The conventional bias circuit 8 is configured to arrange inductors with higher self-resonant frequencies and smaller inductances closer to the connection point with the transmission line 4. Therefore, the trailing leading chip inductor L1, which has a self-resonant frequency of 10 to 30 GHz and is closest to the connection point with the transmission line 4, generates losses through the propagating signal s with a frequency lower than 10 GHz and converts them into heat. For this reason, as shown in the graph, the transmission characteristic S21 of the transmission line 4 is below the target line 25 in the frequency band indicated by the ellipse 26 lower than 10 GHz. For this reason, the bias circuit 8 cannot maintain the transmission characteristic S21 of the transmission line 4 at -0.5 dB or higher over an ultra-wide band from several MHz to several tens of GHz.

However, according to the wiring board 1A of the first embodiment, the propagation signal s in the frequency band lower than 10 GHz that was causing loss in the inductor (chip inductor L1) located closest to the connection point with the transmission line 4 on the wiring board 1Z is reflected by the impedance of the leading chip inductor L2, which has the second highest self-resonant frequency after the trailing leading chip inductor L1, and is prevented from entering the bias circuit 3. Therefore, the propagation signal s in the low frequency band that was causing loss no longer causes loss in the leading chip inductor L2 located closest to the connection point with the transmission line 4.

In addition, the propagation signal s in the high frequency band of the largest self-resonant frequency of the trailing leading chip inductor L1 passes through the leading inductor L2 and penetrates into the trailing leading chip inductor L1, and as shown in the cross-sectional view of the wiring board 1Z shown in FIG. 6, in the path from the leading chip inductor L2 to the trailing leading chip inductor L1, it tries to leak from the transmission line 4 to the ground surface 1b through the parasitic capacitance C generated between the leading chip inductor L2 and the ground surface 1b on the back side of the component mounting surface. Note that FIG. 6 is a cross-sectional view of the wiring board 1Z shown in FIG. 4, in which the arrangement of each chip inductor L1, L2, and L3 is the same as that of the wiring board 1A, cut along the line VI-VI and viewed from the direction of the arrow. However, in the ground surface 1b in the wiring board 1A, as shown in FIG. 2(b), the conductive portion 1b2 of the area 1b1 located on the back side of the component mounting surface portion on which the bias circuit 3 is mounted is removed, so that the occurrence of such parasitic capacitance C is reduced, and the propagation signal s in the high frequency band is prevented from leaking from the transmission line 4 to the ground surface 1b. This makes it possible to maintain high transmission characteristics S21 of the transmission line 4 over an ultra-wide band.

In addition, each of the chip inductors L1, L2, and L3 constituting the bias circuit 3 is composed of a surface-mount type chip inductor. Therefore, each of the chip inductors L1, L2, and L3 constituting the bias circuit 3 can be mounted on the wiring board 1A without occupying a large area, like the inductor formed in a conical structure with a transmission line pattern disclosed in Patent Document 1. Therefore, the area of the conductive part removal area 1b1 located on the ground surface 1b on the back side of the component mounting surface portion on which the bias circuit 3 is mounted can be reduced, thereby preventing the impedance of the ground surface 1b from increasing. As a result, noise problems due to potential vibrations generated on the ground surface 1b do not occur.

To confirm the above-mentioned effects of the wiring board 1A according to the first embodiment, the transmission characteristic S21 of the transmission line 4 was actually measured. Figure 7(a) is a component layout diagram of the measurement board 1A' used in this measurement, Figure 7(b) is a diagram of the wiring patterns formed on the front and back surfaces of the measurement board 1A', and Figure 8 is a cross-sectional view of the measurement board 1A' cut along line VIII-VIII shown in Figure 7(a) and viewed from the direction of the arrows. The numerical values in each of these figures are in mm.

As shown in Figure 7 (a), the measurement board 1A' has a size of 12 mm square, and a transmission line 4 with a characteristic impedance of 51 Ω is formed as a coplanar line at a position 5 mm away from the upper end. The transmission line 4 has a width of 0.20 mm, with the left end being the signal input terminal 4a and the right end being the signal output terminal 4b. Surface grounds 6, 6 are formed on both sides of the transmission line 4 with a gap of 0.1 mm. A resistor R of 1,000 Ω is connected in parallel to the trailing chip inductor L3. The center lines of the leading chip inductor L2 and the trailing leading chip inductor L1 coincide with the center line of the trailing chip inductor L3, and each center line is on line VIII-VIII.

As shown in Figure 7 (b), chip inductors L1, L2, and L3, indicated by dashed lines, are connected in series by wiring patterns 5a and 5b. The last subsequent chip inductor L3 is connected to the board ground instead of the power supply by wiring pattern 5c. Mounting pads 5d and 5e for mounting the subsequent chip inductor L3 are formed between the wiring patterns 5b and 5c, and mounting pads 5f and 5g for mounting resistors R are formed in parallel to each mounting pad 5d and 5e. The conductive portion 1b2 of area 1b1 on the back surface of the bias circuit 3 has been removed.

As shown in Figure 8, the ground planes 1b, 1c, and 1d on the back surface of the board are arranged in three layers with 0.15 mm intervals. The conductive portion removal area 1b1 is formed in the layer closest to the surface of the measurement board 1A'.

Figure 9 is a perspective view showing the measurement system used to measure the transmission characteristic S21 of the transmission line 4 in the measurement board 1A'. The measurement was performed using a network analyzer 31 (model: N5222A) manufactured by Keysight, a prober 32 (model: SUMMIT9000) manufactured by Cascade Microtech, and an RF probe 33 (model: ACP65A-GSG-250). The network analyzer 31 to the tip of the RF probe 33 was calibrated by applying OPEN/LOAD/SHORT correction, and the S parameters between the input terminal 4a and the output terminal 4b at both ends of the transmission line 4 in the measurement board 1A' were measured. The measured S parameters were obtained by de-embedding the transmission line 4, and only the transmission characteristic S21 of the connection part between the bias circuit 3 and the transmission line 4, shown by the white arrow 34 in Figure 7 (b), was obtained.

Figure 10(a) is a graph showing the above measurement results together with a comparative example. The horizontal axis of the graph represents frequency [Hz], and the vertical axis represents transmission characteristic S21 [dB]. The characteristic line 41 represented by a thick solid line shows the transmission characteristic S21 of the transmission line 4 measured as described above when the bias circuit 3 in the measurement substrate 1A' is configured by connecting chip inductors L2, L1, and L3 in series in this order as shown in Figure 10(b) and the conductive portion removed area 1b1 is formed on the back ground 1b. The characteristic line 42 represented by a thin solid line shows the transmission characteristic S21 of the transmission line 4 measured as described above when the bias circuit 3 in the measurement substrate 1A' is configured by connecting chip inductors L2, L1, and L3 in series in this order as shown in Figure 10(c), but the conductive portion removed area 1b1 is not formed on the back ground 1b. The dashed characteristic line 43 indicates the transmission characteristic S21 of the transmission line 4 measured as described above when the bias circuit 3' in the measurement substrate 1A' is configured by connecting chip inductors L1, L2, and L3 in series in this order, as shown in FIG. 10(d), and no conductive portion removed area 1b1 is formed in the back-surface ground 1b.

From this graph, it was confirmed that when the transmission line 4 is connected to the bias circuit 3 as in the wiring board 1A of the first embodiment, the transmission characteristic S21 of the transmission line 4 represented by the characteristic line 41 exceeds the target line 25 over an ultra-wide band from several MHz to several tens of GHz, and the transmission characteristic S21 of the transmission line 4 is maintained above the target value over the ultra-wide band.

In addition, when the conductive portion removal area 1b1 is not formed on the back surface of the bias circuit 3, the transmission characteristic S21 of the transmission line 4 represented by the characteristic line 42 falls below the target line 25 in the high frequency band above about 55 GHz due to the influence of the stray capacitance C (see Figure 6), and it was confirmed that the high frequency characteristics are deteriorated.

In addition, when the chip inductors L1, L2, and L3 are connected in series in descending order of self-resonant frequency as in the conventional case, the transmission characteristic S21 of the transmission line 4 represented by the characteristic line 43 falls below the target line 25 in the low frequency band of 10 GHz or less, as explained in the problem of the conventional technology using FIG. 5, and it was confirmed that the low frequency characteristic is deteriorated. This is because the chip inductor L1, which has a self-resonant frequency of 10 to 30 GHz, has a low impedance of 1 to 10 GHz (see FIG. 3), and passes the propagation signal s in this 1 to 10 GHz frequency band. At this time, the propagation signal s in this 1 to 10 GHz frequency band is converted into heat due to the loss of the chip inductor L1, so if the chip inductor L1 is placed immediately adjacent to the connection point with the transmission line 4, the transmission characteristic S21 of the transmission line 4 will decrease in this low frequency band.

For this reason, in this embodiment, the leading chip inductor L2, which has a self-resonant frequency band of 1 to 10 GHz, is placed in front of the trailing leading chip inductor L1, that is, immediately adjacent to the connection point with the transmission line 4, so that the propagation signal s of this frequency band does not reach the trailing leading chip inductor L1. At this time, since the trailing leading chip inductor L1 is placed away from the transmission line 4, a parasitic capacitance C that interferes with the high-frequency propagation signal s is likely to occur between the connection point with the transmission line 4 and the trailing leading chip inductor L1. This parasitic capacitance C reduces the characteristic impedance of the connection point between the transmission line 4 and the bias circuit 3, deteriorating the transmission characteristic S21 of the transmission line 4. For this reason, in this embodiment, the region 1b1 on the ground surface 1b on the back side of the bias circuit 3 is deleted to reduce the occurrence of the parasitic capacitance C and maintain the transmission characteristic S21.

These measurement results confirmed the effectiveness of the wiring board 1A according to the first embodiment. That is, the wiring board 1A according to the first embodiment makes it possible to maintain the transmission line 4 at a high transmission characteristic S21 over an ultra-wide band, and also makes it possible to mount a bias circuit 3 on the wiring board 1A that does not cause noise problems due to potential oscillations on the ground surface 1b.

Figure 11 is a cross-sectional view of a wideband transmission line wiring board 1B according to a second embodiment of the present invention.

In this wiring board 1B, the ground surface on the back side of the board has the conductive portion removed from the back side of the component mounting surface portion on which the bias circuit 3 is mounted on multiple layer surfaces, including the layer surface closest to the component mounting surface 1a. For example, as shown in the figure, the conductive portion 1b2 of the region 1b1 located on the back side of the component mounting surface portion on which the bias circuit 3 is mounted on the ground surface 1b of the layer surface closest to the component mounting surface 1a is removed, and the conductive portion 1c2 of the region 1c1 located on the back side of the component mounting surface portion on which the bias circuit 3 is mounted on the ground surface 1c of the layer surface next closest to the component mounting surface 1a is removed.

According to the wiring board 1B equipped with the bias circuit 3 according to the second embodiment, the conductive parts 1b2, 1c2 of the regions 1b1, 1c1 located on the back side of the component mounting surface portion on which the bias circuit 3 is mounted are removed on multiple layer surfaces including the layer surface closest to the component mounting surface 1a on which the bias circuit 3 is mounted, so that the parasitic capacitance C generated between, for example, the ground surfaces 1b, 1c on each layer surface on the back side of the component mounting surface is reduced on the path from the leading inductor L2 to the trailing leading chip inductor L1. Therefore, the magnitude of the parasitic capacitance C is further suppressed, and the leakage of the propagation signal s in the high frequency band from the transmission line 4 to, for example, the ground surfaces 1b, 1c is more effectively prevented. Therefore, it is possible to further improve the transmission characteristic S21 of the transmission line 4 in the high frequency band.

Figure 12 is a cross-sectional view of a wideband transmission line wiring board 1C according to a third embodiment of the present invention, and Figure 13 is a diagram of the wiring patterns formed on the front and back surfaces of the wiring board 1C.

In this wiring board 1C, the ground surface on the back side of the board is removed, and only the conductive portion 1b2 in the area 1b3 located on the back side of the component mounting surface portion where the bias circuit 3 is mounted, from the leading chip inductor L2 to the point where the trailing leading chip inductor L1 is mounted, is removed.

According to the wiring board 1C of the third embodiment, the area where the conductive part of the ground surface is removed to reduce the occurrence of parasitic capacitance C is limited to only the area located on the back side of the component mounting surface from the leading chip inductor L2 to the location where the trailing leading chip inductor L1 is mounted. This is because the deterioration of the transmission characteristic S21 in the high frequency band is caused by the parasitic capacitance C that occurs between the connection point of the transmission line 4 and the bias circuit 3 and the trailing leading chip inductor L1, which reduces the characteristic impedance. Therefore, even if the removal area of the back ground is narrowed down to the area from the connection point to the trailing leading chip inductor L1, the effect of suppressing the deterioration of the transmission characteristic in the high frequency band is not significantly impaired.

According to the wiring board 1C of the third embodiment, the area of the conductive portion removal region 1b3 located on the ground surface 1b on the back side of the component mounting surface portion on which the bias circuit 3 is mounted can be further reduced, thereby further suppressing an increase in the impedance of the ground surface 1b. This makes it possible to minimize the occurrence of noise problems due to potential oscillations occurring on the ground surface 1b, which are calculated by the product of the current amplitude and the ground impedance when an AC current flows through the ground surface 1b.

1, 1A, 1B, 1C... Wiring board 1a... Component mounting surface 1b, 1c, 1d... Ground surface 1b1, 1c1, 1b3... Area 1b2, 1c2... Conductive part 2... IC
3: Bias circuit 4: Transmission line 5a, 5b, 5n-1, 5n: Wiring patterns 5d, 5e, 5f, 5g: Mounting pads 6: Surface ground 7: Through hole L1: Subsequent leading chip inductor L2: Leading chip inductor L3, Ln: Subsequent chip inductor

Claims (4)

a transmission line formed on the component mounting surface through which a high frequency signal propagates;
a bias circuit including a first chip inductor having one end connected to the transmission line at a location on the component mounting surface closest to a connection point with the transmission line and mounted on the component mounting surface, and a plurality of subsequent chip inductors connected in series to the first chip inductor from a location second closest to the connection point and mounted on the component mounting surface, the last one connected in series being connected to a DC power source, the self-resonant frequency of the subsequent first chip inductor among the subsequent chip inductors connected next to the first chip inductor at the location second closest to the connection point being the largest, the first chip inductor being the second largest after the subsequent first chip inductor, and the subsequent chip inductors following the subsequent first chip inductor being set to the same frequency as the first chip inductor or successively smaller frequencies than the first chip inductor;
a ground surface formed on a rear surface of the component mounting surface, the ground surface being formed by removing a conductive portion in an area located on the rear surface of the component mounting surface on which the bias circuit is mounted. The wideband transmission line wiring board according to claim 1, characterized in that the ground plane is formed by removing conductive portions in an area located on the back side of the component mounting surface on which the bias circuit is mounted, on a plurality of layer surfaces including the layer surface closest to the component mounting surface. The broadband transmission line wiring board according to claim 1, characterized in that the ground plane is removed from the conductive portion only in the area located on the back side of the component mounting surface portion on which the bias circuit is mounted, from the first chip inductor to the location where the subsequent first chip inductor is mounted. A wideband transmission line wiring board as described in any one of claims 1 to 3, characterized in that the bias circuit has a resistor connected in parallel to at least one of the leading chip inductor and the trailing chip inductor.

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