JP7525740B2 - Power conversion device and power conversion method - Google Patents

Description

The present invention relates to a power conversion device and a power conversion method that employ a power semiconductor element having multiple gate control terminals.

Power conversion devices used to control motors in railway vehicles and the like control high voltage and large current, so if the power semiconductor elements that make up the device are miscontrolled, causing a power supply short circuit, the device itself can be severely damaged.
Therefore, if a power semiconductor element operates abnormally, it is necessary to immediately stop the device to avoid damage to the device.

To achieve this, as shown in Patent Document 1, a method is adopted in which the switching command (PWM command) for the power semiconductor element is compared with the actual on/off state of the power semiconductor element, and when a mismatch occurs, it is determined that there is an abnormality in the power semiconductor element or the circuit that drives the power semiconductor element, and the operation of the gate drive circuit is stopped.

On the other hand, in recent years, driving technologies for power semiconductor elements having multiple gate control terminals (hereinafter referred to as "multi-gate semiconductor elements") have been developed as a technology for reducing losses in power semiconductor elements, and the two technologies described below have been disclosed.

The first is a technology related to the dual-gate IGBT described in Patent Document 2. This dual-gate IGBT has two gate terminals (switching gate terminal Gs and carrier control gate terminal Gc) for one collector terminal and one emitter terminal. By controlling the gate commands input to the two gate terminals in a predetermined sequence based on the PWM command, the switching loss is reduced more than in conventional IGBTs.

The second technology is related to MOS-controlled diodes, which are described in Patent Document 3. This MOS-controlled diode is provided with an insulated gate of a MOS structure in the diode, and by applying a voltage to the insulated gate in a predetermined sequence based on a PWM command, the amount of internal charge is controlled, thereby reducing diode loss.

JP 2009-201311 A JP 2019-161720 A JP 2015-204723 A

In a power conversion device using the above multi-gate semiconductor element, in addition to the means for generating a PWM command, it is necessary to add a means for generating multiple gate commands based on the PWM command and switch the multi-gate semiconductor element based on the multiple gate commands. Therefore, in the event of an abnormality, a method is required for emergency stopping the switching of the multi-gate semiconductor element while taking into account the sequence of the multiple gate commands.

For example, when applying the MOS-controlled diode described in Patent Document 3, it is necessary to delay the PWM command by a predetermined time from the command given to the gate terminal of the MOS-controlled diode, so that the cessation of switching when an abnormality occurs must not be delayed.

In addition, in high-voltage, high-current power conversion devices used in railway vehicles and the like, a low-current controller (hereinafter referred to as the "control logic unit") consisting of a PWM command generation unit etc., and a high-current unit (hereinafter referred to as the "power unit") consisting of a gate drive circuit and power semiconductor elements are often wired together via insulating elements.

In this case, when a power conversion device using a multi-gate semiconductor element places a means for generating multiple gate commands within the control logic unit, the number of wiring increases and the device size becomes larger than in a power conversion device using a single-gate power semiconductor element.

In order to solve the above problems, the present invention aims to provide a power conversion device using a multi-gate semiconductor element, which suppresses the increase in size of the device due to an increase in the number of wirings, and is capable of quickly stopping the switching of the multi-gate semiconductor element when an abnormality occurs in the device.

In order to solve the above problems, one representative power conversion device of the present invention comprises a power converter composed of a multi-gate semiconductor element having multiple gate control terminals, and which switches the multi-gate semiconductor element to control the power supplied to a load, a gate drive unit which drives the multi-gate semiconductor element, and a control logic unit which generates a PWM command to be given to the gate drive unit, wherein the gate drive unit generates a drive signal to be given to the multiple gate control terminals based on the PWM command and also generates a feedback signal indicating the on/off state of the multi-gate semiconductor element, and the control logic unit compares the PWM command with the feedback signal and generates a command different from the PWM command based on the result of the comparison and superimposes it on the PWM command.

According to the present invention, it is possible to prevent the power conversion device using a multi-gate semiconductor element from becoming larger in size, and to increase the safety of the power conversion device by quickly stopping the switching of the multi-gate semiconductor element when an abnormality in the device occurs.
Problems, configurations and effects other than those described above will become apparent from the description of the following embodiments.

1 is a diagram showing a configuration of a power conversion device according to a first embodiment of the present invention; FIG. 11 is a time chart of upper and lower arm PWM commands generated by a PWM command generating unit; FIG. 13 is a diagram showing a time chart of signals generated by an emergency stop command generating unit and a gate driving unit for the U-phase upper arm under normal conditions. FIG. 13 is a time chart showing a case where a feedback signal is erroneously turned off as an abnormality. FIG. 13 is a time chart showing a case where a false ON occurs in a feedback signal as an abnormality. FIG. 11 is a diagram showing a configuration of a power conversion device according to a second embodiment of the present invention.

In the following, examples 1 and 2 will be described with reference to the drawings as a form for implementing the present invention. Note that the present invention is not limited to these embodiments. In addition, in the description of the drawings, the same parts are denoted by the same reference numerals.

FIG. 1 is a diagram showing a configuration of a power conversion device according to a first embodiment of the present invention.
The power conversion device shown in FIG. 1 is a three-phase inverter system that receives DC power from a DC power source 3 and controls the speed of a three-phase AC motor 4 , and is made up of a control logic unit 1 and a power unit 2 .

In addition, the control logic unit 1 receives as input the motor current detected by the current sensors 38 to 40 and the power supply voltage detected by the voltage sensor 41.

The power unit 2 is composed of multi-gate semiconductor elements 32-37 and gate drive units 21-26, and a gate drive unit shown inside the reference symbol 21 and a multi-gate semiconductor element shown inside the reference symbol 32 are arranged on each of the three-phase positive potential side (hereinafter referred to as the "upper arm") and the three-phase negative potential side (hereinafter referred to as the "lower arm") of the DC power supply 3.

Here, the multi-gate semiconductor element shown inside the reference numeral 32 is a semiconductor element composed of a dual-gate IGBT 27 and a MOS control diode 28, and has three gate terminals: a Gs terminal 29 for switching commands, a Gc terminal 30 for carrier control, and a Gd terminal 31 for the MOS control diode. In addition, although a type having three gate terminals is shown in FIG. 1, this is not limited thereto, and a multi-gate semiconductor element having two gate terminals, the Gs terminal and the Gc terminal, as described above, may also be used.

The gate driving unit shown inside the reference symbol 21 includes a control command generating unit 18 that generates gate commands to be given to the Gs terminal 29, the Gc terminal 30 and the Gd terminal 31 based on the PWM command input from the control logic unit 1, a gate driving circuit 19 that converts the gate command of the control command generating unit 18 into a voltage capable of driving the multi-gate semiconductor element 32, and a feedback signal generating unit 20 that detects the on/off state of the multi-gate semiconductor element 32 based on the voltage applied to the Gs terminal 29 and converts the on/off state into a binary feedback signal.

Here, as shown in FIG. 1, the PWM commands input to the gate drive units 21 to 26 of the three-phase upper and lower arms are PWM_u1, PWM_u2, PWM_v1, PWM_v2, PWM_w1 and PWM_w2, and the feedback signals output from the gate drive units 21 to 26 of the three-phase upper and lower arms are FB_u1, FB_u2, FB_v1, FB_v2, FB_w1 and FB_w2.

The control logic unit 1 includes a voltage command generation unit 5 which generates a voltage command for controlling the three-phase AC motor, a PWM command generation unit 6 which generates switching commands (PWM commands) for the multi-gate semiconductor elements 32-37 based on the voltage command from the voltage command generation unit 5, emergency stop command generation units 10-15 which generate emergency stop commands for the multi-gate semiconductor elements 32-37, and an OR circuit 16 which performs an OR operation on the emergency stop detection flags of the emergency stop command generation units 10-15.

Here, as shown in FIG. 1, the PWM commands for the three-phase upper and lower arms output from the PWM command generating unit 6 are PWM_u1', PWM_u2', PWM_v1', PWM_v2', PWM_w1' and PWM_w2', and the emergency stop flags output from the emergency stop command generating units 10 to 15 are Flg_u1, Flg_u2, Flg_v1, Flg_v2, Flg_w1 and Flg_w2.

The emergency stop command generating unit shown inside the reference symbol 10 includes a PWM command delay unit 7 that delays the PWM command, a PWM command comparison unit 9 that compares the delayed PWM command with a feedback signal, and a command superposition unit 8 that superimposes the emergency stop command on the PWM command, and this emergency stop command generating unit is disposed for each of the three-phase upper and lower arms.

The PWM commands output from the emergency stop command generating units 10 to 15 and the feedback signals output from the gate driving units 21 to 26 are transmitted using wiring 17 between the control logic unit 1 and the power unit 2.

In addition, the voltage command generation unit 5 performs analog-to-digital conversion of the three-phase motor currents Iu, Iv, and Iw detected by the current sensors 38-40, and the voltage Vdc of the DC power supply 3 detected by the voltage sensor 41. Then, using the detected values of Iu, Iv, Iw, and Vdc, the voltage command is calculated by feedback control so that Iu, Iv, and Iw become predetermined currents.

Next, the normal operation of the power conversion device according to the first embodiment will be described with reference to FIGS. 2 and 3. FIG.
Fig. 2 is a diagram showing a time chart of PWM commands (PWM_u1' and PWM_u2') for the upper and lower arms generated by the PWM command generating unit 6. Note that Fig. 2 is a time chart using the U phase as an example, and for the V phase and W phase, the phases are shifted by 120 degrees and 240 degrees (not shown) from the time chart in Fig. 2.

As shown in Figure 2, the PWM commands for the upper and lower arms generated by the PWM command generating unit 6 have times when they are turned on and off in opposite phases, and non-overlapping times 42 and 43 when the upper and lower arms are turned off simultaneously before switching on and off.

Next, the normal operation of the emergency stop command generating units 10 to 15 and the gate driving units 21 to 26 will be described with reference to FIG.
3 is a diagram showing a time chart of signals generated by the emergency stop command generator 10 and the gate driver 21 for the U-phase upper arm under normal conditions. The U-phase lower arm, the V-phase upper and lower arms, and the W-phase upper and lower arms also operate in the same manner as in FIG.

Under normal circumstances, the PWM command PWM_u1' input from the PWM command generation unit 6 is output as is from the emergency stop command generation unit 10 as PWM_u1 and input to the control command generation unit 18 in the gate drive unit 21. At this time, when PWM_u1 changes from off to on, a turn-on delay 44 of PWM_u1 occurs from the output of the emergency stop command generation unit 10 to the input of the gate drive unit 21. Similarly to this delay, when PWM_u1 is turned off, a turn-off delay 51 (shown in FIG. 5) also occurs.

Based on PWM_u1, the control command generating unit 18 generates a gate command Gs_u1 for the Gs terminal 29, a gate command Gc_u1 for the Gc terminal 30, and a gate command Gd_u1 for the Gd terminal 31. At this time, in order to provide the three-phase AC motor 4 with an AC voltage according to the voltage command of the voltage command generating unit 5, Gs_u1 needs to have the same on-width as PWM_u1. In addition, to generate the auxiliary gate commands Gc_u1 and Gd_u1, two control times 45 and 46 are provided before and after the edge of Gs_u1. The time charts of Gs_u1, Gc_u1, and Gd_u1 are also explained in Patent Document 2 and Patent Document 3, so they will not be described in this specification.

The gate drive circuit 19 converts Gs_u1, Gc_u1 and Gd_u1 into predetermined command voltages, then inputs them to the three gate terminals of the multi-gate semiconductor element 32, and switches the multi-gate semiconductor element 32 based on the command of Gs_u1.

The feedback signal generating unit 20 monitors the command voltage of Gs_u1 output by the gate drive circuit 19 and detects the on/off state of the Gs terminal. It then converts this on/off state into a binary digital signal and outputs it to the PWM command comparison unit 9 in the emergency stop command generating unit 10 as the feedback signal FB_u1.

The emergency stop command generation unit 10 compares PWM_u1' with FB_u1 in the PWM command comparison unit 9. At this time, due to a command propagation delay that occurs within the power conversion device, the on/off timing of FB_u1 is delayed relative to PWM_u1'. Therefore, to prevent the PWM command comparison unit 9 from erroneously detecting an abnormality, PWM_u1' is delayed in the PWM command delay unit 7. There are two types of delay time: a turn-on delay time 49 and a turn-off delay time 50.

The turn-on delay time 49 is determined based on the time Ton (not shown) from when PWM_u1' is turned on until the Gs terminal 29 of the multi-gate semiconductor element 32 is turned on and the feedback signal FB_u1 input to the PWM command comparison unit 9 is turned on. Specifically, Ton varies depending on the temperature fluctuations and characteristic variations of the control logic unit 1, the circuits in the gate drive unit 21, and the multi-gate semiconductor element 32, so a maximum value of Ton is set taking the range of fluctuation into consideration.
Similarly, for the turn-off delay time 50, the maximum value of the time Toff (not shown) from when PWM_u1' is turned off to when FB_u1 is turned off is set.

The PWM command comparison unit 9 compares PWM_u1d, which is PWM_u1' delayed by the PWM command delay unit 7, with FB_u1, and if the two match (normal), turns off the emergency stop flag Flg_u1.

Furthermore, if the comparison result of the PWM command comparison unit 9 is a match, the PWM command comparison unit 9 gives a "no emergency stop" command to the command superimposition unit 8. When the command superimposition unit 8 receives the "no emergency stop" command, it outputs PWM_u1' as PWM_u1 without any change.

Next, an operation of the power conversion device according to the first embodiment when an abnormality occurs will be described with reference to FIG. 4 and FIG.
As in FIG. 3, FIG. 4 and FIG. 5 show time charts for the U-phase upper arm command, but the U-phase lower arm, the V-phase upper and lower arms, and the W-phase upper and lower arms also have time charts similar to those in FIG.

Figure 4 is a diagram showing a time chart when an erroneous turn-off occurs in the feedback signal FB_u1 as an abnormality. In Figure 4, the erroneous turn-off occurs at the timing indicated by the reference numeral 52. Examples of causes of this erroneous turn-off include a failure in the gate drive unit and an open failure in the multi-gate semiconductor element.

When a false OFF occurs in the feedback signal FB_u1, the PWM command comparison unit 9 detects a mismatch between PWM_u1d and FB_u1, turns on the emergency stop flag Flg_u1, and outputs an emergency stop command to the command superimposition unit 8. At this time, the emergency stop flag Flg_u1 is held on until a recovery command is received from a system (not shown) external to the control logic unit 1.

When an emergency stop command is input while PWM_u1' is on, the command superimposition unit 8 superimposes a one-shot off pulse 54 shown in Fig. 4 on PWM_u1. Here, the pulse width 55 of the one-shot off pulse 54 is set to be shorter than the minimum off pulse width of the PWM command so that it can be distinguished from the PWM command.

When the control command generating unit 18 in the gate driving unit 21 receives the PWM_u1 with the emergency stop command superimposed thereon, it detects the one-shot off pulse 54 in the PWM_u1 and turns off the three gate commands (Gs_u1, Gc_u1, and Gd_u1) at the timing of reference symbol 58 shown in FIG. 4. At this time, the time from when the feedback signal FB_u1 is erroneously turned off to when the three gate commands (Gs_u1, Gc_u1, and Gd_u1) are turned off is the sum of the one-shot off pulse width 55 and the turn-off delay 48 of PWM_u1.

Figure 5 is a time chart showing an abnormality in which a false ON occurs in the feedback signal FB_u1. In Figure 5, the false ON occurs at the timing indicated by the reference numeral 59. Thereafter, in the same manner as when a false OFF occurs, the PWM command comparison unit 9 detects a mismatch between PWM_u1d and FB_u1, turns on the emergency stop flag Flg_u1, and outputs an emergency stop command to the command superposition unit 8.

When an emergency stop command is input while PWM_u1' is off, the command superimposition unit 8 superimposes a one-shot on pulse 61 shown in FIG. 5 on PWM_u1. Like the pulse width 55 of the one-shot off pulse 54, the pulse width 62 of the one-shot on pulse 61 is also set to a width shorter than the minimum on pulse width of the PWM command so that it can be distinguished from the PWM command.

When the control command generating unit 18 in the gate driving unit 21 receives the PWM_u1 with the emergency stop command superimposed thereon, it detects the one-shot on pulse 61 in the PWM_u1 and turns off the three gate commands (Gs_u1, Gc_u1, and Gd_u1) at the timing of 64 shown in Fig. 5. At this time, the time from when the feedback signal FB_u1 is erroneously turned on to when the three gate commands (Gs_u1, Gc_u1, and Gd_u1) are turned off is the sum of the one-shot on pulse width 62 and the turn-off delay 51 of PWM_u1.

Here, as mentioned above, if one arm undergoes an emergency stop, the power conversion device will be in a state where one arm is missing and control is performed. In that case, there is a risk that the motor current will become an overcurrent due to control divergence, so when one arm undergoes an emergency stop, it is necessary to stop the operation of all other arms.

Therefore, in the power conversion device of Example 1, an OR circuit 16 is provided inside the control logic unit 1 to take the OR of the emergency stop flags of the three-phase upper and lower arms, and the result (Flg_Gate_err shown in Figure 1) is input to the voltage command generation unit 5 and the PWM command generation unit 6.

As shown in Figures 4 and 5, when the emergency stop flag Flg_u1 is turned on, Flg_Gate_err is also turned on via the OR circuit 16, and the voltage command generating unit 5 and the PWM command unit 6 turn off the voltage command and the PWM commands for all three-phase upper and lower arms after a certain time (time element 57 shown in Figure 4) has elapsed.

This allows the operation of all multi-gate semiconductor elements in the other arms to be stopped when an abnormality occurs in one arm. Here, time element 57 is the time required for control command generator 18 to detect the off-on change of one-shot off pulse 54 or one-shot on pulse 61, and should be shorter than the time required for the system to recover from an emergency stop.

Next, the effects of the first embodiment will be described.
In a power conversion device that uses a multi-gate semiconductor element, multiple gate commands must be generated based on a PWM command generated by a control logic unit, so there is a concern that an increase in the number of wiring (and thus an increase in the size of the device) will accompany the increase in gate commands.

In the present invention, multiple gate commands are generated within the power unit, which reduces the number of wires between the control logic unit and the power unit compared to generating them in the control logic unit, thereby preventing the device from becoming larger.

On the other hand, since multiple gate commands are generated within the power unit, a means of transmitting an abnormality to the power unit when an abnormality occurs and a means of quickly stopping the multiple gate commands when an abnormality occurs are required.

Therefore, in the present invention, when an abnormality occurs, a narrow one-shot pulse that can be distinguished from the PWM command is superimposed on the PWM command to emergency stop the switching of the multi-gate semiconductor element. Because a signal indicating an abnormality in the device is superimposed on the PWM command, wiring to transmit the abnormality is not required, and the size of the device can be reduced.

As described above, the present invention prevents the power conversion device using a multi-gate semiconductor element from becoming larger, and can quickly stop switching of the multi-gate semiconductor element when an abnormality occurs in the device, thereby improving the safety of the power conversion device.

FIG. 6 is a diagram showing a configuration of a power conversion device according to a second embodiment of the present invention.
The power conversion device shown in FIG. 6 has the same configuration as the power unit in the first embodiment, but has a different configuration for the control logic unit.

The control logic unit 100 of the second embodiment is obtained by adding to the control logic unit 1 of the first embodiment a voltage monitoring unit 101 that monitors the DC voltage Vdc and detects an overvoltage of this Vdc, a current monitoring unit 102 that monitors the three-phase motor currents Iu, Iv and Iw and detects an overcurrent of the motor current, and an OR circuit 103 that performs an OR operation on the overvoltage flag (Flg_Ovd shown in FIG. 6) detected by the voltage monitoring unit 101 and the overcurrent flag (Flg_Ocd shown in FIG. 6) detected by the current monitoring unit 102.

In addition, the output of the OR circuit 103 (Flg_Gate_stop shown in Figure 6) is input to the emergency stop command generating units 10 to 15.

In the control logic unit 100, when the voltage monitoring unit 101 detects an overvoltage in the DC voltage Vdc, or when the current monitoring unit 102 detects an overcurrent in any of the three-phase motor currents Iu, Iv, and Iw, the Flg_Gate_stop output of the OR circuit 103 is turned on.

When Flg_Gate_stop is turned on, the emergency stop command generation units 10 to 15 provide this on change to the command superimposition unit 8 (indicated by * in FIG. 6). As a result, the command superimposition unit 8 superimposes a one-shot pulse on the PWM command, as in the first embodiment, to bring about an emergency stop of the switching of the multi-gate semiconductor element.

Although the above describes embodiments 1 and 2 of the present invention, the present invention is not limited to the above-mentioned embodiments 1 and 2, and various modifications are possible without departing from the spirit and scope of the present invention.

1, 100: control logic unit, 2: power unit, 3: DC power supply, 4: three-phase AC motor, 5: voltage command generation unit, 6: PWM command generation unit, 7: PWM command delay unit, 8: command superposition unit, 9: PWM command comparison unit, 10, 11, 12, 13, 14, 15: emergency stop command generation unit, 16: OR circuit, 17: wiring, 18: control command generation unit, 19: gate drive circuit, 20: feedback signal generation unit, 21, 22, 2 3, 24, 25, 26: gate driver, 27: dual gate IGBT, 28: MOS control diode, 29: Gs terminal, 30: Gc terminal, 31: Gd terminal, 32, 33, 34, 35, 36, 37: multi-gate semiconductor element, 38, 39, 40: current sensor, 41: voltage sensor, 42, 43: non-lap time, 44: turn-on delay of PWM command from emergency stop command generator output to gate driver input 45: control time 1 of Gs command, 46: control time 2 of Gs command, 47: turn-on delay of feedback signal, 48: turn-off delay of feedback signal, 49: delay time of PWM command at turn-on, 50: delay time of PWM command at turn-off, 51: turn-off delay of PWM command from output of emergency stop command generating unit to input of gate driving unit, 52: timing of occurrence of false off of feedback signal, 53, 60: timing to start superimposing emergency stop command, 54: one-shot off pulse, 55: one-shot off pulse width, 61: one-shot on pulse, 62: one-shot on pulse width, 56, 63: timing to stop PWM command in abnormality, 57: timing to stop PWM command, 58, 64: off timing of Gs command, Gc command, Gd command, 101: voltage monitoring unit, 102: current monitoring unit, 103: OR circuit

Claims (9)

a power conversion unit configured by a multi-gate semiconductor element having a plurality of gate control terminals, and controlling power supplied to a load by switching the multi-gate semiconductor element;
a gate driver for driving the multi-gate semiconductor device;
a control logic unit that generates a PWM command to be provided to the gate driver;
the gate driver generates drive signals to be provided to the gate control terminals based on the PWM command, and generates a feedback signal indicating an on/off state of the multi-gate semiconductor device;
The control logic unit generates a short pulse that is distinguishable from the PWM command as an emergency stop command and superimposes it on the PWM command when the comparison result between the PWM command and the feedback signal indicates a mismatch. (delete) The power conversion device according to claim 1,
The control logic unit
If the PWM command is an ON command, the short pulse is converted into a one-shot OFF pulse to generate the emergency stop command,
When the PWM command is an OFF command, the short pulse is turned into a one-shot ON pulse to generate the emergency stop command. The power conversion device according to claim 3,
The power conversion device according to claim 1, wherein the control logic unit turns off the PWM command after generating the emergency stop command and until a recovery command is issued. The power conversion device according to claim 3 or 4,
The width of the one-shot on-pulse is shorter than the minimum on-pulse width of the PWM command,
A power conversion device, characterized in that a width of the one-shot off-pulse is shorter than a minimum off-pulse width of the PWM command. A power conversion device according to any one of claims 1 and 3 to 5,
The power conversion device is configured using a three-phase inverter that drives and controls a three-phase AC load,
the power conversion unit and the gate drive unit are provided for each of upper and lower three-phase arms for a positive potential side and a negative potential side of a DC power supply of the three-phase inverter,
The power conversion device, wherein the control logic unit generates the PWM commands corresponding to the respective gate drivers. The power conversion device according to claim 6,
a monitoring unit that monitors a voltage detection signal of the DC power supply or an output current detection signal of the three-phase inverter,
the monitoring unit outputs an abnormality signal to the control logic unit when detecting an overvoltage from the voltage detection signal or an overcurrent from the output current detection signal;
The power conversion device according to claim 1, wherein the control logic unit, when receiving the abnormality signal, superimposes a short pulse, which is distinguishable from the PWM command, on the PWM command as an emergency stop command. A power conversion unit is configured by a multi-gate semiconductor element having a plurality of gate control terminals, and controls power supplied to a load by switching the multi-gate semiconductor element.
generating drive signals to be provided to the plurality of gate control terminals based on a PWM command;
generating a feedback signal indicative of an on/off state of the multi-gate semiconductor device;
A power conversion method comprising: comparing the PWM command with the feedback signal; and if the comparison results in a mismatch, generating a short pulse distinguishable from the PWM command as an emergency stop command and superimposing the short pulse on the PWM command. (delete)

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